KR102189572B1 - Liquid Crystal Display Device - Google Patents

Abstract

The liquid crystal display device according to the present invention includes a liquid crystal panel on which a gate line including an odd gate line and an odd gate line and a data line are formed, a first gate driver providing a gate pulse to the odd gate line, and a gate pulse to the excellent gate line. And a second gate driver providing a second gate driver, a data driver providing a data voltage to a data line, and a timing controller providing a gate timing control signal controlling an output timing of a gate pulse to the first and second gate drivers. The timing controller outputs a gate timing control signal to receive a gate pulse whose polling time is delayed as a gate line connected to a horizontal line receiving a data voltage late is provided.

Description

Liquid Crystal Display Device

The present invention relates to a liquid crystal display device.

Flat panel display devices include Liquid Crystal Display (LCD), Field Emission Display (FED), Plasma Display Panel (PDP), and Organic Light Emitting Diode Device (OLED). ), etc. In the flat panel display, data lines and gate lines are arranged to be orthogonal, and a region where data lines and gate lines are orthogonal is defined as one pixel. A plurality of pixels are formed in a matrix form in the panel. In order to drive each pixel, a video data voltage to be displayed is supplied to the data lines and a gate pulse is sequentially supplied to the gate lines. In addition, the video data voltage is supplied to pixels of the display line to which the gate pulse is supplied, and all display lines are sequentially scanned by the gate pulse to display video data.

Recently, as the resolution of the liquid crystal panel increases and the number of gate lines increases, the time to scan one gate line is decreasing. Correspondingly, in order to secure the scan time of the gate lines, a double-scan driving method in which each gate driver drives 1/2 of the gate lines using two gate drivers is used.

In the double-scan driving method, pixels located at the edge of the liquid crystal panel have different data charging timings between adjacent horizontal lines because the delays of gate pulses provided from each gate driver are different. That is, even if adjacent horizontal pixels in the same column try to display the same data, since the data charging timing is different, a difference in luminance occurs between them. In the horizontal lines at the rear stage receiving the data voltage late, the delay of the data voltage becomes severe, and the luminance deviation between adjacent horizontal lines increases, resulting in a horizontal dim phenomenon that is easily distinguished by the naked eye.

Accordingly, an object of the present invention is to provide a display device and a method for compensating the data charging deviation thereof to alleviate the data charging deviation for each position of a liquid crystal panel.

In order to achieve the above object, a liquid crystal display device according to the present invention includes a liquid crystal panel on which a gate line including an odd gate line and an odd gate line and a data line are formed, a first gate driver providing a gate pulse to the odd gate line, A second gate driver providing a gate pulse to an excellent gate line, a data driver providing a data voltage to a data line, and a timing providing a gate timing control signal controlling the output timing of the gate pulse to the first and second gate drivers Includes a controller. The timing controller outputs a gate timing control signal to receive a gate pulse whose polling time is delayed as a gate line connected to a horizontal line receiving a data voltage late is provided.

According to the present invention, a difference in brightness between pixels formed on an odd horizontal line and an even horizontal line adjacent to each other can be reduced by the data voltage delay.

1 is a diagram showing the configuration of a liquid crystal display device according to the present invention.
2 is a diagram showing a configuration of a data driver according to the present invention.
3 is a diagram showing the configuration of a gate driver according to the present invention.
4 and 5 are diagrams for explaining a horizontal dim phenomenon.
6 is a diagram illustrating a gate control signal and a gate pulse according to the first embodiment.
7 is a diagram for explaining a principle of improving the horizontal dim phenomenon.
8 is a diagram illustrating a gate control signal and a gate pulse according to the second embodiment.
9 is a diagram illustrating a gate control signal and a gate pulse according to a third embodiment.
10 is a diagram illustrating a gate control signal and a gate pulse according to a fourth embodiment.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, focusing on a liquid crystal display. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that detailed descriptions of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

1 is a diagram showing the configuration of a liquid crystal display device according to the present invention.

Referring to FIG. 1, a liquid crystal display (LCD) according to the present invention includes a liquid crystal panel 100, a timing controller 200, a data driver 300, and first and second gate drivers 410 and 420. Include.

The liquid crystal panel 100 includes a thin film transistor array substrate on which a thin film transistor array is formed and a color filter substrate on which a color filter is formed, and a liquid crystal layer is formed between the thin film transistor array substrate and the color filter substrate.

In the thin film transistor array substrate of the liquid crystal panel 100, pixels P defined by the gate lines GL and data lines DL1 to DLn arranged vertically and horizontally are arranged in a matrix form. The gate lines GL1 to GL2m include odd gate lines GL1 to GL[2m-1] and even gate lines GL2 to GL2m. Odd gate lines GL1 to GL[2m-1] are connected to pixels arranged on odd-numbered horizontal lines, and even gate lines GL2 to GL[2m] are connected to pixels arranged on even-numbered horizontal lines. do.

The pixel P may be defined as a region where the gate line GL and the data line DL cross, and includes a thin film transistor TFT, a storage capacitor Cst, and a liquid crystal capacitor Clc.

The thin film transistor TFT is connected to the gate line GL and the data line DL, and the storage capacitor Cst and the liquid crystal capacitor Clc are connected to the thin film transistor TFT. The liquid crystal capacitor Clc is composed of a pixel electrode (not shown) connected to the thin film transistor TFT, a liquid crystal layer, and a common electrode, and serves to display a gray level corresponding to a data signal applied to the pixel electrode. (Cst) stores the data signal for one frame to keep the voltage of the pixel electrode constant.

The data driver 300 receives digital video data RGB from the timing controller 210. The data driver 300 converts digital video data (RGB) into a positive/negative analog data voltage in response to a source timing control signal provided from the timing controller 210 and converts the data voltage into a gate pulse (or scan pulse). ) Is supplied to the data lines of the display panel 100 so as to be synchronized.

2 is a block diagram showing the configuration of the data driver 300.

Referring to FIG. 2, the data driver 300 includes a register unit 310, a first latch 320, a second latch 330, and a digital to analog converter (hereinafter, referred to as DAC) 340. ) And an output unit 350.

The register unit 310 samples the RGB digital video data bits of the input image using data control signals SSC and SSP provided from the timing controller 200 and provides the data to the first latch 320.

The first latch 320 samples and latches digital video data bits according to a clock sequentially provided from the register unit 310, and simultaneously outputs the latched data. The second latch 330 latches data provided from the first latch 310 and simultaneously outputs the latched data in response to the source output enable signal SOE.

The DAC 340 converts the video data input from the second latch unit 330 into a gamma compensation voltage (GMA) to generate an analog video data voltage.

The output unit 350 provides the analog data voltage DATA output from the DAC 247 to the data lines DL during the low logic period of the source output enable signal SOE.

The first gate driver 410 generates a gate pulse provided to the (2k-1)th (k is a natural number less than m) gate line in response to a gate timing control signal provided from the timing controller 200. To this end, as shown in FIG. 3, the first gate driver 410 includes a shift register 411, a level shifter 415, and a plurality of AND gates connected between the shift register 411 and the level shifter 415 (hereinafter , &Quot;AND gate") 412 is provided.

The shift register 411 sequentially shifts a gate start pulse (GSP) according to a gate shift clock (GSC) by using a plurality of flip-flops that are dependently connected. Each of the AND gates 412 generates an output by logically multiplying a non-inverted output signal of a flip-flop of the shift register 411 and an inverted signal of a gate output enable signal (GOE). The gate output enable signal GOE is inverted by the inverter 413 and is input to an input terminal of one side of the AND gate 412. The level shifter 415 shifts the swing width of the output voltage of the AND gate 412 to the swing width in which the TFT of the liquid crystal display panel can operate. The output signals G1 to G[2m-1] of the level shifter 415 are sequentially supplied to m (k is an integer) gate lines.

Similarly, the second gate driver 420 generates a gate pulse provided to the second k (k is a natural number less than m) gate line in response to a gate timing control signal provided from the timing controller 200.

The timing controller 200 receives timing signals such as vertical/horizontal synchronization signals (Vsync, Hsync), data enable signals (Data Enable, DE), and clock signals (CLK) from a system board (not shown) and outputs data. It generates an enable signal and an output clock signal. The timing controller 200 controls operation timings of the first and second gate drivers 410 and 420 in order to control the data voltage charger between the horizontal lines. The reason why the timing controller 200 controls the operation timing of the first and second gate drivers 410 and 420 is to improve the occurrence of horizontal dim due to a difference between the data voltage chargers. The horizontal dim phenomenon due to the difference between the data voltage chargers is as follows.

When the thin film transistor TFT is turned on by a gate pulse, the pixels P of the liquid crystal panel 100 are charged by a data voltage provided through the data line DL. Since the intervals between the horizontal lines and the data driver 300 are different from each other, the degree of delay of the data voltage provided to the horizontal lines is also different. For example, as shown in FIG. 4, if the data voltage is delayed by'△t0' at a position close to the first horizontal line, the data voltage is delayed by'△t1' longer than'△t0' at a position close to the 2m horizontal line. do. In addition, as the delay phenomenon of the data voltage increases, the rate at which the data voltage is charged becomes slower, so that the data voltage charging graph has a gentler slope than when there is no delay. The delay phenomenon of the data voltage causes a difference in charging of the data voltage between horizontal lines. Since the delay phenomenon of the data voltage is proportional to the length of the data line, the charging deviation of the data voltage between adjacent horizontal lines is similar. Therefore, due to the delay of the data voltage, a luminance deviation with a similar difference occurs between horizontal lines, which does not significantly affect the user's visibility.

However, when the gate line GL is divided into odd gate lines GL1 to GL[2m-1] and even gate lines GL2 to GL[2m] and double-scanned, the adjacent gate line GL is Since the delay level of the provided gate pulse is also changed, the difference in luminance between the horizontal lines due to the delay of the data voltage increases. For example, a data charging deviation of the first pixel P1 and the second pixel P2 illustrated in FIG. 4 will be described as follows. The first and second pixels P1 and P2 are pixels located in the edge region of the liquid crystal panel 100 in which the first gate driver 410 is disposed. The first pixel P1 is connected to the horizontal line HL[2k-1] in the (2k-1)-th row, and the second pixel P2 is connected to the horizontal line HL2k in the 2k-th row. Accordingly, the first pixel P1 is scanned by the gate pulse provided through the first gate driver 410, and the second pixel P2 is scanned by the gate pulse provided through the second gate driver 420. do. Since the first and second pixels P1 and P2 are located close to the first gate driver 410, the (2k-1)th gate pulse G provided to the first pixel P1 is The delay of the 2k gate pulse G[2k] provided to the second pixel P2 is more severe than that of [2k-1]). Accordingly, the falling timing of the 2k second gate pulse G[2k] provided to the second pixel P2 is also the (2k-1)th gate pulse G1 to G2m provided to the first pixel P1 It is delayed by'△tf' than the polling point of. In addition, since the first and second pixels P1 and P2 are located farther from the data driver 300 than other horizontal lines, a data voltage delay is also severe. Therefore, the (2k-1)th gate pulse G[2-1] and the 2k gate pulse G[2k] provided to the first and second pixels P1 and P2 are completely charged with the data voltage. Polled before.

It shows the same form as the data charging characteristic graph (Vdata) shown in the drawing where actual pixels are charged. Therefore, the difference between the charging amount of the data voltage by the (2k-1)th gate pulse G[2k-1] and the 2k second gate pulse G[2k] input to the first pixel P1 is'ΔV1. It corresponds to'. That is, the first and second pixels P1 and P2 have a luminance deviation by a voltage difference of'ΔV1'.

This difference is because the charging amount of the data voltage per unit time varies with time.

In order to improve the deviation of the charging amount of the data voltage, the timing controller 200 according to the present invention makes the polling timing of the gate pulses provided to each of the gate lines GL1 to GL[2m] different. In particular, the timing controller 200 delays the polling timing of the gate pulses provided to the gate lines GL1 to GL[2m] located far from the data driver 300.

6 is a diagram illustrating gate timing control signals according to the first embodiment and output timing of a gate pulse using the same. Referring to FIG. 6, the timing controller 200 controls the gate timing control signal to scan 2m (m is a natural number) gate lines during a 2m horizontal period. That is, in the first embodiment, the first and second gate drivers 410 and 420 alternately output gate pulses G1 to G2m. For example, in the first horizontal period (1H), the first gate driver 410 outputs the first gate pulse (G1), and in the second horizontal period (2H), the second gate driver 420 is the second gate Outputs pulse G2. Since the liquid crystal display according to the first embodiment outputs gate pulses from both sides of the liquid crystal panel 100 using the first and second gate drivers 410 and 420, the bezel is evenly positioned at both edges of the liquid crystal panel 100. Can be dispersed.

And the timing controller 200 according to the first embodiment maintains the same width of the first to 2m gate pulses (G1 to G2m), and the rising time and polling of the first to 2m gate pulses (G1 to G2m) The time point is sequentially delayed. In other words, when the interval between the start of the i-th horizontal period iH and the output timing of the i-th gate pulse Gi is the i-th delay period Tdi, the timing controller 200 is Tdi<Td(i+). The timing at which the ith gate pulse Gi is output may be controlled to satisfy the condition of 1). For example, the timing controller 200 determines that the second delay period Td2 from the start of the second horizontal period 2H to the output of the second gate pulse G2 is the first time from the start of the first horizontal period 1H. The output timing of the first and second gate pulses G1 and G2 may be controlled longer than the first delay period Td1 until the output timing of the first gate pulse G1. Similarly, in the timing controller 200, the 2m-th delay period (Td[2m]) from the start of the 2m-th horizontal period (H2m) to the output of the 2m-th gate pulse (G2m) is the 2m-th horizontal period (2mH). Gate pulses G1 to G2m to be longer than the (2m-1)th delay period (T[2m-1]) from the start point until the (2m-1)th gate pulse G[2m-1] is output The output timing of can be controlled.

The timing controller 200 may control the output timing of the i-th gate pulse Gi using the i-th gate output enable signal. For example, the timing controller 200 may control the timing of outputting the gate pulse Gi by controlling the timing of the i th gate output enable signal being polled from the start of the i th horizontal period iH.

Since the pulse width of each of the gate pulses G1 to G2m is kept the same, the polling timing of the gate pulses G1 to G2m is also delayed as the output timing of the gate pulses G1 to G2m is delayed. Therefore, the i-th gate-off period Toff[i] from the falling point of the i-th gate pulse Gi to the end of the i-th horizontal period iH is the (i-1)th gate-off period Toff[i It becomes shorter than -1]).

In addition, the timing controller 200 uses the gate pulses G1 to G2m so that the 2m-th gate-off period Toff[2m], which is the gate-off period of the 2m-th horizontal line HL2m receiving the data voltage, is greater than '0'. Controls the output timing of ). That is, the timing controller 200 controls the timing of the gate pulses G1 to G2m so that the i-th gate pulse Gi is applied within the i-th horizontal period iH.

7 is a diagram illustrating improvement of a horizontal dim phenomenon in the liquid crystal display according to the first embodiment.

The data voltage charging characteristic graph Vdata shown in FIG. 7 represents the amount of charging the data voltage Data according to time. The data voltage charging characteristic graph (Vdata) shows that the data voltage charging amount for the unit time change decreases as time elapses. This is because the data voltage is rapidly charged at the initial stage of charging, and then the charging rate decreases as time passes, and the data voltage becomes saturated after a certain time.

In addition, the data voltage charging characteristic graph Vdata is shifted along the time axis by the delay of the data voltage. Therefore, the gate pulses G1 to G2m are polled before the data voltage is saturated. The (2i-1)-th gate pulses G1 to G2m and the 2i-th gate pulses G1 to G2m respectively provided to the first and second pixels P1 and P2 shown in FIG. 4 have a polling point of'tf1'. 'And'tf2', a luminance difference corresponding to the first voltage difference ΔV1 occurs between the first and second pixels P1 and P2.

The liquid crystal display according to the first embodiment delays the polling timing of the (2i-1)th gate pulse G[2i-1] and the 2i-th gate pulse G[2i] to'tf3' and'tf4'. Let it. Accordingly, a difference in luminance corresponding to the second voltage difference ΔV2 occurs between the first and second pixels P1 and P2.

Even if the time difference between'tf1' and'tf2' and the time difference between'tf3' and'tf4' are almost the same, the second voltage difference (△V2) is the first voltage difference (△V1) due to the data voltage charging characteristic. ) Is less than. This is because, as mentioned above, the amount of data voltage charged to the pixel decreases over time. That is, the liquid crystal display according to the first embodiment delays the gate pulses G1 to G2m, thereby reducing a difference in luminance between pixels formed on an odd horizontal line and an even horizontal line adjacent to each other by a data voltage delay. .

The liquid crystal display according to the first exemplary embodiment delays the polling point of the gate pulses G1 to G2m, thereby minimizing luminance deviation due to the data voltage delay. Since the delay phenomenon of the data voltage is proportional to the length of the data line, the change of the gate pulse polling time between adjacent gate lines is all set equally. In other words, the intervals between adjacent gate-off sections may all be set equally. That is, the difference between the (i-1)th gate-off period Toff[i-1] and the i-th gate-off period Toff[i] is the (i+1)th gate-off period Toff[i+1]. ]) and the i-th gate-off period Toff[i].

8 is a diagram showing timing of a gate timing control signal and a gate pulse according to the second embodiment. The timing controller 200 according to the second exemplary embodiment controls the gate timing control signal to scan 2m (m is a natural number) gate lines during a 2m horizontal period. That is, in the second embodiment, the first and second gate drivers 410 and 420 alternately output gate pulses G1 to G2m. For example, in the first horizontal period (1H), the first gate driver 410 outputs the first gate pulse (G1), and in the second horizontal period (2H), the second gate driver 420 is the second gate Outputs pulse G2.

The timing controller 200 according to the second embodiment maintains a constant rising time of the first to 2m-th gate pulses G1 to G2m and sequentially delays the polling time. In other words, when the interval between the start of the i-th horizontal period iH and the output time of the i-th gate pulse Gi is the i-th delay period Tdi, the timing controller 200 is Tdi=Td(i+) The timing at which the ith gate pulse Gi is output may be controlled to satisfy the condition of 1). In addition, the timing controller 200 controls the timing of the gate pulse so that the i-th gate pulse Gi has a width greater than that of the (i-1)-th gate pulse G[i-1].

The timing controller 200 may control the output timing of the i-th gate pulse Gi using the i-th gate output enable signal. For example, the timing controller 200 maintains the same time point at which the gate output enable signal GOE is polled, and sequentially increases the low level maintenance period of the gate output enable signal GOE provided to each horizontal line. .

As described above, since the width of the gate pulses G1 to G2m according to the second embodiment is increased while the output timing is maintained the same, the polling timing of the gate pulses G1 to G2m is also delayed. Accordingly, the i-th gate-off period Tfi from the falling point of the i-th gate pulse Gi to the end of the i-th horizontal period iH is shorter than the (i-1)th gate-off period Toff.

In addition, the timing controller 200 has a 2m-th gate-off period Toff[2m], which is a gate-off period of the 2m-th horizontal line HL[2m], which receives the data voltage most recently, is '0'. The output timing of the gate pulses G1 to G2m is controlled to be larger. That is, the timing controller 200 controls the timing of the gate pulse so that the i-th gate pulse Gi is applied within the i-th horizontal period iH.

As described above, the first and second embodiments refer to an embodiment in which the first and second gate drivers 410 and 420 scan odd gate lines and even gate lines, respectively. In the case of performing double-scan by dividing the gate lines, in order to sequentially provide data voltages, a method of sequentially scanning odd-numbered gate lines and even gate lines as in the first and second embodiments is used. If the same data is provided to adjacent horizontal lines, such as when there is a difference in the resolution of the image and the resolution of the liquid crystal display panel, the odd gate line and the even gate line may be scanned simultaneously. The following third and fourth embodiments apply the embodiments of the present invention to a method of simultaneously scanning odd-numbered gate lines and even-numbered gate lines.

9 is a diagram illustrating gate timing control signals according to the third embodiment and output timing of gate pulses G1 to G2m using the same. The timing controller 200 according to the third embodiment controls the gate timing to scan m odd gate lines and m even gate lines during m horizontal periods to scan 2 m (m is a natural number) gate lines during m horizontal periods. Control the signal. That is, in the third embodiment, the first and second gate drivers 410 and 420 are simultaneously driven. For example, in the first horizontal period 1H, the first gate driver 410 outputs the first gate pulse G1, and the second gate driver 420 outputs the second gate pulse G2. And, within the m-th horizontal period (mH), the first gate driver 410 outputs the (2m-1)th gate pulse (G[2m-1]), and the second gate driver 420 is the 2m-th gate Outputs pulse (G2m).

The liquid crystal display according to the third embodiment can increase the time to scan one gate line by driving the first and second gate drivers 410 and 420 at the same time, thereby securing a large data charging time.

In addition, the timing controller 200 according to the third embodiment maintains the same widths of the first to (2m-1)th gate pulses G1 to G[2m-1] provided to the odd gate line, and the first To (2m-1)th gate pulses G1 to G[2m-1] are sequentially delayed in rising time and polling time. That is, the timing controller 200 has a (2i-1) (i is a natural number equal to or greater than 1 and equal to or less than m) horizontal period from the start of the (2i-1)th gate pulse output time to the (2i-3) horizontal period. The gate timing control signal is controlled to be set longer than the period between the start of the (2i-3)th gate pulse and the output point of the (2i-3)th gate pulse.

In addition, the timing controller 200 maintains the same width of the second to 2m gate pulses G2 to G2m provided to the excellent gate line, and the rising time of the second to 2m gate pulses G2 to G2m and The polling time is sequentially delayed. That is, in the timing controller 200, the section between the start of the 2i-th horizontal period and the output time of the 2i-th gate pulse is greater than the section between the start of the (2i-2)th and the output time of the (2i-2)th gate pulse. The gate timing control signal is controlled to be set long.

10 is a diagram illustrating gate timing control signals according to a fourth embodiment and output timing of gate pulses G1 to G2m using the same. The timing controller 200 according to the fourth embodiment controls the gate timing to scan m odd gate lines and m even gate lines during m horizontal periods to scan 2 m (m is a natural number) gate lines during m horizontal periods. Control the signal. That is, in the fourth embodiment, the first and second gate drivers 410 and 420 are simultaneously driven.

In addition, the timing controller 200 according to the fourth embodiment has the same rising times of the first to (2m-1)th gate pulses G[2m-1] provided to the odd gate line, and (2m-1) Increase the width of the gate pulses (G1~G[2m-1]). That is, the timing controller 200 controls the (2i-1)th gate pulse provided to the (2i-1) odd-numbered gate line from the start of the (2i-1)th (i is a natural number of 1 or more and m or less) horizontal period. The section between the output times and the section between the output times of the (2i-3)th gate pulse provided to the (2i-3) odd-numbered gate line from the start of the (2i-3)th horizontal period are the same. Further, the timing controller 200 controls the gate timing control signal so that the width of the (2i-1)th gate pulse is longer than that of the (2i-3)th gate pulse.

Similarly, the timing controller 200 equalizes the rising timing of the second to 2m gate pulses G2 to G2m provided to the excellent gate line, and increases the width of the second to 2m gate pulses G2 to G2m. . That is, the timing controller 200 includes a section between the start of the 2i-th horizontal period and the output point of the 2i-th gate pulse provided to the 2i-th excellent gate line and the (2i-2)-th from the start of the (2i-2)th horizontal period. The interval between the output points of the pulses of the (2i-2)th gate pulse provided to the even gate line is set to be the same. In addition, the timing controller 200 controls the gate timing control signal so that the width of the 2i-th gate pulse is longer than that of the (2i-2)-th gate pulse.

In addition, the liquid crystal display according to the first to fourth embodiments described above controls the output timing of the gate pulse using the gate output enable signal GOE. However, the technical idea of the present invention is not limited thereto, and it is obvious that it can be used in a liquid crystal display device having a gate-in-panel (GIP) structure. That is, instead of the gate output enable signal, the output timing of the gate pulse may be controlled by delaying the output of the gate clock signal or the like.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

100: liquid crystal panel 200: timing controller
300: data driver 410: first gate driver
420: second gate driver

Claims (8)

delete A liquid crystal panel on which gate lines and data lines including odd gate lines and even gate lines are formed;
A first gate driver providing a gate pulse to the odd gate line;
A second gate driver providing a gate pulse to the even gate line;
A data driver providing a data voltage to the data line; And
And a timing controller providing a gate timing control signal for controlling an output timing of the gate pulse to the first and second gate drivers.
The timing controller outputs the gate timing control signal to receive the gate pulse whose polling timing is delayed as the gate line connected to the horizontal line receiving the data voltage late,
When the data voltage charge amount charged to the pixels of the liquid crystal panel decreases with time according to the data voltage charge characteristic curve,
The timing controller delays the gate pulse to move the falling timing of the gate pulse provided to the adjacent gate line and the even gate line to a later stage along a time axis in the data voltage charging characteristic curve.
A liquid crystal panel on which gate lines and data lines including odd gate lines and even gate lines are formed;
A first gate driver providing a gate pulse to the odd gate line;
A second gate driver providing a gate pulse to the even gate line;
A data driver providing a data voltage to the data line; And
And a timing controller providing a gate timing control signal for controlling an output timing of the gate pulse to the first and second gate drivers.
The timing controller outputs the gate timing control signal to receive the gate pulse whose polling timing is delayed as the gate line connected to the horizontal line receiving the data voltage late,
The timing controller is
Controlling the gate timing control signal to scan 2m (m is a natural number) gate lines during a 2m horizontal period,
The i-th gate pulse provided to the i-th gate line (i is a natural number of 1 or more and 2 m or less) and the (i-1)-th gate pulse provided to the (i-1)-th gate line have the same pulse width,
The gate timing so that the period between the start of the i-th horizontal period and the output time of the i-th gate pulse is set longer than the period between the start of the (i-1)th horizontal period and the output time of the (i-1)th gate pulse A display device that controls a control signal.
A liquid crystal panel on which gate lines and data lines including odd gate lines and even gate lines are formed;
A first gate driver providing a gate pulse to the odd gate line;
A second gate driver providing a gate pulse to the even gate line;
A data driver providing a data voltage to the data line; And
And a timing controller providing a gate timing control signal for controlling an output timing of the gate pulse to the first and second gate drivers.
The timing controller outputs the gate timing control signal to receive the gate pulse whose polling timing is delayed as the gate line connected to the horizontal line receiving the data voltage late,
The timing controller is
Controlling the gate timing control signal to scan 2m (m is a natural number) gate lines during a 2m horizontal period,
The i-th (i is a natural number of 1 or more and 2m or less) from the start of the horizontal period to the period between the output time of the i-th gate pulse provided to the i-th gate line and the (i-1)th horizontal period ) The section between the output points of the (i-1)th gate pulse provided to the gate line is the same,
The display device controlling the gate timing control signal such that the width of the i-th gate pulse is greater than the width of the (i-1)-th gate pulse.
A liquid crystal panel on which gate lines and data lines including odd gate lines and even gate lines are formed;
A first gate driver providing a gate pulse to the odd gate line;
A second gate driver providing a gate pulse to the even gate line;
A data driver providing a data voltage to the data line; And
And a timing controller providing a gate timing control signal for controlling an output timing of the gate pulse to the first and second gate drivers.
The timing controller outputs the gate timing control signal to receive the gate pulse whose polling timing is delayed as the gate line connected to the horizontal line receiving the data voltage late,
The timing controller is
M number of odd gate lines and m number of even gate lines are scanned during m horizontal periods to scan 2 m (m is a natural number) gate lines during m horizontal period,
(2i-1)th gate pulse provided to the (2i-1)th (i is a natural number of 1 or more and m or less) odd gate line and (2i-3) gate provided to the (2i-3) odd gate line The pulse width of the pulse is the same,
The section between the start of the (2i-1)th horizontal cycle and the output time of the (2i-1)th gate pulse is between the start of the (2i-3)th horizontal cycle and the output time of the (2i-3)th gate pulse Is set longer than the section,
The pulse widths of the 2i-th gate pulse provided to the 2i-th excellent gate line and the (2i-2)-th gate pulse provided to the (2i-2)-th excellent gate line are the same,
The gate timing so that the period between the start of the 2i-th horizontal period and the output time of the 2i-th gate pulse is set longer than the period between the start of the (2i-2)th horizontal period and the output time of the (2i-2)-th gate pulse A display device that controls a control signal.
A liquid crystal panel on which gate lines and data lines including odd gate lines and even gate lines are formed;
A first gate driver providing a gate pulse to the odd gate line;
A second gate driver providing a gate pulse to the even gate line;
A data driver providing a data voltage to the data line; And
And a timing controller providing a gate timing control signal for controlling an output timing of the gate pulse to the first and second gate drivers.
The timing controller outputs the gate timing control signal to receive the gate pulse whose polling timing is delayed as the gate line connected to the horizontal line receiving the data voltage late,
The timing controller is
M number of odd gate lines and m number of even gate lines are scanned during m horizontal periods to scan 2 m (m is a natural number) gate lines during m horizontal period,
(2i-1) (i is a natural number greater than or equal to 1 and less than or equal to m) from the start of the horizontal period to the period between the output time of the (2i-1)th gate pulse provided to the (2i-1)-th gate line and the (2i)th -3) The interval between the start of the horizontal period and the output point of the (2i-3)th gate pulse provided to the (2i-3) odd-numbered gate line is the same,
The width of the (2i-1)th gate pulse is maintained longer than that of the (2i-3)th gate pulse,
The period between the start of the 2i-th horizontal period and the output point of the 2i-th gate pulse provided to the 2i-th even gate line and the (2i-2)th ( 2i-2) The interval between the output points of the gate pulse pulse is the same,
A display device for controlling the gate timing control signal such that the width of the 2i-th gate pulse is maintained longer than that of the (2i-2)-th gate pulse.
A liquid crystal panel on which gate lines and data lines including odd gate lines and even gate lines are formed;
A first gate driver providing a gate pulse to the odd gate line;
A second gate driver providing a gate pulse to the even gate line;
A data driver providing a data voltage to the data line; And
And a timing controller providing a gate timing control signal for controlling an output timing of the gate pulse to the first and second gate drivers.
The timing controller outputs the gate timing control signal to receive the gate pulse whose polling timing is delayed as the gate line connected to the horizontal line receiving the data voltage late,
The timing controller is
Controlling the gate timing control signal to scan 2m (m is a natural number) gate lines during a 2m horizontal period,
When the i-th gate-off period is the period between the falling point of the i-th gate pulse provided to the i-th (i is a natural number of 1 or more and 2m or less) and the end of the i-th horizontal period as the i-th gate-off period The display device controlling the gate timing control signal such that a difference in an interval between the (i-1)th gate-off period is equal to a difference in the interval between the (i+1)th gate-off period and the i-th gate-off period. delete

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