KR20160070446A - Display device and method for driving the same - Google Patents

Abstract

The present invention relates to a display device capable of low refresh rate (LRR) driving for each gate line and a method for driving the same. The display device comprises: a display panel having a plurality of gate lines and a plurality of data lines disposed to cross each of the gate lines; a gate driver having a shift register to sequentially drive the gate lines; and a timing controller supplying a plurality of carrying clock pulses and a plurality of scanning clock pulses to the gate driver. If still images are partially present on a video screen, the timing controller supplies the carrying clock pulses and the scanning clock pulses to a frequency driving a video when gate lines corresponding to the video are driven, supplies the carrying clock pulses to the frequency driving the video when gate lines corresponding to the still image are driven, and supplies the scanning clock pulses to a frequency lower than the frequency driving the video.

Description

[0001] Description [0002] DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME [0002]

The present invention relates to a display device, and more particularly, to a display device capable of driving LRR (Low Refresh Rate) line by line and a driving method thereof.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a configuration circuit diagram showing a driving device of a general liquid crystal display device. FIG.

1, a liquid crystal display device generally includes a liquid crystal panel 2 for displaying an image, a gate driver 6 for driving the gate lines GL1 to GLn of the liquid crystal panel 2, A data driver 4 for driving the data lines DL1 to DLm of the liquid crystal panel 2 and a driving circuit 4 for supplying image data RGB inputted from outside to the data driver 4, And a timing controller 8 for generating data control signals GCS and DCS to control the gate and data drivers 6 and 4, respectively.

The liquid crystal panel 2 includes a thin film transistor (TFT) formed in each pixel region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, And a liquid crystal capacitor Clc. The liquid crystal capacitor Clc is composed of a pixel electrode connected to the thin film transistor, and a common electrode arranged between the pixel electrode and the liquid crystal. The thin film transistor supplies a video signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn.

The liquid crystal capacitor Clc charges the difference voltage between the video signal supplied to the pixel electrode and the common voltage SVcom applied to the common electrode and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage Thereby implementing the gradation. At this time, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line sandwiched by the insulating film, and a parasitic capacitor Cgs may be further formed between the source electrode of the thin film transistor and the gate line GL.

The data driver 4 receives a data control signal DCS from the timing controller 8, for example, a source start signal SSP, a source shift clock SSC, And converts the aligned data Data from the timing controller 8 into an analog voltage, that is, a video signal, using an SOE (Source Output Enable) signal and an inversion signal (Pol Signal). Specifically, the data driver 4 latches the aligned data Data through the timing controller 8 in accordance with the SSC, and then, in response to the SOE signal, supplies the scan pulses to the gate lines GL1 to GLn And supplies video signals for one horizontal line to each of the data lines DL1 to DLm for each horizontal period.

The gate driver 6 sequentially drives the gate lines GL1 to GLn according to the gate control signal GCS from the timing controller 8. [ Specifically, the gate driver 4 outputs a gate start signal (GSP), a gate shift clock (GSC), a gate output enable (GOE) signal Or the like so that the scan pulses of the gate high voltage (VGH) level are sequentially supplied to the gate lines GL1 to GLn. And the gate-low voltage is supplied to the remaining period in which the scan pulse is not supplied.

The timing controller 8 controls the data driver 4 and the gate driver 6 in accordance with image data RGB and a plurality of synchronization signals DCLK, Hsync, Vsync and DE from the outside. Specifically, the timing controller 8 arranges image data (RGB) input from the outside so as to be suitable for driving the liquid crystal panel 2, and supplies the image data to the data driver 4. A gate control signal GCS and a data control signal GCS are generated by using at least one of a synchronizing signal input from the outside, that is, a dot clock DCLK, a data enable signal DE, and horizontal and vertical synchronizing signals Hsync and Vsync DCS, and supplies them to the gate driver 6 and the data driver 4, respectively.

In such a liquid crystal display device, the driving frequency is varied according to the image to be displayed, and the number of times that the entire screen is refreshed in one second is varied according to the driving frequency.

That is, when the full screen displays a moving picture or a partial moving picture, it operates at a frame frequency of 60 Hz. When the entire screen displays a still picture, it operates at a frame frequency of 1 Hz.

Driving at a frame frequency of 60 Hz means that the liquid crystal capacitor Clc of each sub pixel is charged 60 times per second. Driving at a frame frequency of 1 Hz is performed once per second to the liquid crystal capacitor Clc of each sub pixel It is a case of charging.

2 (a) shows a case where a gate start pulse Vst and a scan pulse Vg_out1... Vg_outn are shown when a full screen is driven at a frame frequency of 60 Hz. FIG. 2 (b) The gate-start pulse Vst and the scan pulse Vg_out1 .... Vg_outn are shown.

When driving at a frequency of 1 Hz, scan pulses of all gates are output at the same 1H timing as when driven at a frequency of 60 Hz, and then held without being driven for the remaining time of one frame. Therefore, the power consumption is small when driving at a frequency of 1 Hz as compared with driving at a frequency of 60 Hz.

However, such a conventional method of driving a display device has the following problems.

In other words, since the entire area of the display device is driven at the same frequency, low frequency (1 Hz) drive is possible only in the case of a still image in which the entire screen remains unchanged. ) Can not be driven, and must be driven at a high frequency (60 Hz). Therefore, unnecessary power is consumed because high frequency driving is performed such that the area occupied by the still image in the entire screen is wider than the area occupied by the moving image.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display apparatus and a driving method thereof that can drive a display panel with different driving frequencies on a line-by-line basis.

According to an aspect of the present invention, there is provided a display device including: a display panel having a plurality of gate lines and a plurality of data lines arranged to intersect with the gate lines; A gate driver having a shift register to sequentially drive the plurality of gate lines; When a plurality of carry clock pulses and a plurality of scan clock pulses are supplied to the gate driver and a still image is partially present on the moving picture screen, And supplies a clock pulse for a carry and a plurality of scan clock pulses at a frequency for driving the motion picture, and for driving the gate lines corresponding to the still picture, supplies the carry clock pulses for a plurality of times to a frequency for driving the motion picture And a timing controller for supplying the plurality of scanning clock pulses at a frequency lower than a frequency for driving the moving image.

Here, the shift register includes a plurality of stages, and each of the stages includes a carry pulse or a start pulse output from the previous stage and a carry pulse output from the next stage, A carry pulse output section for receiving a clock pulse for carry and outputting a carry pulse, and a carry pulse output section for outputting a carry pulse or a start pulse output from the previous stage and a carry pulse output from the next stage, And a scan pulse output unit for receiving one carry clock pulse and outputting a scan pulse to the corresponding gate line.

Wherein the shift register includes a plurality of stages, each of the stages including a node controller for controlling a Q node and a QB node according to a carry pulse or a start pulse output from the front stage and a carry pulse output from the next stage, A carry pulse output unit for receiving a carry clock pulse of one of the carry clock pulses and outputting a carry pulse according to a voltage of a Q node and a QB node of the node controller; And a scan pulse output unit receiving a clock pulse for one of the carry signals and outputting a scan pulse to the corresponding gate line according to the voltages of the Q and QB nodes of the node control unit.

According to another aspect of the present invention, there is provided a method of driving a display device including a shift register embedded in a gate driver for sequentially driving a plurality of gate lines, the shift register including a plurality of stages, Each of the stages receives a carry pulse for one of a plurality of carry clock pulses according to a carry pulse or a start pulse output from the previous stage and a carry pulse output from the next stage, And a carry pulse output from the previous stage and a carry pulse output from the next stage, and receives a carry clock pulse for one of the plurality of scan clock pulses and supplies the carry pulse to the corresponding gate line A scan pulse output section for outputting a scan pulse A plurality of scan clock pulses for driving and a plurality of scan clock pulses for scan are driven in synchronism with the driving of the gate lines corresponding to the moving image, And supplying the plurality of carry clock pulses to a frequency for driving the moving image, and supplying the plurality of scanning clock pulses to the driving unit for driving the moving image, It is characterized in that it is supplied at a frequency lower than the driving frequency.

The display device and the driving method thereof according to the present invention having the above features have the following effects.

According to the present invention, since the gate lines corresponding to the still image can be driven at a low frequency (1 Hz) when there is a still image partially in driving the moving image, power consumption can be reduced, It is possible to reduce power consumption in all non-video driving.

1 is a circuit diagram showing a driving apparatus of a general liquid crystal display device.
2 (a) and 2 (b) show gate-start pulses and scan pulse timing diagrams according to the drive mode of the conventional liquid crystal display device
3 is a circuit diagram of a driving circuit of a display device according to an embodiment of the present invention.
4 is a timing chart of various signals and output signals input to the shift register of FIG.
5 is a detailed configuration diagram of the shift register SR shown in FIG. 3. FIG.
6 is a diagram showing the configuration of any one stage according to the first embodiment of the present invention
7 is a diagram showing the configuration of any one stage according to the second embodiment of the present invention
8 is a block diagram of a display image for explaining a driving method of the display device according to the present invention
FIG. 9 is a timing diagram of various signals and output signals according to FIG. 8, showing various signals for driving gate lines corresponding to still images and timing diagrams of output signals

Hereinafter, a display device and a driving method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a diagram showing a driving circuit of a display device according to an embodiment of the present invention, and FIG. 4 is a timing chart of various signals and output signals input to the shift register of FIG.

The shift register of the gate driver according to the embodiment of the present invention includes i shift clock pulses C-CLK_ # from the timing controller TC and j scan clock pulses S -CLK_ #). Specifically, the timing controller TC sequentially outputs the carry clock pulses C-CLK_ # of i (i is a natural number greater than 1), and j (j is a natural number greater than 1) Clock pulses S-CLK_ #, and supplies them to the shift register SR. In other words, the timing controller TC outputs the clock pulses for the i-th phase and the clock pulses for the j-th scan. As an example, in FIG. 4, six-phase carry clock pulses (C-CLK_1 to C-CLK_6) having different phase differences and six-phase scan clock pulses (S-CLK_1 to S -CLK_6).

As shown in FIG. 4, the pulse widths of the i carry clock pulses do not overlap with each other, and the pulse widths of the j scan clock pulses do not overlap each other. However, as another embodiment, the output timings of the i carry clock pulses may be adjusted so that the pulse widths between the carry clock pulses output in the adjacent period overlap each other, and the output clock pulses The output timings of the i carry clock pulses may be adjusted so that the pulse widths between the carry clocks overlap each other.

The shift register SR sequentially generates a plurality of outputs on the basis of i clock pulses for carry and j clock pulses for scanning provided from the timing controller TC, And a plurality of stages for sequentially generating such a plurality of outputs. The output generated from each stage is composed of a pair of carry pulses and scan pulses that correspond to each other. In a pair of carry pulses and scan pulses, the carry pulse is supplied to at least one of the subsequent stage and the preceding stages, while the scan pulse is supplied to one of the gate lines.

At this time, the timing controller TC controls a scan clock pulse so that a scan pulse of a different driving frequency is outputted to the gate lines corresponding to the still image and the gate lines corresponding to the still image among the displayed images .

For example, in the timing controller TC, as shown in FIG. 4, a plurality of scan clock pulses (hereinafter referred to as " scan pulse pulses ") are applied to stages for outputting scan pulses to gate lines, (S-CLK_1 to S-CLK_6).

However, the timing controller TC outputs a plurality of scan clock pulses S-CLK_1 to S-CLK_6 to the stages for outputting scan pulses to the gate lines corresponding to the still image among the displayed images I never do that.

A more specific method will be described later.

5 is a detailed configuration diagram of the shift register SR shown in FIG.

The shift register SR according to the present invention includes a plurality of stages ST_n-2 to ST_n + 2, as shown in FIG. Here, each stage includes a total of six terminals I, II, III, IV, V, VI.

The carry clock pulse of any one of the plurality of carry clock pulses C-CLK_1 to C-CLK_6 is applied to the fourth terminal IV of each stage, (Or one of the carry pulses CRPn-2 to CRPn + 2) through the second terminal II (hereinafter referred to as carry pulse output terminal COT) to which the carry pulse (or the start pulse Vst) do.

In addition, any one of scan clock pulses (S-CLK_1 to S-CLK_6) for the plurality of scan clock pulses is applied to the fifth terminal (V) of each stage, and the sixth terminal The output carry pulse is applied and one scan pulse (one of the scan pulses SCPn-2 to SCPn + 2) is output through the third terminal III (hereinafter, referred to as a scan pulse output terminal SOT).

Therefore, the carry pulse and the scan pulse as described above are independently output at the second and third terminals of each stage.

If the carry clock pulses C-CLK_1 to C-CLK_6 for six phases and the clock pulses S-CLK_1 to S-CLK_6 for scan are provided to the shift register as shown in FIG. 4, , and the 6k + 1th (k is a natural number including 0) stages among the stages including the (n-2) th to (n + 2) th stages ST_n-2 to ST_n + The second scan clock pulse (C-CLK_2) and the second scan clock pulse (S-CLK_2), and the 6k + 2 & 4th stages are connected to the fourth carry clock pulse (C-CLK_4) and the fourth carry (C-CLK_4) for the fourth scan, and the third scan clock pulse (6K + 5) -th stages carry the fifth carry clock pulse (C-CLK_5) and the fifth scan clock pulse (S-CLK_5), and the 6k + 6th stages carry the sixth carry Clock pulse (C-CLK_6) And a sixth scan clock pulse (S-CLK_6).

Each stage controls the operation of the stage located at the rear end of the stage and the stage located at the front end using a carry pulse. In addition, each stage drives a gate line connected to itself using a scan pulse. On the other hand, although not shown, a dummy stage for supplying a carry pulse to the final stage may further be provided at a rear stage of the last stage positioned at the end. Depending on the configuration of the shift register SR, this dummy stage may be plural instead of one. Since this dummy stage is not connected to the gate line, the scan pulse is not output.

Such a shift register SR may be embedded in the display panel. That is, the display panel has a display portion for displaying an image and a non-display portion surrounding the display portion, and the shift register SR can be embedded in the non-display portion (GIP).

6 is a diagram showing the configuration of any one stage according to the first embodiment of the present invention.

As shown in Fig. 6, each stage has a carry pulse output section 10 and a scan pulse output section 20 separately.

The carry pulse output section 10 of each stage (n-th stage) outputs a carry pulse (CRP_n + 1) or a start pulse (Vst) output from the previous stage) (C-CLK_ #) of one of the plurality of carry clock pulses (C-CLK_1 to C-CLK_6) is received by the node controller 11 for controlling the Q node and the QB node And a carry pulse output unit 12 for outputting a carry pulse CRP_n according to the voltages of the Q node and the QB node of the node control unit 11. [

The scan pulse output section 20 of each stage (n-th stage) receives the carry pulse CRP_n-1 or the start pulse Vst output from the previous stage and the carry pulse CRP_n + CLK_ #) of any one of the plurality of scan clock pulses (S-CLK_1 to S-CLK_6) for controlling the Q node and the QB node according to the scan clock pulses (S- And a scan pulse output unit 22 for outputting a scan pulse SCP_n according to the voltages of the Q and QB nodes of the node controller 21. [

In FIG. 6, the carry pulse output unit 10 and the scan pulse output unit 20 include the node controllers 11 and 21, respectively, but they can be commonly used.

7 is a diagram showing the configuration of any one stage according to the second embodiment of the present invention.

7, the carry pulse (CRP_n-1) or the start pulse (Vst) output from the previous stage) and the start pulse (Vst) output from the previous stage, and A node controller 11 for controlling a Q node and a QB node according to a carry pulse CRP_n + 1 output from the next stage, and a node controller 11 for controlling either one of the plurality of carry clock pulses C-CLK_1 to C-CLK_6 A carry pulse output section 12 for receiving a clock pulse for carry (C-CLK_ #) of the node control section 11 and outputting a carry pulse (CRP_n) according to the voltages of the Q node and the QB node of the node control section 11, CLK_ #) for one of the scan clock pulses (S-CLK_1 to S-CLK_6) and outputs a scan pulse (S-CLK_ #) according to the voltage of the Q node and the QB node of the node controller And a scan pulse output section 22 for outputting a scan pulse SCP_n.

A driving method of the display device according to the present invention having the above-described structure will now be described.

FIG. 8 shows a configuration of a display image for explaining a driving method of a display device according to the present invention. FIG. 9 is a timing diagram of various signals and output signals according to FIG. 8, And Fig.

Fig. 8 illustrates that, in the video displayed on the entire screen, a moving image is partially present and a still image is displayed on the remaining portion.

As shown in FIG. 8, when a still image partially exists in the still image, the gate lines corresponding to the motion image are driven at 60 Hz, and the gate lines corresponding to the remaining still images are driven at 1 Hz.

That is, in order to drive the gate lines corresponding to the moving image at 60 Hz, as shown in FIG. 4, in the timing controller TC, the carry clock pulses C-CLK_1 to C-CLK_6 ) And j scan clock pulses (S-CLK_1 to S-CLK_6) at a frequency of 60 Hz to the corresponding stage of the gate driver.

In order to drive the gate lines corresponding to the still image at 1 Hz, as shown in FIG. 9, clock pulses (C-CLK_1 to C-CLK_6) for i-phase in the timing controller (TC) To the corresponding stage of the gate driver at a frequency of 60 Hz, and the scan clock pulses (S-CLK_1 to S-CLK_6) on the j-th stage output at a frequency of 1 Hz.

Thus, regardless of the moving image and the still image, the timing controller TC outputs the clock pulses C-CLK_1 to C-CLK_6 for the i-th phase at 60 Hz, CLK_1 to S-CLK_6 at the j-th phase in the section where the still image is driven, and outputs the scanning clock pulses S-CLK_1 to S-CLK_6 at the j- ) Is output at a frequency of 1 Hz, so that even when a moving image is partially present, low frequency driving is possible for each gate line.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

Claims (4)

A display panel having a plurality of gate lines and a plurality of data lines arranged to cross the gate lines;
A gate driver having a shift register to sequentially drive the plurality of gate lines;
Wherein a plurality of carry clock pulses and a plurality of scan clock pulses are supplied to the gate driver, and when a still image is partially present on the motion picture image, driving of the gate lines corresponding to the motion picture is performed for the plurality of carry And supplying clock pulses and a plurality of scanning clock pulses to a frequency for driving the moving image, and driving the gate lines corresponding to the still image to supply the plurality of carry clock pulses to a frequency for driving the moving image, And a timing controller for supplying a plurality of scanning clock pulses at a frequency lower than a frequency for driving the moving picture. The method according to claim 1,
The shift register includes a plurality of stages,
Each of the stages receives a carry pulse for one of the plurality of carry clock pulses according to a carry pulse or a start pulse output from the previous stage and a carry pulse output from the next stage, The pulse output section
A carry pulse for one of the plurality of scan clock pulses according to a carry pulse or a start pulse output from the preceding stage and a carry pulse output from the next stage and outputs a scan pulse to the gate line And a scan pulse output unit. The method according to claim 1,
The shift register includes a plurality of stages,
Wherein each of the stages includes a node controller for controlling a Q node and a QB node according to a carry pulse or a start pulse output from the front stage and a carry pulse output from the next stage,
A carry pulse output unit receiving a carry clock pulse of any one of the plurality of carry clock pulses and outputting a carry pulse according to a voltage of a Q node and a QB node of the node controller;
And a scan pulse output unit receiving a clock pulse for one of the plurality of scan clock pulses and outputting a scan pulse to the corresponding gate line according to a voltage of a Q node and a QB node of the node controller, / RTI > And a shift register included in a gate driver for sequentially driving a plurality of gate lines, wherein the shift register includes a plurality of stages, each of the stages including a carry pulse or a start pulse output from the front stage, A carry pulse output section for receiving a carry clock pulse of any one of a plurality of carry clock pulses according to a carry pulse output from the carry pulse output section and outputting a carry pulse, And a scan pulse output unit for receiving a clock pulse for one of a plurality of scan clock pulses according to a carry pulse output from the scan pulse output unit and outputting a scan pulse to the corresponding gate line,
And supplying the plurality of carry clock pulses and the plurality of scan clock pulses at a frequency for driving the moving image when the gate lines corresponding to the moving image partially exist in the moving image screen, Wherein the driving of the gate lines corresponding to the still image supplies the plurality of carry clock pulses at a frequency for driving the moving image and supplies the plurality of scanning clock pulses at a frequency lower than a frequency for driving the moving image And a driving method of the display device.

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