KR20080002570A - Driving circuit for liquid crystal display device and method for driving the same - Google Patents

Abstract

An apparatus for driving an LCD(Liquid Crystal Display) device and a driving method thereof are provided to improve the aperture ratio of pixel areas by driving divided gate lines using plural gate drivers. An apparatus for driving an LCD(Liquid Crystal Display) device includes a liquid crystal panel(20), data drivers(31,32), and first and second gate drivers(41,42). The liquid crystal panel includes plural first gate lines and plural second gate lines, which are separated from the first gate lines in parallel, and plural first and second data lines, which are crossed with the first and second gate lines. The data drivers drive the first and second data lines based on time division. The first and second gate drivers, formed at one and the other sides of the liquid crystal panel, drive the first and second gate lines, respectively.

Description

Driving device for liquid crystal display and driving method thereof {Driving circuit for liquid crystal display device and method for driving the same}

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of driving signals for explaining an operation of the liquid crystal display shown in FIG. 1.

＊ Explanation of symbols for main parts of drawing *

31, 32: first and second data driver

41, 42: first and second gate drivers

AGL1 to AGLn: A1 to An gate line

BGL1 to BGLn: B1 to Bn gate line

AP1 to APm: A1 pixel area to Am pixel area

BP1 to BPm: B1 pixel area to Bm pixel area

AGL1 Out: A1 Gate Line Output Signal

BGL1 Out: B1 Gate Line Output Signal

CLK1 to CLK4: first to fourth clock pulses

The present invention relates to a driving device of a liquid crystal display device and a driving method thereof which can increase the aperture ratio of a pixel area while reducing the number of data drivers.

Recently, in order to reduce the manufacturing cost of the liquid crystal display, a liquid crystal display capable of reducing the number of data drivers has been developed. The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and pixel regions are positioned in respective regions defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed. Each of the pixel electrodes is connected to a thin film transistor (TFT) which is a switching element.

Each TFT between two adjacent pixel regions is connected to one data line and sequentially supplied data signals, and turned on by scan pulses sequentially supplied from each of the two gate lines. That is, TFTs adjacent to each other are turned on by scan pulses from two gate lines, respectively, so that data signals from one data line are sequentially charged to the pixel electrode.

The driving circuit includes a gate driver for driving gate lines, a data driver for driving data lines, and a timing controller for supplying a gate control signal and a data control signal to control the gate driver and the data driver.

The data driver converts a digital image data signal into an analog image data signal according to a data control signal from a timing controller and supplies one horizontal line of image data signal to the data line every horizontal period in which a scan pulse is supplied to the gate line. .

The gate driver has a shift register for sequentially outputting scan pulses. The shift register is composed of a number of stages connected dependently to each other. The plurality of stages sequentially output scan pulses to sequentially scan the gate lines of the liquid crystal panel.

However, as described above, the liquid crystal display device capable of reducing the number of data drivers has a gate line twice the number of data lines of the liquid crystal panel. That is, since each data signal supplied to adjacent pixel areas is supplied through a single data line, the scan lines should be sequentially supplied to the adjacent pixel areas with double gate lines. As a result, the area occupied by the gate lines formed by twice the number increases, which causes a problem that the aperture ratio of each pixel region is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a driving device of a liquid crystal display device and a driving method thereof which can increase the aperture ratio of a pixel area while reducing the number of data drivers.

In order to achieve the above object, a driving apparatus of a liquid crystal display according to the present invention includes a plurality of first gate lines and a plurality of second gate lines and a plurality of second gate lines respectively separated in a horizontal direction from the plurality of first gate lines. A liquid crystal panel having an image display unit including a plurality of first and second data lines intersecting the first and second gate lines, a data driver for time-divisionally driving the plurality of first and second data lines, And a first gate driver provided at one side to drive the plurality of first gate lines, and a second gate driver provided at the other side of the liquid crystal panel to drive the plurality of second gate lines.

In addition, a method of driving a liquid crystal display according to the present invention for achieving the above object is a liquid crystal having an image display unit including a plurality of first and second data lines crossing the plurality of first and second gate lines. Driving a plurality of first gate lines, supplying image data to the plurality of first data lines that intersect the plurality of first gate lines, in one horizontal period of driving the panel; Driving the plurality of second gate lines horizontally separated from the first gate line of the plurality of second gate lines, and supplying image data to the plurality of second data lines crossing the plurality of second gate lines. And repeating the above steps every horizontal period.

Hereinafter, a driving apparatus and a driving method thereof of a liquid crystal display according to an exemplary embodiment of the present invention having the above characteristics will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

The liquid crystal display shown in FIG. 1 includes a liquid crystal panel 20 formed with a plurality of gate lines AGL1 to BGLn and a plurality of data lines ADL1 to BDLm on a TFT array substrate 10, and a plurality of data. The first and second circuit films 33 and 34 mounted with the first and second data drivers 31 and 32 for driving the lines ADL1 to BDLm, and the plurality of gate lines AGL1 to BGLn, First and second gate drivers 41 and 42 for driving.

The A1 to An gate lines AGL1 to AGLn are connected to the first gate driver 41 to receive scan pulses sequentially from the first gate driver 41. The B1 to Bn gate lines BGL1 to BGLn are connected to the second gate driver 42 to receive scan pulses sequentially from the second gate driver 42. That is, the A1 to An gate lines AGL1 to AGLn and the B1 to Bn gate lines BGL1 to BGLn are separated in the horizontal direction and connected to the first or second gate drivers 41 and 42, respectively.

The plurality of data lines ADL1 to BDLm are connected to the first or second data drivers 31 and 32 through the first or second circuit films 33 and 34, respectively.

In detail, each of the A1 to A3 data lines ADL1 to ADL3 receives image data from the first data driver 31 through the first circuit film 33. The B1 to B3 data lines BDL1 to BDL3 are branched from the A1 to A3 data lines ADL1 to ADL3, respectively, and receive image data from the A1 to A3 data lines ADL1 to ADL3.

Each of the Am-2 to Am data lines ADLm-2 to ADLm receives image data from the second data driver 32 through the second circuit film 34. The Bm-2 to Bm data lines (BDLm-2 to BDLm) are branched from the Am-2 to Am data lines (ADLm-2 to ADLm), respectively, and the image data from the Am-2 to Am data lines (ADLm-2 to ADLm). Get supplied.

The liquid crystal panel 20 includes TFTs and pixel electrodes formed in the plurality of pixel areas AP1 to nBPn defined by the plurality of gate lines AGL1 to BGLn and the plurality of data lines ADL1 to BDLm. The TFT supplies the data signals from the data lines ADL1 to BDLm to the pixel electrodes in response to the scan pulses from the gate lines AGL1 to BGLn.

The first and second data drivers 31 and 32 align and latch digital image data from the outside so as to be suitable for driving the respective data lines ADL1 to BDLm. The digital image data is converted into analog image data to supply analog image data of one horizontal line to the plurality of data lines ADL1 to BDLm every horizontal period in which scan pulses are supplied to the plurality of gate lines AGL1 to BGLn. do.

Specifically, the first data driver 31 has the A1 to A3 data lines ADL1 to ADL3 and B1 because the B1 to B3 data lines BDL1 to BDL3 are branched from the A1 to A3 data lines ADL1 to ADL3, respectively. To latch the digital image data to be supplied to the data lines BDL1 to BDL3. That is, image data to be displayed through the A1 data line ADL1, image data to be displayed through the B1 data line BDL1, image data to be displayed through the A2 data line ADL2, and display through the B2 data line BDL2. The image data to be displayed, the image data to be displayed through the A3 data line ADL3 and the image data to be displayed through the B3 data line BDL3 are aligned and latched.

Like the first data driver 31, the second data driver 32 also branches from the Am-2 to Am data lines ADLm-2 to Am and the Bm-2 to Bm data lines BDLm-2 to BDLm, respectively. Therefore, the digital image data to be supplied to the Am-2 to Am data lines ADLm-2 to Am and the Bm-2 to Bm data lines BDLm-2 to BDLm are aligned and latched. That is, image data to be displayed through the Am-2 data line ADLm-2, image data to be displayed through the Bm-2 data line BDLm-2, and to be displayed through the Am-1 data line ADLm-1. Align and latch image data, image data to be displayed through the Bm-1 data line BDLm-1, image data to be displayed through the Am data line ADLm, and image data to be displayed through the Bm data line BDLm. .

As described above, the first and second data drivers 31 and 32 allow two data lines to be driven through one data line output in one horizontal section, that is, the plurality of data lines ADL1 to BDLm are time-divisionally driven. The digital video data is sorted so that it can be converted into analog video data. The gamma voltage having a predetermined level is selected according to the grayscale value of the analog image data, and the selected gamma voltage is supplied to the data lines ADL1 to BDLm.

Here, the process of aligning the digital image data such that the ADL1 to ADLm data lines ADL1 to ADLm and the BDL1 to BDLm data lines BDL1 to BDLm can be time-divisionally driven is not illustrated, but the first and second data drivers are illustrated. It is made through at least one shift register and at least one latch portion embedded in (31, 32). That is, the at least one shift register and the at least one latch unit align the digital image data to be suitable for driving the plurality of data lines ADL1 to BDLm according to control signals from a timing controller (not shown) and at least one latch. Latch on the unit.

The first and second gate drivers 41 and 42 each include a shift register for sequentially outputting a plurality of scan pulses and cause the TFTs to be turned on in response to these scan pulses. Each shift register is integrated into and integrated in the TFT array substrate 10 forming the liquid crystal panel 20.

Specifically, although not shown in the drawing, the first gate driver 41 includes a shift register for sequentially outputting scan pulses. The shift register is composed of a number of stages connected dependently to each other. The plurality of stages sequentially output scan pulses to sequentially scan the A1 to An gate lines AGL1 to AGLn of the liquid crystal panel 20. Here, each of the plurality of stages receives at least one clock pulse among a plurality of clock pulses having a sequential phase difference from each other.

The second gate driver 42 also includes a shift register for sequentially outputting scan pulses. Similar to the first gate driver 41, the shift register of the second gate driver 42 includes a plurality of stages connected dependently to each other. The plurality of stages sequentially output scan pulses to sequentially scan the B1 to Bn gate lines BGL1 to BGLn of the liquid crystal panel 20.

Here, each of the stages of the second gate driver 42 receives at least one clock pulse among a plurality of clock pulses having a sequential phase difference from the clock pulses supplied to the stages of the first gate driver 41. .

FIG. 2 is a waveform diagram of driving signals for explaining an operation of the liquid crystal display shown in FIG. 1.

The start signal SP and the first to fourth clock pulses CLK1 to CLK4 shown in FIG. 2 are used to drive the first and second gate drivers 41 and 42. 42 is a gate drive signal supplied to each. Latch data represents data arranged to be suitable for time division driving of the plurality of data lines ADL1 to BDLm from the first and second data drivers 31 and 32, and the output data Out Data is the first data. And analog image data for one horizontal period output from the second data drivers 31 and 32. FIG. The timings of the scan pulses AGL1 Out to BGm Out supplied to the plurality of gate lines AGL1 to BGm from the first and second gate drivers 41 and 42, respectively, are shown.

A driving method of a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2 as follows.

The first and second data drivers 31 and 32 form latch data by aligning the digital image data to be suitable for driving the plurality of data lines ADL1 to BDLm according to a control signal from the timing controller. . That is, latching is performed so that 1A data and 1B data can be sequentially supplied to the A1 to Am data lines ADL1 to ADLm and the B1 to Bm data lines BDL1 to BDLm through the A1 to Am data lines ADL1 to ADLm. . Next, latching is performed so that 2A data and 2B data can be supplied to the A1 to Am data lines ADL1 to ADLm and the B1 to Bm data lines BDL1 to BDLm through the A1 to Am data lines ADL1 to ADLm. In this way, the 3A data and the 3B data, the 4A data and the 4B data, the 5A data and the 5B data are aligned and latched by one horizontal line so as to be sequentially supplied.

In this case, when the start signal SP is supplied from the timing controller so that the first and second gate drivers 41 and 42 are synchronized with the operations of the first and second data drivers 31 and 32, the plurality of gate lines AGL1 to the first and second gate drivers 41 and 42 are synchronized with each other. The scan pulse is sequentially supplied to BGLm).

In detail, the shift register of the first gate driver 41 sets the first clock pulse CLK1 to the first scan pulse AGL1 Out as the start signal SP is input as a trigger signal to the first stage. AGL1). The second stage receiving the first scan pulse AGL1 Out as the trigger signal supplies the third clock pulse CLK3 to the A2 gate line AGL2 as the second scan pulse AGL2 Out. As described above, the first gate driver 41 sequentially supplies scan pulses to the A1 to An gate lines AGL1 to AGLn using the first and third clock pulses CLK1 and CLK3 in a repeated operation process.

On the other hand, the shift register of the second gate driver 42 converts the second clock pulse CLK2 into the first scan pulse BGL1 Out as the start signal SP is input as a trigger signal to the first stage. Supplies). The second stage receiving the first scan pulse BGL1 Out as the trigger signal supplies the fourth clock pulse CLK4 to the A2 gate line AGL2 as the second scan pulse AGL2 Out. As described above, the second gate driver 42 sequentially supplies scan pulses to the B1 to Bn gate lines BGL1 to BGLn using the second and fourth clock pulses CLK2 and CLK4.

As described above, the first gate driver 41 and the second gate driver 42 sequentially scan the A1 to Bn gate lines AGL1 to BGLn by alternately outputting scan pulses as shown in FIG. 2. Scanning is done with.

Hereinafter, a process of displaying image data on the liquid crystal panel 20 in the liquid crystal display device driven as described above will be described in more detail.

 First, the first and second data drivers 31 and 32 supply one horizontal line of image data Out Data to the plurality of data lines ADL1 to BDLm according to a control signal from the timing controller. That is, one horizontal line of 1A data and 1B data are sequentially supplied to the A1 to Am data lines ADL1 to ADLm and the B1 to Bm data lines BDL1 to BDLm through the A1 to Am data lines ADL1 to ADLm. do.

At the same time, the first and second gate drivers 41 and 42 first respond to the start signal SP, and the first gate driver 41 first transmits the first clock pulse CLK1 to the A1 gate line AGL1. Outputs the scan pulse (AGL1 Out). Accordingly, the 1A data, which is first supplied through the A1 to Am data lines ADL1 to ADLm, is charged to the pixel electrode to which the A1 gate line AGL1 is connected to the pixel areas AP1 to APm to which the A1 gate line AGL1 is connected. Is displayed. The second gate driver 42 outputs the second clock pulse CLK2 to the B1 gate line BGL1 as the first scan pulse BGL1 Out. Accordingly, the 1B data supplied after the 1A data is charged in the pixel electrode connected to the B1 gate line BGL1 and displayed in the pixel areas BP1 to BPm connected to the B1 gate line BGL1, respectively.

Next, 2A data and 2B data for one horizontal line are sequentially arranged on the A1 to Am data lines ADL1 to ADLm and the B1 to Bm data lines BDL1 to BDLm through the A1 to Am data lines ADL1 to ADLm. Supplied.

At the same time, the first gate driver 41 outputs the third clock pulse CLK3 to the A2 gate line AGL2 as the second scan pulse AGL2 Out. Accordingly, the 2A data supplied first is charged in the pixel electrode to which the A2 gate line AGL2 is connected and displayed in the pixel area. The second gate driver 42 outputs the fourth clock pulse CLK4 to the B2 gate line BGL2 as the second scan pulse BGL1 Out. Therefore, the next supplied 2B data is charged in the pixel electrode connected to the B2 gate line BGL2 and displayed in the pixel region, respectively.

Next, 3A data and 3B data for one horizontal line are sequentially arranged on the A1 to Am data lines ADL1 to ADLm and the B1 to Bm data lines BDL1 to BDLm through the A1 to Am data lines ADL1 to ADLm. Supplied.

At the same time, the first gate driver 41 outputs the first clock pulse CLK1 to the A3 gate line AGL3 as the third scan pulse AGL3 Out. Accordingly, the 3A data is charged in the pixel electrode to which the A3 gate line AGL3 is connected and displayed in the pixel region to which the A3 gate line AGL3 is connected. The second gate driver 42 outputs the second clock pulse CLK2 to the B3 gate line BGL3 as the third scan pulse BGL3 Out. Accordingly, 3B data is charged in the pixel electrode connected to the B3 gate line BGL3 and displayed in the pixel region, respectively.

Next, 4A data and 4B data for one horizontal line are sequentially arranged on the A1 to Am data lines ADL1 to ADLm and the B1 to Bm data lines BDL1 to BDLm through the A1 to Am data lines ADL1 to ADLm. Supplied.

At the same time, the first gate driver 41 outputs the third clock pulse CLK3 to the A4 gate line AGL4 as a fourth scan pulse AGL4 Out. The 4A data is charged in the pixel electrode to which the A4 gate line AGL4 is connected and displayed in each pixel area. The second gate driver 42 outputs the fourth clock pulse CLK2 as the fourth scan pulse BGL4 Out to the B4 gate line BGL4. Accordingly, 4B data is charged in the pixel electrode connected to the B4 gate line BGL4 to be displayed in each pixel area.

The above-described process is repeated until all of the image data of one frame is displayed. In each frame, the first and second data drivers 31 and 32 align and latch the image data as described above and output them to the A1 to Am data lines ADL1 to ADlm. In addition, as the start signal SP is also supplied to the first and second gate drivers 41 and 42 at the start timing of every frame, an image is displayed on the liquid crystal panel 20 every frame by the above process.

In the liquid crystal display according to the exemplary embodiment of the present invention, the gate driver AGL1 to BGm is provided in each pixel area while the number of data drivers 31 and 32 can be reduced by half. Since it is connected, the aperture ratio of the pixel region can be increased.

In a conventional liquid crystal panel, regions in which data lines are formed are maintained at regular intervals in order to reduce interference between pixel regions. Accordingly, even if the number of data lines increases, the aperture ratio by the data lines does not decrease unless two data lines are formed between each pixel region.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the driving device of the liquid crystal display device and the driving method thereof according to the present invention have the following effects.

According to the present invention, at least one data driver drives each of the data lines branched from the plurality of data lines and divides the gate lines with the plurality of gate drivers. Accordingly, the aperture ratio of the pixel region can be increased while driving by cutting the number of data drivers in half.

Claims (11)

A plurality of first gate lines, a plurality of second gate lines horizontally separated from the plurality of first gate lines, and a plurality of first and second data lines crossing the plurality of first and second gate lines, respectively. A liquid crystal panel having an image display unit including; A data driver for time-divisionally driving the plurality of first and second data lines; A first gate driver provided at one side of the liquid crystal panel to drive the plurality of first gate lines; And And a second gate driver provided at the other side of the liquid crystal panel to drive the plurality of second gate lines. The method of claim 1, The first and second gate drivers And generating a plurality of scan pulses alternately with each other so that scan pulses are alternately supplied to the plurality of first gate lines and the plurality of second gate lines. The method of claim 2, The first and second gate drivers And sequentially supplying the plurality of scan pulses alternately generated to the plurality of first gate lines and the plurality of second gate lines. The method of claim 1, The plurality of second data lines And a plurality of branches from the plurality of first data lines. The method of claim 4, wherein The data driver The plurality of first data lines and the plurality of image data for one horizontal line supplied to the plurality of first data lines and the plurality of second data lines through the plurality of first data lines in one horizontal section. A drive device for a liquid crystal display device, characterized in that sequentially supplied to the second data line. The method of claim 5, The image data supplied first among the image data corresponding to one horizontal line sequentially supplied through the plurality of first data lines is displayed on the plurality of pixel regions connected to the plurality of first gate lines and the plurality of first data lines. A drive device for a liquid crystal display device, characterized in that. The method of claim 6, The image data supplied later among the image data of one horizontal line sequentially supplied through the plurality of first data lines is displayed on the plurality of pixel regions connected to the plurality of second gate lines and the plurality of second data lines. A drive device for a liquid crystal display device, characterized in that. In one horizontal period of driving a liquid crystal panel having an image display section including a plurality of first and second data lines intersecting a plurality of first and second gate lines, Driving the plurality of first gate lines; Supplying image data to the plurality of first data lines that intersect the plurality of first gate lines; Driving the plurality of second gate lines horizontally separated from the plurality of first gate lines; And Supplying image data to the plurality of second data lines that intersect the plurality of second gate lines; And repeating the above steps every horizontal period. The method of claim 8, Driving the plurality of first and second gate lines Generating a plurality of scan pulses alternately with each other; And alternately supplying scan pulses to the plurality of first gate lines and the plurality of second gate lines. The method of claim 9, The step of supplying the scan pulse alternately with each other And sequentially supplying the plurality of scan pulses alternately generated to the plurality of first gate lines and the plurality of second gate lines. The method of claim 8, The driving of the plurality of first and second data lines may include: The plurality of first data lines and the plurality of image data for one horizontal line supplied to the plurality of first data lines and the plurality of second data lines through the plurality of first data lines in one horizontal section. And a second data line is sequentially supplied to the second data line.

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