JP2005165038A - Liquid crystal display device and its driving method, and gate driver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a gate signal width variable according to the source potential to be written in order to assure a panel charging time. <P>SOLUTION: The liquid crystal display device 1 is provided with TFTs of respective pixels in compliance with a prescribed TFT arrangement pattern in such a manner the inversion driving of every vertical two dots can be performed. A scanning line driving circuit applies a gate signal longer in the gate pulse width Tp when the drain signal of a positive polarity is applied by a signal line driving circuit than the gate pulse width Tn when the drain signal of a negative polarity is applied. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a liquid crystal display device, and more particularly to an active matrix liquid crystal display device using amorphous silicon, a driving method thereof, and a gate driver.

  Conventionally, as a driving method of an active matrix liquid crystal display device using amorphous silicon (a-Si), in order to reduce flicker, driving for inverting the polarity of a drain signal for each gate line, that is, line inversion driving is used. Has been done.

  However, in line inversion driving, since the driving capability of amorphous silicon TFTs (thin film transistors) is low, if the field effect mobility is reduced due to process variations or the like, even the display of about 480 lines becomes difficult to drive.

  The main cause is that the drain signal at the time of positive polarity is not sufficiently applied to the liquid crystal terminal portion via the amorphous silicon TFT. This is because the on-resistance of the TFT gradually increases because the gate-source potential VGS in the device operation of the TFT decreases as the potential of the liquid crystal terminal increases when the drain signal is positive. On the other hand, when the drain signal is negative, VGS is constant regardless of the decrease in the potential of the liquid crystal terminal portion, so the on-resistance of the TFT is sufficiently low. Therefore, when the drain signal is negative, the drain signal is applied to the liquid crystal terminal portion at a relatively high speed.

  For the purpose of solving this problem, Patent Document 1 discloses a pixel TFT provided so as to correspond to each pixel arranged in the matrix direction and a gate electrode of the TFT commonly connected for each row. Electrode, signal electrode for commonly connecting the drain of the TFT for each column, display electrode for each pixel connected to the source of the TFT, scanning side driving circuit for controlling output of a driving signal to the scanning electrode, to signal electrode In the signal side driving circuit for controlling the driving signal output and the liquid crystal display device having the inversion driving for each row, the gate pulse width when the positive drain signal is applied is the same as that when the negative drain signal is applied. A liquid crystal display device longer than the gate pulse width has been proposed. FIG. 19 is a timing chart of gate signals by line inversion driving in the liquid crystal display device.

  According to the driving method of the liquid crystal display device, when the drain signal is positive, the gate pulse width is longer than the gate pulse width when the drain signal is negative. Therefore, although the driving capability of the amorphous silicon TFT is low at the positive polarity, the gate pulse width is long, so that the drain signal is sufficiently applied to the liquid crystal terminal portion. Therefore, it is said that a liquid crystal display device with excellent display quality can be provided even if the field effect mobility of the TFT is reduced due to process variations or the like.

  In addition, when driving a conventional active matrix liquid crystal display device, (1) the frame inversion method covers the entire screen, (2) the gate / line inversion method is in the scanning line direction, and (3) the drain / line inversion method. However, there is a problem that flickers of the frame frequency are conspicuous in the signal line direction.

  In order to solve this problem, Patent Document 2 discloses a liquid crystal display device in which a pixel electrode 101 and a TFT 102 are provided in a region partitioned by scanning electrodes X1 to Xn and signal electrodes Y1 to Ym, respectively. Proposed. In this liquid crystal display device, the gate of the TFT is connected to the scanning electrode and the source / drain is connected to the signal electrode. However, in the TFT arranged in the region sandwiched between the two scanning electrodes, the gate is The scan electrodes are alternately connected to different scanning electrodes. FIG. 20 is a plan view showing an electrode structure of the liquid crystal display device.

According to the above liquid crystal display device, the polarity of the voltage applied to the signal electrodes Y1 to Ym is reversed every time the selection of the scanning electrode is changed (so-called gate / line inversion method), and the polarity for each dot of the screen Is applied (dot inversion method), and flicker appearing at the frame frequency is suppressed. FIG. 21 is an explanatory diagram showing a state in which positive and negative voltages that are inverted for each dot are applied when the liquid crystal display device is driven by the gate-line inversion method.
JP-A-4-322216 (publication date: November 12, 1992) JP-A-4-223428 (Publication date: August 13, 1992)

  In a liquid crystal panel having a conventional structure, when the TFT is an n-channel transistor having an inverted stagger structure, the charging capability varies as follows depending on whether the polarity of writing is positive or negative. (a) When writing plus, the signal becomes the drain and the source is charged. Therefore, the gate-source voltage VGS is reduced, and the current supply capability is reduced. In contrast, when (b) minus is written, the signal becomes the source, and the signal source is a low impedance source driver, so the source potential does not fluctuate. Therefore, the current supply capability does not change.

  On the other hand, liquid crystal panels have recently been increasing in size and definition. However, when the liquid crystal panel is increased in size and definition with the conventional structure, particularly in the case of a liquid crystal panel using amorphous silicon, there is a problem that the charging time cannot be secured. Specifically, in a large-sized and high-definition liquid crystal panel, pixels are dense, so that the writing time per pixel is shortened. That is, the charging time that can be applied to one transistor has been shortened. As a result, although it is necessary to charge in a short time, as described above, the current supply capability is reduced when writing plus, so that the charging time is insufficient. Note that in order not to reduce the aperture ratio of the panel, the transistor must be made small, but when it becomes small, the driving force is lowered.

  Further, the dot inversion method described in Patent Document 2 has a killer pattern in which display is disturbed.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a liquid crystal display device capable of changing the gate signal width in accordance with the source potential to be written in order to ensure the panel charging time. Another object of the present invention is to provide a gate driver.

In order to solve the above problems, a liquid crystal display device according to the present invention includes a TFT provided so as to correspond to each pixel arranged in a matrix direction, a scanning line commonly connecting the gates of the TFT, and a drain of the TFT. A signal line for commonly connecting, a pixel electrode of each pixel connected to the source of the TFT, a scanning line driving circuit for controlling a gate signal to the scanning line, and a signal line driving circuit for controlling a drain signal to the signal line A liquid crystal display device having TFTs in the effective display area so as to repeat a predetermined TFT arrangement pattern;
The TFT arrangement pattern is such that the gates of the TFTs provided in the pixels Cx, y in the x rows and y columns of the effective display area are the p th scanning line of the effective display area, and the drain is the q th signal line of the effective display area. When noting that Ci, j = (p, q) is connected,
Ci, j = (i + 1, j), Ci, j + 1 = (i, j + 1),
Ci, j + 2 = (i + 1, j + 2), Ci, j + 3 = (i, j + 3),
Ci + 1, j = (i + 1, j + 1), Ci + 1, j + 1 = (i + 2, j + 1),
Ci + 1, j + 2 = (i + 1, j + 3), Ci + 1, j + 3 = (i + 2, j + 3),
Ci + 2, j = (i + 2, j), Ci + 2, j + 1 = (i + 3, j + 1),
Ci + 2, j + 2 = (i + 2, j + 2), Ci + 2, j + 3 = (i + 3, j + 3),
Ci + 3, j = (i + 4, j), Ci + 3, j + 1 = (i + 3, j + 2),
Ci + 3, j + 2 = (i + 4, j + 2), Ci + 3, j + 3 = (i + 3, j + 4)
Pattern of
The signal line driving circuit includes pixels Ci, j, Ci, j + 2, Ci + 1, j, Ci + 1, j + 2, which constitute the first pixel group.
Ci + 2, j + 1, Ci + 2, j + 3, Ci + 3, j + 1, Ci + 3, j + 3
Pixels Ci, j + 1, Ci, j + 3, Ci + 1, j + 1, Ci + 1, j + 3 constituting the second pixel group
Ci + 2, j, Ci + 2, j + 2, Ci + 3, j, Ci + 3, j + 2
Are driven by inversion by applying drain signals having opposite polarities to each other.

  According to the TFT arrangement pattern, the TFT arrangement as shown in FIG. 1 is obtained. Specifically, the pixels Ci, j to Ci + 3, j + 3 correspond to 16 pixels in which the display data D1,2 to D4,5 of FIG. 1 are written. Then, by applying drain signals having opposite polarities to the first pixel group and the second pixel group, inversion driving using a set of two vertical dots as shown in FIG. 1 is possible.

  Therefore, it is possible to accurately display a so-called killer pattern in which display is disturbed by inversion driving for each line or inversion driving for each dot. Therefore, a liquid crystal display device with better display quality can be realized.

  Here, in the liquid crystal panel in which the TFTs are arranged according to the TFT arrangement pattern, the polarity of the drain signal of the pixel to which one scanning line applies the gate signal is unified to either positive polarity or negative polarity. That is, the TFT arrangement pattern arranges the TFTs so that one scanning line can supply a gate signal having one kind of gate pulse width corresponding to the polarity of the drain signal to all the pixels in one scan. To do. Therefore, as described later, the liquid crystal display device makes the gate pulse width Tp when the positive drain signal is applied different from the gate pulse width Tn when the negative drain signal is applied. Thus, a gate signal can be applied.

In the liquid crystal display device according to the present invention, the TFT arrangement pattern is
Ci, j = (i, j), Ci, j + 1 = (i + 1, j + 1),
Ci, j + 2 = (i, j + 2), Ci, j + 3 = (i + 1, j + 3),
Ci + 1, j = (i + 2, j), Ci + 1, j + 1 = (i + 1, j + 2),
Ci + 1, j + 2 = (i + 2, j + 2), Ci + 1, j + 3 = (i + 1, j + 4),
Ci + 2, j = (i + 3, j), Ci + 2, j + 1 = (i + 2, j + 1),
Ci + 2, j + 2 = (i + 3, j + 2), Ci + 2, j + 3 = (i + 2, j + 3),
Ci + 3, j = (i + 3, j + 1), Ci + 3, j + 1 = (i + 4, j + 1),
Ci + 3, j + 2 = (i + 3, j + 3), Ci + 3, j + 3 = (i + 4, j + 3)
This pattern may be used.

In the liquid crystal display device according to the present invention, the TFT arrangement pattern is
Ci, j = (i + 1, j + 1), Ci, j + 1 = (i, j + 1),
Ci, j + 2 = (i + 1, j + 3), Ci, j + 3 = (i, j + 3),
Ci + 1, j = (i + 1, j), Ci + 1, j + 1 = (i + 2, j + 1),
Ci + 1, j + 2 = (i + 1, j + 2), Ci + 1, j + 3 = (i + 2, j + 3),
Ci + 2, j = (i + 2, j), Ci + 2, j + 1 = (i + 3, j + 2),
Ci + 2, j + 2 = (i + 2, j + 2), Ci + 2, j + 3 = (i + 3, j + 4),
Ci + 3, j = (i + 4, j), Ci + 3, j + 1 = (i + 3, j + 1),
Ci + 3, j + 2 = (i + 4, j + 2), Ci + 3, j + 3 = (i + 3, j + 3)
This pattern may be used.

In the liquid crystal display device according to the present invention, the TFT arrangement pattern is
Ci, j = (i, j), Ci, j + 1 = (i, j + 2),
Ci, j + 2 = (i, j + 2), Ci, j + 3 = (i + 1, j + 4),
Ci + 1, j = (i + 2, j), Ci + 1, j + 1 = (i + 1, j + 1),
Ci + 1, j + 2 = (i + 2, j + 2), Ci + 1, j + 3 = (i + 1, j + 3),
Ci + 2, j = (i + 3, j + 1), Ci + 2, j + 1 = (i + 2, j + 1),
Ci + 2, j + 2 = (i + 3, j + 3), Ci + 2, j + 3 = (i + 2, j + 3),
Ci + 3, j = (i + 3, j), Ci + 3, j + 1 = (i + 4, j + 1),
Ci + 3, j + 2 = (i + 3, j + 2), Ci + 3, j + 3 = (i + 4, j + 3)
This pattern may be used.

  Furthermore, the liquid crystal display device according to the present invention may have the same TFT arrangement pattern for the pixels in the first row and the pixels in the second row. Further, in the liquid crystal display device according to the present invention, the arrangement pattern of the TFTs in the first row pixels and the second row pixels may be different.

  Furthermore, in the liquid crystal display device according to the present invention, the scanning line driving circuit has a gate pulse width Tp when a positive drain signal is applied by the signal line driving circuit and a negative drain signal is applied. A gate signal longer than the gate pulse width Tn is applied.

  As a result, the gate pulse width Tp can be increased when a positive drain signal is applied, and the gate pulse width Tn when a negative drain signal is applied. Therefore, when a positive drain signal is applied, it is possible to secure a long gate pulse width Tp so as to compensate for the shortage of charging due to a decrease in current supply capability. Therefore, the panel charging time can be secured by changing the gate signal width according to the source potential to be written. Therefore, in a large and high-definition liquid crystal panel, even if the pixels are dense and the charging time that can be applied to one transistor is shortened, insufficient charging can be prevented.

  Furthermore, the liquid crystal display device according to the present invention is characterized in that the gate pulse width is set to satisfy Tp + Tn ≦ 2H when one horizontal scanning period is H.

  Accordingly, the gate pulse width in the unit of 2H is interchanged from the gate pulse width when the negative polarity drain signal having a sufficient charge time is applied to the gate pulse width when the positive polarity drain signal is applied. Tp and Tn can be optimized.

  In addition, after securing both charging times, when Tp + Tn <2H, a time during which no gate signal is applied may be provided. Conversely, when Tp + Tn> 2H, the gate pulse width Tn when applying a negative drain signal may be shortened so that Tp + Tn = 2H.

  Furthermore, the liquid crystal display device according to the present invention distributes display data for each pixel into data written by a positive drain signal and data written by a negative drain signal, and supplies the data to the signal line driver circuit. The scanning line sequential conversion means is provided.

  Thereby, as shown in FIG. 1, inversion driving with a set of two vertical dots is possible. Note that the scanning line sequential conversion means can be realized by two FIFO memories and frame memories respectively corresponding to the first pixel group and the second pixel group.

  The liquid crystal display device according to the present invention is a liquid crystal display device in which TFTs are provided so as to correspond to the respective pixels arranged in the matrix direction, and are connected to the gates of the TFTs of the pixels and have different polarities. A first scan line and a second scan line for driving the pixels, wherein the first scan line is connected to TFTs of two adjacent pixels in the same pixel column, and the second scan A line is connected to TFTs of two pixels located at one diagonal for every four pixels in 2 rows and 2 columns.

  If TFTs are arranged in this way, the above TFT arrangement pattern can be repeated. That is, the TFT is arranged as shown in FIG. Then, by applying drain signals having opposite polarities to the first pixel group and the second pixel group, inversion driving using a set of two vertical dots as shown in FIG. 1 is possible.

  Therefore, it is possible to accurately display a so-called killer pattern in which display is disturbed by inversion driving for each line or inversion driving for each dot. Therefore, a liquid crystal display device with better display quality can be realized.

  Furthermore, the liquid crystal display device according to the present invention is a scanning line drive that applies a gate signal whose gate pulse width when a positive drain signal is applied is longer than the gate pulse width when a negative drain signal is applied. It is characterized by comprising a circuit.

  This further increases the gate pulse width Tp when applying a positive drain signal and shortens the gate pulse width Tn when applying a negative drain signal. Therefore, when a positive drain signal is applied, it is possible to secure a long gate pulse width Tp so as to compensate for the shortage of charging due to a decrease in current supply capability. Therefore, the panel charging time can be secured by changing the gate signal width according to the source potential to be written. Therefore, in a large and high-definition liquid crystal panel, even if the pixels are dense and the charging time that can be applied to one transistor is shortened, insufficient charging can be prevented.

  Furthermore, the liquid crystal display device according to the present invention is characterized in that the pixels in the effective display area are driven to be inverted every two pixels in the column direction and every pixel in the row direction.

  As a result, it is possible to perform dot inversion driving by shifting by one pixel, every two pixels in the column direction, and every one pixel in the row direction.

  Furthermore, in the liquid crystal display device according to the present invention, when the effective display area is m columns and n rows, the number of source signal lines for driving the pixels may be m + 1. In the liquid crystal display device according to the present invention, when the effective display area is m columns and n rows, the number of source signal lines for driving the pixels may be m.

  Furthermore, in the liquid crystal display device according to the present invention, when the effective display area is m columns and n rows, the number of source drivers for driving the pixels may be m + 1. In the liquid crystal display device according to the present invention, when the effective display area is m columns and n rows, the number of source drivers that drive the pixels may be m.

  The gate driver according to the present invention is a gate driver of a liquid crystal display device, and includes a shift register and a plurality of output circuits, and each of the output circuits inputs a gate output enable signal for controlling an output. Therefore, it is characterized in that it is connected to one of the first gate output enable signal line and the second gate output enable signal line.

  As a result, the output of the gate driver that drives the odd-numbered scanning lines is controlled by the first gate output enable signal, and the output of the gate driver that drives the even-numbered scanning lines by the second gate output enable signal. Can be controlled. Specifically, when the gate output enable signal is in a high state, the output of the gate driver may be passed, and when it is in a low state, the output of the gate driver may be turned off. In this way, by providing a plurality of gate output enable signals, the gate pulse can be easily changed between two gate pulses without complicating the configuration of the shift register (without increasing the number of stages). Since pause periods (t5, t6 (see FIG. 18)) can be provided, display data can be accurately written to the pixels.

  The gate driver according to the present invention is a gate driver of a liquid crystal display device, and includes a first gate line driving pulse and a second gate line driving pulse having different pulse widths as the first gate line driving pulse and the first gate line driving pulse. The two gate line driving pulses become a high level voltage which is a gate line driving signal once during two horizontal scanning periods, and the first gate line driving pulse and the second gate line driving pulse It is characterized in that it is output to the scanning line so as to generate a period during which no gate line is driven.

  This makes it possible to easily provide a pause period (t5, t6 (see FIG. 18)) between the two gate pulses, so that display data can be accurately written to the pixels. .

  In addition, a liquid crystal display device according to the present invention includes the above gate driver.

  Thereby, in order to secure the panel charging time, the gate signal width can be changed according to the source potential to be written. Therefore, a liquid crystal display device with better display quality can be realized.

Further, the driving method of the liquid crystal display device according to the present invention includes a TFT provided so as to correspond to each pixel arranged in the matrix direction, a scanning line commonly connecting the TFT gates, and a common drain connecting the TFT drains. A signal line, a pixel electrode of each pixel connected to the source of the TFT, a scanning line driving circuit for controlling a gate signal to the scanning line, a signal line driving circuit for controlling a drain signal to the signal line, In the effective display area, TFTs are provided to repeat a predetermined TFT arrangement pattern,
The TFT arrangement pattern is such that the gates of the TFTs provided in the pixels Cx, y in the x rows and y columns of the effective display area are the p th scanning line of the effective display area, and the drain is the q th signal line of the effective display area. When noting that Ci, j = (p, q) is connected,
Ci, j = (i + 1, j), Ci, j + 1 = (i, j + 1),
Ci, j + 2 = (i + 1, j + 2), Ci, j + 3 = (i, j + 3),
Ci + 1, j = (i + 1, j + 1), Ci + 1, j + 1 = (i + 2, j + 1),
Ci + 1, j + 2 = (i + 1, j + 3), Ci + 1, j + 3 = (i + 2, j + 3),
Ci + 2, j = (i + 2, j), Ci + 2, j + 1 = (i + 3, j + 1),
Ci + 2, j + 2 = (i + 2, j + 2), Ci + 2, j + 3 = (i + 3, j + 3),
Ci + 3, j = (i + 4, j), Ci + 3, j + 1 = (i + 3, j + 2),
Ci + 3, j + 2 = (i + 4, j + 2), Ci + 3, j + 3 = (i + 3, j + 4)
A method for driving a liquid crystal display device having a pattern of
The signal line driving circuit includes pixels Ci, j, Ci, j + 2, Ci + 1, j, Ci + 1, j + 2 constituting the first pixel group,
Ci + 2, j + 1, Ci + 2, j + 3, Ci + 3, j + 1, Ci + 3, j + 3
Pixels Ci, j + 1, Ci, j + 3, Ci + 1, j + 1, Ci + 1, j + 3 constituting the second pixel group
Ci + 2, j, Ci + 2, j + 2, Ci + 3, j, Ci + 3, j + 2
Are inverted and driven by applying drain signals having opposite polarities to each other.

  According to the TFT arrangement pattern, the TFT arrangement as shown in FIG. 1 is obtained. Specifically, the pixels Ci, j to Ci + 3, j + 3 correspond to 16 pixels in which the display data D1,2 to D4,5 of FIG. 1 are written. Then, by applying drain signals having opposite polarities to the first pixel group and the second pixel group, inversion driving using a set of two vertical dots as shown in FIG. 1 is possible.

  Therefore, it is possible to accurately display a so-called killer pattern in which display is disturbed by inversion driving for each line or inversion driving for each dot. Therefore, a liquid crystal display device with better display quality can be realized.

  Here, in the liquid crystal panel in which the TFTs are arranged according to the TFT arrangement pattern, the polarity of the drain signal of the pixel to which one scanning line applies the gate signal is unified to either positive polarity or negative polarity. That is, the TFT arrangement pattern arranges the TFTs so that one scanning line can supply a gate signal having one kind of gate pulse width corresponding to the polarity of the drain signal to all the pixels in one scan. To do. Therefore, the liquid crystal display device differs in the gate pulse width Tp when a positive drain signal is applied and the gate pulse width Tn when a negative drain signal is applied, It becomes possible to apply.

Further, in the driving method of the liquid crystal display device according to the present invention, the TFT arrangement pattern is
Ci, j = (i, j), Ci, j + 1 = (i + 1, j + 1),
Ci, j + 2 = (i, j + 2), Ci, j + 3 = (i + 1, j + 3),
Ci + 1, j = (i + 2, j), Ci + 1, j + 1 = (i + 1, j + 2),
Ci + 1, j + 2 = (i + 2, j + 2), Ci + 1, j + 3 = (i + 1, j + 4),
Ci + 2, j = (i + 3, j), Ci + 2, j + 1 = (i + 2, j + 1),
Ci + 2, j + 2 = (i + 3, j + 2), Ci + 2, j + 3 = (i + 2, j + 3),
Ci + 3, j = (i + 3, j + 1), Ci + 3, j + 1 = (i + 4, j + 1),
Ci + 3, j + 2 = (i + 3, j + 3), Ci + 3, j + 3 = (i + 4, j + 3)
This pattern may be used.

Further, in the driving method of the liquid crystal display device according to the present invention, the TFT arrangement pattern is
Ci, j = (i + 1, j + 1), Ci, j + 1 = (i, j + 1),
Ci, j + 2 = (i + 1, j + 3), Ci, j + 3 = (i, j + 3),
Ci + 1, j = (i + 1, j), Ci + 1, j + 1 = (i + 2, j + 1),
Ci + 1, j + 2 = (i + 1, j + 2), Ci + 1, j + 3 = (i + 2, j + 3),
Ci + 2, j = (i + 2, j), Ci + 2, j + 1 = (i + 3, j + 2),
Ci + 2, j + 2 = (i + 2, j + 2), Ci + 2, j + 3 = (i + 3, j + 4),
Ci + 3, j = (i + 4, j), Ci + 3, j + 1 = (i + 3, j + 1),
Ci + 3, j + 2 = (i + 4, j + 2), Ci + 3, j + 3 = (i + 3, j + 3)
This pattern may be used.

Further, in the driving method of the liquid crystal display device according to the present invention, the TFT arrangement pattern is
Ci, j = (i, j), Ci, j + 1 = (i, j + 2),
Ci, j + 2 = (i, j + 2), Ci, j + 3 = (i + 1, j + 4),
Ci + 1, j = (i + 2, j), Ci + 1, j + 1 = (i + 1, j + 1),
Ci + 1, j + 2 = (i + 2, j + 2), Ci + 1, j + 3 = (i + 1, j + 3),
Ci + 2, j = (i + 3, j + 1), Ci + 2, j + 1 = (i + 2, j + 1),
Ci + 2, j + 2 = (i + 3, j + 3), Ci + 2, j + 3 = (i + 2, j + 3),
Ci + 3, j = (i + 3, j), Ci + 3, j + 1 = (i + 4, j + 1),
Ci + 3, j + 2 = (i + 3, j + 2), Ci + 3, j + 3 = (i + 4, j + 3)
This pattern may be used.

  Further, in the driving method of the liquid crystal display device according to the present invention, the scanning line driving circuit applies a drain signal whose gate pulse width Tp is negative when a positive drain signal is applied by the signal line driving circuit. A gate signal longer than the gate pulse width Tn when applied is applied.

  This further increases the gate pulse width Tp when applying a positive drain signal and shortens the gate pulse width Tn when applying a negative drain signal. Therefore, when a positive drain signal is applied, it is possible to secure a long gate pulse width Tp so as to compensate for the shortage of charging due to a decrease in current supply capability. Therefore, the panel charging time can be secured by changing the gate signal width according to the source potential to be written. Therefore, in a large and high-definition liquid crystal panel, even if the pixels are dense and the charging time that can be applied to one transistor is shortened, insufficient charging can be prevented.

  Furthermore, the driving method of the liquid crystal display device according to the present invention is characterized in that the gate pulse width is set to satisfy Tp + Tn ≦ 2H when one horizontal scanning period is H.

  As a result, the gate pulse width when applying a negative polarity drain signal with sufficient charge time to the gate pulse width when applying a positive polarity drain signal can be used to gate in 2H units. The pulse widths Tp and Tn can be optimized.

  In addition, after securing both charging times, when Tp + Tn <2H, a time during which no gate signal is applied may be provided. Conversely, when Tp + Tn> 2H, the gate pulse width Tn when applying a negative drain signal may be shortened so that Tp + Tn = 2H.

  In the liquid crystal display device driving method according to the present invention, the pixels in the first row of the effective display area are driven by dot inversion, and the pixels in the second and subsequent rows are driven every two pixels in the column direction and every pixel in the row direction. In addition, the gate signal is inverted and driven with a polarity different from that of the first row, and the gate pulse width when the positive drain signal is applied is longer than the gate pulse width when the negative drain signal is applied. Is applied to the pixel.

  This makes it possible to accurately display a so-called killer pattern in which display is disturbed by inversion driving for each line or inversion driving for each dot. Therefore, a liquid crystal display device with better display quality can be realized.

  Further, the gate pulse width Tp can be increased when a positive drain signal is applied, and the gate pulse width Tn when a negative drain signal is applied. Therefore, when a positive drain signal is applied, it is possible to secure a long gate pulse width Tp so as to compensate for the shortage of charging due to a decrease in current supply capability. Therefore, the panel charging time can be secured by changing the gate signal width according to the source potential to be written. Therefore, in a large and high-definition liquid crystal panel, even if the pixels are dense and the charging time that can be applied to one transistor is shortened, insufficient charging can be prevented.

As described above, in the liquid crystal display device according to the present invention, TFTs are provided so as to repeat a predetermined TFT arrangement pattern in the effective display area, and the TFT arrangement pattern includes pixels in x rows and y columns in the effective display area. Ci, j = (p, q) that the gate of the TFT provided in Cx, y is connected to the pth scanning line in the effective display region and the drain is connected to the qth signal line in the effective display region. When writing,
Ci, j = (i + 1, j), Ci, j + 1 = (i, j + 1),
Ci, j + 2 = (i + 1, j + 2), Ci, j + 3 = (i, j + 3),
Ci + 1, j = (i + 1, j + 1), Ci + 1, j + 1 = (i + 2, j + 1),
Ci + 1, j + 2 = (i + 1, j + 3), Ci + 1, j + 3 = (i + 2, j + 3),
Ci + 2, j = (i + 2, j), Ci + 2, j + 1 = (i + 3, j + 1),
Ci + 2, j + 2 = (i + 2, j + 2), Ci + 2, j + 3 = (i + 3, j + 3),
Ci + 3, j = (i + 4, j), Ci + 3, j + 1 = (i + 3, j + 2),
Ci + 3, j + 2 = (i + 4, j + 2), Ci + 3, j + 3 = (i + 3, j + 4)
Pattern of
The signal line driving circuit includes pixels Ci, j, Ci, j + 2, Ci + 1, j, Ci + 1, j + 2, which constitute the first pixel group.
Ci + 2, j + 1, Ci + 2, j + 3, Ci + 3, j + 1, Ci + 3, j + 3
Pixels Ci, j + 1, Ci, j + 3, Ci + 1, j + 1, Ci + 1, j + 3 constituting the second pixel group
Ci + 2, j, Ci + 2, j + 2, Ci + 3, j, Ci + 3, j + 2
Are inverted by applying drain signals having opposite polarities to each other.

  According to the TFT arrangement pattern, the TFT arrangement as shown in FIG. 1 is obtained. Specifically, the pixels Ci, j to Ci + 3, j + 3 correspond to 16 pixels in which the display data D1,2 to D4,5 of FIG. 1 are written. Then, by applying drain signals having opposite polarities to the first pixel group and the second pixel group, inversion driving using a set of two vertical dots as shown in FIG. 1 is possible.

  Therefore, it is possible to accurately display a so-called killer pattern in which display is disturbed by inversion driving for each line or inversion driving for each dot. Therefore, the liquid crystal display device with better display quality can be realized.

  Here, in the liquid crystal panel in which the TFTs are arranged according to the TFT arrangement pattern, the polarity of the drain signal of the pixel to which one scanning line applies the gate signal is unified to either positive polarity or negative polarity. That is, the TFT arrangement pattern arranges the TFTs so that one scanning line can supply a gate signal having one kind of gate pulse width corresponding to the polarity of the drain signal to all the pixels in one scan. To do. Therefore, the liquid crystal display device differs in the gate pulse width Tp when a positive drain signal is applied and the gate pulse width Tn when a negative drain signal is applied, It becomes possible to apply.

In the liquid crystal display device according to the present invention, the TFT arrangement pattern is
Ci, j = (i, j), Ci, j + 1 = (i + 1, j + 1),
Ci, j + 2 = (i, j + 2), Ci, j + 3 = (i + 1, j + 3),
Ci + 1, j = (i + 2, j), Ci + 1, j + 1 = (i + 1, j + 2),
Ci + 1, j + 2 = (i + 2, j + 2), Ci + 1, j + 3 = (i + 1, j + 4),
Ci + 2, j = (i + 3, j), Ci + 2, j + 1 = (i + 2, j + 1),
Ci + 2, j + 2 = (i + 3, j + 2), Ci + 2, j + 3 = (i + 2, j + 3),
Ci + 3, j = (i + 3, j + 1), Ci + 3, j + 1 = (i + 4, j + 1),
Ci + 3, j + 2 = (i + 3, j + 3), Ci + 3, j + 3 = (i + 4, j + 3)
Even with this pattern, the same effects as described above are obtained.

In the liquid crystal display device according to the present invention, the TFT arrangement pattern is
Ci, j = (i + 1, j + 1), Ci, j + 1 = (i, j + 1),
Ci, j + 2 = (i + 1, j + 3), Ci, j + 3 = (i, j + 3),
Ci + 1, j = (i + 1, j), Ci + 1, j + 1 = (i + 2, j + 1),
Ci + 1, j + 2 = (i + 1, j + 2), Ci + 1, j + 3 = (i + 2, j + 3),
Ci + 2, j = (i + 2, j), Ci + 2, j + 1 = (i + 3, j + 2),
Ci + 2, j + 2 = (i + 2, j + 2), Ci + 2, j + 3 = (i + 3, j + 4),
Ci + 3, j = (i + 4, j), Ci + 3, j + 1 = (i + 3, j + 1),
Ci + 3, j + 2 = (i + 4, j + 2), Ci + 3, j + 3 = (i + 3, j + 3)
Even with this pattern, the same effects as described above are obtained.

In the liquid crystal display device according to the present invention, the TFT arrangement pattern is
Ci, j = (i, j), Ci, j + 1 = (i, j + 2),
Ci, j + 2 = (i, j + 2), Ci, j + 3 = (i + 1, j + 4),
Ci + 1, j = (i + 2, j), Ci + 1, j + 1 = (i + 1, j + 1),
Ci + 1, j + 2 = (i + 2, j + 2), Ci + 1, j + 3 = (i + 1, j + 3),
Ci + 2, j = (i + 3, j + 1), Ci + 2, j + 1 = (i + 2, j + 1),
Ci + 2, j + 2 = (i + 3, j + 3), Ci + 2, j + 3 = (i + 2, j + 3),
Ci + 3, j = (i + 3, j), Ci + 3, j + 1 = (i + 4, j + 1),
Ci + 3, j + 2 = (i + 3, j + 2), Ci + 3, j + 3 = (i + 4, j + 3)
Even with this pattern, the same effects as described above are obtained.

  Furthermore, in the liquid crystal display device according to the present invention, the scanning line driving circuit has a gate pulse width Tp when a positive drain signal is applied by the signal line driving circuit and a negative drain signal is applied. A gate signal longer than the gate pulse width Tn is applied.

  As a result, the gate pulse width Tp can be increased when a positive drain signal is applied, and the gate pulse width Tn when a negative drain signal is applied. Therefore, when a positive drain signal is applied, it is possible to secure a long gate pulse width Tp so as to compensate for the shortage of charging due to a decrease in current supply capability. Therefore, the panel charging time can be secured by changing the gate signal width according to the source potential to be written. Therefore, in a large-sized and high-definition liquid crystal panel, even if the pixels are dense and the charging time that can be applied to one transistor is shortened, it is possible to prevent insufficient charging.

  The liquid crystal display device according to the present invention is a liquid crystal display device in which TFTs are provided so as to correspond to the respective pixels arranged in the matrix direction, and are connected to the gates of the TFTs of the pixels and have different polarities. A first scan line and a second scan line for driving the pixels, wherein the first scan line is connected to TFTs of two adjacent pixels in the same pixel column, and the second scan In this configuration, the line is connected to the TFTs of two pixels located at one diagonal for every four pixels in two rows and two columns.

  If TFTs are arranged in this way, the above TFT arrangement pattern can be repeated. Therefore, the same effect as described above is obtained.

  One embodiment of the present invention will be described below with reference to FIGS.

  FIG. 2 is a block diagram showing an outline of the configuration of the active matrix liquid crystal display device 1 according to the present embodiment. In the following description, a TFT (thin film transistor) type liquid crystal display device, which is a typical example of the active matrix type, is exemplified. However, the present invention can be widely applied to so-called electro-optic modulation elements, and is particularly suitable for a display device using a matrix type TFT, and is not limited to a liquid crystal display device.

  The liquid crystal display device 1 includes a liquid crystal display unit and a liquid crystal driving device that drives the liquid crystal display unit. The liquid crystal display unit includes a TFT liquid crystal panel 11. In the liquid crystal panel 11, a liquid crystal display element (not shown) and a counter electrode (common electrode) are provided. On the other hand, the liquid crystal driving device includes a source driver 12 and a gate driver 13, each of which is composed of an IC (Integrated Circuit), a controller 14, and a liquid crystal driving power source (not shown).

  In general, the source driver 12 and the gate driver 13 are, for example, a TCP (Tape Carrier Package) in which a previous IC chip is mounted on a film with wiring, and an ITO (Indium Tin Oxide) film on a liquid crystal panel. ) It can be mounted and connected on the terminal, or the previous IC chip can be directly bonded to the ITO terminal on the liquid crystal panel via ACF (Anisotropic Conductive Film) and mounted and connected. It is configured. In order to cope with the downsizing of the liquid crystal display device, the controller 14, the source driver 12, the gate driver 13, and the liquid crystal driving power source may be configured by one chip or by two to three chips.

  The controller 14 outputs digitized display data (for example, RGB signals corresponding to red, green, and blue) and various control signals to the source driver 12 and outputs various control signals to the gate driver 13. Yes. Main control signals to the source driver 12 include a horizontal synchronization signal, a start pulse signal, a source driver clock signal, and the like. On the other hand, main control signals to the gate driver 13 include a vertical synchronization signal and a gate driver clock signal.

  The controller 14 generates display data from a video signal input from the outside, controls timing and the like, and then inputs the display data (Data) to the source driver 12. In particular, the controller 14 includes a scanning line sequential conversion unit 41 that converts display data based on the video signal into a display order on the liquid crystal panel 11. The converted display data is the display data (Data) in FIG. The configuration of the scanning line sequential conversion unit 41 will be described later.

  The source driver 12 and the gate driver 13 are supplied with a liquid crystal panel display voltage from a liquid crystal driving power source. In the figure, a power source for driving each IC is omitted.

  The source driver 12 latches the input display data internally in a time-sharing manner, and then latches the signal to a horizontal synchronization signal (also referred to as a latch signal) input from the controller 14 and DA (digital-analog) in synchronization with this signal. ) Perform conversion. The source driver 12 drives the liquid crystal driving analog voltage (tone display voltage) obtained by DA conversion from the liquid crystal driving voltage output terminal via the signal line (source signal line). The voltage is output to a liquid crystal display element (not shown) in the liquid crystal panel 11 corresponding to the voltage output terminal. Therefore, as illustrated in FIG. 2, the source driver 12 includes a shift register circuit 21, a data latch circuit 22, a D / A conversion circuit 23, and an output circuit 24.

  Next, the liquid crystal panel 11 will be described. The liquid crystal panel 11 is provided with a pixel electrode, a pixel capacitance, a TFT as an element for turning on / off a voltage applied to the pixel, a signal line (source signal line), a scanning line (gate signal line), and a counter electrode. . Note that the pixel electrode sandwiches the liquid crystal layer with the counter electrode.

  A gradation display voltage corresponding to the brightness of the display target pixel is applied from the source driver 12 to the signal line. A scanning signal is given to the scanning line from the gate driver 13 so that the TFTs are sequentially turned on.

  When a signal line voltage is applied to the pixel electrode connected to the drain of the TFT through the TFT in the ON state, charge is accumulated in the pixel capacitor between the pixel electrode and the counter electrode. Thereby, the light transmittance is changed in the liquid crystal, and display is performed.

  In the liquid crystal display device 1 according to the present embodiment, TFTs provided so as to correspond to the respective pixels arranged in the matrix direction, scanning lines G that commonly connect the gates of the TFTs, and drains of the TFTs are commonly connected. A signal line G, a pixel electrode of each pixel connected to the source of the TFT, a gate driver (scanning line driving circuit) 13 for controlling a gate signal to the scanning line G, and a source for controlling a drain signal to the signal line SD A driver (signal line driver circuit) 12 is included.

  Hereinafter, a display panel 11 having m pixels in the row direction and n pixels in the column direction will be described as a specific example. Each pixel is represented as Cm, n. Further, display data spatially corresponding to each pixel is denoted as Dm, n. In the figure, the TFT provided in the pixel is indicated by a square.

  FIG. 1 is an explanatory diagram showing the arrangement of TFTs of the display panel 11 and the polarities of the pixels of the l-th frame Fl. FIG. 3 is an explanatory diagram showing an example of driving the l-th frame Fl. FIG. 4 is an explanatory diagram showing the polarities of the pixels of the (l + 1) th frame Fl + 1. FIG. 5 is an explanatory diagram showing an example of driving the (l + 1) th frame Fl + 1.

  As shown in FIG. 1, the display panel 11 is provided with one TFT for each pixel. Each TFT has a gate connected to one scanning line Gn, a drain connected to one signal line SDn, and a source connected to the pixel electrode.

  Here, TFTs are provided in the effective display area of the display panel 11 so as to repeat a predetermined TFT arrangement pattern. In FIG. 1, the area below the second row is a TFT arrangement pattern repeating area. The same applies to FIGS. 4, 6 to 8, 10, and 14.

In the repetitive pattern, the gates of the TFTs provided in the pixels Cx, y in the x rows and y columns of the repetitive region are connected to the p th scanning line in the repetitive region, and the drain is connected to the q th signal line in the repetitive region. Is expressed as Ci, j = (p, q),
Ci, j = (i + 1, j), Ci, j + 1 = (i, j + 1),
Ci, j + 2 = (i + 1, j + 2), Ci, j + 3 = (i, j + 3),
Ci + 1, j = (i + 1, j + 1), Ci + 1, j + 1 = (i + 2, j + 1),
Ci + 1, j + 2 = (i + 1, j + 3), Ci + 1, j + 3 = (i + 2, j + 3),
Ci + 2, j = (i + 2, j), Ci + 2, j + 1 = (i + 3, j + 1),
Ci + 2, j + 2 = (i + 2, j + 2), Ci + 2, j + 3 = (i + 3, j + 3),
Ci + 3, j = (i + 4, j), Ci + 3, j + 1 = (i + 3, j + 2),
Ci + 3, j + 2 = (i + 4, j + 2), Ci + 3, j + 3 = (i + 3, j + 4)
It can be expressed as. Specifically, the 16 pixels in which the display data D1,2 to D4,5 of FIG. 1 are written correspond to the above-described pixels Ci, j to Ci + 3, j + 3.

  In addition to the above pattern, the following three patterns are possible as the TFT arrangement repetitive pattern.

  FIG. 6 is an explanatory diagram showing another arrangement of TFTs of the display panel 11 and the polarities of the pixels of the l-th frame Fl. In FIG. 6, the TFTs are arranged according to the following repeating pattern.

Ci, j = (i, j), Ci, j + 1 = (i + 1, j + 1),
Ci, j + 2 = (i, j + 2), Ci, j + 3 = (i + 1, j + 3),
Ci + 1, j = (i + 2, j), Ci + 1, j + 1 = (i + 1, j + 2),
Ci + 1, j + 2 = (i + 2, j + 2), Ci + 1, j + 3 = (i + 1, j + 4),
Ci + 2, j = (i + 3, j), Ci + 2, j + 1 = (i + 2, j + 1),
Ci + 2, j + 2 = (i + 3, j + 2), Ci + 2, j + 3 = (i + 2, j + 3),
Ci + 3, j = (i + 3, j + 1), Ci + 3, j + 1 = (i + 4, j + 1),
Ci + 3, j + 2 = (i + 3, j + 3), Ci + 3, j + 3 = (i + 4, j + 3)
FIG. 7 is an explanatory diagram showing another arrangement of TFTs of the display panel 11 and the polarities of the pixels of the l-th frame Fl. In FIG. 7, the TFTs are arranged according to the following repeating pattern.

Ci, j = (i + 1, j + 1), Ci, j + 1 = (i, j + 1),
Ci, j + 2 = (i + 1, j + 3), Ci, j + 3 = (i, j + 3),
Ci + 1, j = (i + 1, j), Ci + 1, j + 1 = (i + 2, j + 1),
Ci + 1, j + 2 = (i + 1, j + 2), Ci + 1, j + 3 = (i + 2, j + 3),
Ci + 2, j = (i + 2, j), Ci + 2, j + 1 = (i + 3, j + 2),
Ci + 2, j + 2 = (i + 2, j + 2), Ci + 2, j + 3 = (i + 3, j + 4),
Ci + 3, j = (i + 4, j), Ci + 3, j + 1 = (i + 3, j + 1),
Ci + 3, j + 2 = (i + 4, j + 2), Ci + 3, j + 3 = (i + 3, j + 3)
If the TFT arrangement pattern of FIG. 7 is used, the order of the data input to the shift register circuit may be processed such that, for example, the display data D1,3 comes before the display data D1,2. In addition, the processing can be performed by a scanning line sequential conversion unit 41 described later.

  FIG. 8 is an explanatory diagram showing another arrangement of TFTs of the display panel 11 and the polarities of the pixels of the l-th frame Fl. In FIG. 8, TFTs are arranged according to the following repeating pattern.

Ci, j = (i, j), Ci, j + 1 = (i, j + 2),
Ci, j + 2 = (i, j + 2), Ci, j + 3 = (i + 1, j + 4),
Ci + 1, j = (i + 2, j), Ci + 1, j + 1 = (i + 1, j + 1),
Ci + 1, j + 2 = (i + 2, j + 2), Ci + 1, j + 3 = (i + 1, j + 3),
Ci + 2, j = (i + 3, j + 1), Ci + 2, j + 1 = (i + 2, j + 1),
Ci + 2, j + 2 = (i + 3, j + 3), Ci + 2, j + 3 = (i + 2, j + 3),
Ci + 3, j = (i + 3, j), Ci + 3, j + 1 = (i + 4, j + 1),
Ci + 3, j + 2 = (i + 3, j + 2), Ci + 3, j + 3 = (i + 4, j + 3)
In the pattern of FIG. 8, the TFT of the pixel displaying “−” may be connected to the signal line on the right side.

  Here, as shown in FIG. 1 (the same applies to FIGS. 4, 6 to 8, 10, and 14), the odd-numbered scanning lines G 3, G 5,. (First scanning line) is connected to TFTs of two adjacent pixels (D1, 2 and D1, 3 etc.) in the same pixel column, and even-numbered scanning lines G2, G4,. Scanning line) is connected to TFTs of two pixels (D2, 3 and D3,4, etc.) located at one diagonal for every four pixels in 2 rows and 2 columns. That is, as will be described later, odd-numbered scanning lines G3, G5,... And even-numbered scanning lines G2, G4,... Are connected to pixels driven with different polarities.

  Further, the TFT arrangement of the pixels in the first row of the effective display area may be the same as or different from the arrangement of the TFTs provided in the other rows. That is, when dot inversion driving is performed every two pixels in the column direction shifted by one pixel, the pixels in the first row and the pixels in the second and subsequent rows may or may not have the same TFT arrangement.

  In the dot inversion driving, it is sufficient to drive the TFTs in one column having the same polarity with G1 being the same scanning line, and either the even-numbered column or the odd-numbered column of pixels that are driven in one column. A TFT may be provided on one side (FIGS. 1 and 10). In the next scanning line G2, the pixels in the first row that are not driven by the scanning line G1 and the pixels in the second row that are driven by the scanning line G1 are driven by the pixels in the second row. TFT was provided.

  That is, in FIG. 1, the TFT provided on the scanning line G1 is connected to the even-numbered signal line SD2k. Alternatively, as shown in FIG. 10, the TFT provided on the scanning line G1 may be connected to an odd-numbered signal line SD2k-1 (except for SD1).

  Further, according to the present invention, two pixels adjacent to each other in the column direction are driven by the same scanning line by skipping one pixel in the column direction, and the other polarity pixel is driven by the same polarity. A liquid crystal display device driven by another same scanning line, which is different from the scanning line, and the same scanning line as a first pixel group in which TFTs are provided in a staggered manner with respect to the same scanning line in the same pixel column On the other hand, it may be configured to have a second pixel group in which TFTs are arranged in a staggered manner in units of two pixels in the row direction.

  Note that a dummy pixel or a dummy scanning line may be provided in a row above the first row of pixels. The dummy means a pixel outside the effective display area, a scanning line for driving the pixel, and the like. By providing dummy pixels and dummy scanning lines, the load of scanning lines driven with the same polarity can be made uniform, and the effect of crosstalk of effective pixels received from signal lines can be made the same in the first and other rows. It becomes possible to do.

  FIG. 10 is an explanatory diagram showing another arrangement of TFTs of the display panel 11 and the polarities of the pixels of the l-th frame Fl. FIG. 11 is an explanatory diagram showing an example of driving the l-th frame Fl.

For the liquid crystal panel 11 having the above structure, the source driver 12 includes pixels Ci, j, Ci, j + 2, Ci + 1, j, Ci + 1, j + 2 constituting the first pixel group. ,
Ci + 2, j + 1, Ci + 2, j + 3, Ci + 3, j + 1, Ci + 3, j + 3
Pixels Ci, j + 1, Ci, j + 3, Ci + 1, j + 1, Ci + 1, j + 3 constituting the second pixel group
Ci + 2, j, Ci + 2, j + 2, Ci + 3, j, Ci + 3, j + 2
Are inverted by applying drain signals having opposite polarities to each other. That is, drain signals having opposite polarities are applied to the pixels (first pixel group) indicated as “+” and the pixels (second pixel group) indicated as “−” in FIG. Further, the source driver 12 inverts the polarity for each frame. Thereby, it is possible to perform inversion driving in which two vertical dots are grouped.

  On the other hand, when a positive drain signal is applied to a pixel to which a gate signal is applied, the gate driver 13 sets the gate pulse width to Tp (first gate line drive pulse width) and applies a negative drain signal. Sometimes the gate pulse width is Tn (second gate line drive pulse width). Since the TFTs are arranged according to the TFT arrangement pattern described above, the polarity of the drain signal of the pixel to which one scanning line applies the gate signal is unified to either positive polarity or negative polarity.

  Here, FIG. 9 is a block diagram showing a configuration example of the gate driver 13.

  As shown in FIG. 9, the gate driver 13 can be composed of a shift register 31 and an output circuit 32. A gate output enable signal GOE1 and a gate output enable signal GOE2 are input from the controller 14 to the output circuit 32. In the gate driver 13, when the gate output enable signals GOE1 and GOE2 are "H", a gate pulse is output to the scanning line Gn. Thereby, it is possible to easily control the switching timing of the odd-numbered scanning line G2k-1 from on to off and the switching timing of the even-numbered scanning line G2k from off to on. Note that when the number of stages of the shift register is reduced, the timing at which the odd-numbered scanning line G2k-1 is turned on from off coincides with the timing at which the even-numbered scanning line G2k is turned on from off.

  Next, the configuration of the scanning line sequential conversion unit 41 and the process of converting the display data into the order of display on the liquid crystal panel 11 will be described. The scanning line sequential conversion unit 41 has a function of supplying display data for each pixel to the source driver 12 by dividing the display data into one written by a positive drain signal and one written by a negative drain signal. The display data Dm, n is converted into scanning line sequential by the scanning line sequential conversion unit 41.

  FIG. 3 is an explanatory diagram illustrating an example of conversion of display data by the scanning line sequential conversion unit 41. The row in FIG. 3 shows display data written by the scanning line Gn, and the column shows display data applied by the signal line SDm. The same applies to FIGS. 5, 11, and 15. Further, Dm, n in FIG. 3 indicates display data for driving pixels in m columns and n rows. The same applies to FIGS. 1, 4, 5 to 8, 10, 11, 14, and 15.

  FIG. 12 is a block diagram illustrating a configuration example of the scanning line sequential conversion unit 41 corresponding to FIG. In the scanning line sequential conversion unit 41 configured as shown in FIG. 12, display data is distributed to a FIFO (first in, first out) memory 42 and a FIFO memory 43. Specifically, when there is display data D1,1, D2,1, D3,1, D4,1, D5,1, D6,1, the FIFO memory 42 has D2,1, D4,1, D6,1. , D1,1, D3,1, D5,1 are allocated to the FIFO memory 43, respectively. Then, the data converted into the scanning line sequential by the scanning line sequential conversion unit 41 is shifted by the shift register 21 and then latched by the data latch circuit 22. The data latched is D / A converted by the D / A conversion circuit 23, outputted from the output circuit 24 to the signal line SDm, and written by scanning the scanning line.

  In the scanning line sequential conversion unit 41 configured as shown in FIG. 12 or FIG. 13, the display data is line-sequentially from Data In to display data corresponding to the pixels in the first row to display data corresponding to the pixels in the nth row. Are input during one vertical display period at a constant cycle. That is, display data D1,1, D2,1, D3,1, D4,1, D5,1, D6,1 are input in this order, and then display data D1,2, corresponding to the pixels in the second row, D2,2, D3,2, D4,2, D5,2, D6,2 are inputted in this order, and finally, display data D1, n, D2, n, D3 corresponding to the pixels in the n-th row , n, D4, n, D5, n, D6, n are input in this order.

  In order to display the display data on the display panel 11 having the TFT arrangement shown in FIG. 1, the scanning line sequential conversion unit 41 in FIG. 12 scans the display data with the switches SW1 and SW2 and the FIFO memories 42 and 43. The scanning lines for scanning the display data in units of two rows are changed in the line order (G1, G2, G3, G4).

  FIG. 13 is a block diagram showing a configuration example of the scanning line sequential conversion unit 41 corresponding to FIG. As shown in FIG. 13, the scanning line sequential conversion unit 41 can be configured by a frame memory 44.

  The scanning line sequential conversion unit 41 in FIG. 13 stores the display data in the frame memory 44 at an address spatially corresponding to the display data.

  FIG. 3 shows the position of the display data after the scanning line sequential conversion is performed in order to display the display data on the liquid crystal panel 11 of FIG. FIG. 3 shows a scanning line that scans in the row direction, and a source driver that applies display data to the pixels in the column direction. More specifically, the display data D2,1 indicates that + polarity display data is applied to the pixel from the source driver SD2 when the scanning line G1 is selected.

  If attention is paid to the display data D6, 5 in FIG. 3, the source driver to be driven is SD7 at the Data In stage, which is the sixth position from the head data in one scanning period. The same applies to FIG. That is, as can be seen from FIG. 3 and FIG. 11, the display data is Dm, n at the stage of Data In, but the number of source drivers for driving the pixels is m + 1.

  As described above, when the dot inversion driving is performed by shifting one pixel, every two pixels in the column direction, and one pixel in the row direction, by line inversion driving, C (n rows, m columns) unless the TFT arrangement shown in FIG. ) Requires m + 1 source drivers. That is, if TFTs are arranged as shown in FIGS. 1 and 10, a liquid crystal display device composed of pixels in n rows and m columns for dot inversion driving for every two pixels in the column direction and for every one pixel in the row direction, the number of source drivers Can be composed of m + 1 pieces.

  Here, as can be seen from FIGS. 3, 5, and 11, the liquid crystal display device 1 uses m + 1 source drivers to display m pixels in one row.

  Next, FIG. 14 is an explanatory diagram showing still another arrangement of TFTs of the display panel 11 and the polarities of the pixels of the l-th frame Fl. FIG. 15 is an explanatory diagram showing an example of driving the l-th frame Fl. FIG. 16 is a block diagram illustrating a configuration example of the scanning line sequential conversion unit 41 corresponding to FIG.

  FIG. 15 shows the position of the display data after the scanning line sequential conversion is performed in order to display the display data on the display panel 11 having the TFT arrangement shown in FIG. FIG. 15 shows a scanning line that scans in the row direction, and a source driver that applies display data to the pixels in the column direction.

  In the TFT arrangement of FIG. 14, even if the display panel 11 composed of pixels in n rows and m columns is shifted by one pixel and dot inversion driving is performed every two pixels in the column direction and every one pixel in the row direction, the necessary source driver The number is m. That is, if TFTs are arranged as shown in FIG. 14, a liquid crystal display device composed of pixels in n rows and m columns for dot inversion driving every two pixels in the column direction and one pixel in the row direction, and the number of source drivers is m. Can be configured.

  As shown in FIG. 14, the drains of the TFTs of the pixels C2,4, C4,4, C6,4 are connected to the signal lines SD1, SD3, SD5, respectively. Such connection is possible, for example, by providing the drains of the TFTs of the pixels C2, 4 across the signal line SD2, that is, cross-under.

  With the configuration shown in FIG. 14, the scanning line sequential conversion is performed as shown in FIG. Therefore, driving of m pixels in one row can be realized with m source drivers. As a result, the scanning line sequential conversion unit 41 can be realized by one line memory 45 as shown in FIG. That is, the configuration of the scanning line sequential conversion unit 41 can be simplified.

  FIG. 17 is a timing chart of the scanning line Gn and the signal line SDm.

  As shown in the timing chart of the scanning line Gn, the gate driver 13 outputs a gate pulse so that the gate-on time when the voltage written to the pixel is positive is longer than the gate-on time when the voltage is negative. The total of one positive period and one negative period is two horizontal scanning periods (2H).

  The polarity switching of the data SDm may be controlled by transmitting a polarity switching signal from the controller 14 to the D / A conversion circuit 23.

  In FIG. 17, the horizontal synchronization signal HD is distinguished into (positive polarity writing period) and HD2 (negative polarity writing period). This is for clarifying the timing relationship of the gate-on time control. The method is not limited. That is, the controller 14 may generate the horizontal synchronization signal HD at regular intervals regardless of the polarity.

  FIG. 18 is a timing chart of the gate driver 13 (scanning line driving unit GD). The timing chart of FIG. 15 will be described with reference to the shift register shown in FIG.

  The clock is composed of a first pulse (high period: t1, low period: t2) having a high period twice in a 2H period and a second pulse (high period t3, low period: t4).

  When the cyst start signal SP is input, the shift register 31 starts shifting the shift signal in the shift register 31. Then, the shift register that drives the scanning line G1 goes high at the rising edge of the first pulse, the shift register that drives the scanning line G1 goes low at the rising edge of the second pulse, and the shift that drives the scanning line G2. The register goes high. Thus, the shift register 31 sequentially shifts the shift signal.

  In particular, the gate driver 13 outputs gate output enable signals GOE1 and GOE2. The gate output enable signal GOE1 controls the output of the gate driver that drives the odd-numbered scanning lines, and the gate output enable signal GOE2 controls the output of the gate driver that drives the even-numbered scanning lines. The output circuit 32 controls the output of the gate driver to pass through when the gate output enable signals GOE1 and GOE2 are in the high state, and turns off the output of the gate driver when GOE1 and GOE2 are in the low state.

  Thus, by providing a plurality of gate output enable signals, the gate pulse can be paused easily between Tp and Tn without complicating the configuration of the shift register 31 (without increasing the number of stages). Since t5 and t6 (FIG. 18) which are periods can be provided, display data can be accurately written to the pixels.

  As described above, the gate driver 13 generates a gate signal whose gate pulse width Tp when the positive drain signal is applied by the source driver 12 is longer than the gate pulse width Tn when the negative drain signal is applied. Apply.

  Here, the gate pulse width is set to satisfy Tp + Tn ≦ 2H, where H is one horizontal scanning period. Accordingly, the gate pulse width in the unit of 2H is interchanged from the gate pulse width when the negative polarity drain signal having a sufficient charge time is applied to the gate pulse width when the positive polarity drain signal is applied. Tp and Tn can be optimized. The ratios of the gate pulse widths Tp and Tn can be determined by simulating the charging time based on the capacitor current equation and the triode region current equation.

  Hereinafter, a method for determining the gate pulse widths Tp and Tn will be described in detail.

  The current-voltage characteristic of a TFT has a non-saturated region and a saturated region, but there is no problem when considered in the non-saturated region. When the drain voltage of the TFT is Vd, the source voltage is Vs, the gate voltage is Vg, the rising voltage is VT, and the source current is Is, the source current Is is expressed by the following equation (1).

Is = k * {(Vg- Vs-VT) * (Vd-Vs)} - (Vd-Vs) 2/2}
(1)
The COM potential Vcom is 5V, the capacitance of each pixel is C, the charge stored in the capacitor C is Q, Vg = 15V, VT = 2.5V, positive display data is 10V, and negative display data is 0V. Then, the positive data write time tp and the negative data write time tn can be obtained by solving the following equations.

Tn period;
dQ / dt = k * {12.5 * (5-Q / C) - (5-Q / C) 2/2}
(2)
Q ^{2 -15CQ-75C 2} = roots α1 of 0, [alpha] 2, and when the constant is -k / 2C ^{2,
tn = (k / 2C 2)} * [ln {(5C-α1) ( 5C-α2)}
−ln {(5C + α1) (5C + α2)}] (3)
Tp period;
dQ / dt = k * {(7.5-Q / C} * (5-Q / C)
^{- (5-Q / C)} 2/2} ··· (4)
If the root of Q ² -15CQ + 50C ² = 0 is α3, α4 and the constant is k / 2C ² ,
tp = (k / 2C2) [ln {(5C-α3) (5C-α4)}
−ln {(5C + α3) (5C + α4)}] (5)
Therefore,
tn / tp = [ln {(5C-α1) (5C-α2)}
−ln {(5C + α1) (5C + α2)}]
/ [Ln {(5C-α3) (5C-α4)}
−ln {(5C + α3) (5C + α4)}] (6)
Comparing Equation (2) and Equation (4), the current per unit time flows more in the Tn period, and the amplitude at which the capacitor C is charged / discharged is 10 V in both the Tn period and the Tp period. Obviously, the period may be shorter.

  Since (Vd−Vs) = 0 and Is is 0, charging / discharging takes time in the vicinity of (Vd−Vs) ≈0. Therefore, it is not necessary to completely match the drain voltage and the source voltage of the TFT. . In other words, the display state that is output may be set in advance so that the display data that is input is in a predetermined display state.

  In any case, as described above, the ratio of tn / tp can also be obtained by calculation by measuring parameters. However, in practice, Tn and Tp may be varied within the 2H period and set within a range in which display data is normally written to pixels. For example, it may be set to a time ratio in which flicker does not occur in halftone solid display.

  As described above, the gate pulse widths Tp and Tn can be determined independently and arbitrarily. Therefore, even if one becomes longer, it is not always necessary to shorten the other. For example, when Tp + Tn <2H after securing both charging times, a time during which no gate signal is applied may be provided. Conversely, when Tp + Tn> 2H, the gate pulse width Tn when applying a negative drain signal may be shortened so that Tp + Tn = 2H.

  As described above, according to the liquid crystal display device 1, one scanning line can supply a gate signal having one kind of gate pulse width corresponding to the polarity of the drain signal to all pixels in one scanning. In addition, the TFTs are arranged according to a predetermined TFT arrangement pattern. Therefore, it is possible to apply a gate signal whose gate pulse width Tp when a positive drain signal is applied is longer than the gate pulse width Tn when a negative drain signal is applied.

  Therefore, when a positive drain signal is applied, a long gate pulse width Tp can be secured so as to compensate for the shortage of charging due to a decrease in the current supply capability of the TFT. Therefore, the panel charging time can be secured by changing the gate signal width according to the source potential to be written. Therefore, in a large-sized and high-definition liquid crystal panel, even if the pixels are dense and the charging time that can be applied to one transistor is shortened, it is possible to prevent insufficient charging.

  The liquid crystal display device 1 can accurately display a so-called killer pattern in which display is disturbed by inversion driving for each line or inversion driving for each dot. Therefore, better display quality can be realized.

  The present embodiment does not limit the scope of the present invention, and various modifications are possible within the scope of the present invention. For example, the present embodiment can be configured as follows.

  The display device according to the present invention is a display device composed of effective pixels of n rows and m columns, and the TFT of the pixel in the first row is connected to one of a plurality of signal lines adjacent to the pixel. Also good.

  The display device according to the present invention may be a display device composed of effective pixels of n rows and m columns, and may be driven by a driver whose number of source drivers is m + 1.

  The display device according to the present invention is a display device including effective pixels of n rows and m columns, and the TFT drains of some pixels in the same column may be connected to non-adjacent signal lines.

  In the display device according to the present invention, the TFT arrangement pattern may be as shown in FIGS. 1, 6 to 8, 10, and 14.

  In the display device according to the present invention, the gate-on time may be controlled by the two gate output enable signals for the output of the gate driver.

  The liquid crystal display device according to the present invention is a liquid crystal display device that is driven by a scanning line for driving a pixel having one polarity and a scanning line for driving a pixel having a polarity different from that of the pixel. A first pixel group in which TFTs are provided in a column in a staggered manner with respect to the same scanning line, and a second pixel in which TFTs are arranged in a staggered manner in units of two pixels in the row direction with respect to the same scanning line. You may have a group.

  In the driving method of the liquid crystal display device according to the present invention, the pixels in the first row of the effective display area are driven by dot inversion, and the second and subsequent rows are driven every two pixels in the column direction and one pixel in the row direction. A driving method of a liquid crystal display device in which the polarity is different from the polarity of the row and the inversion driving is performed from the second row, and a drain signal having a negative gate pulse width Tp when a positive polarity drain signal is applied is applied. A method of applying a gate signal longer than the gate pulse width Tn at the time may be used.

  The liquid crystal display device according to the present invention is a liquid crystal display device composed of effective pixels of dot inversion driving (m columns, n rows) for every two pixels in the column direction and every one pixel in the row direction. The number of source signal lines for driving may be m + 1.

  The liquid crystal display device according to the present invention is a liquid crystal display device composed of effective pixels of dot inversion driving (m columns, n rows) for every two pixels in the column direction and every one pixel in the row direction. The number of source signal lines for driving may be m.

  The liquid crystal display device according to the present invention is a liquid crystal display device composed of effective pixels of dot inversion driving (m columns, n rows) for every two pixels in the column direction and every one pixel in the row direction. The number of source drivers for driving may be m + 1.

  The liquid crystal display device according to the present invention is a liquid crystal display device composed of effective pixels of dot inversion driving (m columns, n rows) for every two pixels in the column direction and every one pixel in the row direction. There may be m source drivers for driving.

  The gate driver (scanning line driving circuit) of the liquid crystal display device according to the present invention includes a shift register and a plurality of output circuits, each of which is a first gate output enable signal GOE1 or a second gate output. It may be connected to any one of the gate output enable signals of the enable signal GOE2.

  The gate driver (scanning line driving circuit) of the liquid crystal display device according to the present invention includes a plurality of systems of a first gate line (scanning line) driving pulse width Tp and a second gate line (scanning line) driving pulse width Tn. A gate driver that outputs a gate line driving pulse to a scanning line, wherein the first gate line driving pulse and the second gate line driving pulse are each a high level that is a gate line driving signal for two horizontal scanning periods A voltage of a level may be sequentially output, and a period in which none of the gate lines is driven may be between the first gate line driving pulse and the second gate line driving pulse.

  The liquid crystal display device according to the present invention can change the gate signal width in accordance with the source potential to be written, so that the panel charging time can be secured, and is particularly suitable for a large-sized and high-definition liquid crystal panel.

FIG. 3 is an explanatory diagram showing the arrangement of TFTs of the display panel shown in FIG. 2 and the polarities of pixels in the l-th frame. It is a block diagram which shows the outline of a structure of the liquid crystal display device which concerns on one embodiment of this invention. FIG. 8 is an explanatory diagram illustrating an example of driving the l-th frame of the display panel illustrated in FIG. 1. FIG. 3 is an explanatory diagram showing the arrangement of TFTs of the display panel shown in FIG. 2 and the polarities of the pixels of the l + 1th frame. FIG. 5 is an explanatory diagram showing an example of driving the l + 1-th frame of the display panel shown in FIG. 4. It is explanatory drawing which shows other arrangement | positioning of TFT of the display panel shown in FIG. It is explanatory drawing which shows other arrangement | positioning of TFT of the display panel shown in FIG. It is explanatory drawing which shows other arrangement | positioning of TFT of the display panel shown in FIG. FIG. 3 is a block diagram illustrating a configuration example of a gate driver illustrated in FIG. 2. FIG. 4 is an explanatory diagram showing another arrangement of TFTs of the display panel shown in FIG. 2 and the polarities of the pixels of the l-th frame. FIG. 11 is an explanatory diagram illustrating an example of driving the l-th frame of the display panel illustrated in FIG. 10. FIG. 3 is a block diagram illustrating a configuration example of a scanning line sequential conversion unit of the controller illustrated in FIG. 2. FIG. 4 is a block diagram illustrating another configuration example of the scanning line sequential conversion unit of the controller illustrated in FIG. 2. FIG. 10 is an explanatory diagram showing still another arrangement of TFTs of the display panel shown in FIG. 2 and the polarities of the pixels of the l-th frame. FIG. 15 is an explanatory diagram illustrating an example of driving the l-th frame of the display panel illustrated in FIG. 14. FIG. 10 is a block diagram showing still another configuration example of the scanning line sequential conversion unit of the controller shown in FIG. 2. 3 is a timing chart of scanning lines and signal lines of the display panel shown in FIG. 2. 3 is a timing chart of scanning lines of the display panel shown in FIG. 7 is a timing chart of gate signals by line inversion driving in a liquid crystal display device according to the background art. It is a top view which shows the electrode structure of the liquid crystal display device which concerns on background art. FIG. 21 is an explanatory diagram showing a state in which positive and negative voltages that are inverted for each dot are applied when the liquid crystal display device shown in FIG. 20 is driven by a gate-line inversion method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 12 Source driver (signal line drive circuit)
13 Gate driver (scan line drive circuit)
41 Scanning line sequential conversion unit (scanning line sequential conversion means)

Claims (26)

TFTs provided so as to correspond to the respective pixels arranged in the matrix direction, scanning lines that commonly connect the gates of the TFTs, signal lines that commonly connect the drains of the TFTs, and respective sources connected to the sources of the TFTs A liquid crystal display device having a pixel electrode of a pixel, a scanning line driving circuit for controlling a gate signal to the scanning line, and a signal line driving circuit for controlling a drain signal to the signal line,
In the effective display area, TFTs are provided to repeat a predetermined TFT arrangement pattern,
The TFT arrangement pattern is such that the gates of the TFTs provided in the pixels Cx, y in the x rows and y columns of the effective display area are the p th scanning line of the effective display area, and the drain is the q th signal line of the effective display area. When noting that Ci, j = (p, q) is connected,
Ci, j = (i + 1, j), Ci, j + 1 = (i, j + 1),
Ci, j + 2 = (i + 1, j + 2), Ci, j + 3 = (i, j + 3),
Ci + 1, j = (i + 1, j + 1), Ci + 1, j + 1 = (i + 2, j + 1),
Ci + 1, j + 2 = (i + 1, j + 3), Ci + 1, j + 3 = (i + 2, j + 3),
Ci + 2, j = (i + 2, j), Ci + 2, j + 1 = (i + 3, j + 1),
Ci + 2, j + 2 = (i + 2, j + 2), Ci + 2, j + 3 = (i + 3, j + 3),
Ci + 3, j = (i + 4, j), Ci + 3, j + 1 = (i + 3, j + 2),
Ci + 3, j + 2 = (i + 4, j + 2), Ci + 3, j + 3 = (i + 3, j + 4)
Pattern of
The signal line driving circuit includes pixels Ci, j, Ci, j + 2, Ci + 1, j, Ci + 1, j + 2, which constitute the first pixel group.
Ci + 2, j + 1, Ci + 2, j + 3, Ci + 3, j + 1, Ci + 3, j + 3
Pixels Ci, j + 1, Ci, j + 3, Ci + 1, j + 1, Ci + 1, j + 3 constituting the second pixel group
Ci + 2, j, Ci + 2, j + 2, Ci + 3, j, Ci + 3, j + 2
Are driven by inversion by applying drain signals having opposite polarities to each other. TFTs provided so as to correspond to the respective pixels arranged in the matrix direction, scanning lines that commonly connect the gates of the TFTs, signal lines that commonly connect the drains of the TFTs, and respective sources connected to the sources of the TFTs A liquid crystal display device having a pixel electrode of a pixel, a scanning line driving circuit for controlling a gate signal to the scanning line, and a signal line driving circuit for controlling a drain signal to the signal line,
In the effective display area, TFTs are provided to repeat a predetermined TFT arrangement pattern,
The TFT arrangement pattern is such that the gates of the TFTs provided in the pixels Cx, y in the x rows and y columns of the effective display area are the p th scanning line of the effective display area, and the drain is the q th signal line of the effective display area. When noting that Ci, j = (p, q) is connected,
Ci, j = (i, j), Ci, j + 1 = (i + 1, j + 1),
Ci, j + 2 = (i, j + 2), Ci, j + 3 = (i + 1, j + 3),
Ci + 1, j = (i + 2, j), Ci + 1, j + 1 = (i + 1, j + 2),
Ci + 1, j + 2 = (i + 2, j + 2), Ci + 1, j + 3 = (i + 1, j + 4),
Ci + 2, j = (i + 3, j), Ci + 2, j + 1 = (i + 2, j + 1),
Ci + 2, j + 2 = (i + 3, j + 2), Ci + 2, j + 3 = (i + 2, j + 3),
Ci + 3, j = (i + 3, j + 1), Ci + 3, j + 1 = (i + 4, j + 1),
Ci + 3, j + 2 = (i + 3, j + 3), Ci + 3, j + 3 = (i + 4, j + 3)
Pattern of
The signal line driving circuit includes pixels Ci, j, Ci, j + 2, Ci + 1, j, Ci + 1, j + 2, which constitute the first pixel group.
Ci + 2, j + 1, Ci + 2, j + 3, Ci + 3, j + 1, Ci + 3, j + 3
Pixels Ci, j + 1, Ci, j + 3, Ci + 1, j + 1, Ci + 1, j + 3 constituting the second pixel group
Ci + 2, j, Ci + 2, j + 2, Ci + 3, j, Ci + 3, j + 2
Are driven by inversion by applying drain signals having opposite polarities to each other. TFTs provided so as to correspond to the respective pixels arranged in the matrix direction, scanning lines that commonly connect the gates of the TFTs, signal lines that commonly connect the drains of the TFTs, and respective sources connected to the sources of the TFTs A liquid crystal display device having a pixel electrode of a pixel, a scanning line driving circuit for controlling a gate signal to the scanning line, and a signal line driving circuit for controlling a drain signal to the signal line,
In the effective display area, TFTs are provided to repeat a predetermined TFT arrangement pattern,
The TFT arrangement pattern is such that the gates of the TFTs provided in the pixels Cx, y in the x rows and y columns of the effective display area are the p th scanning line of the effective display area, and the drain is the q th signal line of the effective display area. When noting that Ci, j = (p, q) is connected,
Ci, j = (i + 1, j + 1), Ci, j + 1 = (i, j + 1),
Ci, j + 2 = (i + 1, j + 3), Ci, j + 3 = (i, j + 3),
Ci + 1, j = (i + 1, j), Ci + 1, j + 1 = (i + 2, j + 1),
Ci + 1, j + 2 = (i + 1, j + 2), Ci + 1, j + 3 = (i + 2, j + 3),
Ci + 2, j = (i + 2, j), Ci + 2, j + 1 = (i + 3, j + 2),
Ci + 2, j + 2 = (i + 2, j + 2), Ci + 2, j + 3 = (i + 3, j + 4),
Ci + 3, j = (i + 4, j), Ci + 3, j + 1 = (i + 3, j + 1),
Ci + 3, j + 2 = (i + 4, j + 2), Ci + 3, j + 3 = (i + 3, j + 3)
Pattern of
The signal line driving circuit includes pixels Ci, j, Ci, j + 2, Ci + 1, j, Ci + 1, j + 2, which constitute the first pixel group.
Ci + 2, j + 1, Ci + 2, j + 3, Ci + 3, j + 1, Ci + 3, j + 3
Pixels Ci, j + 1, Ci, j + 3, Ci + 1, j + 1, Ci + 1, j + 3 constituting the second pixel group
Ci + 2, j, Ci + 2, j + 2, Ci + 3, j, Ci + 3, j + 2
Are driven by inversion by applying drain signals having opposite polarities to each other. TFTs provided so as to correspond to the respective pixels arranged in the matrix direction, scanning lines that commonly connect the gates of the TFTs, signal lines that commonly connect the drains of the TFTs, and respective sources connected to the sources of the TFTs A liquid crystal display device having a pixel electrode of a pixel, a scanning line driving circuit for controlling a gate signal to the scanning line, and a signal line driving circuit for controlling a drain signal to the signal line,
In the effective display area, TFTs are provided to repeat a predetermined TFT arrangement pattern,
The TFT arrangement pattern is such that the gates of the TFTs provided in the pixels Cx, y in the x rows and y columns of the effective display area are the p th scanning line of the effective display area, and the drain is the q th signal line of the effective display area. When noting that Ci, j = (p, q) is connected,
Ci, j = (i, j), Ci, j + 1 = (i, j + 2),
Ci, j + 2 = (i, j + 2), Ci, j + 3 = (i + 1, j + 4),
Ci + 1, j = (i + 2, j), Ci + 1, j + 1 = (i + 1, j + 1),
Ci + 1, j + 2 = (i + 2, j + 2), Ci + 1, j + 3 = (i + 1, j + 3),
Ci + 2, j = (i + 3, j + 1), Ci + 2, j + 1 = (i + 2, j + 1),
Ci + 2, j + 2 = (i + 3, j + 3), Ci + 2, j + 3 = (i + 2, j + 3),
Ci + 3, j = (i + 3, j), Ci + 3, j + 1 = (i + 4, j + 1),
Ci + 3, j + 2 = (i + 3, j + 2), Ci + 3, j + 3 = (i + 4, j + 3)
Pattern of
The signal line driving circuit includes pixels Ci, j, Ci, j + 2, Ci + 1, j, Ci + 1, j + 2, which constitute the first pixel group.
Ci + 2, j + 1, Ci + 2, j + 3, Ci + 3, j + 1, Ci + 3, j + 3
Pixels Ci, j + 1, Ci, j + 3, Ci + 1, j + 1, Ci + 1, j + 3 constituting the second pixel group
Ci + 2, j, Ci + 2, j + 2, Ci + 3, j, Ci + 3, j + 2
Are driven by inversion by applying drain signals having opposite polarities to each other.   5. The liquid crystal display device according to claim 1, wherein the first and second rows of pixels have the same TFT arrangement pattern. 6.   5. The liquid crystal display device according to claim 1, wherein the first and second row pixels have different TFT arrangement patterns. 6.   The scanning line driving circuit applies a gate signal whose gate pulse width Tp when a positive drain signal is applied by the signal line driving circuit is longer than a gate pulse width Tn when a negative drain signal is applied. The liquid crystal display device according to claim 1, wherein The gate pulse width is as follows when one horizontal scanning period is H.
Tp + Tn ≦ 2H
The liquid crystal display device according to claim 7, wherein the liquid crystal display device is set to be   Scan line sequential conversion means for distributing display data for each pixel to those written by positive drain signals and those written by negative drain signals and supplying the data to the signal line driver circuit is provided. The liquid crystal display device according to any one of claims 1 to 8. A liquid crystal display device provided with TFTs so as to correspond to each pixel arranged in a matrix direction,
A first scan line and a second scan line for driving pixels of different polarities connected to the gate of the pixel TFT;
The first scanning line is connected to TFTs of two adjacent pixels in the same pixel column,
2. The liquid crystal display device according to claim 1, wherein the second scanning line is connected to TFTs of two pixels located at one diagonal for every four pixels in two rows and two columns.   11. A scanning line driving circuit for applying a gate signal whose gate pulse width when a positive drain signal is applied is longer than a gate pulse width when a negative drain signal is applied. A liquid crystal display device according to 1.   12. The liquid crystal display device according to claim 10, wherein the pixels in the effective display area are driven to be inverted every two pixels in the column direction and every pixel in the row direction.   13. The liquid crystal display device according to claim 12, wherein when the effective display area is m columns and n rows, the number of source signal lines for driving the pixels is m + 1.   13. The liquid crystal display device according to claim 12, wherein when the effective display area is m columns and n rows, the number of source signal lines for driving the pixels is m.   13. The liquid crystal display device according to claim 12, wherein when the effective display area is m columns and n rows, the number of source drivers for driving the pixels is m + 1.   13. The liquid crystal display device according to claim 12, wherein when the effective display area is m columns and n rows, the number of source drivers for driving the pixels is m. A gate driver for a liquid crystal display device,
It consists of a shift register and multiple output circuits.
Each of the output circuits is connected to one of the first gate output enable signal line and the second gate output enable signal line in order to input a gate output enable signal for controlling the output. A gate driver characterized by that. A gate driver for a liquid crystal display device,
The first gate line driving pulse and the second gate line driving pulse having different pulse widths are divided into the gate line once each of the first gate line driving pulse and the second gate line driving pulse during two horizontal scanning periods. The scanning line has a high level voltage as a driving signal and generates a period in which neither gate line is driven between the first gate line driving pulse and the second gate line driving pulse. A gate driver characterized by output.   A liquid crystal display device comprising the gate driver according to claim 17. TFTs provided so as to correspond to the respective pixels arranged in the matrix direction, scanning lines that commonly connect the gates of the TFTs, signal lines that commonly connect the drains of the TFTs, and respective sources connected to the sources of the TFTs A pixel electrode of the pixel, a scanning line driving circuit for controlling a gate signal to the scanning line, a signal line driving circuit for controlling a drain signal to the signal line,
In the effective display area, TFTs are provided to repeat a predetermined TFT arrangement pattern,
The TFT arrangement pattern is such that the gates of the TFTs provided in the pixels Cx, y in the x rows and y columns of the effective display area are the p th scanning line of the effective display area, and the drain is the q th signal line of the effective display area. When noting that Ci, j = (p, q) is connected,
Ci, j = (i + 1, j), Ci, j + 1 = (i, j + 1),
Ci, j + 2 = (i + 1, j + 2), Ci, j + 3 = (i, j + 3),
Ci + 1, j = (i + 1, j + 1), Ci + 1, j + 1 = (i + 2, j + 1),
Ci + 1, j + 2 = (i + 1, j + 3), Ci + 1, j + 3 = (i + 2, j + 3),
Ci + 2, j = (i + 2, j), Ci + 2, j + 1 = (i + 3, j + 1),
Ci + 2, j + 2 = (i + 2, j + 2), Ci + 2, j + 3 = (i + 3, j + 3),
Ci + 3, j = (i + 4, j), Ci + 3, j + 1 = (i + 3, j + 2),
Ci + 3, j + 2 = (i + 4, j + 2), Ci + 3, j + 3 = (i + 3, j + 4)
A method for driving a liquid crystal display device having a pattern of
The signal line driving circuit includes pixels Ci, j, Ci, j + 2, Ci + 1, j, Ci + 1, j + 2 constituting the first pixel group,
Ci + 2, j + 1, Ci + 2, j + 3, Ci + 3, j + 1, Ci + 3, j + 3
Pixels Ci, j + 1, Ci, j + 3, Ci + 1, j + 1, Ci + 1, j + 3 constituting the second pixel group
Ci + 2, j, Ci + 2, j + 2, Ci + 3, j, Ci + 3, j + 2
Are driven by inversion by applying drain signals having opposite polarities to each other. TFTs provided so as to correspond to the respective pixels arranged in the matrix direction, scanning lines that commonly connect the gates of the TFTs, signal lines that commonly connect the drains of the TFTs, and respective sources connected to the sources of the TFTs A pixel electrode of the pixel, a scanning line driving circuit for controlling a gate signal to the scanning line, a signal line driving circuit for controlling a drain signal to the signal line,
In the effective display area, TFTs are provided to repeat a predetermined TFT arrangement pattern,
The TFT arrangement pattern is such that the gates of the TFTs provided in the pixels Cx, y in the x rows and y columns of the effective display area are the p th scanning line of the effective display area, and the drain is the q th signal line of the effective display area. When noting that Ci, j = (p, q) is connected,
Ci, j = (i, j), Ci, j + 1 = (i + 1, j + 1),
Ci, j + 2 = (i, j + 2), Ci, j + 3 = (i + 1, j + 3),
Ci + 1, j = (i + 2, j), Ci + 1, j + 1 = (i + 1, j + 2),
Ci + 1, j + 2 = (i + 2, j + 2), Ci + 1, j + 3 = (i + 1, j + 4),
Ci + 2, j = (i + 3, j), Ci + 2, j + 1 = (i + 2, j + 1),
Ci + 2, j + 2 = (i + 3, j + 2), Ci + 2, j + 3 = (i + 2, j + 3),
Ci + 3, j = (i + 3, j + 1), Ci + 3, j + 1 = (i + 4, j + 1),
Ci + 3, j + 2 = (i + 3, j + 3), Ci + 3, j + 3 = (i + 4, j + 3)
A method for driving a liquid crystal display device having a pattern of
The signal line driving circuit includes pixels Ci, j, Ci, j + 2, Ci + 1, j, Ci + 1, j + 2 constituting the first pixel group,
Ci + 2, j + 1, Ci + 2, j + 3, Ci + 3, j + 1, Ci + 3, j + 3
Pixels Ci, j + 1, Ci, j + 3, Ci + 1, j + 1, Ci + 1, j + 3 constituting the second pixel group
Ci + 2, j, Ci + 2, j + 2, Ci + 3, j, Ci + 3, j + 2
Are driven by inversion by applying drain signals having opposite polarities to each other. TFTs provided so as to correspond to the respective pixels arranged in the matrix direction, scanning lines that commonly connect the gates of the TFTs, signal lines that commonly connect the drains of the TFTs, and respective sources connected to the sources of the TFTs A pixel electrode of the pixel, a scanning line driving circuit for controlling a gate signal to the scanning line, a signal line driving circuit for controlling a drain signal to the signal line,
In the effective display area, TFTs are provided to repeat a predetermined TFT arrangement pattern,
The TFT arrangement pattern is such that the gates of the TFTs provided in the pixels Cx, y in the x rows and y columns of the effective display area are the p th scanning line of the effective display area, and the drain is the q th signal line of the effective display area. When noting that Ci, j = (p, q) is connected,
Ci, j = (i + 1, j + 1), Ci, j + 1 = (i, j + 1),
Ci, j + 2 = (i + 1, j + 3), Ci, j + 3 = (i, j + 3),
Ci + 1, j = (i + 1, j), Ci + 1, j + 1 = (i + 2, j + 1),
Ci + 1, j + 2 = (i + 1, j + 2), Ci + 1, j + 3 = (i + 2, j + 3),
Ci + 2, j = (i + 2, j), Ci + 2, j + 1 = (i + 3, j + 2),
Ci + 2, j + 2 = (i + 2, j + 2), Ci + 2, j + 3 = (i + 3, j + 4),
Ci + 3, j = (i + 4, j), Ci + 3, j + 1 = (i + 3, j + 1),
Ci + 3, j + 2 = (i + 4, j + 2), Ci + 3, j + 3 = (i + 3, j + 3)
A method for driving a liquid crystal display device having a pattern of
The signal line driving circuit includes pixels Ci, j, Ci, j + 2, Ci + 1, j, Ci + 1, j + 2 constituting the first pixel group,
Ci + 2, j + 1, Ci + 2, j + 3, Ci + 3, j + 1, Ci + 3, j + 3
Pixels Ci, j + 1, Ci, j + 3, Ci + 1, j + 1, Ci + 1, j + 3 constituting the second pixel group
Ci + 2, j, Ci + 2, j + 2, Ci + 3, j, Ci + 3, j + 2
Are driven by inversion by applying drain signals having opposite polarities to each other. TFTs provided so as to correspond to the respective pixels arranged in the matrix direction, scanning lines that commonly connect the gates of the TFTs, signal lines that commonly connect the drains of the TFTs, and respective sources connected to the sources of the TFTs A pixel electrode of the pixel, a scanning line driving circuit for controlling a gate signal to the scanning line, a signal line driving circuit for controlling a drain signal to the signal line,
In the effective display area, TFTs are provided to repeat a predetermined TFT arrangement pattern,
The TFT arrangement pattern is such that the gates of the TFTs provided in the pixels Cx, y in the x rows and y columns of the effective display area are the p th scanning line of the effective display area, and the drain is the q th signal line of the effective display area. When noting that Ci, j = (p, q) is connected,
Ci, j = (i, j), Ci, j + 1 = (i, j + 2),
Ci, j + 2 = (i, j + 2), Ci, j + 3 = (i + 1, j + 4),
Ci + 1, j = (i + 2, j), Ci + 1, j + 1 = (i + 1, j + 1),
Ci + 1, j + 2 = (i + 2, j + 2), Ci + 1, j + 3 = (i + 1, j + 3),
Ci + 2, j = (i + 3, j + 1), Ci + 2, j + 1 = (i + 2, j + 1),
Ci + 2, j + 2 = (i + 3, j + 3), Ci + 2, j + 3 = (i + 2, j + 3),
Ci + 3, j = (i + 3, j), Ci + 3, j + 1 = (i + 4, j + 1),
Ci + 3, j + 2 = (i + 3, j + 2), Ci + 3, j + 3 = (i + 4, j + 3)
A method for driving a liquid crystal display device having a pattern of
The signal line driving circuit includes pixels Ci, j, Ci, j + 2, Ci + 1, j, Ci + 1, j + 2 constituting the first pixel group,
Ci + 2, j + 1, Ci + 2, j + 3, Ci + 3, j + 1, Ci + 3, j + 3
Pixels Ci, j + 1, Ci, j + 3, Ci + 1, j + 1, Ci + 1, j + 3 constituting the second pixel group
Ci + 2, j, Ci + 2, j + 2, Ci + 3, j, Ci + 3, j + 2
Are driven by inversion by applying drain signals having opposite polarities to each other.   The scanning line driving circuit applies a gate signal whose gate pulse width Tp when a positive drain signal is applied by the signal line driving circuit is longer than a gate pulse width Tn when a negative drain signal is applied. 24. The method for driving a liquid crystal display device according to claim 20, wherein the liquid crystal display device is driven. The gate pulse width is as follows when one horizontal scanning period is H.
Tp + Tn ≦ 2H
25. The driving method of the liquid crystal display device according to claim 24, wherein the driving method is set to be The pixels in the first row of the effective display area are driven by dot inversion, and the pixels in the second and subsequent rows are driven by inversion with a polarity different from the polarity of the first row every two pixels in the column direction and every pixel in the row direction. And
A driving method of a liquid crystal display device, wherein a gate signal whose gate pulse width when a positive drain signal is applied is longer than a gate pulse width when a negative drain signal is applied is applied to a pixel.

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