KR20090004234A - Liquid crystal display device and driving method thereof - Google Patents

Abstract

A liquid crystal display device and driving method thereof is provided to save the manufacturing cost by reducing the number of data driver IC and to improve working efficiency by installing the data driver IC as a bank type in case of high resolution liquid crystal display. A liquid crystal display device includes a first substrate including a plurality of TFT, a second substrate one-to-one correspondence the unit pixel of the first substrate and liquid crystal filled between the first and second substrate. A gate driver(103) supplies a gate voltage by a control signal of a timing controller(113) of the gate voltage. A multiplexer(105) supplies specific pixel data through the selected switching device according to a control signal of the timing controller. A display panel(101) comprises the polysilicon type TFT in the intersection of n data lines of m gate lines.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND DRIVING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof for enabling the black and white image of a polysilicon liquid crystal display device having a multiplexer.

In general, the liquid crystal display device implements an image by controlling the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel. Here, the gate lines and the data lines are arranged to cross on the liquid crystal panel, and the liquid crystal cells are positioned in an area defined by the gate lines and the data lines intersecting. In addition, the liquid crystal panel is provided with a pixel electrode and a common electrode for applying an electric field to the respective liquid crystal cells. Each pixel electrode is connected to one of the data lines via the source and drain terminals of a thin film transistor (TFT), which is a switching element, and the gate terminal of the TFT has a pixel voltage signal of one pixel line. Are connected to any one of the gate lines to be applied to them.

The driving circuit includes a gate driver for driving gate lines, a data driver for driving data lines, and a common voltage generator for driving a common electrode. The gate driver sequentially supplies scanning signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line of the horizontal line, and the data driver each time a gate signal is supplied to any one of the gate lines. The video signal is supplied to the data lines, and the common voltage generator supplies the common voltage signal to the common electrode. As a result, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the video signal for each liquid crystal cell.

TFTs applied to such liquid crystal display devices are classified into amorphous silicon type and polysilicon type liquid crystal display devices according to which one of amorphous silicon and poly silicon is used as a semiconductor layer. The amorphous silicon TFT has an advantage that the amorphous silicon film is relatively uniform and the characteristics are stable, but it is difficult to apply when the pixel density is improved due to the relatively low charge mobility. In addition, in the case of using an amorphous silicon type TFT, peripheral driving circuits such as the gate driver and the data driver have to be manufactured separately and mounted on the liquid crystal panel, so that the manufacturing cost of the liquid crystal display device is high. On the other hand, the polysilicon TFT is not only difficult to increase the pixel density as the charge mobility is high, but also has the advantage of lowering the manufacturing cost since the peripheral driving circuits are embedded in the liquid crystal panel. In this regard, liquid crystal display devices employing polysilicon TFTs have been in the spotlight.

Hereinafter, a liquid crystal display device employing polysilicon will be described with reference to the accompanying drawings.

1 is a schematic configuration diagram of a general polysilicon liquid crystal display.

As shown in FIG. 1, a polysilicon liquid crystal display device includes a liquid crystal panel 10 including a gate driver 13 and an image display unit 11 formed of polysilicon, and a driving IC formed by a separate manufacturing process. (Integrated Circuit) is provided with a data driver 20 mounted on a polymer film in a TCP method, and a control unit 30 for controlling the gate driver 13 and the data driver 20.

First, the liquid crystal cells Clc are arranged in a matrix form on the image display unit 11 to display an image. Each liquid crystal cell Clc includes a switching element, that is, a TFT, formed at an intersection of a gate line GL and a data line DL. These TFTs use polysilicon 100 times faster than amorphous silicon, so the response speed to the signal is high. In addition, the data lines DL receive a video signal from the data driver 20 and the gate lines GL receive a scan pulse from the gate driver 13.

The controller 30 transmits pixel data supplied from the outside to the data driver 20 and provides driving control signals necessary for the data driver 20 and the gate driver 13.

The data driver 20 is configured of a plurality of shift registers (not shown), each having an output terminal connected to the data lines DL, to sequentially supply data pulses.

The gate driver 13 includes a plurality of shift registers (not shown), each having an output terminal connected to the gate lines GL. The shift registers sequentially supply scan pulses to the gate lines GL by shifting a start pulse from the controller 30.

However, in the conventional LCD having the above-described configuration, as the image display unit for implementing an image increases, the number of data lines increases in proportion to the number of data drive ICs. As a result, there is a limit to reducing the manufacturing cost of the liquid crystal display device.

In addition, in the case of a high resolution liquid crystal display device, since the pitch between subpixels is small, there is a limit in reducing the output pitch of a data drive IC mounted in a tape carrier package (TCP) method on a polymer film. In order to maintain the output pitch at an appropriate interval, a polymer film mounted with a data drive IC has to be attached to both sides of the liquid crystal panel in a double bank type, which is accompanied by the troublesome work.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a first object thereof is divided into subpixels of dot units corresponding to one horizontal line during one horizontal period of a polysilicon liquid crystal display having excellent charge mobility. An object of the present invention is to provide a liquid crystal display device having a multiplexer for outputting pixel data.

However, in the liquid crystal display according to the first object, the data stored for each subpixel is slightly different due to the coupling effect between the data lines whenever charging and discharging of adjacent data lines is implemented in the black and white image. Difficult image quality may occur.

Accordingly, the second object of the present invention is to form a plurality of gate lines that correspond to the number of sub pixels in dots per horizontal line of each liquid crystal display device and to connect the plurality of gate lines, and to apply a gate voltage to the gate lines and to form a multiplexer. An object of the present invention is to provide a liquid crystal display device that controls at least one switching element and outputs pixel data for each sub-pixel to which the gate voltage is applied.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a timing controller configured to receive data from outside and vertical / horizontal synchronization signals to generate data realignment and control signals; A gate driver sequentially supplying gate voltages for each sub-pixel in a dot unit for one horizontal period according to a control signal from the timing controller; A data driver for outputting data in accordance with a control signal from the timing controller; A plurality of switching elements connected to an output of the data driver are provided in a group, and the gate voltage is applied when at least one of the switching elements is controlled in synchronization with gate voltages applied to the subpixels. A multiplexer for outputting data to the subpixels; And a liquid crystal panel which implements an image according to output data from the multiplexer.

In addition, the driving method of the liquid crystal display device includes applying a first gate voltage on a first sub-pixel corresponding to one horizontal line during one horizontal period; Applying first data on the first subpixel; Shifting the first gate voltage to apply a second gate voltage on a second subpixel corresponding to one horizontal line during one horizontal period; Applying second data on the second subpixel; Shifting the second gate voltage to apply a third gate voltage onto a third subpixel corresponding to one horizontal line during one horizontal period; And applying third data on the third subpixel.

The liquid crystal display device according to the present invention can reduce the manufacturing cost by reducing the number of data drive ICs by providing a multiplexer, and in the case of a high-resolution liquid crystal display device, the data drive IC can be provided as a single bank type, thereby making it easier to work.便 易 性 can be planned.

In addition, the liquid crystal display according to the second exemplary embodiment of the present invention eliminates the coupling effect between adjacent data lines that occurs whenever the pixel data is charged and discharged for each sub-pixel in dot units when implementing a monochrome image. As a result, image quality can be improved.

Hereinafter, the configuration will be described in detail with reference to the accompanying drawings.

FIG. 2 is a configuration diagram of a liquid crystal display device according to a first embodiment of the present invention, and FIG. 3 is a partially enlarged view of portion A shown in FIG.

As shown in FIGS. 2 and 3, first, the liquid crystal panel 100 of the liquid crystal display according to the first exemplary embodiment of the present invention has a plurality of gate lines GL1 to GLn and data lines DL1 to DLm on a glass substrate. ) And a first substrate having a plurality of TFTs formed in a matrix form at the intersections of the gate lines GL1 to GLn and the data lines DL1 to DLm with each other. And a second substrate displaying monochrome in one-to-one correspondence with a unit pixel, and a liquid crystal filled between the first substrate and the second substrate.

Here, on the second substrate, chromium / chromium oxide (Cr /) may be formed at a corresponding portion to prevent light from being transmitted to the gate lines GL1 to GLn, the data lines DL1 to DLm, and the TFT on the first substrate. Black Matrix (CrOx) is provided. In addition, an overcoat layer for planarizing the black matrix and a common electrode are formed on the black matrix on the black matrix.

The gate driver 103 and the timing controller 113 which generate gate voltages Vgl and Vgh on the first substrate and apply the gate voltages Vgl and Vgh according to control signals from the timing controller 113. A multiplexer 105 for allowing specific pixel data among R, G, and B data to be applied for each sub-pixel through the switching devices SW1 to SW3 selected according to the control signal from the P-MOS (or N-). A pixel region is defined by data lines DL1 to DLm connected to the gate driver 103 having a MOS type and having gate lines GL1 to GLn formed to cross the gate lines GL1 to GLn. It is configured to include an image display unit 101.

Here, the image display unit 101 of the liquid crystal panel 100 includes a polysilicon TFT formed at an intersection of n gate lines GL1 to GLn and m data lines DL1 to DLm, respectively. And liquid crystal cells arranged in a matrix form. The TFT supplies the pixel data from the data lines DL1 to DLm to the liquid crystal cell in response to the gate pulses from the gate lines GL1 to GLn. Further, since the liquid crystal cell is composed of a common electrode on a second substrate facing each other with a liquid crystal interposed therebetween and a pixel electrode on a first substrate connected to the TFT, it can be equivalently represented by a liquid crystal capacitor Clc. Includes a storage capacitor connected to the gate lines GL1 to GLn of the previous stage in order to maintain the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged.

The multiplexer 105 uses a P-MOS (or N−) for each of the data lines DL1 to DLm connecting R, G, and B subpixels defined in the pixel area in units of dots (or pixels) to each subpixel. MOS) type switching elements SW1 to SW3 are provided. The multiplexer 105 has a plurality of switching elements SW1 to SW3 connected in parallel to respective latch stages formed in the data driver 150, that is, switching elements SW1 to SW3 provided for each of the data lines DL1 to DLm. Since the drain terminals of the respective FETs (Field Effect Transistors) are commonly connected to the outputs connected to the respective latches in the data driver 150, and each source terminal is connected to each of the subpixels forming a dot unit, Among the pixels, pixel data of the R subpixel, pixel data of the G subpixel, and pixel data of the B subpixel are respectively sequentially stored in a latch, and the corresponding switching turned on according to a control signal from the timing controller 113. Each subpixel is output through the device.

Of course, the switching elements SW1 to SW3 are preferably formed in accordance with the number of sub-pixels in dot units by connecting to each latch as shown in the drawing. However, the plurality of switching elements that form the multiplexer 105 in a group may vary depending on the circuit configuration, and thus the present invention will not be limited thereto.

Hereinafter, an image implementation method for implementing an image on the liquid crystal panel 100 having the above configuration will be described.

Pixel data R, G, and B suitable for the liquid crystal display may be supplied by a system driver (not shown) configured at a previous stage of the timing controller 113. At this time, the system driver converts the input pixel data R, G, and B to suit the resolution of the liquid crystal display and outputs the converted liquid crystal display. In addition, the system driver generates control signals such as a clock signal DCLK and vertical and horizontal synchronization signals Vsync and Hsync suitable for the resolution of the liquid crystal display.

The DC / DC converter 111 converts the DC voltage Vdc provided from the outside to generate at least one different DC voltage. In other words, the DC / DC converter 111 generates a power supply voltage Vdd for adjusting the liquid crystal transmittance in the LCD panel unit, or uses the common voltage signal provided from the DC / DC converter 111. In the figure, a common voltage Vcom is generated and provided to the LCD panel. In addition, it generates various voltages required for driving the LCD, such as generating gate voltages Vgl and Vgh for generating gate signal voltages. The power supply voltage Vdd generated from the DC / DC converter 111 is applied to a gamma voltage generation unit (not shown), where a plurality of gamma reference voltages Vref for driving the pixels of the liquid crystal panel 100 are used. ), And the gamma reference voltage Vref is provided to the data driver 150 again.

The timing controller 113 includes a data rearranging unit, a control signal generation unit, and the like, which are formed in a predetermined circuit therein. Here, the data rearranging unit receives and rearranges the pixel data R, G, and B from the system driver using the logic voltage Vlogic from the DC / DC converter 111 and rearranges the rearranged data. The control signal generator generates control signals for controlling timing of the gate driver 103 and the data driver 150 in response to the control signal from the system driver.

More specifically, the control signal generator in the timing controller 113 is a gate shift clock (GSC) and a gate output enable (GOE) as a control signal for controlling the gate driver 103. To generate a gate start pulse (GSP). Here, GSC is a signal that determines the time when the gate of the TFT is turned on / off. GOE is a signal that controls the output of the gate driver, and GSP is a signal indicating the first driving line of the screen out of one vertical synchronization signal.

In addition, the control signal generation unit as a control signal required for the data driver 150, Source Sampling Clock (SSC), Source Output Enable (SOE), Source Start Pulse (SSP) And generate a polarity reverse (POL), data polarity (REV), odd / even pixel data (Odd / Even Data) signal, and the like. Here, the SSC is used as a sampling clock to latch data in the data driver and determines the driving frequency of the data drive IC. The SOE allows the data latched by the SSC to be transferred to the liquid crystal panel. The SSP is a signal indicating the start of latching or sampling of data during one horizontal synchronization period. POL is a signal indicating the polarity to drive the liquid crystal positively and negatively for inversion driving of the liquid crystal. REV is a signal for selecting the polarity of the data to be transmitted, and odd / even pixel data are signals representing odd data of odd pixels and even data of even pixels.

In addition, the control signal generator generates control signals for controlling the individual switching elements SW1, SW2, and SW3 of the multiplexer 105 formed on the liquid crystal panel 100 in conjunction with the data driver 150. do. For example, the mux control signals MUX1, MUX2, and MUX3 may be a plurality of switching elements formed in a group corresponding to each subpixel in dot units during a horizontal period in which a gate voltage is applied to the first gate line GL1. The fields SW1 to SW3 are sequentially controlled. As a result, the pixel data of the R subpixel among the pixels corresponding to the first horizontal line is simultaneously output from the multiplexer 105, followed by the pixel data of the G subpixel and the pixel data of the B subpixel, respectively.

The gate driver 103 controls the gate terminals of the TFTs arranged on the liquid crystal panel 100 on / off line by line in response to the control signals input from the timing controller 113 to the data driver 150. The pixel voltage supplied through the selected switching element of the multiplexer 105 can be applied to the respective pixels connected to the TFTs.

The data driver 150 samples the digital pixel data R, G, and B from the timing controller 113, latches the data, and then uses an gamma voltage as an analog voltage that can represent gray scale in the liquid crystal cell. After the conversion, the converted voltage is applied to the liquid crystal panel 100. More specifically, the data driver 150 includes a memory 115 to which data (R, G, B) is input from the timing controller 113 to an external (or internal), a shift register for generating a sampling clock, And divides the first latch, the second latch, and the gamma reference voltages connected between the shift register and the m data lines DL1 through DLm to supply a digital to analog converter (DAC). Gray voltage circuit, digital / analog converter, and the like.

Here, the memory 115 temporarily stores the data R, G, and B from the timing controller 113, and then stores pixel data for each subpixel of R, G, and B among pixels corresponding to the one horizontal line. To the first latch sequentially.

The shift register shifts the source start pulse SSP from the timing controller 113 according to the source sampling clock SSC to generate a sampling signal. In addition, the shift register shifts the source start pulse SSP to transfer the carry signal CAR to the next shift register.

The first latch samples the digital pixel data R, G, and B from the memory 115 in response to the sampling signals sequentially input from the shift register, and horizontally converts the digital pixel data R, G, and B into one horizontal line. Of the pixels corresponding to the line, the pixel data of the R subpixel, the pixel data of the G subpixel, and the pixel data of the B subpixel are respectively latched in this order.

The second latch latches pixel data R, G, and B for each sub-pixel input from the first latch, and then latches the latched digital pixel data R, G, and B to the SOE signal from the timing controller 113. In response, data can be output at the same time. That is, the second latch simultaneously outputs the stored R pixel data onto the R subpixel among pixels corresponding to one horizontal line of the liquid crystal panel 100 and then stores the G pixel data stored again in the second latch. The B pixel data stored in the second latch is sequentially output to the corresponding subpixels.

The gamma gradation voltage circuit divides the gamma reference voltages firstly divided by the reference voltage generator using the voltage input from the DC / DC converter 111 to generate gamma gradation voltages corresponding to each gradation.

The DAC outputs a gradation voltage of the corresponding level supplied from the gamma gradation voltage circuit in response to the pixel data R, G, and B from the second latch. Of course, the gray scale voltage may be output as one of positive and negative voltages according to the polarity control signal from the timing controller 113.

FIG. 4 is a diagram illustrating a driving method of FIG. 2, which is a waveform diagram illustrating an operating state of a multiplexer versus a gate voltage during one horizontal period of a gate line.

As shown in FIG. 4, when the FET, which is a switching element, is formed in the P-MOS type, the gate low voltage generated by the gate driver 103 is generated in response to the control signal from the timing controller 113. Is applied. After the gate low voltage is applied in this manner, the first switching device SW1 to the third switching device SW3 are sequentially operated for one horizontal period. That is, all of the first switching elements SW1 formed on one horizontal line and corresponding to the R, G, and B subpixels forming the dot unit are simultaneously turned on and then turned off. And the first switching devices SW1 are turned off and all the second switching devices SW2 are turned on. At this time, the gate voltage is continuously applied to the R, G, and B subpixels forming the dot unit.

For example, when all of the first switching elements SW1 on the first horizontal line are turned on at the same time, pixel data of the R sub pixel among the pixels corresponding to the first horizontal line stored in the data driver 150 are output. do. Subsequently, when the pixel data of the R sub pixel corresponding to the first horizontal line is output, the first switching device SW1 is turned off and at the same time, the second switching device SW2 is turned on to the data driver 150. Pixel data of the G subpixel among the pixels corresponding to the first horizontal line stored are output. After the pixel data of the G subpixel corresponding to the first horizontal line is output, the second switching device SW2 is turned off and at the same time, the third switching device SW3 is turned on to turn on the data driver 150. Pixel data of the B sub-pixels among the pixels corresponding to the first horizontal line stored in the B-P is output.

In this manner, the pixel data of the R sub pixel, the pixel data of the G sub pixel, and the pixel data of the B sub pixel corresponding to the first horizontal line while the gate voltage is applied to and maintained in the first gate line GL1. Are sequentially applied to the corresponding subpixels, and are sequentially shifted back to the second gate line GL2 to the (n-1) th gate line GLn-1 in this manner, and the above operation is repeated. The pixel data of the R subpixel, the pixel data of the G subpixel, and the pixel of the B subpixel among the pixels corresponding to the first horizontal line while the gate voltage is applied to the nth gate line GLn and maintained. When data is applied to the corresponding subpixels, a unit frame image is implemented at this time.

However, in the LCD having the above configuration, when all of the first switching elements SW1 of the multiplexer 105 are turned on in the black and white image, data is output from the data driver 150 and applied to the corresponding subpixels. After that, when the first switching device SW1 is turned off and the second switching device SW2 is turned on, new data from the data driver 150 is output and applied to the corresponding subpixels. The data input through the one switching element SW1 is electrically floating while being stored in the storage capacitor through the data lines DL1 through DLm.

As a result, the pixel data value inputted for each subpixel may be slightly different due to the coupling effect between the data lines DL1 to DLm when charging and discharging pixel data through adjacent data lines DL1 to DLm. As a result, in the case of a black and white liquid crystal display device, a difference in the value may occur for each pixel data stored for each sub-pixel, and thus, an image quality defect of a periodic vertical dim may occur in the entire screen.

As part of the above solution, a liquid crystal display device according to a second embodiment of the present invention will be described below with reference to the accompanying drawings.

5 is a configuration diagram of a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 6 is a partially enlarged view of part B shown in FIG. 5.

5 and 6, the liquid crystal panel 200 of the liquid crystal display according to the second exemplary embodiment of the present invention has a plurality of gate lines GL1 to GLn and data lines DL1 to DLm on a glass substrate. And a first substrate having a plurality of TFTs formed in a matrix form at intersections of the gate lines GL1 to GLn and the data lines DL1 to DLm by crossing each other, and a unit of the first substrate. And a second substrate for implementing monochrome in one-to-one correspondence with the pixel, and a liquid crystal filled between the first substrate and the second substrate.

Here, on the second substrate, chromium / chromium oxide (Cr /) may be formed at a corresponding portion to prevent light from being transmitted to the gate lines GL1 to GLn, the data lines DL1 to DLm, and the TFT on the first substrate. A black matrix made of CrOx) is provided. Further, on the black matrix, an overcoat for planarization of the black matrix and a common electrode are formed on the overcoat layer, respectively.

The gate driver 203 and the timing controller 213 which generate gate voltages Vgl and Vgh on the first substrate and apply the gate voltages Vgl and Vgh according to a control signal from the timing controller 213. A multiplexer 205 for applying pixel voltages of specific data among R, G, and B data for each sub-pixel through the switching elements SW1 to SW3 selected according to the control signal from the P-MOS (or N). And a plurality of gate lines GL1a, GL1b, and GL1c are formed in a group for each horizontal line, and the plurality of gate lines GL1a and GL1b are connected to each other. And an image display unit 201 in which a pixel region is defined by data lines DL1 to DLm intersecting with GL1c.

More specifically, the image display unit 201 of the liquid crystal panel 200 includes a plurality of sub pixels arranged in a matrix to form a plurality of horizontal lines. The number of sub pixels forming a dot unit for each horizontal line, for example, "RGB. A plurality of gate lines GL1a, GL1b, and GL1c corresponding to three in the case of "RG4" and four in the case of "RGGB" are formed in a group to form n groups of gate lines GL1 to GLn as a whole. It is. In this case, each of the sub-gate lines GL1a, GL1b, and GL1c forming a group is connected to each subpixel in a dot unit, and thus, each of the first subgate lines GL1a and the first sub-gate line GL1 of the first group of gate lines GL1. The second sub gate line GL1b and the third sub gate line GL1c are electrically separated from each other, and a gate voltage is applied thereto. Further, m data lines DL1 to DLm are formed to cross the gate lines GL1 to GLn formed of the n groups.

In addition, the image display unit 201 of the liquid crystal panel 200 according to the second exemplary embodiment of the present invention has an intersection of the gate lines GL1 to GLn and m data lines DL1 to DLm forming n groups. And poly-silicon TFTs respectively formed on the substrates, and liquid crystal cells connected to the TFTs and arranged in a matrix. Here, the TFT sequentially supplies the pixel data from the data lines DL1 to DLm to the liquid crystal cell in response to the gate pulses of the gate lines GL1 to GLn. Further, since the liquid crystal cell is composed of a common electrode on a second substrate facing each other with a liquid crystal interposed therebetween and a pixel electrode on a first substrate connected to the TFT, it can be equivalently represented by a liquid crystal capacitor Clc. Includes a storage capacitor connected to the gate lines GL1 to GLn of the previous stage in order to maintain the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged.

The multiplexer 205 is a P-MOS (or N-MOS) type switching for each data line DL1 to DLm connected to each subpixel using R, G, and B subpixels defined in the pixel area in units of dots. The elements are connected and configured. The multiplexer 205 is a drain of a FET which is a switching device (SW1 to SW3) provided in parallel connection to each latch stage formed in the data driver 250, that is, for each of the data lines DL1 to DLm. Since the terminal is commonly connected to the output unit connected to each latch in the data driver 250, and the source terminal is connected to each of the sub-pixels in dots, the pixel data of the R sub-pixels among the pixels is interlocked. The pixel data of the G subpixel and the pixel data of the B subpixel are sequentially stored in the latch and output for each subpixel through the corresponding switching element turned on according to a control signal from the timing controller 213.

Of course, as described above, the switching elements SW1 to SW3 are preferably formed in accordance with the number of subpixels connected to each latch in units of dots. However, since the multiplexer 205 can be configured by forming switching elements below or above, the present invention will not be limited thereto.

FIG. 7 is a diagram illustrating a driving method of FIG. 5, which is a waveform diagram illustrating an operating state of a multiplexer compared to one horizontal period of a group of gate lines.

5 to 7, when the FETs, which are the switching elements SW1 to SW3, are formed in the P-MOS type, the gate low voltage generated by the gate driver 203 according to the control signal from the timing controller 213 is reduced. When sequentially applied to each of the first group of sub gate lines GL1a, GL1b, and GL1c during one horizontal period, the gate row voltages of the respective sub gate lines GL1a, GL1b, and GL1c are synchronized with each other on one horizontal line. All of the first to third switching devices SW1 to SW3 are sequentially turned on and then turned off.

For example, when the gate low voltage is applied to the first sub-gate line GL1a of the first group and all the first switching elements SW1 on the first horizontal line are turned on, the data is stored in the data driver 250 at the same time. Pixel data of the R sub-pixels among the pixels corresponding to the first horizontal line that existed are output. Subsequently, when the gate high voltage is applied to the first sub gate line GL1a of the first group and the first switching device SW1 is turned off, the gate low voltage is applied to the second sub gate line GL1b of the first group. At the same time, the second switching device SW2 is turned on to output pixel data of the G subpixel among pixels corresponding to the first horizontal line stored in the data driver 250. In addition, when the gate high voltage is applied to the second sub gate line GL1b of the first group and the second switching device SW2 is turned off, the gate low voltage is applied to the third sub gate line GL1c of the first group. At the same time, the third switching device SW3 is turned on and the pixel data of the B subpixel among the pixels corresponding to the first horizontal line stored in the data driver 250 are output and applied to the corresponding subpixels. do.

In this manner, when the gate low voltage is applied by sequentially shifting from the first subgate line GL1a of the first group to the third subgate line GLnc of the nth group, the first horizontal line is simultaneously applied. The pixel data of the R subpixel, the pixel data of the G subpixel, and the pixel data of the B subpixel among the corresponding pixels are sequentially output from the data driver 250 to the image display unit 201 to realize a unit frame image. do.

Based on the above, the channel of the switching element for driving the mux circuit of the multiplexers 105 and 205 is composed of polysilicon or similar micro crystalline having a high electron mobility of 10 cm 2 / Vsec or more. It is desirable to be.

However, in the case where the channel of the switching element constituting each pixel of the image display units 101 and 201 of the liquid crystal panel 100 and 200 uses amorphous silicon, the amorphous silicon may be locally subjected to laser or heat treatment to form a mux circuit. May be formed of polysilicon or microcrystals.

1 is a block diagram of a polysilicon liquid crystal display device according to the prior art

2 is a configuration diagram of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 3 is a partially enlarged view of A shown in FIG. 2. FIG.

FIG. 4 is a diagram illustrating a driving method of FIG. 2 and illustrates a waveform diagram illustrating an operating state of a multiplexer compared to one horizontal period of a gate line. FIG.

5 is a configuration diagram of a liquid crystal display according to a second embodiment of the present invention.

FIG. 6 is an enlarged view of a portion B of FIG. 5; FIG.

FIG. 7 is a diagram illustrating a driving method of FIG. 5 and illustrates waveforms of an operating state of a multiplexer compared to one horizontal period of a gate line of each group; FIG.

Claims (12)

A timing controller configured to receive data from the outside and vertical / horizontal synchronization signals to generate data realignment and control signals; A gate driver sequentially supplying gate voltages for each sub-pixel in dot units for one horizontal period according to a control signal from the timing controller; A data driver for outputting data in accordance with a control signal from the timing controller; A plurality of switching elements connected to an output of the data driver are provided in a group, and the gate voltage is applied when at least one of the switching elements is controlled in synchronization with the gate voltages applied to the subpixels. A multiplexer for outputting data to the subpixels; And And a liquid crystal panel for realizing an image according to output data from the multiplexer. The liquid crystal display device according to claim 1, wherein the liquid crystal panel is formed of a polysilicon type including a gate driver and a multiplexer. The liquid crystal display device according to claim 1, wherein the plurality of switching elements are provided for each data line such that a drain terminal is commonly connected to a latch of the data driver, and a source terminal is connected to each subpixel. The liquid crystal display of claim 1, wherein the sub-pixels in dot units are R, G, and B pixels. A plurality of sub pixels formed in a matrix in dot units; A plurality of gate lines formed to match the number of sub-pixels in dots for each horizontal line formed by the plurality of sub-pixels; Data lines intersecting the gate lines and connected to the sub-pixels, respectively; A gate driver connected to a plurality of gate lines formed for each of the horizontal lines, and sequentially applying a gate voltage to each gate line; And A plurality of switching elements formed in a group on one side of a data line connected to the sub-pixels in the dot unit, and at least one of the switching elements may be controlled in synchronization with a gate voltage applied to the sub-pixels. And a multiplexer configured to output data for each subpixel to which the gate voltage is applied. The liquid crystal panel of claim 5, wherein the gate driver and the multiplexer are made of polysilicon. 6. The liquid crystal display device according to claim 5, wherein the plurality of switching elements are provided for each data line such that a drain terminal is commonly connected to a latch of the data driver, and a source terminal is connected to each subpixel. 6. The liquid crystal panel of claim 5, wherein the sub-pixels in dot units are R, G, and B pixels. Applying a first gate voltage on a first subpixel corresponding to one horizontal line during one horizontal period; Applying first data on the first subpixel; Shifting the first gate voltage to apply a second gate voltage on a second subpixel corresponding to one horizontal line during one horizontal period; Applying second data on the second subpixel; Shifting the second gate voltage to apply a third gate voltage onto a third subpixel corresponding to one horizontal line during one horizontal period; And applying third data onto the third subpixel. 10. The method of claim 9, wherein the first data on the first subpixel is R data. 10. The method of claim 9, wherein the second data on the second subpixel is G data. 10. The method of claim 9, wherein the third data on the third subpixel is B data.

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