KR20170023239A - Flat Panel Display Having Narrow Bezel - Google Patents

Abstract

The present invention relates to a flat panel display in which a width of a top or bottom bezel region is reduced to maximize a display region. According to the present invention, the flat panel display includes a substrate, a display region, a non-display region, a pad connection region, and a tape carrier package. The display region is defined as a region that displays video display information on the substrate. The non-display region is defined in a periphery of the display region on the substrate, and includes a pad region and a link region. The pad region is disposed adjacent to one side of the substrate. The link region extends from the pad region to the display region by a first distance. The pad connection region overlaps with an entire pad region and at least a part of the link region. The tape carrier package is attached to the substrate while facing the substrate such that the tape carrier package overlaps the pad connection region.

Description

[0001] The present invention relates to a flat panel display having a narrow bezel structure,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device in which a width of a top or bottom bezel region is reduced to maximize a display area. Particularly, the present invention relates to a flat panel display device having a narrow bezel structure in which the width of a top / bottom bezel region is reduced by minimizing a region of a driving connection portion connected to a top side and / or a bottom side in a flat panel display device.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. As a result, it has rapidly developed into a flat panel display device (FPD) capable of replacing a bulky cathode ray tube (CRT) with a thin, light and large area. The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display device : ED) have been developed and utilized.

A flat panel display device displays an image using a gate driving circuit for supplying a scan signal to gate wirings of a display panel and a data driving circuit for supplying a data voltage to the data wirings. For example, the gate driving circuit is formed by a TAB (Tape Automated Bonding) method in which a printed circuit board mounting a plurality of gate drive integrated circuits is mounted on a display panel.

1 is a plan view showing a schematic structure of a flat panel display device formed by a conventional TAB method. Referring to FIG. 1, a data driver DIC connected to a data line of the display panel DPL is disposed on one side of the upper end of the display panel DPL in a TAB manner. That is, the data driver DIC is mounted on a tape carrier package (TCP) TP, and one side of the tape carrier package TP is mounted on one side of the upper portion of the display panel DPL. Lt; / RTI > On one side of the left side of the display panel DPL, a gate driver GIP connected to the gate line is directly disposed on the substrate. A control unit TCON for controlling the data driver DIC and the gate driver GIP and a power supply unit PIC for supplying power are mounted on a printed circuit board PCB and a tape carrier The pad portion of the printed circuit board (PCB) is connected to the other side of the package TP.

The display panel DPL constituting the flat panel display device having such a structure includes a thin film transistor substrate on which thin film transistors allocated in a pixel region arranged in a matrix manner are arranged. For example, a liquid crystal display device (LCD) displays an image by adjusting the light transmittance of a liquid crystal using an electric field. In the case of an organic light emitting diode display (OLED), an image is displayed by adjusting the amount of light emitted from the organic light emitting layer interposed between the anode electrode and the cathode electrode.

The bezel area corresponds to the non-display area NA of the side surface on which the gate driver GIP is formed and the non-display area NA of the top side to which the tape carrier package TP is attached. Although FIG. 1 shows the case where the gate driver GIP is disposed only on the left side, the gate driver GIP may be disposed on the right side, and the left and right bezel regions may have substantially the same area. 1 shows a case where the tape carrier package TP is disposed only on the upper side, but in some cases, the tape carrier package TP may be disposed only on the lower side or on both the upper side and the lower side.

In the flat panel display device shown in Fig. 1, the gate driver may be formed directly on the display panel DPL to provide a structure in which the bezel areas on the left and / or right sides are minimized. However, as shown in FIGS. 2 and 3, no specific structure for achieving the narrow bezel has yet been proposed for the upper and / or lower bezel regions to which the data driver is connected.

It is an object of the present invention to provide a flat panel display device having a narrow bezel structure, which is designed to overcome the above problems. Another object of the present invention is to provide a flat panel display device having a narrow bezel structure in which a bezel region on the upper side and / or a lower side of a substrate is minimized by disposing a pad region to which a tape carrier package is attached in a superposed relationship with a link region .

In order to achieve the object of the present invention, the flat panel display according to the present invention includes a substrate, a display region, a non-display region, a pad connection region, and a tape carrier package. The display area is defined as an area that represents video display information on the substrate. The non-display area is defined around the display area on the substrate. Further, the non-display area includes a pad area and a link area. The pad region is disposed adjacent to one side of the substrate. The link area extends a first distance from the pad area to the display area. The pad connection area is disposed over the entire pad area and at least a part of the link area. A tape carrier package is attached opposite the substrate to overlap the pad connection area.

For example, it further includes a pad electrode, a link wiring, a pad terminal, and a tape carrier pad terminal. The pad electrode is disposed in the pad region. The link wiring is disposed in the link region and extends from one end of the pad electrode to the display region. The pad terminals are in surface contact with the pad electrodes, overlapping the link wirings, and disposed in the pad connection region. The tape carrier pad terminal is disposed in the tape carrier package and is connected to the pad terminal via a conductive paste.

For example, the tape carrier pad terminals have the same size and the same shape as the pad terminals, and are arranged so as to face each other.

For example, it further includes an insulating film and a pad contact hole. The insulating film covers the pad electrode and the link wiring. The pad contact hole exposes most of the pad electrode in the insulating film. The pad terminal is disposed on the insulating film, is in surface contact with the pad electrode through the pad contact hole, and overlaps the link wiring with the insulating film therebetween.

In one example, the insulating film includes at least one stacked insulating layer containing an organic insulating material.

In one example, the pad terminal is arranged overlapping at least a part of the link wiring extending from the pad electrode and at least a part of the second link wiring neighboring the link wiring.

As an example, it further includes a multiplex area. The multiplex area extends a second distance from the link area to the display area.

The present invention can realize a flat panel display device in which the upper side and / or the lower side bezel area of the display panel is minimized. Further, the present invention can minimize the bezel area on the upper or lower side of the display device by changing the structure of the pad area so as to overlap the tape carrier package attached to the upper and / or lower sides of the display panel with the link area. Therefore, it is possible to realize a flat panel display in which not only the left and right bezel areas of the display panel but also the upper and lower bezel areas are minimized.

1 is a plan view showing a schematic structure of a flat panel display device formed by a conventional TAB method.
2 is a plan view showing the structure of a display panel with a tape carrier package according to a first embodiment of the present invention;
FIG. 3 is a cross-sectional view showing the structure of the upper bezel region cut in the cutting line I-I 'in FIG. 2 in detail.
4 is a plan view showing the structure of a display panel with a tape carrier package according to a second embodiment of the present invention.
5 is a cross-sectional view showing in detail the structure of the upper bezel region cut into a perforated line II-II 'in FIG. 4;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, a detailed description of known technologies or configurations related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured.

≪ Embodiment 1 >

Hereinafter, a first embodiment of the present invention will be described with reference to Figs. 2 and 3. Fig. 2 is a plan view showing the structure of a substrate SUB of a display panel DPL with a tape carrier package according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view showing the structure of the upper bezel region cut in the cutting line I-I 'in FIG. 2 in detail.

The surface of the substrate SUB includes a display area AA for displaying image information and a non-display area NA disposed on the upper side of the display area. Though not shown in the drawings, the thin film transistors and the pixel electrodes are arranged in a matrix manner in the display area AA. The non-display area NA is an area in which image information is not displayed, and a pad connection area COF, a link area LINK, and a multiplex area MUX for supplying a signal to the display area AA are arranged . The non-display area NA is defined as a bezel area BZ.

A pad terminal DPT and a pad electrode DP for connecting to the tape carrier package TP are disposed in the pad connection region COF. The tape carrier package TP has a tape carrier wiring TPL and a tape carrier pad TPT in order to transmit signals to the display panel DPL. The tape carrier pad TPT is disposed at the end of the tape carrier wiring TPL and is disposed opposite to the pad terminal DPT with almost the same size. The tape carrier package TP is bonded by the pad connection area COF and the conductive paste CA. A large amount of conductive balls are contained in the conductive paste (CA), and this conductive ball electrically connects the tape carrier pad (TPT) and the pad terminal (DPT).

The tape carrier pads TPT and the pad terminals DPT of the tape carrier package TP must have a minimum contact area in order to maintain an intact adhesive force. The contact areas have the same size and are determined by the width and length of the opposing tape carrier pads TPT and the pad terminals DPT. For convenience, only the width and length of the pad terminal DPT will be described below.

The width of the pad terminal (DPT) is gradually reduced. Therefore, in order to secure the contact area, the length of the pad terminal (DPT) must be sufficient. In consideration of the display device density specification and the patterning technique, the length of the pad terminal (DPT) should be at least 1,000 탆. As a result, the pad area (COF) must be at least 1,100 μm long.

The link area LINK is formed by arranging the link wirings LN, LN + 1, LN + 2, LN + 3, ... for transferring the signal applied from the pad terminal DPT to the display area AA do. The link wirings may be formed of a gate electrode material or a source-drain electrode material disposed in the display area AA. The link wirings LN, LN + 1, LN + 2, LN + 3, ... are formed in a sparse shape because they are formed to be narrower than the entire width of the pad connection region COF and the width of the display region AA. Respectively. Since the link wirings LN, LN + 1, LN + 2, LN + 3, ... are effectively arranged, a sufficient length must be ensured. It is preferable that the link area LINK has a length of at least 1,400 mu m.

In the multiplex area, a plurality of elements for distributing a signal received via the link area LINK to the display area AA are arranged. Although not shown in the figure, a thin film transistor may be disposed. The multiplex region preferably has a length of at least 700 mu m.

It is advantageous in terms of the use side and the product design side that the display area AA in the same display panel DPL has the maximum size. Therefore, a narrow bezel structure with a minimized bezel area is required. As described above, even if all the fine pattern technologies developed up to now are applied, the upper bezel BZ, which is the upper non-display area of the display panel DPL, can be ensured to be about 3,200 mu m, thereby achieving a narrow bezel structure.

Referring to FIG. 3, the sectional structure of the bezel region BZ is as follows. The pad electrode DP, the link wirings LN, LN + 1, LN + 2, LN + 3, ..., and the multiplex MUX are disposed on the substrate SUB. The multiplex MUX is connected to a wiring connected in the display area AA. The link wirings LN, LN + 1, LN + 2, LN + 3, ... have a wiring structure connected by a multiplexer (MUX). The pad electrode DP is disposed at the end of each of the link wirings LN, LN + 1, LN + 2, LN + 3, ....

The insulating film IN is covered on the upper surface of the pad electrode DP, the link wirings LN, LN + 1, LN + 2, LN + 3, ..., the multiplex MUX and the display area AA have. The pad electrode DP is mostly exposed by the pad contact hole DPH passing through the insulating film IN. A pad terminal (DPT) is formed on the insulating film (IN). The pad terminal DPT makes surface contact with the pad electrode DP through the pad contact hole DPH.

As described above, the pad connection area COF for connecting the tape carrier package TP is secured. Both the link area LINK and the multiplex area MUX are included in the bezel area BZ. As a result, a narrow bezel structure in which the bezel region BZ is defined with a length of 3,200 mu m can be achieved.

However, a structure having a narrower bezel area than the first embodiment of the present invention is required. In the first embodiment, the pad region PAD and the pad connecting region COF have substantially the same size. In the second embodiment, the pad connecting area COF is arranged so as to overlap not only the pad area PAD but also a part of the link area LINK to provide a narrow bezel structure in which the bezel area BZ is further reduced do.

≪ Embodiment 2 >

Hereinafter, a second embodiment of the present invention will be described with reference to Figs. 4 is a plan view showing a structure of a display panel with a tape carrier package according to a second embodiment of the present invention. 5 is a cross-sectional view illustrating the structure of the upper bezel region cut in the cutting line II-II 'in FIG.

The substrate SUB includes a display area AA for displaying image information defined on its surface and a non-display area NA disposed around the display area. The display area AA occupies most of the substrate SUB. The non-display area NA is disposed on at least one of the upper side, the lower side, the left side and / or the right side of the display area AA. Though not shown in the drawings, the thin film transistors and the pixel electrodes may be arranged in the display area AA in a matrix manner. The non-display area NA is an area which does not display image information and includes a pad area PAD, a link area LINK and a multiplex area MUX for supplying a signal to the display area AA. Particularly, in the present invention, the entire pad area PAD and a part of the link area LINK are defined as a pad connection area COF. The non-display area NA is defined as a bezel area BZ.

A pad electrode DT is disposed in the pad region PAD. It is preferable that the pad electrode DT has a size capable of maintaining minimum contact with the pad terminal DPT. For example, it is necessary to ensure a sufficient contact area such that the contact resistance does not increase so that the voltage of the electric signal transmitted from the pad terminal (DPT) does not change. Therefore, it is preferable that at least the length of the pad electrode DT is secured to 400 mu m.

The link region LINK includes link interconnections LN, LN + 1, LN + 2, LN + 3, ... for transferring a signal applied through the pad electrode DT to the display region AA . The link wirings may be formed of a gate electrode material or a source-drain electrode material disposed in the display area AA. The link wirings LN, LN + 1, LN + 2, LN + 3, ... are diffused in a corrugated shape because the total width of the pad area PAD is significantly different from the width of the display area AA . Since the link wirings LN, LN + 1, LN + 2, LN + 3, ... are effectively arranged, a sufficient length must be ensured. It is preferable that the link area LINK has a length of at least 1,400 mu m.

In the multiplex area, a plurality of elements for distributing a signal received via the link area LINK to the display area AA are arranged. Although not shown in the figure, a thin film transistor may be disposed. With current technology, a multiplexed (MUX) region must have a length of at least 700 μm.

A key feature of the present invention is that the pad connection area (COF) is disposed over the pad area (PAD) and the link area (LINK). For example, the pad connecting area COF is disposed over the entire pad area PAD and at least a part of the area of the link area LINK.

A pad terminal (DPT) for connection with the tape carrier package (TP) is disposed in the pad connection area (COF). The tape carrier package TP has a tape carrier wiring TPL and a tape carrier pad TPT in order to transmit signals to the display panel DPL. The tape carrier pad TPT is disposed at the end of the tape carrier wiring TPL and is disposed opposite to the pad terminal DPT with almost the same size. The tape carrier package TP is bonded by the pad connection area COF and the conductive paste CA. A large amount of conductive balls are contained in the conductive paste (CA), and this conductive ball electrically connects the tape carrier pad (TPT) and the pad terminal (DPT).

The tape carrier pads TPT and the pad terminals DPT of the tape carrier package TP must have a minimum contact area in order to maintain an intact adhesive force. The contact areas have the same size and are determined by the width and length of the opposing tape carrier pads TPT and the pad terminals DPT. For convenience, only the width and length of the pad terminal DPT will be described below.

The width of the pad terminal (DPT) is gradually reduced. Therefore, in order to secure the contact area, the length of the pad terminal (DPT) must be sufficient. Considering the current display device density specification and pattern technology, the length of the pad terminal (DPT) can be formed to be at least 1,100 μm. Particularly, in the present invention, the pad terminal DPT is arranged so as to overlap the entire pad electrode DT and at least any part of the link interconnections LN, LN + 1, LN + 2, LN + 3, .

Therefore, even when the length of the pad connecting region COF is 1,100 mu m, which is a sufficient length, the pad region PAD is smaller than the pad connecting region COF, so that the length of the bezel region BZ is 2,500 Mu m or less.

Referring to FIG. 5, the sectional structure of the bezel region BZ is as follows. The pad electrode DP, the link wirings LN, LN + 1, LN + 2, LN + 3, ..., and the multiplex MUX are disposed on the substrate SUB. The multiplex MUX is connected to a wiring connected in the display area AA. The link wirings LN, LN + 1, LN + 2, LN + 3, ... have a wiring structure connected by a multiplexer (MUX). The pad electrode DP is disposed at the end of each of the link wirings LN, LN + 1, LN + 2, LN + 3, ....

The insulating film IN is covered on the upper surface of the pad electrode DP, the link wirings LN, LN + 1, LN + 2, LN + 3, ..., the multiplex MUX and the display area AA have. The pad electrode DP is mostly exposed by the pad contact hole DPH passing through the insulating film IN. A pad terminal (DPT) is formed on the insulating film (IN). The pad terminal DPT makes surface contact with the pad electrode DP through the pad contact hole DPH. Particularly, the pad terminal DPT has a structure extending over the insulating film IN so as to overlap with a part of the link wirings LN, LN + 1, LN + 2, LN + 3,.

In other words, the pad electrode DP is formed to have a minimum size of 400 mu m that can ensure contact resistance with the pad terminal DPT. On the other hand, the pad terminal DPT is formed to be 1,100 mu m so as to maintain sufficient surface contact with the pad terminal TPT of the tape carrier package TP. In order to ensure a sufficient length of the pad terminal DPT, the pad terminal DPT is formed such that the link wirings LN, LN + 1, LN + 2, LN + 3, Extended.

The pad terminal (DPT) is connected to the pad electrode (DT) disposed at the end of one of the link wirings (LN). Therefore, even if the pad terminal DPT is overlapped with the link wiring LN, there is no great problem. However, if the pad terminal DPT is overlapped with any one of the adjacent neighboring interconnect wirings LN + 1, LN + 2, and LN + 3, a parasitic capacitance may be generated to cause a problem in signal transmission. In this case, when the insulating film IN is made of an organic insulating material having a low dielectric constant, or when a multilayered structure in which an inorganic insulating film and an organic insulating film are laminated is used, generation of parasitic capacitance can be suppressed. In particular, in the structure in which the color filter is directly formed on the thin film transistor substrate, the pad terminal DPT may be formed on the insulating film IN and the color filter. In this structure, even if the pad terminal DPT is arranged so as to overlap the neighboring link wirings LN + 1, LN + 2, LN + 3, no distortion occurs in signal transmission.

Although not shown in the drawings, the link region LINK can be formed by narrowing the link region LINK within a length region of 1,000 m or less. Also in this case, the pad terminal DPT can be arranged so as to overlap the link region LINK and the multiplex region MUX. As a result, it is possible to achieve a narrow bezel structure in which the bezel region is further reduced while ensuring a sufficient adhesion force between the pad terminal DPT and the tape carrier package TP.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

SUB: Substrate DPL: Display panel
DP: pad electrode DPT: pad terminal
DPH: pad contact hole IN: insulating film
AA: display area NA: non-display area
BZ: Bezel area COF: Pad connection area
LINK: Link area MUX: Multiplex (area)
PAD: Pad area

Claims (7)

Board;
A display area defined on the substrate;
A non-display area defined around the display area on the substrate, the non-display area including a pad area disposed adjacent to one side of the substrate and a link area extending from the pad area to the display area by a first distance;
A pad connection area disposed over the entire pad area and at least a part of the link area; And
And a tape carrier package mounted opposite to the substrate so as to overlap with the pad connection region.
The method according to claim 1,
A pad electrode disposed in the pad region;
A link wiring disposed in the link region and extending from one end of the pad electrode to the display region;
A pad terminal which is in surface contact with the pad electrode and which overlaps with the link wiring, and which is disposed in the pad connection region; And
And a tape carrier pad terminal disposed on the tape carrier package and connected to the pad terminal via a conductive paste.
3. The method of claim 2,
Wherein the tape carrier pad terminals have the same size and the same shape as the pad terminals and are arranged so as to be opposed to each other.
3. The method of claim 2,
An insulating film covering the pad electrode and the link wiring; And
And a pad contact hole exposing most of the pad electrode in the insulating layer,
Wherein the pad terminal is disposed on the insulating film and is in surface contact with the pad electrode through the pad contact hole and overlapped with the link wiring with the insulating film interposed therebetween.
5. The method of claim 4,
Wherein the insulating layer is formed by stacking at least one insulating layer containing an organic insulating material.
5. The method of claim 4,
Wherein the pad terminal comprises:
And a plurality of second wiring wirings adjacent to the link wirings, and at least a part of the second wiring wirings adjacent to the link wirings.
The method according to claim 1,
Further comprising: a multiplex area extending a second distance from the link area to the display area.

Images