KR102433358B1 - Display device - Google Patents

Abstract

A display device according to an embodiment of the present invention includes a substrate, a plurality of high-potential voltage wires disposed on the substrate, a plurality of low-potential voltage wires and a plurality of LEDs, a plurality of first link wires disposed under the substrate, and a plurality of a plurality of first auxiliary wirings and a plurality of second link wirings connected to the first link wiring of of side wiring. Accordingly, it is possible to reduce the number of masks required to form various wirings disposed in the display device.

Description

display device {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device using a Light Emitting Diode (LED) and having reduced production costs.

Liquid crystal display devices (LCDs) and organic light emitting display devices (OLEDs), which have been widely used up to now, are gradually expanding their application ranges.

Liquid crystal displays and organic light emitting display devices are widely applied to screens of everyday electronic devices, for example, cell phones, laptops, etc. due to their advantages of being able to provide high-resolution screens and being lightweight and thin is expanding

However, the liquid crystal display device and the organic light emitting display device have a limit in reducing the size of a bezel region recognized by a user as a region in which an image is not displayed in the display device. For example, in the case of a liquid crystal display, since a sealant must be used to seal the liquid crystal and bond the upper and lower substrates together, there is a limit to reducing the size of the bezel area. In addition, in the case of an organic light emitting diode display, since the organic LED is made of an organic material and is very vulnerable to moisture or oxygen, an encapsulation for protecting the organic LED must be disposed, so there is a limitation in reducing the size of the bezel area. In particular, since it is impossible to implement a super-large screen as a single panel, when a plurality of liquid crystal display panels or a plurality of organic light emitting display panels are arranged in a tile form to implement a super-large screen, bezels between adjacent panels There may be a problem that the area is recognized by the user.

As an alternative to this, a display device including an LED has been proposed. Since the LED is made of an inorganic material rather than an organic material, it has excellent reliability and thus has a longer lifespan compared to a liquid crystal display device or an organic light emitting display device. In addition, LED is a device suitable for application to very large screens because it not only has a fast lighting speed, but also consumes less power, has excellent stability due to strong impact resistance, and can display high-brightness images.

Accordingly, an LED element is generally used in a display device for providing an extra-large screen capable of minimizing a bezel area.

According to the inventors of the present invention, since LEDs have better luminous efficiency than organic LEDs, in the case of a display device including an LED, the size of one pixel, that is, in order to emit light of the same luminance, compared to a display device using an organic LED. It has been recognized that the size of the required light emitting area is very small. Accordingly, the inventors of the present invention found that when a display device is implemented using an LED, the distance between the emission regions of adjacent pixels is greater than the distance between the emission regions of adjacent pixels in the organic light emitting display device having the same resolution. I realized it was very long. Accordingly, the inventors of the present invention, when implementing a tiling display implemented by arranging a plurality of panels in a tile form, the distance between the outermost LED of one panel and the outermost LED of the other adjacent panel is one It was recognized that it is possible to implement a zero bezel in which there is practically no bezel area because it can be implemented to be the same as the distance between the LEDs in the panel.

However, as described above, in order to realize the distance between the outermost LED of one panel and the outermost LED of another adjacent panel to be the same as the distance between the LEDs in one panel, in the prior art, the upper surface of the panel Various drivers, such as the gate driver and the data driver, which were positioned in the , should be positioned on the rear surface of the panel instead of on the upper surface of the panel. Accordingly, the inventors of the present invention have arranged devices such as transistors and LEDs, data wiring, gate wiring, high potential voltage wiring and low potential voltage wiring, etc. A technique for arranging the above voltage link wiring and the low potential voltage link wiring was invented.

In addition, the inventors of the present invention have invented a high potential voltage link wiring and an auxiliary wiring connected to the low potential voltage link wiring in order to reduce the voltage drop of the high potential voltage and the low potential voltage transmitted to the plurality of pixels. However, when an additional process is required to form the auxiliary wiring, a mask for forming the auxiliary wiring must be added, and if the number of masks is increased, the time and cost required for the manufacturing process of the display device increases, resulting in a problem. can be

Accordingly, the inventors of the present invention implement a zero bezel and change the arrangement of the high-potential voltage link wiring and the low-potential voltage link wiring to reduce the number of masks required to form the wiring, thereby reducing the time and cost required for the process. A display device having a new structure that can reduce the size of the display has been invented.

The problem to be solved by the present invention is to minimize the number of masks used to form the various link wirings by all of the various link wirings arranged on the rear surface of the panel made of the same material and arranged on the same layer, and thus, the process cost It is to provide a display device that is reduced in size.

In addition, another problem to be solved by the present invention is to provide a display device capable of reducing the cost of the flexible film by all of a plurality of wirings arranged on the flexible film bonded to the substrate being made of the same material and arranged in a single layer will do

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, a display device according to an embodiment of the present invention provides a substrate, a plurality of high-potential voltage wires, a plurality of low-potential voltage wires and a plurality of LEDs disposed on the substrate, and a plurality of LEDs disposed under the substrate a plurality of first link wirings, a plurality of first auxiliary wirings and a plurality of second link wirings connected to the plurality of first link wirings, a plurality of high-potential voltage wirings and a plurality of low-potential voltage wirings, respectively, and a plurality of first link wirings and a plurality of A plurality of side wires connecting each of the second link wires may be included. Accordingly, it is possible to reduce the number of masks required to form various wirings disposed in the display device.

A display device according to another embodiment of the present invention includes a substrate, a plurality of high-potential voltage wires disposed on the substrate, a plurality of low-potential voltage wires and a plurality of LEDs, and disposed on the same layer to minimize manufacturing cost under the substrate, A plurality of link wires made of the same material and a first auxiliary wire connected to a part of the plurality of link wires, a plurality of high potential voltage wires and a plurality of low potential voltage wires, respectively, and a plurality of link wires It may include a plurality of side wirings disposed on the lower surface. Accordingly, it is possible to minimize the process cost and time for manufacturing the display device.

The details of other embodiments are included in the detailed description and drawings.

According to the present invention, the number of masks required to form various wirings arranged in a display device can be reduced, thereby reducing process cost and time.

In addition, according to the present invention, wiring of a flexible film such as a COF (Chip On Film) is arranged in a single layer, and manufacturing cost can be reduced compared to a case in which a plurality of conductive layers are arranged on the flexible film.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a schematic top view of a display device according to an exemplary embodiment.
2 is a schematic rear view of a display device according to an exemplary embodiment.
3 is a rear view before bonding a flexible film to a display device according to an exemplary embodiment.
4 is a rear view after bonding a flexible film to a display device according to an exemplary embodiment.
FIG. 5 is a cross-sectional view taken along line V-V' of FIG. 4 .
FIG. 6 is a cross-sectional view taken along line VI-VI' of FIG. 4 .
7 is a rear view of a display device according to another exemplary embodiment.
8 is a rear view before bonding a flexible film to a display device according to another exemplary embodiment of the present invention.
9 is a rear view after bonding a flexible film to a display device according to another exemplary embodiment of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless specifically stated otherwise.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

Reference to a device or layer “on” another device or layer includes any intervening layer or other device directly on or in the middle of another device.

Although first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated component.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and as those skilled in the art will fully understand, technically various interlocking and driving are possible, and each embodiment may be independently implemented with respect to each other, It may be possible to implement together in a related relationship.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In particular, the display device according to the present invention can be applied to a display device including a micro light emitting diode (μ-LED). By placing an image on each pixel of the , it is possible to reduce power consumption, miniaturization, and weight reduction, and has the advantage that it can be applied to a wide range of fields including flexible display devices, wearable devices, body-mounted medical devices, and wireless communication fields.

The micro light emitting diode as a light source can be formed using various materials on various substrates according to the three primary color elements of red, green, and blue. For example, light emitting on a gallium arsenide (GaAs), sapphire, or silicon (Si) substrate. Depending on the color, it may be formed using an inorganic material such as gallium nitride (GaN), gallium phosphide (GaP), or aluminum gallium arsenide (AlGaAs).

1 is a schematic top view of a display device according to an exemplary embodiment. 2 is a schematic rear view of a display device according to an exemplary embodiment. The first sub substrate 111 of FIG. 1 and the second sub substrate 112 of FIG. 2 include the first sub substrate 111 and the second sub substrate 112 before the first sub substrate 111 and the second sub substrate 112 are bonded. The second sub-substrate 112 .

First, referring to FIG. 1 , the first sub-substrate 111 is a substrate that supports components disposed on the first sub-substrate 111 , and may be an insulating substrate. The first sub-substrate 111 may be made of glass or resin. Also, the first sub-substrate 111 may include a polymer or plastic. In some embodiments, the first sub-substrate 111 may be made of a plastic material having flexibility.

A display area AA and a non-display area NA surrounding the display area AA may be defined in the first sub-substrate 111 . The display area AA is an area where an image is actually displayed in the display device 100 , and an LED, which will be described later, a transistor for driving the LED, etc. may be disposed in the display area AA. The non-display area NA is an area in which an image is not displayed and may be defined as an area surrounding the display area AA. Various lines such as a gate line GL and a data line DL connected to the LEDs and transistors disposed in the display area AA may be disposed in the non-display area NA.

Although it has been described herein that the first sub-substrate 111 is defined as the display area AA and the non-display area NA, the present disclosure is not limited thereto, and may be defined as having no non-display area NA. That is, when a tiling display is implemented using the display device 100 according to an embodiment of the present invention, the interval between the outermost LED of one panel and the outermost LED of another panel adjacent thereto is one. It can be implemented in the same way as the distance between the LEDs in the panel. Accordingly, it is possible to implement a zero bezel in which there is substantially no bezel area. Accordingly, the first sub-substrate 111 may be defined as having only the display area AA and the non-display area NA may not be defined in the first sub-substrate 111 . Accordingly, the non-display area NA may be defined only as an outer area.

A plurality of pixels PX are defined in the display area AA of the first sub-substrate 111 . Each of the plurality of pixels PX is an individual unit emitting light, and the plurality of pixels PX may include a red pixel PX, a green pixel PX, and a blue pixel PX, but is limited thereto. not. A transistor and an LED are formed in each of the plurality of pixels PX. A more detailed description of the transistor and the LED will be described later with reference to FIG. 6 .

A plurality of data lines DL, a plurality of gate lines GL, a plurality of high potential voltage lines VDDL, and a plurality of low potential voltage lines VSSL are disposed on the first sub-substrate 111 . Specifically, the plurality of data lines DL are lines that transmit data signals to each of the plurality of pixels PX. The plurality of high potential voltage lines VDDL are wirings that apply high potential voltages to the plurality of pixels PX. The plurality of low potential voltage lines VSSL are wirings that apply a low potential voltage to the plurality of pixels PX. In addition, the plurality of gate lines GL are lines that transmit gate signals to each of the plurality of pixels PX. The plurality of data lines DL, the plurality of high potential voltage lines VDDL, and the plurality of low potential voltage lines VSSL may extend in the same first direction to be connected to each of the plurality of pixels PX. Also, the plurality of gate lines GL may extend in a second direction different from the first direction in which the plurality of data lines DL extend to be connected to each of the plurality of pixels PX.

Referring to FIG. 2 , the second sub-substrate 112 is a substrate that supports components disposed under the second sub-substrate 112 , and may be an insulating substrate. For example, the second sub-substrate 112 may be made of glass or resin. Also, the second sub-substrate 112 may include a polymer or plastic. The second sub-substrate 112 may be made of the same material as the first sub-substrate 111 . In some embodiments, the second sub-substrate 112 may be made of a plastic material having flexibility.

A plurality of gate link lines GLL, a plurality of data link lines DLL, a plurality of first link lines LL1 and a plurality of second link lines LL2 are disposed on the rear surface of the second sub-substrate 112 . .

The plurality of gate link lines GLL is a line for connecting the plurality of gate lines GL disposed on the upper surface of the first sub-substrate 111 and the gate driver, and the plurality of data link lines DLL is the first sub-substrate 111 . A wiring for connecting the plurality of data lines DL disposed on the substrate 111 and the flexible film. In addition, the plurality of first link wires LL1 are wires for connecting the plurality of high potential voltage wires VDDL disposed on the upper surface of the first sub-board 111 and the flexible film. That is, the plurality of first link wires LL1 may be a plurality of high potential voltage link wires. The plurality of second link wires LL2 are wires for connecting the plurality of low potential voltage wires VSSL disposed on the upper surface of the first sub-board 111 and the flexible film. That is, the plurality of second link wires LL2 may be a plurality of low-potential voltage link wires.

The plurality of gate link lines GLL, the plurality of data link lines DLL, the plurality of first link lines LL1 , and the plurality of second link lines LL2 are connected to the second end of the second sub-substrate 112 . It may extend toward the center of the sub-substrate 112 .

Although not shown in FIG. 2 , a gate driver may be disposed under the second sub-substrate 112 to be electrically connected to the plurality of gate link lines GLL. In addition, a flexible film may be disposed under the second sub-substrate 112 to be electrically connected to the plurality of data link wires DLL, the plurality of first link wires LL1 , and the plurality of second link wires LL2 . can In this case, the gate driver may be directly formed under the second sub-substrate 112 or may be disposed under the second sub-substrate 112 in a COF method, but is not limited thereto.

In FIGS. 1 and 2 , two substrates, a first sub substrate 111 and a second sub substrate 112 , are shown to be used in the display device 100 , but one single substrate is used for the display device 100 . may be That is, the first sub substrate 111 and the second sub substrate 112 may be the same one substrate, and various wirings disposed on the first sub substrate 111 are arranged on one substrate, and the second sub substrate 111 may be the same. Various link wires disposed under the sub-board 112 may be disposed under one substrate.

Hereinafter, for a more detailed description of various components disposed under the second sub-substrate 112 of the display device 100 , reference is also made to FIG. 3 .

3 is a rear view before bonding a flexible film to a display device according to an exemplary embodiment.

Referring to FIG. 3 , a plurality of data link lines DLL, a plurality of first link lines LL1 , a plurality of second link lines LL2 , and a first auxiliary line AL1 are under the second sub-board 112 . ), a plurality of first pads P1 , a plurality of gate drivers GD, a plurality of gate link lines GLL, a plurality of second pads P2 , and a plurality of gate driver link lines GDLL are disposed.

Specifically, a plurality of first link lines LL1 are disposed under the second sub-board 112 . The plurality of first link wires LL1 are wires connected to the plurality of high potential voltage wires VDDL disposed on the first sub-substrate 111 to apply a high potential voltage to each of the plurality of pixels PX. That is, the first link line LL1 is a high potential voltage link line. The plurality of first link wirings LL1 extend from the end of the lower surface of the second sub substrate 112 in a first direction that is an inner direction of the second sub substrate 112 . Each of the plurality of first link wires LL1 may be connected to each of the plurality of high potential voltage wires VDDL disposed on the first sub-board 111 through a plurality of side wires.

A first auxiliary line AL1 is disposed under the second sub-board 112 . The first auxiliary line AL1 is a line connected to all of the plurality of first link lines LL1 . The first auxiliary line AL1 extends in a second direction that is different from a first direction that is an extension direction of the plurality of first link lines LL1 . In addition, the first auxiliary line AL1 is disposed closer to the center of the second sub-substrate 112 than the plurality of first link lines LL1 . That is, the first auxiliary wiring AL1 is in contact with the central end of the second sub-board 112 of the plurality of first link wires LL1 , and is in contact with the second sub-board 112 rather than the plurality of first link wires LL1 . ) can be placed close to the center of the The first auxiliary line AL1 contacts all of the plurality of first link lines LL1 and electrically connects all of the plurality of first link lines LL1 .

A width of the first auxiliary line AL1 may be greater than a width of the first link line LL1 . That is, in order to minimize the voltage drop of the high potential voltage in the first auxiliary line AL1 , the width of the first auxiliary line AL1 in the longitudinal direction is greater than the width of the first link line LL1 in the longitudinal direction. can

A plurality of first pads P1 are disposed on a lower surface of the second sub-substrate 112 . The plurality of first pads P1 is a wire connecting the flexible film and the first auxiliary wire AL1 . The plurality of first pads P1 are disposed in contact with both ends of the first auxiliary line AL1 . The first auxiliary line AL1 extends in a direction different from the extending direction of the plurality of first link lines LL1 , and both ends of the first auxiliary line AL1 in the extending direction of the first auxiliary line AL1 . Each of the first pads P1 may be connected to the portion. Accordingly, the plurality of first pads P1 , the first auxiliary line AL1 , and the plurality of first link lines LL1 may be electrically connected to each other.

The plurality of first pads P1 , the first auxiliary wires AL1 , and the plurality of first link wires LL1 may be formed of the same material. That is, the plurality of first pads P1 , the first auxiliary wirings AL1 , and the plurality of first link wirings LL1 may be formed of the same material on the same layer. Accordingly, the plurality of first pads P1 , the first auxiliary wires AL1 , and the plurality of first link wires LL1 extend integrally and may be formed through the same process.

A plurality of second link lines LL2 are disposed under the second sub-board 112 . The plurality of second link wires LL2 are wires connected to the plurality of low potential voltage wires VSSL disposed on the first sub-board 111 . That is, the second link wiring LL2 is a low potential voltage link wiring. The plurality of second link wirings LL2 extend from an end under the second sub substrate 112 in a first direction that is a center direction of the second sub substrate 112 . Each of the plurality of second link wires LL2 may be connected to each of the plurality of low potential voltage wires VSSL disposed on the first sub-board 111 through a plurality of side wires.

The plurality of second link lines LL2 may be made of the same material as the plurality of first link lines LL1 and may be disposed on the same layer. The plurality of first link wires LL1 may be made of the same material as the plurality of first pads P1 and the first auxiliary wires AL1 and may be disposed on the same layer. Accordingly, the plurality of second link wirings LL2 are made of the same material as the plurality of first link wirings LL1 , and thus the plurality of first link wirings LL1 , the plurality of first pads P1 and the light first auxiliary lines LL1 . It may be made of the same material as the wiring AL1 , may be disposed on the same layer, and may be formed through the same process.

A plurality of data link lines DLLs are disposed under the second sub-board 112 . The plurality of data link lines DLL is connected to the plurality of data lines DL disposed on the first sub-substrate 111 to apply a data signal to each of the plurality of pixels PX. The plurality of data link lines DLL extends from an end under the second sub-board 112 in a first direction that is a center direction of the second sub-board 112 . Each of the plurality of data link lines DLL may be connected to each of the plurality of data lines DL disposed on the first sub-board 111 through a plurality of side lines.

The plurality of data link lines DLL may be made of the same material as the plurality of first link lines LL1 and may be disposed on the same layer. Accordingly, various link wires disposed under the second sub-substrate 112 including the plurality of data link wires DLL and the plurality of first link wires LL1 may be made of the same material and disposed on the same layer. have. Accordingly, various link lines including the plurality of data link lines DLL and the plurality of first link lines LL1 disposed on the lower surface of the second sub substrate 112 may be simultaneously formed through the same process.

A plurality of gate link lines GLL are disposed under the second sub-substrate 112 . The plurality of gate link lines GLL are connected to the plurality of gate lines GL disposed on the first sub-substrate 111 to apply a gate signal to each of the plurality of pixels PX. The plurality of gate link wirings GLL extend from the end of the lower surface of the second sub substrate 112 in the inner direction of the second sub substrate 112 . In this case, the plurality of gate link lines GLL may extend in the same direction as the second direction in which the first auxiliary lines AL1 extend. Each of the plurality of gate link lines GLL may be connected to each of the plurality of gate lines GL disposed on the upper surface of the first sub substrate 111 through a plurality of side lines.

A plurality of gate drivers GD are disposed under the second sub-substrate 112 . The gate driver GD outputs a gate signal under the control of the timing controller and selects the pixel PX in which the data signal is charged through the gate link line GLL. Specifically, the gate driver GD may be connected to the plurality of gate link lines GLL. The gate driver GD transmits a gate signal to the plurality of gate link lines GLL, and each of the plurality of gate link lines GLL transmits a gate signal to each of the plurality of pixels PX through the plurality of gate lines GL. can be transmitted as The gate driver GD may be mounted on the lower surface of the second sub-substrate 112 by a COF method or may be formed by a GIP (Gate In Panel) method.

A plurality of second pads P2 and a plurality of gate driver link lines GDLL are disposed under the second sub-substrate 112 . The gate driver link line GDLL is a line connecting the second pad P2 and the gate driver GD. The second pad P2 and the gate driver GD are respectively connected to both ends of the gate driver link line GDLL. In this case, the second pad P2 is a pad connecting the gate driver GD and the flexible film. The second pad P2 may be connected to the flexible film to transmit a signal from the flexible film to the gate driver GD.

Accordingly, a plurality of first link lines LL1 , a plurality of second link lines LL2 , a first auxiliary line AL1 , a plurality of data link lines DLLs, a plurality of gate link lines GLL, a plurality of The gate driver link line GDLL, the plurality of first pads P1 , and the plurality of second pads P2 are all made of the same material and may be disposed on the same layer. As described above, a plurality of first link lines LL1 , a first auxiliary line AL1 , a plurality of first pads P1 , a plurality of second link lines LL2 , and a plurality of data link lines DLLs may be all made of the same material. In this case, the plurality of gate link lines GLL, the plurality of gate driver link lines GDLL, and the plurality of second pads P2 are made of the same material as the plurality of first link lines LL1 and are formed on the same layer. can be placed. Accordingly, a plurality of first link lines LL1 , a plurality of second link lines LL2 , a first auxiliary line AL1 , a plurality of data link lines DLL, a plurality of gate link lines GLL, a plurality of The gate driver link line GDLL, the plurality of first pads P1 and the plurality of second pads P2 may all be formed through the same process.

Hereinafter, in order to describe in more detail in relation to signal transmission through the flexible film, reference is also made to FIG. 4 .

4 is a rear view after bonding a flexible film to a display device according to an exemplary embodiment. In the case of the flexible film 170 of FIGS. 4 to 6 , the driving IC is omitted. In addition, in FIG. 4 , only the first base film 171a of the first base film 171a and the second base film 171b of the flexible film 170 is illustrated for convenience of explanation. Also, FIG. 6 illustrates a state in which the flexible film 170 is bent inside the display device 100 .

Referring to FIG. 4 , a flexible film 170 is disposed under the second sub-substrate 112 . Specifically, the flexible film 170 may be bonded to the printed circuit board 180 to transmit various signals from the printed circuit board 180 to the plurality of pixels PX. For example, the flexible film 170 supplies a high potential voltage and a low potential voltage to the plurality of pixels PX, and processes and transmits a data signal for displaying an image and a driving signal for processing the same. The flexible film 170 may supply a high potential voltage, a low potential voltage, and a data signal to the plurality of pixels PX through various wirings disposed under the second sub substrate 112 .

The flexible film 170 may include a base film 171 , a driving IC, and a plurality of pads. The base film 171 is a film supporting the flexible film 170 . The base film 171 may be made of an insulating material, for example, may be made of an insulating material having flexibility. Specifically, the base film 171 may be composed of a plurality of layers. 5 to 6 , the base film 171 may include a first base film 171a and a second base film 171b disposed to overlap. A conductive layer may be disposed between the first base film 171a and the second base film 171b. The first base film 171a and the second base film 171b may be made of an insulating material, and a conductive layer made of a conductive material may be disposed between the first base film 171a and the second base film 171b. have. The conductive layer disposed between the first base film 171a and the second base film 171b may include a plurality of wires. The plurality of wires disposed on the flexible film 170 may be formed by patterning a conductive layer disposed between the first base film 171a and the second base film 171b. The base film 171 of FIGS. 5 to 6 includes a first base film 171a and a second base film 171b and is illustrated as being composed of two layers, but is not limited thereto.

A driving IC may be disposed on the base film 171 of the flexible film 170 . The driving IC is a component that processes a data signal for displaying an image and a driving signal.

4 to 6 , the flexible film 170 includes a plurality of first wires L1 , a plurality of second wires L2 , a plurality of third wires L3 , and a plurality of fourth wires L4 . , a plurality of fifth wirings L5 and second auxiliary wirings AL2 are disposed. That is, the conductive layer of the flexible film 170 includes a plurality of first wirings L1 , a plurality of second wirings L2 , a plurality of third wirings L3 , a plurality of fourth wirings L4 , and a plurality of second wirings L1 . A fifth line L5 and a second auxiliary line AL2 may be included.

The plurality of first wires L1 are wires connecting each of the plurality of first pads P1 disposed under the second sub-board 112 and the printed circuit board 180 . Referring to FIG. 5 , the plurality of first wirings L1 are disposed between the first base film 171a and the second base film 171b.

In this case, each of the plurality of first wirings L1 is connected to each of the plurality of first pads P1 disposed on the second sub-substrate 112 by the adhesive layer 190 . In addition, each of the plurality of first wirings L1 is connected to the printed circuit board 180 by the adhesive layer 190 . The adhesive layer 190 is a layer made of an adhesive material for connecting the first wiring L1 and the first pad P1 to each other and connecting the first wiring L1 and the printed circuit board 180 . The adhesive layer 190 is disposed to overlap both ends of the first wiring L1 . The first base film 171a is not disposed in a region where the adhesive layer 190 and the first wiring L1 overlap. Accordingly, the adhesive layer 190 may contact each of the first wiring L1 and the first pad P1 between the first wiring L1 and the first pad P1 . Also, the adhesive layer 190 may be in contact with each of the first wiring L1 and the printed circuit board 180 between the first wiring L1 and the printed circuit board 180 .

The adhesive layer 190 may include a plurality of conductive balls dispersed in an adhesive resin. The conductive ball is a conductive particle for electrically connecting one end of the first wiring L1 and the first pad P1. An adhesive layer 190 including a plurality of conductive balls may be disposed between one end of the first wire L1 and the first pad P1 , and one end of the first wire L1 and the first pad P1 may be connected to each other. In order to be attached, pressure may be applied to the flexible film 170 and the second sub-substrate 112 . The plurality of conductive balls may be broken or deformed by pressure, and the plurality of conductive balls may be connected to each other. Accordingly, the first wiring L1 and the first pad P1 may be electrically connected to each other by a plurality of broken or deformed conductive balls. For example, the adhesive layer 190 may be an anisotropic conductive film (ACF), but is not limited thereto.

Similarly, the adhesive layer 190 may adhere one end of the first wire L1 to which the first pad P1 is attached and the other end of the first wire L1 opposite to that of the printed circuit board 180 . An adhesive layer 190 including a plurality of conductive balls may be disposed between the other end of the first wiring L1 and the pad 181 of the printed circuit board 180 . An input may be applied to the flexible film 170 and the printed circuit board 180 . Accordingly, the plurality of conductive balls may be broken or deformed, and the other end of the first wiring L1 and the pad 181 of the printed circuit board 180 may be electrically connected.

As each of the plurality of first wires L1 electrically connects the printed circuit board 180 and each of the plurality of first pads P1 , a high potential voltage may be applied to the plurality of first pads P1 . . A high potential voltage is applied from the printed circuit board 180 to the plurality of first wires L1 , and a plurality of first pads P1 and first auxiliary wires AL1 sequentially connected to each of the plurality of first wires L1 , respectively. ) and a high potential voltage may be applied to the plurality of first link lines LL1 . Accordingly, a high potential voltage is applied to the plurality of high potential voltage wires VDDL disposed on the first sub-substrate 111 connected to each of the plurality of first link wires LL1 , and a high potential voltage is applied to the plurality of pixels PX. A voltage may be applied.

The plurality of third wirings L3 are wirings connecting each of the plurality of data link wirings DLL disposed under the second sub-board 112 and the printed circuit board 180 . The third line L3 extends in the same direction as the first direction, which is an extension direction of the plurality of data link lines DLL disposed on the second sub-board 112 .

Each of the plurality of third wires L3 may connect each of the plurality of data link wires DLL disposed under the second sub-board 112 to the printed circuit board 180 . In detail, one of both ends of the plurality of third lines L3 may be connected to each of the plurality of data link lines DLL. An adhesive layer 190 may be disposed between the plurality of third wires L3 and the plurality of data link wires DLL. Accordingly, the third line L3 and the data link line DLL may be electrically connected to each other by a plurality of conductive balls of the adhesive layer 190 .

In addition, the other end of the plurality of third lines L3 opposite to the end overlapping the plurality of data link lines DLL may be connected to the driving IC of the flexible film 170 . However, in FIG. 5 , the illustration of the driving IC is omitted for convenience of illustration. In FIG. 4 , portions connected to the printed circuit board 180 of the plurality of third wirings L3 are omitted.

The plurality of third wirings L3 may be formed of the same material as the plurality of first wirings L1 . The plurality of third wirings L3 and the plurality of first wirings L1 may be made of the same material in the flexible film 170 and may be disposed on the same layer.

The plurality of fifth wires L5 are wires connecting each of the plurality of second pads P2 disposed on the second sub-board 112 and the printed circuit board 180 . The plurality of fifth wirings L5 is disposed between the first base film 171a and the second base film 171b.

Each of the plurality of fifth wirings L5 is electrically connected to each of the plurality of second pads P2 disposed under the second sub-substrate 112 by an adhesive layer 190 including conductive balls. In addition, each of the plurality of fifth wirings L5 is electrically connected to the printed circuit board 180 by an adhesive layer 190 including conductive balls. Specifically,

The plurality of fifth wirings L5 may be formed of the same material as the plurality of first wirings L1 . The plurality of fifth wirings L5 and the plurality of first wirings L1 may be made of the same material in the flexible film 170 and may be disposed on the same layer.

4 and 6 , the plurality of second wirings L2 connect each of the plurality of second link wirings LL2 disposed on the lower surface of the second sub-board 112 and the printed circuit board 180 . it is wiring The plurality of second wirings L2 are disposed on one side of the flexible film 170 . Referring to FIG. 6 , the plurality of second wirings L2 are disposed between the first base film 171a and the second base film 171b. In addition, each of the plurality of second wirings L2 is connected to each of the plurality of second link wirings LL2 disposed on the second sub-substrate 112 by the adhesive layer 190 . The adhesive layer 190 is disposed to overlap an end of the second wiring L2 .

A second auxiliary line AL2 is disposed on the flexible film 170 . The second auxiliary line AL2 is a line connecting the plurality of first lines L1 . The second auxiliary line AL2 extends in a direction different from the extending direction of the plurality of second lines L2 . The second auxiliary wiring AL2 is in contact with the inner end of the flexible film 170 of the plurality of second wirings L2 and electrically connects all of the plurality of second wirings L2 . Referring to FIG. 6 , the second auxiliary line AL2 is disposed between the first base film 171a and the second base film 171b, and the second auxiliary line AL2 is formed between the second line L2 and the second line L2. It is disposed between the four wirings L4 to connect the second wiring L2 and the fourth wiring L4.

A width of the second auxiliary line AL2 may be greater than a width of the second line L2 . That is, in order to minimize the voltage drop of the low potential voltage in the second auxiliary line AL2 , the width of the second auxiliary line AL2 in the longitudinal direction may be greater than the width of the second line L2 in the longitudinal direction. have.

A plurality of fourth wirings L4 are disposed on the flexible film 170 . The plurality of fourth wirings L4 are wirings connecting the second auxiliary wiring AL2 and the printed circuit board 180 . The plurality of fourth wirings L4 extend in the same direction as the first direction in which the plurality of second wirings L2 extend. One end of the fourth wiring L4 may be in contact with the second auxiliary wiring AL2 , and the other end of the fourth wiring L4 may extend in a direction in which the printed circuit board 180 is disposed. Referring to FIG. 6 , each of the plurality of fourth wirings L4 is connected to the printed circuit board 180 by an adhesive layer 190 .

In this case, the plurality of second wirings L2 , the second auxiliary wirings AL2 , and the plurality of fourth wirings L4 may be formed of the same material. Specifically, the plurality of second wirings L2 , the second auxiliary wirings AL2 , and the plurality of fourth wirings L4 may be made of the same material as the plurality of first wirings L1 . Accordingly, the plurality of first wirings L1, the plurality of second wirings L2, the second auxiliary wirings AL2, and the plurality of fourth wirings L4 are all made of the same material and may be disposed on the same layer. have. Accordingly, the flexible film 170 may be implemented as a flexible film 170 including a single conductive layer.

Referring to FIG. 6 , the flexible film 170 may be bent. Specifically, a plurality of second wirings L2 are disposed on one side of the flexible film 170 . In addition, the flexible film 170 may be bent so that one side and the other side of the flexible film 170 may face each other. The flexible film 170 may be bent so that one side and the other side of the flexible film 170 face each other. Accordingly, the flexible film 170 and the printed circuit board 180 protrude to the outside of the first sub-board 111 and the second sub-board 112 and are prevented from being recognized by the user, and a plurality of panels are arranged in a tile form. A tiling display can be implemented.

Referring to FIG. 6 , various components of the display device 100 disposed in the display area AA will be described. The transistor 120 is disposed on the first sub-substrate 111 . Specifically, the gate electrode 121 is disposed on the first sub-substrate 111 , and the active layer 122 is disposed on the gate electrode 121 . A gate insulating layer 113 for insulating the gate electrode 121 and the active layer 122 is disposed between the gate electrode 121 and the active layer 122 . A source electrode 123 and a drain electrode 124 are disposed on the active layer 122 .

A low potential voltage line VSSL is disposed on the first sub substrate 111 . The low potential voltage line VSSL and the gate electrode 121 may be formed of the same material on the same layer. A gate insulating layer 113 is disposed on a portion of the low potential voltage line VSSL. In addition, although the low potential voltage line VSSL is illustrated in FIG. 6 , the gate line GL, the data line DL, and the high potential voltage line VDDL may also be formed to the same effect as the low potential voltage line VSSL. have.

A low potential voltage line VSSL is disposed on the gate insulating layer 113 . The low potential voltage line VSSL is a line for applying a low potential voltage, for example, a common voltage, to the LED 130 , and may be disposed to be spaced apart from the gate line GL or the data line DL. Also, the low potential voltage line VSSL may extend in the same direction as the data line DL. The low potential voltage line VSSL may be formed of the same material on the same layer as the source electrode 123 and the drain electrode 124 of the transistor 120 .

The passivation layer 114 is disposed on the gate insulating layer 113 , the transistor 120 , and the low potential voltage line VSSL. The passivation layer 114 may be disposed on the transistor 120 to protect the source electrode 123 and the drain electrode 124 of the transistor 120 . However, the passivation layer 114 may be omitted according to embodiments.

A plurality of reflective layers 143 are disposed on the passivation layer 114 . The reflective layer 143 is a layer for reflecting the light emitted toward the first sub-substrate 111 from among the light emitted from the LED 130 to the upper portion of the display device 100 to emit light to the outside of the display device 100 . The reflective layer 143 may be made of a metal material having a high reflectivity.

An adhesive layer 115 covering the plurality of reflective layers 143 is disposed on the reflective layer 143 . The adhesive layer 115 is an adhesive layer 115 for bonding the LED 130 on the reflective layer 143 , and may insulate the reflective layer 143 made of a metal material from the LED 130 . The adhesive layer 115 may be formed of a heat-curable material or a light-curable material, but is not limited thereto. In FIG. 6 , the adhesive layer 115 is illustrated as being disposed to cover only the reflective layer 143 , but the arrangement position of the adhesive layer 115 is not limited thereto.

A plurality of LEDs 130 are disposed on the adhesive layer 115 . The plurality of LEDs 130 are disposed to overlap the plurality of reflective layers 143 . The plurality of LEDs 130 includes an n-type layer 131 , an active layer 132 , a p-type layer 133 , an n-electrode 135 , and a p-electrode 134 . Hereinafter, it will be described that the LED 130 having a lateral structure is used as the LED 130 , but the structure of the LED 130 is not limited thereto.

Specifically, the n-type layer 131 of the LED 130 is disposed to overlap the reflective layer 143 on the adhesive layer 115 . The n-type layer 131 may be formed by implanting n-type impurities into gallium nitride having excellent crystallinity. An active layer 132 is disposed on the n-type layer 131 . The active layer 132 is a light emitting layer emitting light from the LED 130 , and may be made of a nitride semiconductor, for example, indium gallium nitride. A p-type layer 133 is disposed on the active layer 132 . The p-type layer 133 may be formed by implanting p-type impurities into gallium nitride. However, the constituent materials of the n-type layer 131 , the active layer 132 , and the p-type layer 133 are not limited thereto.

A p-electrode 134 is disposed on the p-type layer 133 of the LED 130 . In addition, an n-electrode 135 is disposed on the n-type layer 131 of the LED 130 . The n-electrode 135 is spaced apart from the p-electrode 134 . Specifically, in the LED 130, an n-type layer 131, an active layer 132, and a p-type layer 133 are sequentially stacked, a predetermined portion of the active layer 132 and the p-type layer 133 is etched, and an n-electrode It can be manufactured by forming the 135 and the p-electrode 134 . In this case, the predetermined portion is a space for separating the n-electrode 135 and the p-electrode 134 , and the predetermined portion may be etched to expose a portion of the n-type layer 131 . In other words, the surface of the LED 130 on which the n-electrode 135 and the p-electrode 134 are to be disposed may have different height levels than the planarized surface. Accordingly, the p-electrode 134 is disposed on the p-type layer 133 , the n-electrode 135 is disposed on the n-type layer 131 , and the p-electrode 134 and the n-electrode 135 have different height levels. are spaced apart from each other. Accordingly, the n-electrode 135 may be disposed adjacent to the reflective layer 143 as compared to the p-electrode 134 . In addition, the n-electrode 135 and the p-electrode 134 may be made of a conductive material, for example, a transparent conductive oxide. Also, the n-electrode 135 and the p-electrode 134 may be made of the same material, but are not limited thereto.

A first planarization layer 116 is disposed on the transistor 120 . The first planarization layer 116 is a layer that planarizes the upper surface of the transistor 120 . The first planarization layer 116 may be disposed while planarizing the upper surface of the first planarization layer 116 in an area other than the area where the LED 130 is disposed.

A second planarization layer 117 is disposed on the first planarization layer 116 and the LED 130 . The second planarization layer 117 is a layer that planarizes upper surfaces of the transistor 120 and the LED 130 . 6 illustrates that the first planarization layer 116 and the second planarization layer 117 are disposed and two planarization layers are disposed, but the present invention is not limited thereto, and one planarization layer may be formed. When one planarization layer is disposed, it can be prevented from excessively increasing the time required for the process. In addition, the planarization layer may be composed of two or more layers.

A first electrode 141 and a second electrode 142 are disposed on the first planarization layer 116 and the second planarization layer 117 . The first electrode 141 is an electrode electrically connecting the transistor 120 and the LED 130 . The first electrode 141 is connected to the p-electrode 134 of the LED 130 through a contact hole formed in the second planarization layer 117 . In addition, the first electrode 141 is connected to the source electrode 123 of the transistor 120 through a contact hole formed in the first planarization layer 116 , the second planarization layer 117 , the passivation layer 114 , and the adhesive layer 115 . ) is associated with However, the present invention is not limited thereto, and the first electrode 141 may be connected to the drain electrode 124 of the transistor 120 depending on the type of the transistor 120 . The p electrode 134 of the LED 130 and the source electrode 123 of the transistor 120 are electrically connected by the first electrode 141 .

The second electrode 142 is an electrode that electrically connects the LED 130 and the low potential voltage line VSSL. Specifically, the second electrode 142 is connected to a low potential voltage line (VSSL) through a contact hole formed in the first planarization layer 116 , the second planarization layer 117 , the passivation layer 114 , and the adhesive layer 115 . connected to the n-electrode 135 of the LED 130 through a contact hole formed in the second planarization layer 117 . Accordingly, the low potential voltage line VSSL and the n-electrode 135 of the LED 130 are electrically connected.

When the display device 100 is turned on, voltages of different levels may be applied to each of the source electrode 123 of the transistor 120 and the high potential voltage line VDDL. A voltage applied to the source electrode 123 of the transistor 120 may be applied to the first electrode 141 , and a high potential voltage may be applied to the second electrode 142 . Voltages of different levels may be applied to the p-electrode 134 and the n-electrode 135 through the first electrode 141 and the second electrode 142 , and thus the LED 130 may emit light.

6 illustrates that the transistor 120 is electrically connected to the p-electrode 134 and the high-potential voltage line VDDL is electrically connected to the n-electrode 135 , but the present invention is not limited thereto. The n-electrode 135 may be electrically connected, and the high potential voltage line VDDL may be electrically connected to the p-electrode 134 .

A bank 119 is disposed on the second planarization layer 117 , the first electrode 141 , and the second electrode 142 . The bank 119 is an insulating layer defining a light emitting region. The bank 119 is disposed to overlap an end of the reflective layer 143 , and a portion of the reflective layer 143 that does not overlap the bank 119 may be defined as a light emitting region. The bank 119 may be made of an organic insulating material, and may be made of the same material as the first planarization layer 116 and/or the second planarization layer 117 . In addition, the bank 119 may be configured to include a black material in order to prevent the light emitted from the LED 130 from being transmitted to the adjacent pixel PX from causing a color mixing phenomenon.

A bonding layer 118 is disposed between the first sub-substrate 111 and the second sub-substrate 112 . The bonding layer 118 is a layer that bonds the first sub-substrate 111 and the second sub-substrate 112 to each other. The first sub-substrate 111 and the second sub-substrate 112 may be bonded by a bonding process. Specifically, the bonding layer 118 may be made of a material capable of bonding the first sub-substrate 111 and the second sub-substrate 112 to each other by being cured through various curing methods. The bonding layer 118 may be disposed over the entire area between the first sub-substrate 111 and the second sub-substrate 112 , or may be disposed only on a partial area.

The first sub-substrate 111 and the second sub-substrate 112 shown in FIG. 6 may be substrates after a scribing process. Specifically, scribing lines may be defined on the first sub-substrate 111 and the second sub-substrate 112 . The scribing line is a virtual cutting line used to cut the display device 100 in units of cells after the bonding process of the first sub-substrate 111 and the second sub-substrate 112 is performed. That is, the display device 100 may be simultaneously formed into a plurality of devices and then cut along a scribing line in units of cells. Accordingly, the first sub-substrate 111 and the second sub-substrate 112 shown in FIG. 6 are cut along a scribing line to separate the first sub-substrate 111 and the second sub-substrate 112 in units of cells. ) can be

Side wirings 151 are disposed at corners of the first sub-board 111 and the second sub-board 112 . The side wiring 151 is a wiring connecting the gate wiring GL and the gate link wiring GLL. The side wiring 151 is a wiring connecting the wiring disposed on the first sub-board 111 and the wiring disposed under the second sub-board 112 . The side wiring 151 may be disposed on top and side surfaces of the first sub-board 111 and on the side and bottom surfaces of the second sub-board 112 . For example, the side wiring 151 may be formed through a process of printing a metal material such as silver (Ag) using a pad, but is not limited thereto.

The second link wiring LL2 is connected to the low potential voltage supply wiring disposed on the upper surface of the first sub-board 111 through the side wiring 151 . The side wiring 151 may connect the second link line LL2 which is a low potential voltage link line and the low potential voltage line VSSL. Accordingly, the low potential voltage applied to the second link line LL2 may be transmitted to each of the plurality of pixels PX.

In FIG. 6 , the side wiring 151 connecting the low potential voltage line VSSL and the first link line LL1 is illustrated, but the high potential voltage line VDDL and the high potential voltage link line LL1 are the first link lines LL1 . ), the data line DL and the data link line DLL, and the side line 151 connecting the gate line GL and the gate link line GLL may be disposed to the same effect.

A black insulating layer 160 is disposed on the side wiring 151 . The black insulating layer 160 is an insulating layer covering the side wiring 151 to insulate the side wiring 151 . When the side wiring 151 is made of a metal material, external light may be reflected from the side wiring 151 or light emitted from the LED 130 may be reflected from the side wiring 151 to be visually recognized from the outside. Accordingly, the black insulating layer 160 made of a black material is disposed to cover the side wiring 151 , so that visibility of light from the outside can be prevented.

In the display device 100 according to an embodiment of the present invention, the high potential voltage applied from the printed circuit board 180 is transmitted to each of the plurality of first link wires LL1 through the first auxiliary wire AL1 . Also, a width of the first auxiliary line AL1 may be greater than a width of the plurality of first link lines LL1 . Accordingly, a voltage drop of the high potential voltage applied to the plurality of high potential voltage lines VDDL through the plurality of first link lines LL1 may be minimized. In addition, in the display device 100 according to an embodiment of the present invention, the second auxiliary wiring AL2 is a wiring connected to all the second wirings L2 , and the second link wiring ( AL2 ) through the second wiring L2 . A low potential voltage can be delivered to LL2). Also, the width of the second auxiliary line AL2 may be greater than the width of the second line L2 . Accordingly, a voltage drop of the low potential voltage applied to the plurality of low potential voltage lines VSSL through the plurality of second link lines LL2 may be minimized.

Meanwhile, in a conventional display device, a plurality of data link wires DLL, a plurality of first link wires LL1 , and a plurality of second link wires LL2 in the display device 100 according to an exemplary embodiment of the present invention are used. ), the first auxiliary line AL1 , and the wirings corresponding to the second auxiliary line AL2 are all disposed on the upper surface of the substrate. Accordingly, a portion in which the above-described wirings cross each other occurs, so that the above-described wirings are formed over a plurality of sides. Accordingly, the above-described various wirings may be formed by an etching process using a plurality of different masks. Accordingly, the cost and time required for the manufacturing process of the conventional display device may increase.

In contrast, in the display device 100 according to an exemplary embodiment of the present invention, the first auxiliary wiring AL1 is disposed under the second sub substrate 112 , and the second auxiliary wiring AL1 is disposed on the flexible film 170 . AL2) is placed. In detail, a first auxiliary line AL1 connected to all of the plurality of first link lines LL1 is disposed under the second sub-substrate 112 . The first auxiliary wiring AL1 is connected to the plurality of first pads P1 , and the first pad P1 is connected to the printed circuit board 180 through the flexible film 170 . Accordingly, a high potential voltage may be applied to the plurality of first pads P1 , and a high potential voltage may be applied to the first link wiring LL1 through the first auxiliary wiring AL1 . Accordingly, a high potential voltage may be applied to the high potential voltage line VDDL disposed on the upper surface of the first sub substrate 111 connected to the first link line LL1 .

In addition, a plurality of first link lines LL1 , a plurality of second link lines LL2 , a plurality of data link lines DLLs, and a first auxiliary line AL1 are disposed on the lower surface of the second sub-board 112 . and the plurality of first pads P1 may be made of the same material and disposed on the same layer. Accordingly, the plurality of first link lines LL1 , the plurality of second link lines LL2 , the plurality of data link lines DLLs, the first auxiliary lines AL1 , and the plurality of first pads P1 are connected to one It is formed by a mask, and can be formed simultaneously through the same process. Accordingly, a plurality of first link lines LL1 , a plurality of second link lines LL2 , a plurality of data link lines DLLs, a first auxiliary line AL1 , and a plurality of first pads P1 are formed. The required manufacturing time and cost can be minimized.

In addition, the plurality of gate driver link lines GDLL, the plurality of second pads P2 , and the plurality of gate link lines GLL may all be made of the same material as the plurality of first link lines LL1 . Accordingly, the plurality of first link lines LL1 , the plurality of gate driver link lines GDLL, the plurality of second pads P2 , and the plurality of gate link lines GLL may be disposed on the same layer. Accordingly, the plurality of first link wires LL1 , the plurality of second link wires LL2 , the plurality of data link wires DLLs, the first auxiliary wires AL1 , the plurality of first pads P1 , and the plurality of The gate driver link line GDLL, the plurality of second pads P2 , and the plurality of gate link lines GLL may all be formed through the same process using a single mask. Accordingly, the wiring on the lower surface of the second sub-substrate 112 may be formed in a single-layer structure. Accordingly, the time and cost required to form various wirings disposed under the second sub-substrate 112 may be minimized.

In addition, the second auxiliary wiring AL2 connected to all of the plurality of second wirings L2 is disposed on the flexible film 170 . The second auxiliary wiring AL2 is connected to the plurality of fourth wirings L4 , and the plurality of fourth wirings L4 is connected to the printed circuit board 180 . Accordingly, a low potential voltage may be applied to the second link wiring LL2, which is a low potential voltage link wiring connected to the plurality of second wirings L2, and thus a plurality of pixels (VSSL) through the low potential voltage wiring VSSL. A low potential voltage may be supplied to each of PX).

In addition, the plurality of first wirings L1 , the plurality of second wirings L2 , the plurality of third wirings L3 , the plurality of fourth wirings L4 and the second wirings L1 are disposed on the lower surface of the flexible film 170 . All auxiliary wirings AL2 are made of the same material and may be disposed on the same layer. Accordingly, since various wirings disposed on the flexible film 170 may be disposed on a single conductive layer, manufacturing cost may be minimized compared to a method using a plurality of conductive layers stacked on the flexible film 170 .

Meanwhile, in FIGS. 1 to 6 , the wiring and the wiring have been described as being bonded to each other by the adhesive layer 190, but the present invention is not limited thereto. may be bonded by

7 is a rear view of a display device according to another exemplary embodiment. The display device 700 of FIG. 7 is substantially the same as that of the display device 100 of FIGS. 1 to 6 , except that the flexible film 170 is different, and thus a redundant description will be omitted.

Referring to FIG. 7 , the flexible film 170 includes a plurality of first wirings L1 , a plurality of second wirings L2 , a plurality of third wirings L3 , a plurality of fourth wirings L4 , and a plurality of A fifth line L5 and a second auxiliary line AL2 are disposed. As described above, one end of the plurality of first wires L1 is connected to each of the plurality of first pads P1 disposed under the second sub-board 112 , and the other end of the plurality of first wires L1 is connected to the printed circuit board 180 . is connected with The plurality of second wires L2 are disposed on one side of the flexible film 170 and are connected to the second link wires LL2 disposed under the second sub-substrate 112 . All of the plurality of second wirings L2 are connected to the second auxiliary wirings AL2 extending in a different direction from the plurality of second wirings L2 . The second auxiliary wiring AL2 extends in the same direction as the plurality of second wirings L2 and is connected to the plurality of fourth wirings L4 disposed on the other side of the flexible film 170 . The plurality of fourth wirings L4 are connected to the printed circuit board 180 . The plurality of fifth wirings L5 extend in the same direction as the extending direction of the plurality of first wirings L1 . One end of the plurality of fifth wires L5 is connected to the plurality of second pads P2 disposed under the second sub-board 112 , and the other end is connected to the printed circuit board 180 .

One side of the flexible film 170 , ie, one side on which the plurality of second wires L2 are disposed, is disposed farther from the center of the substrate than the other side of the flexible film 170 . That is, the plurality of second wirings L2 are disposed on one side of the flexible film 170 , and the other side of the flexible film 170 is disposed closer to the center of the second sub-substrate 112 than the one side. The flexible film 170 extends in the central direction of the second sub-substrate 112 from one side on which the plurality of second wirings L2 are disposed. In addition, the printed circuit board 180 is coupled to the other side of the flexible film 170 . Accordingly, the printed circuit board 180 is disposed closer to the center of the second sub-board 112 than the flexible film 170 . Both the flexible film 170 and the printed circuit board 180 are disposed to overlap the second sub-board 112 . In this case, the flexible film 170 and the printed circuit board 180 may overlap the gate driver GD, but the flexible film 170 and the printed circuit board 180 and the gate driver GD through a separate mechanism. Interference between them can be minimized.

In the display device 700 according to another embodiment of the present invention, the other side of the flexible film 170 is larger than the one side of the flexible film 170 , ie, one side on which the plurality of second wires L2 are disposed. Since the second sub-substrate 112 is disposed close to the center, the flexible film 170 may not be bent. When the other side of the flexible film 170 is disposed farther from the center of the second sub-substrate 112 than the one side on which the plurality of second wires L2 are disposed, in order to reduce the overall area of the display device 700 . The flexible film 170 must be bent. When the flexible film 170 is bent, one side and the other side of the flexible film 170 may be disposed to face each other and face each other. In this case, various wirings disposed on the flexible film 170 may be bent, and the wirings may be cracked. When some of the wires disposed on the flexible film 170 are cracked, signals may not be smoothly transmitted from the printed circuit board 180 to the link wires disposed under the second sub-board 112 . Accordingly, in the display device 700 according to another embodiment of the present invention, the other side of the flexible film 170 is disposed closer to the center of the second sub-substrate 112 than the one side, so that the flexible film 170 is bent. it may not be Accordingly, various wires disposed on the flexible film 170 may not be cracked, and thus, signals may be effectively transmitted from the printed circuit board 180 to the link wires of the second sub-board 112 .

8 is a rear view before bonding the flexible film 170 to the display device according to another exemplary embodiment of the present invention. 9 is a rear view after bonding the flexible film 170 to the display device according to another exemplary embodiment of the present invention. The display device 800 of FIGS. 8 to 9 is compared with the display device 100 of FIGS. 1 to 6 , except that there is a difference in the connection between the first link line LL1 and the second link line LL2 . Since they are substantially the same, duplicate descriptions will be omitted.

8 to 9 , a plurality of first link lines LL1 , a plurality of second link lines LL2 , a plurality of data link lines DLLs, and a first auxiliary line are under the second sub-substrate 112 . The wiring AL1, the plurality of first pads P1, the plurality of second pads P2, the plurality of gate drivers GD, the plurality of gate drivers GDLL, and the plurality of gate link wirings GLL are connected to each other. are placed In addition, the flexible film 170 includes a plurality of first wires L1 , a plurality of second wires L2 , a plurality of third wires L3 , a plurality of fourth wires L4 , and a plurality of fifth wires ( L5) and the second auxiliary line AL2 are disposed.

Specifically, the plurality of first link wires LL1 are connected to a plurality of low potential voltage wires VSSL disposed on the first sub-substrate 111 to apply a low potential voltage to each of the plurality of pixels PX. it is wiring That is, the first link wiring LL1 is a low potential voltage link wiring. The first link line LL1 may be connected to the low potential voltage line VSSL through the side line 151 .

All of the plurality of first link lines LL1 are connected to the first auxiliary line AL1 . The first auxiliary line AL1 extends in a direction different from the extending direction of the plurality of first link lines LL1 and is disposed closer to the center of the second sub-board 112 than the plurality of first link lines LL1 . All of the plurality of first link wires LL1 may be electrically connected to each other by the first auxiliary wires AL1 .

A plurality of first pads P1 are respectively connected to both ends of the first auxiliary line AL1 . Each of the plurality of first pads P1 is connected to each of the plurality of first wires L1 disposed on the flexible film 170 . The plurality of first wirings L1 are connected to the printed circuit board 180 to receive a low potential voltage from the printed circuit board 180 . Accordingly, a low potential voltage is applied to the first pad P1 , the first auxiliary line AL1 , and the first link line LL1 , and a low potential voltage is applied to each of the plurality of pixels PX through the low potential voltage line VSSL. A potential voltage may be applied. A voltage drop of the low potential voltage applied to each of the plurality of pixels PX by the first auxiliary line AL1 may be reduced.

In addition, the plurality of second link wires LL2 are connected to the plurality of high potential voltage wires VDDL disposed on the first sub-substrate 111 to apply a high potential voltage to each of the plurality of pixels PX. to be. That is, the second link line LL2 is a high potential voltage link line. The second link line LL2 may be connected to the high potential voltage line VDDL through the side line 151 .

Each of the plurality of second link wires LL2 is connected to each of the plurality of second wires L2 disposed on one side of the flexible film 170 . In addition, all of the plurality of second lines L2 are connected to the second auxiliary line AL2 . The second auxiliary line AL2 extends in a direction different from the extending direction of the plurality of second lines L2 . The second auxiliary wiring AL2 is connected to the plurality of fourth wirings L4 connected to the printed circuit board 180 . The plurality of fourth wirings L4 receive a high potential voltage from the printed circuit board 180 . Accordingly, a high potential voltage may be applied to the second auxiliary line AL2 , the plurality of second lines L2 , and the plurality of second link lines LL2 . Accordingly, a high potential voltage may be applied to each of the plurality of pixels PX through the high potential voltage line VDDL. A voltage drop of the high potential voltage applied to each of the plurality of pixels PX by the second auxiliary line AL2 may be reduced.

In this case, a plurality of first link lines LL1 , a plurality of second link lines LL2 , a plurality of data link lines DLLs, a first auxiliary line AL1 and All of the plurality of first pads P1 may be made of the same material. Specifically, the plurality of first link lines LL1 , the plurality of second link lines LL2 , the plurality of data link lines DLLs, the first auxiliary lines AL1 and the plurality of first pads P1 are all It is made of the same material and may be disposed on the same layer. Accordingly, the plurality of first link lines LL1 , the plurality of second link lines LL2 , the plurality of data link lines DLLs, the first auxiliary lines AL1 , and the plurality of first pads P1 are connected to one It may be formed by an etching process using a mask.

In addition, a plurality of first wirings L1 , a plurality of second wirings L2 , a plurality of third wirings L3 , a plurality of fourth wirings L4 , and a plurality of fifth wirings L1 are disposed on the flexible film 170 . Both the wiring L5 and the second auxiliary wiring AL2 may be formed of the same material. Specifically, a plurality of first wirings L1 , a plurality of second wirings L2 , a plurality of third wirings L3 , a plurality of fourth wirings L4 , a plurality of fifth wirings L5 , and a second wiring All auxiliary wirings AL2 are made of the same material and may be disposed on the same layer. Accordingly, since various wirings disposed on the flexible film 170 may be disposed on a single conductive layer, manufacturing cost may be minimized compared to a method using a plurality of conductive layers stacked on the flexible film 170 .

In the display device 800 according to another embodiment of the present invention, the first link line LL1 is a low potential voltage link line connected to the low potential voltage line VSSL, and the second link line LL2 has a high voltage. It is a high potential voltage link line connected to the upper voltage line VDDL. In addition, various link wires disposed under the second sub-substrate 112 are formed on the same layer using the same material, and various wires disposed on the flexible film 170 are formed on the same layer using the same material. Accordingly, the number of masks required for the manufacturing process of the display device 800 may be reduced.

Display devices according to embodiments of the present invention may be described as follows.

A display device according to an embodiment of the present invention includes a substrate, a plurality of high-potential voltage wires disposed on the substrate, a plurality of low-potential voltage wires and a plurality of LEDs, a plurality of first link wires disposed under the substrate, and a plurality of a plurality of first auxiliary wirings and a plurality of second link wirings connected to the first link wiring of of side wiring.

According to another feature of the present invention, one of the first link wiring and the second link wiring may be a high potential voltage link wiring, and the other may be a low potential voltage link wiring.

According to another feature of the present invention, the substrate includes a first sub-board and a second sub-board, and a plurality of high-potential voltage wires, a plurality of low-potential voltage wires, and a plurality of LEDs are disposed on the first sub-board and the plurality of first link wirings, the first auxiliary wirings, and the plurality of second link wirings may be disposed under the second sub-substrate.

According to another feature of the present invention, the plurality of first link wirings, the first auxiliary wirings, and the plurality of second link wirings may be made of the same material and disposed on the same layer.

According to another feature of the present invention, the first auxiliary wiring may extend in a different direction from the plurality of first link wirings and may be disposed closer to the center of the substrate than the plurality of first link wirings.

According to another feature of the present invention, the display device is disposed under a substrate, and includes a plurality of first pads connected to the first auxiliary wirings, a plurality of first wirings connected to each of the plurality of first pads, and a plurality of second links. The flexible film may further include a plurality of second wires connected to each of the wires, and a second auxiliary wire connected to the plurality of second wires.

According to another feature of the present invention, the plurality of first pads may be made of the same material as the first auxiliary wiring and may be disposed on the same layer.

According to another feature of the present invention, the plurality of first wirings, the plurality of second wirings, and the second auxiliary wiring may be made of the same material and disposed on the same layer.

According to another feature of the present invention, the second auxiliary wiring may extend in a different direction from the plurality of second wirings.

According to still another feature of the present invention, the display device further includes a plurality of data lines disposed on the substrate and a plurality of data link lines disposed under the substrate, and a portion of the plurality of side wirings includes each of the plurality of data lines. and each of the plurality of data link wires may be connected.

According to another feature of the present invention, the display device may further include a plurality of third wires disposed on the flexible film, connected to each of the plurality of data link wires, and made of the same material as the plurality of first wires. .

According to another feature of the present invention, the plurality of data link wirings may be made of the same material as the plurality of first link wirings and disposed on the same layer.

According to another feature of the present invention, the plurality of second wires may be disposed on one side of the flexible film, and the other side of the flexible film may be disposed closer to the center of the substrate than the one side of the flexible film.

According to another feature of the present invention, the plurality of second wires may be disposed on one side of the flexible film, and the flexible film may be bent so that one side and the other side of the flexible film face each other.

According to another feature of the present invention, the display device may further include a black insulating layer covering the plurality of side wirings.

A display device according to another embodiment of the present invention includes a substrate, a plurality of high-potential voltage wires disposed on the substrate, a plurality of low-potential voltage wires and a plurality of LEDs, which are disposed on the same layer under the substrate to minimize manufacturing cost, A plurality of link wires made of the same material and a first auxiliary wire connected to a portion of the plurality of link wires and a plurality of high potential voltage wires and a plurality of low potential voltage wires are connected to each other and each of the plurality of link wires. It may include a plurality of side wirings disposed on the lower surface.

According to another feature of the present invention, among the plurality of link wirings, the first link wiring may be a high potential voltage link wiring, and the second link wiring may be a low potential voltage link wiring.

According to still another feature of the present invention, the display device is disposed under the substrate, and includes a first pad connected to the first auxiliary wiring, a plurality of first wirings connected to each of the plurality of first pads, and a second one of the plurality of link wirings. A flexible film further comprising: a plurality of second wires connected to each of the remaining portions except for a portion connected to one auxiliary wire; and a flexible film on which second auxiliary wires connected to the plurality of second wires are disposed, a plurality of first pads, a plurality of first The first wiring, the plurality of second wirings, and the second auxiliary wiring may be disposed on the same layer and made of the same material to minimize manufacturing cost.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100, 700, 800: display device
111: first sub substrate
112: second sub substrate
113: gate insulating layer
114: passivation layer
115: adhesive layer
116: first planarization layer
117: second planarization layer
118: bonding layer
119: bank
120: transistor
121: gate electrode
122: active layer
123: source electrode
124: drain electrode
130: LED
131: n-type layer
132: active layer
133: p-type layer
134: p electrode
135: n electrode
141: first electrode
142: second electrode
143: reflective layer
151: side wiring
160: black insulating layer
170: flexible film
171: base film
171a: first base film
171b: second base film
180: printed circuit board
181: pad
190: adhesive layer
VSSL: Low-potential voltage wiring
VDDL: high potential voltage wiring
DL: data wiring
GL: gate wiring
PX: pixel
AA: display area
NA: non-display area
GLL: gate link wiring
DLL: Data Link Wiring
LL1: first link wiring
LL2: second link wiring
P1: first pad
P2: second pad
GDLL: gate driver link wiring
AL1: first auxiliary wiring
GD: gate driver
L1: first wiring
L2: second wiring
L3: third wiring
L4: fourth wiring
L5: fifth wiring
AL2: second auxiliary wiring

Claims (18)

Board;
a plurality of high-potential voltage wires, a plurality of low-potential voltage wires, and a plurality of LEDs disposed on the substrate;
a plurality of first link wires disposed under the substrate, first auxiliary wires connected to the plurality of first link wires, and a plurality of second link wires; and
and a plurality of side wirings connecting each of the plurality of high potential voltage wirings and the low potential voltage wirings and each of the plurality of first link wirings and the plurality of second link wirings. According to claim 1,
one of the first link wiring and the second link wiring is a high potential voltage link wiring, and the other is a low potential voltage link wiring. According to claim 1,
The substrate includes a first sub-substrate and a second sub-substrate,
the plurality of high-potential voltage wires, the plurality of low-potential voltage wires, and the plurality of LEDs are disposed on the first sub-board;
The plurality of first link wirings, the first auxiliary wiring, and the plurality of second link wirings are disposed under the second sub-substrate. According to claim 1,
The plurality of first link wirings, the first auxiliary wirings, and the plurality of second link wirings are made of the same material and disposed on the same layer. According to claim 1,
The first auxiliary wiring extends in a different direction from the plurality of first link wirings and is disposed closer to a center of the substrate than the plurality of first link wirings. According to claim 1,
a plurality of first pads disposed under the substrate and connected to the first auxiliary line; and
a flexible film in which a plurality of first wires connected to each of the plurality of first pads, a plurality of second wires connected to each of the plurality of second link wires, and second auxiliary wires connected to the plurality of second wires are disposed; Further comprising, a display device. 7. The method of claim 6,
The plurality of first pads are made of the same material as the first auxiliary wiring and are disposed on the same layer. 7. The method of claim 6,
The plurality of first wirings, the plurality of second wirings, and the second auxiliary wiring are made of the same material and disposed on the same layer. 7. The method of claim 6,
and the second auxiliary wiring extends in a direction different from that of the plurality of second wirings. 7. The method of claim 6,
a plurality of data lines disposed on the substrate; and
a plurality of data link wires disposed under the substrate;
a portion of the plurality of side wirings connects each of the plurality of data lines and each of the plurality of data link lines. 11. The method of claim 10,
and a plurality of third wirings disposed on the flexible film, connected to each of the plurality of data link wirings, and made of the same material as the plurality of first wirings. 11. The method of claim 10,
The plurality of data link wirings are made of the same material as the plurality of first link wirings and are disposed on the same layer. 7. The method of claim 6,
The plurality of second wires are disposed on one side of the flexible film,
The other side of the flexible film is disposed closer to the center of the substrate than the one side of the flexible film. 7. The method of claim 6,
The plurality of second wires are disposed on one side of the flexible film,
The flexible film is bent so that one side and the other side of the flexible film face each other. According to claim 1,
and a black insulating layer covering the plurality of side wirings. Board;
a plurality of high-potential voltage wires, a plurality of low-potential voltage wires, and a plurality of LEDs disposed on the substrate;
a plurality of link wires disposed on the same layer under the substrate and made of the same material to minimize manufacturing cost and a first auxiliary wire connected to a part of the plurality of link wires; and
and a plurality of side wirings disposed on an upper surface, a side surface, and a lower surface of the substrate to connect each of the plurality of high potential voltage wirings and the low potential voltage wirings and each of the plurality of link wirings. 17. The method of claim 16,
A first link wiring among the plurality of link wirings is a high potential voltage link wiring, and a second link wiring is a low potential voltage link wiring. 17. The method of claim 16,
a plurality of first pads disposed under the substrate and connected to the first auxiliary line; and
a plurality of first wires connected to each of the plurality of first pads, a plurality of second wires connected to each other of the plurality of link wires except for a portion connected to the first auxiliary wire, and the plurality of second wires; It further comprises a flexible film on which the connected second auxiliary wiring is disposed,
The plurality of first pads, the plurality of first wires, the plurality of second wires, and the second auxiliary wire are disposed on the same layer and made of the same material to minimize manufacturing cost.

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