KR20190012970A - Light emitting diode display apparatus and multi screen display apparatus using the same - Google Patents

Abstract

According to an example of the present application, a light emitting diode display device comprises: a substrate; a first unit pixel provided in a central region of the substrate; and a second unit pixel provided at a first edge of the substrate located on a first side of the central region. Each of the first unit pixel and the second unit pixel has a plurality of subpixels, and the second unit pixel further includes a first pad part for applying a signal to the plurality of subpixels. Accordingly, the light emitting diode display device having a bezel width suitable for minimizing a boundary part between display devices connected to each other in a multi-screen device can be provided.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode (LED) display device and a multi-screen display device using the same,

The present invention relates to a light emitting diode display device and a multi-screen display device using the same.

In addition to the display screen of a television or a monitor, the display device is widely used as a display screen of a notebook computer, a tablet computer, a smart phone, a portable display device, or a portable information device.

The liquid crystal display device and the organic light emitting display device display images using a transistor (Thin Film Transistor) as a switching element. Since the liquid crystal display device is not a self-luminous type, an image is displayed using light emitted from a backlight unit disposed under the liquid crystal display panel. Since such a liquid crystal display device has a backlight unit, there are restrictions on the design, and the luminance and response speed may be lowered. Since the organic light emitting display includes an organic material, the organic light emitting display device may be susceptible to moisture, leading to a reduction in reliability and lifetime.

In recent years, research and development of a light emitting diode display device using a micro light emitting device have been underway, and such a light emitting diode display device has been attracting attention as a next generation display because of its high image quality and high reliability.

Conventional light emitting diode display devices are manufactured by transferring a micro light emitting device to a thin film transistor array substrate. Due to the time required for transferring the micro light emitting device, current transfer technology has a relatively large size There is a more favorable aspect to the display.

However, in the conventional LED display device, a pad portion for signal application is provided on the edge of the thin film transistor array substrate, and a bezel region is increased due to a mechanism for hiding the pad portion.

In addition, when a conventional LED display device is manufactured in a large size, productivity is deteriorated due to an increase in the defective transfer ratio of the micro light emitting device due to an increase in the number of pixels. In order to solve such a problem, research and development of a multi-screen device which realizes a large size screen by connecting two or more LED display devices having a relatively small size has been progressed. However, in the case of a multi-screen device, a bezel region of each of the two or more light-emitting diode display devices has a boundary portion called a seam between display devices connected to each other. This boundary part gives a sense of disconnection to the whole screen when one image is displayed on the whole screen, thereby lowering the degree of immersion of the image.

SUMMARY OF THE INVENTION The present invention provides a light emitting diode display device having a minimized bezel area and a multi-screen display device using the light emitting diode display device.

It is another object of the present invention to provide a multi-screen display device in which the boundary between adjacent display devices is minimized.

A light emitting diode display device according to the present application includes a substrate, a first unit pixel provided at a central region of the substrate, and a second unit pixel provided at a first edge of the substrate located at a first side of the central region, And each of the second unit pixels has a plurality of subpixels, and the second unit pixel further includes a first pad unit for signaling the plurality of subpixels.

A multi-screen display device according to the present application includes a plurality of screen modules each having a light emitting diode display device and a plurality of module connecting members connecting the plurality of screen modules with each other, the light emitting diode display device including a substrate, And a second unit pixel provided at a first edge of the substrate located on a first side of the central region, wherein each of the first unit pixel and the second unit pixel has a plurality of subpixels, The unit pixel may further include a first pad portion for applying a signal to the plurality of subpixels.

Specific details of other examples are included in the detailed description and drawings.

According to an aspect of the present invention, there is provided a light emitting diode display device having a bezel width suitable for minimizing a boundary between display devices connected to each other in a multi-screen device, It is possible to improve the sharpness accuracy and productivity.

According to the solution of the above-mentioned problem, in the present application, even if a plurality of screen modules are connected side by side in a lattice form, one image can be displayed in which the disconnection is minimized on the whole screen, The immersion degree can be improved.

In addition to the effects of the present application discussed above, other features and advantages of the present application will be set forth below, or may be apparent to those skilled in the art to which the present application belongs from such description and description.

1 is a plan view showing a light emitting diode display device according to an example of the present application.
FIG. 2 is a view for explaining the first unit pixel shown in FIG. 1. FIG.
FIG. 3 is a view for explaining a second unit pixel shown in FIG. 1. FIG.
4 is a view for explaining the third unit pixel shown in FIG.
5 is a view for explaining the fourth unit pixel shown in FIG.
FIG. 6 is a view for explaining one subpixel shown in FIG. 1. FIG.
7 is a view for explaining a cross-sectional structure of the subpixel shown in FIG.
8 is a cross-sectional view illustrating the structure of the light emitting device shown in FIG.
9 is a cross-sectional view taken along the line I-I 'shown in Fig.
10 is a cross-sectional view taken along the line II-II 'shown in FIG.
11 is a plan view for explaining a recess provided in the unit pixel shown in Fig.
12 is a sectional view of III-III 'shown in FIG.
13 is a diagram for explaining a multi-screen display device according to an example of the present application.
14 is a cross-sectional view taken along the line IV-IV 'shown in Fig.
15A and 15B are views showing images displayed on each of the conventional multi-screen display device and the multi-screen display device according to the present application.

Brief Description of the Drawings The advantages and features of the present application, and how to accomplish them, will become apparent upon reference to the following detailed description, taken in conjunction with the accompanying drawings. It will be understood, however, that the invention is not limited to the examples disclosed herein but may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art. Are provided to fully disclose the scope of the invention, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like described in the drawings for describing the example of the present application are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the description of the present application, a detailed description of known related arts will be omitted if it is determined that the gist of the present application may be unnecessarily obscured. In the case where the term "including", "having", or "being done" is used in the present application, other parts may be added unless "~" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

In describing the components of the present application, the terms first and second can be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

Accordingly, the display device of the present application may include a display device itself, such as an LCM, an OLED module or the like, and an application device including an LCM, an OLED module, or the like, or a set device which is an end consumer device.

For example, when the display panel is an organic light emitting (OLED) display panel, it may include a plurality of gate lines and data lines, and pixels formed at intersections of the gate lines and the data lines. An array substrate including a thin film transistor which is a device for selectively applying a voltage to each pixel, an organic light emitting element (OLED) layer on the array substrate, and an encapsulating substrate Or an encapsulation substrate, or the like. The sealing substrate protects the thin film transistor, the organic light emitting element layer, and the like from external impact and can prevent water or oxygen from penetrating into the organic light emitting element layer. In addition, the layer formed on the array substrate may include an inorganic light emitting layer, for example, a nano-sized material layer or a quantum dot.

The display panel may further include a backing such as a metal plate attached to the display panel. The present invention is not limited to the metal plate but may include other structures.

Each of the features of the various embodiments of the present application may be combined or combined with each other partially or entirely, technically various interlocking and driving are possible, and the examples may be independently performed with respect to each other, .

Hereinafter, an example of the present application will be described with reference to the accompanying drawings and examples.

1 is a plan view showing a light emitting diode display device 10 according to an example of the present application.

Referring to FIG. 1, a light emitting diode display 10 includes a substrate 100 and a plurality of unit pixels disposed on the substrate 100. The substrate 100 includes a glass material or a plastic material. The plastic substrate 100 may comprise an opaque or colored polyimide material. Further, the substrate 100 may be represented by a thin film transistor array substrate or a display panel.

Each of the plurality of unit pixels includes a plurality of sub-pixels (SP) provided in a sub-pixel region defined by gate lines and data lines on the substrate (100). Here, each of the plurality of sub-pixels SP may be defined as a minimum unit area for emitting light. For example, each of the plurality of unit pixels may include at least three adjacent sub-pixels SP.

The plurality of unit pixels may include first and second unit pixels UP1 and UP2. The first unit pixel UP1 is provided in the central region of the substrate 100 and may include a plurality of sub-pixels SP. According to an example, the first unit pixel UP1 may include a plurality of first unit pixels UP1 provided in a central region of the substrate 100. [ Each of the plurality of first unit pixels UP1 has a first reference pixel pitch P along a first horizontal axis direction X and a predetermined second reference pixel pitch P along a second horizontal axis direction Y, And may be provided in the central region of the substrate 100 so as to have a pixel pitch. Here, the first horizontal axis direction X may be parallel to the first longitudinal direction X of the substrate 100, for example, the longitudinal direction of the long side of the substrate 100, and the second horizontal axis direction Y May be parallel to the second longitudinal direction Y of the substrate 100, for example, the short side length direction of the substrate 100. [ The first reference pixel pitch P may be defined as a distance between the right central portions of each of the two first unit pixels UP1 adjacent to each other along the first horizontal axis direction X, Can be defined as the distance between the right central portions of the two first unit pixels UP1 adjacent to each other along the horizontal axis direction Y. [

The second unit pixel UP2 is provided at the first edge of the substrate 100 located on the first side of the central region of the substrate 100 and includes a plurality of sub pixels SP and a plurality of sub pixels SP, And a first pad portion for applying a signal to the first pad portion. The second unit pixel UP2 may include a plurality of second unit pixels UP2 provided at a first edge of the substrate 100 located on the left side of the central region of the substrate 100. [ Each of the plurality of second unit pixels UP2 may be provided at the first edge of the substrate 100 so as to have a predetermined second reference pixel pitch along the second horizontal axis direction Y. [ Here, the second horizontal axis direction Y may be parallel to the second longitudinal direction Y of the substrate 100, for example, the longitudinal direction of the short side of the substrate 100, And the center between the two second unit pixels UP2 adjacent to each other in the horizontal axis direction Y. [

The first pad unit may be provided in a part of the second unit pixel UP2 and may apply a signal to each of the plurality of sub-pixels SP. According to an example, when the first pad portion is implemented as a gate pad portion, the first pad portion may be provided in the left region of the second unit pixel UP2 and may provide a gate signal to each of the plurality of sub-pixels SP. Hereinafter, the first pad unit will be described in detail through the second unit pixel UP2 shown in FIG.

According to an example, the second unit pixel UP2 may have a smaller size than the first unit pixel UP1. Specifically, the second unit pixel UP2 may be formed by cutting (or cutting) one side of the unit pixel having the same size as the first unit pixel UP1 by the first width W1. Therefore, the LED display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100 with the same size as the reference pixel pitch, By reducing the size of the second unit pixels UP2 provided at the first edge of the first unit pixel UP2, it is possible to have a bezel width suitable for minimizing the boundary between the LED display devices 10 connected to each other in the multi-screen device. As a result, the multi-screen display device according to the present example has a plurality of light emitting diode display devices (or a plurality of screen modules) It is possible to minimize the dark region generated by the boundary portion provided between the diode display devices 10 and to provide an image in which the sense of disconnection disappears in the entire screen.

The plurality of unit pixels may further include a third unit pixel UP3. The third unit pixel UP3 is provided at the second edge of the substrate 100 located on the second side different from the first side of the central region of the substrate 100 and includes a plurality of sub pixels SP, And a second pad portion for applying a signal to the pixels SP. The third unit pixel UP3 may include a plurality of third unit pixels UP3 provided on the second edge of the substrate 100 located on the upper side of the central region of the substrate 100. [ Each of the plurality of third unit pixels UP3 may be provided at the first edge of the substrate 100 so as to have a predetermined first reference pixel pitch P along the first horizontal axis direction X. [ Here, the first horizontal axis direction X may be parallel to the first longitudinal direction X of the substrate 100, for example, the longitudinal direction of the long side of the substrate 100, and the first reference pixel pitch P May be defined as the distance between the right central portions of each of the two first unit pixels UP1 adjacent to each other along the first horizontal axis direction X. [

The second pad unit may be provided in a part of the third unit pixel UP2 to apply a signal to each of the plurality of sub pixels SP. According to an example, when the second pad portion is implemented as a data pad portion, the second pad portion may be provided in the upper region of the third unit pixel UP2 to provide a data signal to each of the plurality of sub pixels SP. Hereinafter, the second pad unit will be described in detail through the third unit pixel UP3 shown in FIG.

According to an example, the third unit pixel UP3 may have a smaller size than the first unit pixel UP1. Specifically, the third unit pixel UP3 may be formed by cutting (or cutting) one side of a unit pixel having the same size as the first unit pixel UP1 by a second width W2. Therefore, the LED display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100 with the same size as the reference pixel pitch, By reducing the size of the third unit pixels UP3 provided at the two edges, it is possible to have a bezel width suitable for minimizing the boundary between the LED display devices 10 connected to each other in the multi-screen device. In addition, the light emitting diode display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100, each of the first unit pixels UP1 having the same reference pixel pitch, By reducing the size of the second unit pixels UP2 provided at the first edge of the substrate 100 and decreasing the size of the third unit pixels UP3 provided at the second edge of the substrate 100, May have a bezel width that is suitable for minimizing the interface between the devices 10.

The plurality of unit pixels may further include a fourth unit pixel UP4. The fourth unit pixel UP4 is provided at a first edge of the substrate 100 located between the first edge and the second edge of the substrate 100 and includes a plurality of subpixels SP and a plurality of subpixels And a first pad portion and a second pad portion for applying a signal to the signal line SP. According to an example, the fourth unit pixel UP4 may be disposed at a first corner located between the left side and the upper side of the central region of the substrate 100. [

The first pad unit may be provided in a part of the fourth unit pixel UP4 and may apply a signal to each of the plurality of sub-pixels SP. According to an example, when the first pad portion is implemented as a gate pad portion, the first pad portion may be provided in the left region of the fourth unit pixel UP4 and may provide a gate signal to each of the plurality of sub-pixels SP. Hereinafter, the first pad unit will be described in detail through the fourth unit pixel UP4 shown in FIG.

The second pad unit may be provided in a part of the fourth unit pixel UP4 to apply a signal to each of the plurality of sub-pixels SP. According to an example, when the second pad portion is implemented as a data pad portion, the second pad portion may be provided in an upper region of the fourth unit pixel UP4 to provide a data signal to each of the plurality of sub-pixels SP. Hereinafter, the second pad unit will be described in detail through the fourth unit pixel UP4 shown in FIG.

According to one example, the fourth unit pixel UP4 may have a smaller size than the first, second, and third unit pixels UP1, UP2, and UP3. Specifically, the fourth unit pixel UP4 is formed such that one side of the unit pixel having the same size as the first unit pixel UP1 is cut (or cut) by the first width W1, and the other side of the unit pixel (Or cut) by the second width W2. Therefore, the LED display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100 with the same size as the reference pixel pitch, It is possible to have a bezel width suitable for minimizing the boundary between the LED display devices 10 connected to each other in the multi-screen device by reducing the size of the fourth unit pixel UP4 provided at one corner. In addition, the light emitting diode display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100, each of the first unit pixels UP1 having the same reference pixel pitch, The size of the second unit pixels UP2 provided at the first edge of the substrate 100 is reduced and the size of the third unit pixels UP3 provided at the second edge of the substrate 100 is reduced, It is possible to reduce the size of the fourth unit pixel UP4 provided in the multi-screen device to have a bezel width suitable for minimizing the boundary between the LED display devices 10 connected to each other in the multi-screen device.

The plurality of unit pixels may further include a fifth unit pixel UP5. The fifth unit pixel UP5 is provided on the third edge of the substrate 100 located on the third side opposite to the first side of the central region of the substrate 100 and includes a plurality of subpixels SP . The fifth unit pixel UP5 may include a plurality of fifth unit pixels UP5 provided on the third edge of the substrate 100 located on the right side of the central region of the substrate 100. [ Each of the plurality of fifth unit pixels UP5 may be provided at the third edge of the substrate 100 so as to have a predetermined second reference pixel pitch along the second horizontal axial direction (Y). Here, the second horizontal axis direction Y may be parallel to the second longitudinal direction Y of the substrate 100, for example, the longitudinal direction of the short side of the substrate 100, And the center between the two fifth unit pixels UP5 adjacent to each other in the horizontal axis direction Y. [

According to another example, the fifth unit pixel UP5 may further include a first pad portion for applying a signal to each of the plurality of sub-pixels SP. The first pad unit may be provided in a part of the fifth unit pixel UP5 and may apply a signal to each of the plurality of sub-pixels SP. For example, when the first pad portion is implemented as a gate pad portion, the first pad portion may be provided in the right region of the fifth unit pixel UP5 and may provide a gate signal to each of the plurality of sub-pixels SP. As a result, the fifth unit pixel UP5 may or may not include the first pad portion for signal application to each of the plurality of sub-pixels SP. For example, when the light emitting diode display device 10 is manufactured in a large size, the fifth unit pixel UP5 may further include a first pad portion.

According to an example, the fifth unit pixel UP5 may have a smaller size than the first unit pixel UP1. Specifically, the fifth unit pixel UP5 may be formed by cutting (or cutting) one side of the unit pixel having the same size as the first unit pixel UP1 by the fourth width W4. Therefore, the LED display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100 with the same size as the reference pixel pitch, By reducing the size of the fifth unit pixels UP5 provided at the three edges of the display device 10, it is possible to have a bezel width suitable for minimizing the boundary between the LED display devices 10 connected to each other in the multi-screen device. As a result, the multi-screen display device according to the present example has a plurality of light emitting diode display devices (or a plurality of screen modules) It is possible to minimize the dark region generated by the boundary portion provided between the diode display devices 10 and to provide an image in which the sense of disconnection disappears in the entire screen.

The fifth unit pixel UP5 may include a first power supply line, first and second power supply lines. According to one example, the first power supply line may be disposed on one side of the plurality of sub-pixels SP along the first direction X. [ For example, the first power supply line may be disposed on the left side of the plurality of sub-pixels SP.

According to one example, the first and second power supply bridge lines may be disposed on both sides of the plurality of subpixels SP along a second direction Y that is orthogonal to the first direction X. For example, the first power supply bridge line may be disposed above the plurality of subpixels SP, and the second power supply bridge line may be disposed below the plurality of subpixels SP. The first power supply bridge line may connect the first power supply line and each of the plurality of subpixels (SP).

The plurality of unit pixels may further include a sixth unit pixel UP6. The sixth unit pixel UP6 is provided at the second edge of the substrate 100 positioned between the second edge and the third edge of the substrate 100 and includes a plurality of subpixels SP and a plurality of subpixels And a second pad portion for applying a signal to the scan electrode SP. According to an example, the sixth unit pixel UP6 may be disposed at a second corner located between the right side and the upper side of the central region of the substrate 100. [

The second pad unit may be provided in a part of the sixth unit pixel UP6 to apply a signal to each of the plurality of sub-pixels SP. According to an example, when the second pad portion is implemented as a data pad portion, the second pad portion may be provided in an upper region of the sixth unit pixel UP6 to provide a data signal to each of the plurality of sub-pixels SP.

According to another example, the sixth unit pixel UP6 may further include a first pad portion for applying a signal to each of the plurality of sub-pixels SP. The first pad unit may be provided in a part of the sixth unit pixel UP6 to apply a signal to each of the plurality of sub-pixels SP. For example, when the first pad portion is implemented as a gate pad portion, the first pad portion may be provided in the right region of the sixth unit pixel UP6 and may provide a gate signal to each of the plurality of sub-pixels SP. As a result, the sixth unit pixel UP6 may or may not include the first pad portion for signal application to each of the plurality of sub-pixels SP. For example, when the light emitting diode display device 10 is manufactured in a large size, the sixth unit pixel UP6 may further include a first pad portion.

According to an example, the sixth unit pixel UP6 may have a smaller size than the first, second, third, and fifth unit pixels UP1, UP2, UP3, and UP5. Specifically, the sixth unit pixel UP6 is formed such that one side of the unit pixel having the same size as the first unit pixel UP1 is cut (or cut) by the second width W2, and the other side of the unit pixel And cut (or cut) by the fourth width W4. Therefore, the LED display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100 with the same size as the reference pixel pitch, It is possible to have a bezel width suitable for minimizing the boundary between the LED display devices 10 connected to each other in the multi-screen device by reducing the size of the sixth unit pixel UP6 provided at the two corners. In addition, the light emitting diode display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100, each of the first unit pixels UP1 having the same reference pixel pitch, The size of the third unit pixels UP3 at the second edge of the substrate 100 is reduced and the size of the fifth unit pixels UP5 at the third edge of the substrate 100 is reduced, By reducing the size of the sixth unit pixel UP6 provided in the multi-screen device, the bezel width may be suitable to minimize the boundary between the LED display devices 10 connected to each other in the multi-screen device.

The sixth unit pixel UP6 may include a first power supply line, first and second power supply bridge lines. According to one example, the first power supply line may be disposed on one side of the plurality of sub-pixels SP along the first direction X. [ For example, the first power supply line may be disposed on the left side of the plurality of sub-pixels SP.

According to one example, the first and second power supply bridge lines may be disposed on one side of the plurality of subpixels SP along a second direction Y orthogonal to the first direction X. [ The first and second power supply bridge lines may be disposed on the opposite side of the second pad portion along a second direction Y perpendicular to the first direction X. [ For example, the first and second power supply bridge lines may be disposed below the plurality of sub-pixels SP. The first power supply bridge line may connect the first power supply line and each of the plurality of subpixels (SP).

The plurality of unit pixels may further include a seventh unit pixel UP7. The seventh unit pixel UP7 is provided on the fourth edge of the substrate 100 located on the fourth side opposite to the second side of the central region of the substrate 100 and includes a plurality of subpixels SP . The seventh unit pixel UP7 may include a plurality of seventh unit pixels UP7 provided at the fourth edge of the substrate 100 located below the central region of the substrate 100. In this case, Each of the plurality of seventh unit pixels UP7 may be provided at the fourth edge of the substrate 100 so as to have a predetermined first reference pixel pitch P along the first horizontal axis direction X. [ Here, the first horizontal axis direction X may be parallel to the first longitudinal direction X of the substrate 100, for example, the longitudinal direction of the long side of the substrate 100, and the first reference pixel pitch P May be defined as the distance between the right central portions of each of the two first unit pixels UP1 adjacent to each other along the first horizontal axis direction X. [

According to another example, the seventh unit pixel UP7 may further include a second pad portion for applying a signal to each of the plurality of sub-pixels SP. The second pad unit may be provided in a part of the seventh unit pixel UP7 to apply a signal to each of the plurality of sub-pixels SP. For example, when the second pad portion is implemented as a data pad portion, the second pad portion may be provided in a lower region of the seventh unit pixel UP5 to provide a data signal to each of the plurality of sub-pixels SP. As a result, the seventh unit pixel UP7 may or may not include the second pad portion for signal application to each of the plurality of sub-pixels SP. For example, when the light emitting diode display 10 is manufactured in a large size, the seventh unit pixel UP7 may further include a second pad portion.

According to an example, the seventh unit pixel UP5 may have a smaller size than the first unit pixel UP1. Specifically, the seventh unit pixel UP7 may be formed by cutting (or cutting) one side of a unit pixel having the same size as the first unit pixel UP1 by a third width W3. Therefore, the LED display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100 with the same size as the reference pixel pitch, By reducing the size of the seventh unit pixels UP7 provided at the four edges, it is possible to have a bezel width suitable for minimizing the boundary between the LED display devices 10 connected to each other in the multi-screen device. As a result, the multi-screen display device according to the present example has a plurality of light emitting diode display devices (or a plurality of screen modules) It is possible to minimize the dark region generated by the boundary portion provided between the diode display devices 10 and to provide an image in which the sense of disconnection disappears in the entire screen.

The seventh unit pixel UP7 may include first and second power supply lines, first and second power supply bridge lines. According to one example, the first and second power supply lines may be disposed on both sides of the plurality of sub-pixels SP along the first direction X. [ For example, the first power supply line may be disposed on the left side of the plurality of subpixels SP, and the second power supply line may be disposed on the right side of the plurality of subpixels SP. That is, the first and second power supply lines may be spaced apart from each other with a plurality of sub-pixels SP in the first direction X. [

According to one example, the first and second power supply bridge lines may be disposed on one side of the plurality of subpixels SP along a second direction Y orthogonal to the first direction X. [ For example, the first and second power supply bridge lines may be disposed above the plurality of sub-pixels SP. The first power supply bridge line connects the first power supply line and each of the plurality of subpixels SP and the second power supply line connects the second power supply line and each of the plurality of subpixels SP .

The plurality of unit pixels may further include an eighth unit pixel UP8. The eighth unit pixel UP8 is provided at the third edge of the substrate 100 positioned between the first and fourth edges of the substrate 100 and includes a plurality of subpixels SP and a plurality of subpixels And a first pad portion for applying a signal to the scan electrode SP. According to one example, the eighth unit pixel UP8 may be disposed at a third corner located between the left and the lower sides of the central region of the substrate 100. [

The first pad unit may be provided in a part of the eighth unit pixel UP8 to apply a signal to each of the plurality of sub-pixels SP. According to an example, when the first pad portion is implemented as a gate pad portion, the first pad portion may be provided in the left region of the eighth unit pixel UP6 to provide a data signal to each of the plurality of sub-pixels SP.

According to another example, the eighth unit pixel UP8 may further include a second pad portion for applying a signal to each of the plurality of sub-pixels SP. The second pad unit may be provided in a part of the eighth unit pixel UP8 to apply a signal to each of the plurality of sub-pixels SP. For example, when the second pad portion is implemented as a data pad portion, the second pad portion may be provided in a lower region of the eighth unit pixel UP8 to provide a data signal to each of the plurality of sub-pixels SP. As a result, the eighth unit pixel UP8 may or may not include the second pad portion for signal application to each of the plurality of sub-pixels SP. For example, when the light emitting diode display 10 is manufactured in a large size, the eighth unit pixel UP8 may further include a second pad portion.

According to an example, the eighth unit pixel UP8 may have a smaller size than the first, second, third, fifth, and seventh unit pixels UP1, UP2, UP3, UP5, and UP7. Specifically, the eighth unit pixel UP8 is formed such that one side of the unit pixel having the same size as the first unit pixel UP1 is cut (or cut) by the first width W1, and the other side of the unit pixel (Or cut) by a third width W3. Therefore, the LED display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100 with the same size as the reference pixel pitch, It is possible to have a bezel width suitable for minimizing the boundary between the LED display devices 10 connected to each other in the multi-screen device by reducing the size of the eighth unit pixel UP8 provided at the three corners. In addition, the light emitting diode display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100, each of the first unit pixels UP1 having the same reference pixel pitch, The size of the second unit pixels UP2 provided at the first edge of the substrate 100 is reduced and the size of the seventh unit pixels UP7 provided at the fourth edge of the substrate 100 is reduced, By reducing the size of the eighth unit pixel UP8 provided in the multi-screen device, the bezel width may be suitable for minimizing the boundary between the LED display devices 10 connected to each other in the multi-screen device.

The eighth unit pixel UP8 may include a second power supply line, first and second power supply lines. According to one example, the second power supply line may be disposed on one side of the plurality of sub-pixels SP along the first direction X. [ The second power supply line may be disposed on the opposite side of the first pad portion along the first direction (X). For example, the second power supply line may be disposed on the right side of the plurality of sub-pixels SP.

According to one example, the first and second power supply bridge lines may be disposed on one side of the plurality of subpixels SP along a second direction Y orthogonal to the first direction X. [ For example, the first and second power supply bridge lines may be disposed above the plurality of sub-pixels SP. The second power supply bridge line may connect each of the plurality of subpixels (SP) with the second power supply line.

The plurality of unit pixels may further include a ninth unit pixel UP9. The ninth unit pixel UP9 is provided at the fourth edge of the substrate 100 positioned between the third edge and the fourth edge of the substrate 100 and may include a plurality of subpixels SP. According to an example, the ninth unit pixel UP9 may be disposed at a fourth corner located between the right side and the lower side of the central region of the substrate 100. [

According to another example, the ninth unit pixel UP9 may further include a first pad portion for applying a signal to each of the plurality of sub-pixels SP. The first pad unit may be provided in a part of the ninth unit pixel UP9 and may apply a signal to each of the plurality of sub-pixels SP. For example, when the first pad portion is implemented as a gate pad portion, the first pad portion may be provided in the right region of the ninth unit pixel UP9 to provide a gate signal to each of the plurality of sub-pixels SP. As a result, the ninth unit pixel UP9 may or may not include the first pad portion for signal application to each of the plurality of sub-pixels SP. For example, when the light emitting diode display device 10 is manufactured in a large size, the ninth unit pixel UP9 may further include a first pad portion.

According to another example, the ninth unit pixel UP9 may further include a second pad portion for signal application to each of the plurality of sub-pixels SP. The second pad unit may be provided in a part of the ninth unit pixel UP9 to apply a signal to each of the plurality of sub-pixels SP. For example, when the second pad portion is implemented as a data pad portion, the second pad portion may be provided in a lower region of the ninth unit pixel UP9 to provide a data signal to each of the plurality of sub-pixels SP. As a result, the ninth unit pixel UP9 may or may not include a second pad portion for signal application to each of the plurality of sub-pixels SP. For example, when the light emitting diode display device 10 is manufactured in a large size, the ninth unit pixel UP9 may further include a second pad portion.

According to an example, the ninth unit pixel UP9 may have a smaller size than the first, second, third, fifth, and seventh unit pixels UP1, UP2, UP3, UP5, and UP7. Specifically, the ninth unit pixel UP9 is formed such that one side of the unit pixel having the same size as the first unit pixel UP1 is cut (or cut) by the third width W3, and the other side of the unit pixel UP9 is cut And cut (or cut) by the fourth width W4. Therefore, the LED display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100 with the same size as the reference pixel pitch, By reducing the size of the ninth unit pixel UP9 provided at the four corners, it is possible to have a bezel width suitable for minimizing the boundary between the LED display devices 10 connected to each other in the multi-screen device. In addition, the light emitting diode display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100, each of the first unit pixels UP1 having the same reference pixel pitch, The size of the fifth unit pixels UP5 provided at the third edge of the substrate 100 is reduced and the size of the seventh unit pixels UP7 provided at the fourth edge of the substrate 100 is reduced, It is possible to have a bezel width suitable for minimizing the boundary between the LED display devices 10 connected to each other in the multi-screen device by reducing the size of the ninth unit pixel UP9 provided in the multi-screen device.

The ninth unit pixel UP9 may include a first power supply line, first and second power supply lines. According to one example, the first power supply line may be disposed on one side of the plurality of sub-pixels SP along the first direction X. [ For example, the first power supply line may be disposed on the left side of the plurality of sub-pixels SP.

According to one example, the first and second power supply bridge lines may be disposed on one side of the plurality of subpixels SP along a second direction Y orthogonal to the first direction X. [ For example, the first and second power supply bridge lines may be disposed above the plurality of sub-pixels SP. The first power supply bridge line may connect the first power supply line and each of the plurality of subpixels (SP).

FIG. 2 is a view for explaining the first unit pixel shown in FIG. 1. FIG.

2, the first unit pixel UP1 includes a plurality of subpixels SP, first and second mesh power lines PL1 and PL2, a gate line GL, and a data line DL. .

Each of the plurality of sub pixels SP is provided in a sub pixel area defined by the intersection of the gate line GL and the data line DL. Here, each of the plurality of sub-pixels SP may be defined as a minimum unit area for emitting light. Each of the plurality of subpixels SP according to an example may include a first subpixel SPa and a second subpixel SPb. Here, any one of the first subpixel SPa and the second subpixel SPb is formed on the misaligned or electric gate insulating layer generated in the process of mounting the light emitting device ED on the substrate 100 And may be used as a redundancy subpixel provided in advance in case of operation failure due to a plurality of impacts with the first power supply line PL1a.

The first unit pixel UP1 includes at least three sub-pixels SP adjacent in the first direction X of the substrate 100. [ Here, one subpixel SP can be defined as a minimum unit for displaying a color image. For example, the first unit pixel UP1 may include a red subpixel, a green subpixel, and a blue subpixel. Furthermore, the first unit pixel UP1 may further include a white subpixel.

At least three subpixels SP constituting the first unit pixel UP1 are arranged in the subpixel region according to the size set according to the resolution of the LED display device 10, They can be arranged together. Accordingly, the subpixel region may have remaining free space excluding the subpixel arrangement region.

The gate line GL is provided on the front surface of the substrate 100 and extends along the first direction X while extending along the second direction Y intersecting the first direction X They are spaced apart at regular intervals. Here, the first direction X can be defined as a direction parallel to the lateral direction of the substrate 100, and the second direction Y can be defined as a direction parallel to the longitudinal direction of the substrate 100, But may be defined in the opposite direction.

The data lines DL are provided on the front surface of the substrate 100 so as to intersect with the gate lines GL and are extended along the second direction Y while being constantly formed along the first direction X Spaced apart.

The first unit pixel UP1 may include first and second power supply lines PL1a and PL2a, and first and second power supply lines PL1c and PL2c. According to one example, the first and second power supply lines PL1a and PL2a may be disposed on both sides of the plurality of sub-pixels SP along the first direction X. [ For example, the first power supply line PL1a may be disposed on the left side of the plurality of subpixels SP, and the second power supply line PL2a may be disposed on the right side of the plurality of subpixels SP. have. That is, the first and second power supply lines PL1a and PL2a may be spaced apart from each other by a plurality of sub-pixels SP along the first direction X. [

According to one example, the first and second power supply bridge lines PL1c and PL2c are disposed on both sides of the plurality of subpixels SP along a second direction Y orthogonal to the first direction X . For example, the first power supply bridge line PL1c may be disposed above the plurality of subpixels SP, and the second power bridge line PL2c may be disposed below the plurality of subpixels SP. have. That is, the first and second power supply bridge lines PL1c and PL2c may be spaced apart from each other with a plurality of sub-pixels SP therebetween along the second direction Y. [ The first power supply line PL1c connects the first power supply line PL1a and each of the plurality of sub pixels SP and the second power supply line PL2c connects the second power supply line PL2a and a plurality of (SP) of each sub-pixel.

More specifically, the first mesh power line PL1 includes a first power supply line PL1a, a plurality of first pixel power lines PL1b, and a first power supply line PL1c. The first power supply line PL1a may be disposed in a first space provided on one side of the first unit pixel UP1 so as to be parallel to the second direction Y. [

Each of the plurality of first pixel power supply lines PL1b is disposed on one side of each of the plurality of subpixels SP so as to be parallel with the first power supply line PL1a. At this time, each of the plurality of first pixel power supply lines PL1b may be electrically separated from the first power supply line PL1a.

The first power supply bridge line PL1c is disposed in parallel with the first direction X and may intersect each of the first power supply line PL1a and each of the plurality of first pixel power supply lines PL1b. The first power supply bridge line PL1c may be electrically connected to the first power supply line PL1a and the plurality of first pixel power supply lines PL1b through the plurality of first bridge contact holes BCH1. That is, each of the plurality of first bridge contact holes BCH1 is formed at an intersection of the first power supply line PL1c and the first power supply line PL1a, and the first power supply bridge line PL1c is formed of a plurality of And may be electrically connected to the first power supply line PL1a through each of the first bridge contact holes BCH1. Each of the plurality of first bridge contact holes BCH1 is formed at an intersection of the first power supply bridge line PL1c and the first pixel power line PL1b and the first power bridge line PL1c is formed at a plurality of And may be electrically connected to each of the plurality of first pixel power supply lines PL1b through each of the first bridge contact holes BCH1.

Accordingly, the first mesh power line PL1 is connected to the first power supply line PL1a, the plurality of first pixel power lines PL1b, and the first power supply line PL1c via the plurality of subpixels SP The panel load can be reduced and the voltage drop of the first driving power source can be minimized. At this time, if the first power supply line PL1c is made of a metal material having low resistance such as copper (Cu), silver (Ag), aluminum (Al), or gold (Au) , The voltage drop of the first driving power supply can be further reduced.

The second mesh power line PL2 includes a second power supply line PL2a, a plurality of second pixel power lines PL2b, and a second power supply line PL2c. The second power supply line PL2a may be disposed in the second clearance space provided on the other side of the first unit pixel UP1 so as to be parallel to the second direction Y. [

Each of the plurality of second pixel power supply lines PL2b is disposed on one side of each of the plurality of subpixels SP so as to be parallel with the second power supply line PL2a. At this time, each of the plurality of second pixel power supply lines PL2b may be electrically separated from the second power supply line PL2a.

The second power supply line PL2c is disposed in parallel with the first direction X and may intersect each of the second power supply line PL2a and each of the plurality of second pixel power supply lines PL2b. The second power supply bridge line PL2c may be electrically connected to the second power supply line PL2a and the plurality of second pixel power supply lines PL2b through the plurality of second bridge contact holes BCH2. That is, each of the plurality of second bridge contact holes BCH2 is formed at the intersection of the second power supply line PL2c and the second power supply line PL2a, and the second power supply line PL2c is formed at the intersection of the plurality And may be electrically connected to the second power supply line PL2a through each of the second bridge contact holes BCH2. Each of the second bridge contact holes BCH2 is formed at the intersection of the second power supply line PL2c and the second pixel power line PL2b and the second power supply line PL2c is formed at the intersection of the plurality And may be electrically connected to each of the plurality of second pixel power supply lines PL2b through each of the second bridge contact holes BCH2.

Accordingly, the second mesh power line PL2 is connected to the second power supply line PL2a, the plurality of second pixel power lines PL2b, and the second power supply line PL2c through the plurality of subpixels SP The panel load can be reduced and the voltage increase of the second driving power source can be minimized. At this time, when the second power supply line PL2c is made of a metal material having low resistance such as copper (Cu), silver (Ag), aluminum (Al), or gold (Au) , The voltage rise of the second driving power supply can be further reduced.

As described above, the LED display device 10 according to an embodiment of the present invention includes the first mesh power line PL1 and the second mesh power line PL2, thereby reducing the load on the panel and enabling low power driving, And the image quality uniformity can be improved as the voltage drop of the first drive power source and the rise of the second drive power source are reduced.

FIG. 3 is a view for explaining a second unit pixel shown in FIG. 1. FIG.

Referring to FIG. 3, the second unit pixel UP2 includes a plurality of subpixels SP, first and second mesh power supply lines PL1 and PL2, a gate line GL, a data line DL, An electrostatic discharge (ESD) protection circuit, and a first pad portion GP. Here, a redundant description of the plurality of sub-pixels SP, the gate line GL, the data line DL, and the first and second mesh power supply lines PL1 and PL2 will be omitted.

The second unit pixel UP2 may include a second power supply line PL2a, first and second power supply lines PL1c and PL2c. According to an example, the second power supply line PL2a may be disposed on one side of the plurality of sub-pixels SP along the first direction X. [ The second power supply line PL2a may be disposed on the opposite side of the first pad portion GP along the first direction X. [ For example, the second power supply line PL2a may be disposed on the right side of the plurality of subpixels SP.

According to one example, the first and second power supply bridge lines PL1c and PL2c are disposed on both sides of the plurality of subpixels SP along a second direction Y orthogonal to the first direction X . For example, the first power supply bridge line PL1c may be disposed above the plurality of subpixels SP, and the second power bridge line PL2c may be disposed below the plurality of subpixels SP. have. That is, the first and second power supply bridge lines PL1c and PL2c may be spaced apart from each other with a plurality of sub-pixels SP therebetween along the second direction Y. [ The second power supply line PL2c may couple each of the plurality of subpixels SP with the second power supply line PL2a.

The first pad unit GP may be provided in a part of the second unit pixel UP2 and may apply a signal to each of the plurality of sub-pixels SP. According to an example, when the first pad portion GP is implemented as a gate pad portion GP, the first pad portion GP is provided in the left region of the second unit pixel UP2, 0.0 > SP, < / RTI > In addition, the second unit pixel UP2 may further include an electrostatic discharge protection circuit (ESD) connected to one side of the first pad portion GP. The first pad unit GP may be connected to the gate line GL through a link. That is, the first pad unit GP may provide a gate signal to the plurality of sub-pixels SP through the gate line GL.

According to one example, the second unit pixel UP2 may include first and second free spaces provided on both sides of the plurality of sub-pixels SP along the first direction X. [ For example, the first free space corresponds to the left region of the plurality of sub-pixels SP, and the second free space corresponds to the right region of the plurality of sub-pixels SP. The first clearance space can accommodate the first pad portion GP and the electrostatic discharge protection circuit (ESD), and the second clearance space can accommodate the second power supply line PL2a. Accordingly, the second unit pixel UP2 includes the first pad portion GP disposed in the first clearance space and the second power supply line PL2a disposed in the second clearance space, so that the light emitting diode display device 10 Can reduce the size of the unit pixels and does not require a separate space for concealing the first pad portion GP, thereby minimizing the bezel area. In addition, the multi-screen display device including the plurality of light emitting diode display devices 10 can minimize a boundary between the LED display devices 10 connected to each other, thereby displaying a single image with a minimum disconnection on the entire screen .

According to an example, the second unit pixel UP2 may have a smaller size than the first unit pixel UP1. Specifically, the second unit pixel UP2 may be formed by cutting one side of a unit pixel having the same size as the first unit pixel UP1 along a cutting line CPS Line. That is, the second unit pixel UP2 may be formed by cutting (or cutting) the left side of the unit pixel having the same size as the first unit pixel UP1 by the first width W1. Therefore, the LED display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100 with the same size as the reference pixel pitch, By reducing the size of the second unit pixels UP2 provided at the first edge of the first unit pixel UP2, it is possible to have a bezel width suitable for minimizing the boundary between the LED display devices 10 connected to each other in the multi-screen device. As a result, the multi-screen display device according to the present example has a plurality of light emitting diode display devices (or a plurality of screen modules) It is possible to minimize the dark region generated by the boundary portion provided between the diode display devices 10 and to provide an image in which the sense of disconnection disappears in the entire screen.

4 is a view for explaining the third unit pixel shown in FIG.

4, the third unit pixel UP3 includes a plurality of subpixels SP, first and second mesh power supply lines PL1 and PL2, a gate line GL, a data line DL, An electrostatic discharge (ESD) protection circuit, and a first pad portion GP. Here, a redundant description of the plurality of sub-pixels SP, the gate line GL, the data line DL, and the first and second mesh power supply lines PL1 and PL2 will be omitted.

The third unit pixel UP3 may include first and second power supply lines PL1a and PL2a, and first and second power supply lines PL1c and PL2c. According to one example, the first and second power supply lines PL1a and PL2a may be disposed on both sides of the plurality of sub-pixels SP along the first direction X. [ For example, the first power supply line PL1a may be disposed on the left side of the plurality of subpixels SP, and the second power supply line PL2a may be disposed on the right side of the plurality of subpixels SP. have. That is, the first and second power supply lines PL1a and PL2a may be spaced apart from each other by a plurality of sub-pixels SP along the first direction X. [

According to one example, the first and second power supply bridge lines PL1c and PL2c are disposed on one side of the plurality of subpixels SP along a second direction Y orthogonal to the first direction X . The first and second power supply bridge lines PL1c and PL2c may be disposed on the opposite side of the second pad portion DP along the second direction Y orthogonal to the first direction X. [ For example, the first and second power supply bridge lines PL1c and PL2c may be disposed below the plurality of subpixels SP. The first power supply line PL1c connects the first power supply line PL1a and each of the plurality of sub pixels SP and the second power supply line PL2c connects the second power supply line PL2a and a plurality of (SP) of each sub-pixel.

The second pad unit DP may be provided in a part of the third unit pixel UP3 and may apply a signal to each of the plurality of sub-pixels SP. According to an example, when the second pad portion DP is implemented as a data pad portion DP, the second pad portion DP is provided in the upper region of the third unit pixel UP3, Lt; RTI ID = 0.0 > SP. ≪ / RTI > In addition, the third unit pixel UP3 may further include an electrostatic discharge protection circuit (ESD) connected to one side of the second pad portion DP. The second pad portion DP may be connected to the data line DL through a link. That is, the second pad unit DP may provide a data signal to the plurality of sub-pixels SP through the data line DL.

According to one example, the third unit pixel UP3 may include third and fourth free spaces provided on both sides of the plurality of sub-pixels SP along the second direction Y. [ For example, the third spare area corresponds to the upper area of the plurality of subpixels SP, and the fourth spare area corresponds to the lower area of the plurality of subpixels SP. The third clearance space can accommodate the second pad portion DP and the electrostatic discharge protection circuit (ESD), and the fourth clearance space can accommodate the first and second power supply bridge lines PL1c and PL2c . Therefore, the third unit pixel UP3 includes the second pad portion DP arranged in the third free space and the first and second power supply bridge lines PL1c and PL2c arranged in the fourth free space, The light emitting diode display 10 can reduce the size of the unit pixels and does not require a separate space for concealing the second pad portion DP, thereby minimizing the bezel area. In addition, the multi-screen display device including the plurality of light emitting diode display devices 10 can minimize a boundary between the LED display devices 10 connected to each other, thereby displaying a single image with a minimum disconnection on the entire screen .

According to an example, the third unit pixel UP3 may have a smaller size than the first unit pixel UP1. Specifically, the third unit pixel UP3 may be formed by cutting one side of a unit pixel having the same size as the first unit pixel UP1 along a cutting line CPS Line. That is, the third unit pixel UP3 may be formed by cutting (or cutting) the upper side of the unit pixel having the same size as the first unit pixel UP1 by the second width W2. Therefore, the LED display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100 with the same size as the reference pixel pitch, By reducing the size of the third unit pixels UP3 provided at the two edges, it is possible to have a bezel width suitable for minimizing the boundary between the LED display devices 10 connected to each other in the multi-screen device. As a result, the multi-screen display device according to the present example has a plurality of light emitting diode display devices (or a plurality of screen modules) It is possible to minimize the dark region generated by the boundary portion provided between the diode display devices 10 and to provide an image in which the sense of disconnection disappears in the entire screen.

5 is a view for explaining the fourth unit pixel shown in FIG.

5, the fourth unit pixel UP4 includes a plurality of subpixels SP, first and second mesh power supply lines PL1 and PL2, a gate line GL, a data line DL, An electrostatic discharge (ESD) protection circuit, a first pad portion GP, and a second pad portion DP. Here, a redundant description of the plurality of sub-pixels SP, the gate line GL, the data line DL, and the first and second mesh power supply lines PL1 and PL2 will be omitted.

The fourth unit pixel UP4 may include a second power supply line PL2a, first and second power supply lines PL1c and PL2c. According to an example, the second power supply line PL2a may be disposed on one side of the plurality of sub-pixels SP along the first direction X. [ The second power supply line PL2a may be disposed on the opposite side of the first pad portion GP along the first direction X. [ For example, the second power supply line PL2a may be disposed on the right side of the plurality of subpixels SP.

According to one example, the first and second power supply bridge lines PL1c and PL2c are disposed on one side of the plurality of subpixels SP along a second direction Y orthogonal to the first direction X . The first and second power supply bridge lines PL1c and PL2c may be disposed on the opposite side of the second pad portion DP along the second direction Y orthogonal to the first direction X. [ For example, the first and second power supply bridge lines PL1c and PL2c may be disposed below the plurality of subpixels SP. The second power supply line PL2c may couple each of the plurality of subpixels SP with the second power supply line PL2a.

The first pad unit GP may be provided in a part of the fourth unit pixel UP4 and may apply a signal to each of the plurality of sub-pixels SP. According to an example, when the first pad unit GP is implemented as the gate pad unit GP, the first pad unit GP is provided in the left region of the fourth unit pixel UP4, 0.0 > SP, < / RTI > In addition, the fourth unit pixel UP4 may further include an electrostatic discharge protection circuit (ESD) connected to one side of the first pad portion GP. The first pad unit GP may be connected to the gate line GL through a link. That is, the first pad unit GP may provide a gate signal to the plurality of sub-pixels SP through the gate line GL.

The second pad unit DP may be provided in a part of the fourth unit pixel UP4 and may apply a signal to each of the plurality of sub-pixels SP. According to an example, when the second pad portion DP is implemented as a data pad portion DP, the second pad portion DP is provided in an upper region of the fourth unit pixel UP4, Lt; RTI ID = 0.0 > SP. ≪ / RTI > In addition, the fourth unit pixel UP4 may further include an electrostatic discharge protection circuit (ESD) connected to one side of the second pad portion DP. The second pad portion DP may be connected to the data line DL through a link. That is, the second pad unit DP may provide a data signal to the plurality of sub-pixels SP through the data line DL.

According to an example, the fourth unit pixel UP4 may include first and second free spaces provided on both sides of the plurality of sub-pixels SP along the first direction X. [ For example, the first free space corresponds to the left region of the plurality of sub-pixels SP, and the second free space corresponds to the right region of the plurality of sub-pixels SP. The first clearance space can accommodate the first pad portion GP and the electrostatic discharge protection circuit (ESD), and the second clearance space can accommodate the second power supply line PL2a. Accordingly, the fourth unit pixel UP4 includes the first pad portion GP disposed in the first clearance space and the second power supply line PL2a disposed in the second clearance space, so that the light emitting diode display device 10 Can reduce the size of the unit pixels and does not require a separate space for concealing the first pad portion GP, thereby minimizing the bezel area. In addition, the multi-screen display device including the plurality of light emitting diode display devices 10 can minimize a boundary between the LED display devices 10 connected to each other, thereby displaying a single image with a minimum disconnection on the entire screen .

According to one example, the fourth unit pixel UP4 may include third and fourth free spaces provided on both sides of the plurality of sub-pixels SP along the second direction Y. [ For example, the third spare area corresponds to the upper area of the plurality of subpixels SP, and the fourth spare area corresponds to the lower area of the plurality of subpixels SP. The third clearance space can accommodate the second pad portion DP and the electrostatic discharge protection circuit (ESD), and the fourth clearance space can accommodate the first and second power supply bridge lines PL1c and PL2c . Accordingly, the fourth unit pixel UP4 includes the second pad portion DP disposed in the third clearance space and the first and second power supply bridge lines PL1c and PL2c disposed in the fourth clearance space, The light emitting diode display 10 can reduce the size of the unit pixels and does not require a separate space for concealing the second pad portion DP, thereby minimizing the bezel area. In addition, the multi-screen display device including the plurality of light emitting diode display devices 10 can minimize a boundary between the LED display devices 10 connected to each other, thereby displaying a single image with a minimum disconnection on the entire screen .

According to one example, the fourth unit pixel UP4 may have a smaller size than the first, second, and third unit pixels UP1, UP2, and UP3. Specifically, the fourth unit pixel UP4 may be formed by cutting one side and the other side of the unit pixel having the same size as the first unit pixel UP1 along each of the cutting lines (CPS Line). That is, the fourth unit pixel UP4 is formed such that the left side of the unit pixel having the same size as the first unit pixel UP1 is cut (or cut) by the first width W1, and the upper side of the unit pixel is the second width W2) by cutting (or cutting). Therefore, the LED display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100 with the same size as the reference pixel pitch, By reducing the size of the second unit pixels UP2 provided at the first edge of the first unit pixel UP2, it is possible to have a bezel width suitable for minimizing the boundary between the LED display devices 10 connected to each other in the multi-screen device. In addition, the light emitting diode display 10 according to the present embodiment includes the plurality of first unit pixels UP1 provided on the substrate 100, each of the first unit pixels UP1 having the same reference pixel pitch, The size of the second unit pixels UP2 provided at the first edge of the substrate 100 is reduced and the size of the third unit pixels UP3 provided at the second edge of the substrate 100 is reduced, It is possible to reduce the size of the fourth unit pixel UP4 provided in the multi-screen device to have a bezel width suitable for minimizing the boundary between the LED display devices 10 connected to each other in the multi-screen device.

FIG. 6 is a view for explaining one subpixel shown in FIG. 1. FIG.

Referring to FIG. 6, each of a plurality of subpixels SP is provided in a subpixel region defined by the intersection of gate lines GL and data lines DL. Here, each of the plurality of sub-pixels SP may be defined as a minimum unit area for emitting light.

Each of the plurality of subpixels SP may include a first subpixel SPa and a second subpixel SPb. Here, if any one of the first sub-pixel SPa and the second sub-pixel SPb is defective due to misalignment or electric shock generated in the process of mounting the light-emitting device ED on the substrate 100 Pixel can be used as a redundancy subpixel prepared in advance.

Each of the first sub-pixel SPa and the second sub-pixel SPb may include a light-emitting circuit PC and a light-emitting element ED. The pixel circuit PC is provided in a circuit region defined in each subpixel SP and connected to the adjacent gate line GL and the data line DL and the first mesh power supply line PL1. The pixel circuit PC is driven based on the first driving power source supplied from the first mesh power line PL1 in response to the data signal from the data line DL in response to the scan pulse from the gate line GL The light emission of the element EP can be controlled. According to one example, the pixel circuit PC may include a switching thin film transistor T1, a driving thin film transistor T2, and a capacitor Cst.

The switching thin film transistor T1 includes a gate electrode connected to the adjacent gate line GL, a first source / drain electrode connected to the data line DL, and a first node N1 connected to the gate electrode of the driving TFT T2. And a second source / drain electrode connected to the second source / drain electrode. Here, the first and second source / drain electrodes of the switching thin film transistor T1 may be a source electrode or a drain electrode depending on the direction of current. The switching thin film transistor T1 is switched according to a scan pulse supplied to the gate line GL to supply a data signal supplied to the data line DL to the gate electrode of the driving thin film transistor T2.

The driving thin film transistor T2 is turned on by the voltage supplied from the switching thin film transistor T1 and / or the voltage of the capacitor Cst to thereby reduce the amount of current flowing from the first mesh power supply line PL1 to the light emitting element ED . To this end, the driving thin film transistor T2 includes a gate electrode connected to the second source / drain electrode (or the first node N1) of the switching thin film transistor T1, a drain electrode connected to the first mesh power line PL1, And a source electrode connected to the light emitting device ED. The driving thin film transistor T2 controls the data current flowing from the first mesh power supply line PL1 to the light emitting element ED based on the data signal supplied from the switching thin film transistor T1, Can be controlled to the luminance corresponding to the data signal.

The capacitor Cst is provided in an overlapping region between the gate electrode and the source electrode of the driving thin film transistor T2 and stores a voltage corresponding to a data signal supplied to the gate electrode of the driving thin film transistor T2, The transistor T2 can be turned on.

Alternatively, the pixel circuit PC may further include at least one compensating thin film transistor for compensating for a change in threshold voltage of the driving thin film transistor T2, and further may include at least one auxiliary capacitor. The pixel circuit PC may be further supplied with a compensating power such as an initializing voltage depending on the number of the thin film transistors and the auxiliary capacitors. Therefore, since the pixel circuit PC according to the example of the present application drives the light emitting device ED through the current driving method in the same manner as each sub pixel of the organic light emitting display device, it changes to the pixel circuit of the known organic light emitting display device. It is possible.

The light emitting device ED is electrically connected between the pixel circuit PC and the second mesh power supply line PL2 and is connected to the second mesh power supply line PL2 from the pixel circuit PC, And emits light by a flowing current. According to an example, the light emitting device ED may be a micro light emitting device or a micro light emitting diode chip that emits one of red light, green light, blue light, and white light. Here, the micro-light-emitting diode chip may have a scale of 1 to 100 micrometers, but the present invention is not limited thereto. The micro-light-emitting diode chip may have a size smaller than the size of the light-emitting area excluding the circuit area occupied by the pixel circuit (PC) .

Alternatively, the pixel circuit PC of the second sub-pixel SPb may be omitted. In this case, the light-emitting element ED of the second sub-pixel SPb is connected to the pixel circuit of the first sub- The driving current flows from the driving thin film transistor T2 constituted in the first mesh power supply line PL2 to the second mesh power supply line PL2. The switching thin film transistor T1 formed in the pixel circuit PC of the second subpixel SPb may be omitted and the driving thin film transistor T1 formed in the pixel circuit PC of the second subpixel SPb may be omitted. The second transistor T2 may be turned on by the voltage supplied from the switching thin film transistor T1 configured in the pixel circuit PC of the first subpixel SPa and / or the voltage of the capacitor Cst.

Each of the plurality of unit pixels UP may include at least three sub-pixels SP adjacent in the first direction X of the substrate 100. Here, one unit pixel UP may be defined as a minimum unit for displaying a color image. For example, one unit pixel UP may comprise a red subpixel, a green subpixel, and a blue subpixel.

At least three sub-pixels SP constituting one unit pixel UP are arranged in the unit pixel region according to the size set according to the resolution of the LED display device, and they are concentratedly arranged at the central portion of the unit pixel region . Accordingly, the unit pixel region may have remaining free space excluding the sub pixel allocation region.

The first mesh power line PL1 may be formed in a mesh shape on the substrate 100 to supply first driving power to each of the plurality of subpixels SP. According to an example, the first mesh power line PL1 includes a first power supply line PL1a, a plurality of first pixel power lines PL1b, and a first power supply line PL1c.

The first power supply line PL1a may be disposed on one side of the plurality of unit pixels UP along the first direction X. [ The first power supply line PL1a may be disposed in parallel with the data line DL and adjacent to the first subpixel SP or the last subpixel SP of each of the plurality of unit pixels UP. The first power supply line PL1a is connected to the first main power supply line PL1b for supplying the first driving power directly supplied from the outside to each of the plurality of first pixel power lines PL1b provided in the unit pixel UP It can have a relatively thick line width. That is, the first power supply line PL1a may have a relatively larger line width than the first pixel power line PL1b.

Each of the plurality of first pixel power supply lines PL1b may be disposed in each of the plurality of sub-pixels SP. Each of the plurality of first pixel power supply lines PL1b is disposed in parallel with the data line DL and disposed adjacent to each of the plurality of subpixels SP. At this time, each of the plurality of first pixel power supply lines PL1b is individually connected to a pixel circuit PC of each of a plurality of sub-pixels SP arranged along a first direction X, And the pixel circuits PC of the plurality of sub-pixels SP arranged along the Y direction. Each of the plurality of first pixel power supply lines PL1b supplies the first driving power supplied from the first power supply line PL1a to the pixel circuits PC of the corresponding subpixel SP And may have a line width that is relatively thinner than the first power supply line PL1a.

The first power supply bridge line PL1c may connect the first power supply line PL1a and the plurality of first pixel power supply lines PL1b to each other so that the first mesh power supply line PL1 has a mesh shape . The first power supply bridge line PL1c may be disposed in parallel with the first direction X and may intersect each of the first power supply line PL1a and each of the plurality of first pixel power lines PL1b. The first power supply bridge line PL1c is formed on a different layer from the first power supply line PL1a and the plurality of first pixel power lines PL1b and is connected to the first power supply line PL1b crossing the first bridge contact hole, And may be electrically connected to the line PL1a and the plurality of first pixel power lines PL1b, respectively. The first power supply bridge line PL1c may be disposed on at least one of the upper side and the lower side of each of the plurality of unit pixels UP on the basis of the second direction Y. [

The second mesh power line PL2 may be formed in a mesh shape on the substrate 100 to supply a second driving power to each of the plurality of sub pixels SP. According to an example, the second mesh power supply line PL2 includes a second power supply line PL2a, a plurality of second pixel power supply lines PL2b, and a second power supply line PL2c.

The second power supply line PL2a may be disposed on the other side of the plurality of unit pixels UP along the first direction X. [ The second power supply line PL2a is disposed in parallel with the first power supply line PL1a with one unit pixel UP therebetween and is connected to the first subpixel SP of each of the plurality of unit pixels UP, Or adjacent to the last sub-pixel SP. The second power supply line PL2a includes a second main power supply line for supplying a second driving power supplied directly from the outside to each of the plurality of second pixel power lines PL2b provided in the unit pixel UP It can have a relatively thick line width. That is, the second power supply line PL2a may have a relatively larger line width than the second pixel power line PL2b.

Each of the plurality of second pixel power supply lines PL2b may be disposed in each of the plurality of subpixels SP. Each of the plurality of second pixel power supply lines PL2b may be disposed adjacent to each of the plurality of subpixels SP so as to be parallel to the first pixel power supply line PL2b with the corresponding subpixel SP therebetween have. At this time, each of the plurality of second pixel power supply lines PL2b is individually connected to the light emitting device ED of each of the plurality of sub-pixels SP arranged along the first direction X, Y) of the plurality of subpixels (SP) disposed along the common electrode (Y). Each of the plurality of second pixel power supply lines PL2b supplies the second driving power supplied from the second power supply line PL2a to the light emitting element ED of the corresponding subpixel SP And can have a line width that is relatively thinner than the second power supply line PL2a.

Each of the plurality of second power supply bridge lines PL2c connects the second power supply line PL2a and the plurality of second pixel power supply lines PL2b to each other so that the second mesh power supply line PL2 forms a mesh Respectively. The second power source bridge line PL2c may be disposed in parallel with the first direction X and may intersect each of the second power source line PL2a and each of the plurality of second pixel power source lines PL2b. The second power source bridge line PL2c is formed in a different layer from the second power source line PL2a and the plurality of second pixel power source lines PL2b, And may be electrically connected to each of the supply line PL2a and each of the plurality of second pixel power supply lines PL2b. The second power supply bridge line PL2c may be disposed on at least one of the upper side and the lower side of each of the plurality of unit pixels UP with reference to the second direction Y. [

FIG. 7 is a view for explaining a cross-sectional structure of the subpixel shown in FIG. 6, and FIG. 8 is a cross-sectional view for explaining the structure of the light emitting device shown in FIG.

7 and 8, the subpixel SP includes a pixel circuit PC, a first planarization layer 110, a recess 120, a reflection pattern 130, a light emitting device ED, a planarization layer 150, a first electrode connection pattern ECP1, a second electrode connection pattern ECP2, and a pixel isolation layer 160.

The pixel circuit PC includes a switching thin film transistor T1, a driving thin film transistor T2, and a capacitor C. Since the pixel circuit PC is the same as that described above, a detailed description thereof will be omitted. Hereinafter, the structure of the driving thin film transistor T2 will be described by way of example.

The driving thin film transistor T2 includes a gate electrode GE, a semiconductor layer SCL, an ohmic contact layer OCL, a source electrode SE, and a drain electrode DE.

The gate electrode GE is formed on the substrate 100 together with the gate line GL. This gate electrode GE may be covered by the gate insulating layer 101. [ The gate insulating layer 101 may be composed of a single layer or a plurality of layers made of an inorganic material, and may be made of silicon oxide (SiOx), silicon nitride (SiNx), or the like.

The semiconductor layer SCL may be provided in a pattern (or island) pattern previously formed on the gate insulating layer 101 so as to overlap with the gate electrode GE. The semiconductor layer SCL may be formed of a semiconductor material composed of any one of amorphous silicon, polycrystalline silicon, oxide, and organic material, but is not limited thereto.

The ohmic contact layer OCL may be provided on the semiconductor layer SCL in a predetermined pattern or island shape. Here, the ohmic contact layer PCL is for ohmic contact between the semiconductor layer SCL and the source / drain electrodes SE, DE and can be omitted.

The source electrode SE may be formed on one side of the ohmic contact layer OCL so as to overlap with one side of the semiconductor layer SCL.

The drain electrode DE may be formed on the other side of the ohmic contact layer OCL so as to be spaced apart from the source electrode SE while overlapping with the other side of the semiconductor layer SCL. The drain electrode DE is formed together with the source electrode SE and can be branched or protruded from the adjacent first pixel power line PL1b.

The data line DL and the first power supply line PL1a of the first mesh power supply line PL1 and the first pixel power supply line PL1a of the first mesh power supply line PL1, together with the source electrode SE and the drain electrodes DE, The second power supply line PL2a and the second pixel power line PL2b of the second mesh power line PL2 may be formed.

In addition, the switching thin film transistor T1 constituting the pixel circuit PC may be formed in the same structure as the driving thin film transistor T2. At this time, in the switching thin film transistor T1, the gate electrode branches or protrudes from the gate line GL, the first source / drain electrode branches or protrudes from the data line DL, and the second source / And may be connected to the gate electrode GE of the driving thin film transistor T2 through a via hole provided in the insulating layer 101. [

The pixel circuit PC may be covered with the interlayer insulating layer 103. [ The interlayer insulating layer 103 may be provided on the entire front surface of the substrate 100 so as to cover the pixel circuit PC including the driving TFT T2. According to one example, the interlayer insulating layer 103 may be made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), or may be made of an organic material such as benzocyclobutene or photo acryl have. The interlayer insulating layer 103 may be omitted.

The first planarization layer 110 may be formed on the entire front surface of the substrate 100 to cover the pixel circuits PC or on the entire surface of the substrate 100 so as to cover the interlayer insulating layer 103. [ . The first planarization layer 110 can provide a flat surface on the interlayer insulating layer 103 while protecting the pixel circuit PC. According to one example, the first planarization layer 110 may be made of an organic material such as benzocyclobutene or photo acryl, but is preferably made of a photo-acrylic material for convenience of processing.

The recess 120 may be provided in the light emitting region of the sub-pixel region defined in the sub-pixel SP to receive the light emitting element ED. According to an example, the recess 120 may be recessed to have a certain depth from the first planarization layer 110. The concave portion 120 may include a storage space recessed from the top surface 110a of the first planarization layer 110 so as to have a depth corresponding to the thickness (or total height) of the light emitting device ED . Here, the bottom surface of the concave portion 120 is a part of the first planarization layer 110, the entire first planarization layer 110, the first planarization layer 110, A part of the entire interlayer insulating layer 103 or the whole of the first planarization layer 110 and the interlayer insulating layer 103 and the gate insulating layer 101 may be removed. For example, the recess 120 may have a depth of 2 to 6 micrometers from the top surface of the first planarization layer 110. The concave portion 120 may have a groove or a cup shape having a larger size than the rear surface (or bottom surface) of the light emitting device ED.

According to an example, the recess 120 may include an inclined surface provided between a bottom surface and an upper surface 110a of the first planarization layer 110, and the inclined surface may concave the light emitted from the light emitting device ED, Toward the front of the unit 120.

The concave portion 120 is recessed in the first planarization layer 110 overlapping the emission region of the sub pixel region defined in the subpixel SP to serve as an alignment mark, It is possible to minimize the misalignment between the substrate 100 and the light emitting device ED during the transfer process of mounting the light emitting device on the substrate 100. The concave portion 120 may include an inclined surface that reflects light incident from the light emitting device ED, thereby increasing the efficiency of extracting light emitted from the light emitting device ED.

The reflection pattern 130 may be formed on the concave portion 120 to support the light emitting device ED. The reflective pattern 130 is formed to have a predetermined thickness on the inclined surface and the bottom surface of the concave portion 120 and is further provided on the upper surface 110a of the first planarization layer 110 surrounding the concave portion 120 . The reflective pattern 130 may include a metal material having a high reflectivity. For example, the reflection pattern 130 may include a laminated structure of aluminum (Al) and titanium (Ti), a laminated structure of aluminum (Al) and ITO (ITO / Al / ITO) (Pd / Cu) alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO), or may be formed of a metal such as copper, silver, aluminum, molybdenum, Layer structure composed of any one material selected from gold (Au), magnesium (Mg), calcium (Ca), barium (Ba), or two or more alloy materials. In some cases, the reflection pattern 130 may be formed of a transparent electrode material such as ITO. The reflective pattern 130 is formed to surround the rear surface and side surfaces of the light emitting device ED disposed in the concave portion 120 to further increase the efficiency of extracting light emitted from the light emitting device ED.

The light emitting device ED is mounted on the concave portion 120 and electrically connected to the pixel circuit PC and the second pixel power supply line PL2b so that the pixel circuit PC, And can emit light by the current flowing to the power supply line PL2b. According to one example, the light emitting device ED may include a light emitting layer EL, a first electrode (or an anode terminal) E1, and a second electrode (or a cathode terminal) E2.

The light emitting layer EL can emit light according to the recombination of electrons and holes according to the current flowing between the first electrode E1 and the second electrode E2. According to one example, the light emitting layer EL may include a first semiconductor layer SL1, an active layer ACL, and a second semiconductor layer SL2.

The first semiconductor layer SL1 may provide electrons to the active layer ACL. According to an example, the first semiconductor layer SL1 may be made of an n-GaN-based semiconductor material, and the n-GaN-based semiconductor material may be GaN, AlGaN, InGaN, or AlInGaN. Here, Si, Ge, Se, Te, C, or the like may be used as an impurity used for doping the first semiconductor layer SL1.

The active layer ACL may be provided on one side of the first semiconductor layer SL1. The active layer (ACL) has a multi quantum well (MQW) structure having a barrier layer having a higher bandgap than that of the well layer and the well layer. The active layer (ACL) according to an example may have a multiple quantum well structure such as InGaN / GaN.

The second semiconductor layer SL2 may be provided on the active layer ACL to provide holes in the active layer ACL. According to an example, the second semiconductor layer SL2 may be made of a p-GaN semiconductor material, and the p-GaN semiconductor material may be GaN, AlGaN, InGaN, or AlInGaN. As the impurity used for doping the second semiconductor layer SL2, Mg, Zn, Be, or the like may be used.

The first electrode E1 may be provided on the second semiconductor layer SL2. The first electrode E1 may be connected to the source electrode SE of the driving TFT T2.

The second electrode E2 may be provided on the other side of the first semiconductor layer SL1 so as to be electrically separated from the active layer ACL and the second semiconductor layer SL2. And the second electrode E2 may be connected to the second pixel power line PL2b.

Each of the first and second electrodes E1 and E2 may include at least one of a metal material such as Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, And the like. According to another example, each of the first and second electrodes E1 and E2 may be made of a transparent conductive material, and the transparent conductive material may be indium tin oxide (ITO) or indium zinc oxide (IZO) But is not limited thereto.

In addition, the first semiconductor layer SL1, the active layer ACL, and the second semiconductor layer SL2 may be sequentially stacked on the semiconductor substrate. Here, the semiconductor substrate may include a semiconductor material such as a sapphire substrate or a silicon substrate. This semiconductor substrate is used as a growth substrate for growing each of the first semiconductor layer SL1, the active layer ACL and the second semiconductor layer SL2, and thereafter, is removed from the first semiconductor layer SL1 Can be separated. Here, the substrate separation process may be a laser lift off, a chemical lift off, or the like. Accordingly, as the semiconductor substrate for growth is removed from the light emitting device ED, the light emitting device ED can have a relatively thin thickness, and thus the light emitting device ED can be housed in the recess 120 provided in each sub- .

The light emitting device ED can emit light according to the recombination of electrons and holes according to the current flowing between the first electrode E1 and the second electrode E2. Light emitted from the light emitting device ED may be transmitted through the first and second electrodes E1 and E2 and may be emitted to the outside. In other words, the light emitted from the light emitting device ED passes through each of the first and second electrodes E1 and E2 and is emitted in a second direction opposite to the first direction toward the bottom surface of the recess 120 And displays the image.

The light emitting device ED includes a first portion FP or a front portion FP having first and second electrodes E1 and E2 connected to the pixel circuit PC, And two portions (or rear portions) RP. At this time, the first portion FP may be spaced relatively far from the bottom surface of the concave portion 120 than the second portion RP. Here, the first part FP may have a smaller size than the second part RP. In this case, the light emitting device ED has the upper part and the second part RP corresponding to the first part FP, And a trapezoidal cross-section having a base line corresponding to the base. The light emitting device ED may be adhered to the bottom surface of the concave portion 120 through the adhesive member 140.

The adhesive member 140 is interposed between the concave portion 120 and the light emitting device ED to adhere the light emitting device ED to the bottom surface of the concave portion 120 so that the light emitting device ED can be primarily fixed have. The adhesive member 140 is attached (or coated) to the second portion RP of the light emitting device ED, that is, the back surface of the first semiconductor layer SL1, so that the concave portion 120).

The second planarization layer 150 may be provided on the first planarization layer 110 to cover the light emitting device ED. That is, the second planarization layer 150 has a thickness enough to cover the upper surface of the first planarization layer 110, the front surface of the remaining storage space of the concave portion 120 in which the light emitting device ED is housed, May be provided on the first planarization layer 110 so as to have a predetermined thickness.

The second planarization layer 150 may provide a planar surface on the first planarization layer 110. The second planarization layer 150 is buried in the remaining accommodating space of the recess 120 in which the light emitting device ED is housed to fix the position of the light emitting device ED.

The first electrode connection pattern ECP1 connects the first electrode E1 of the light emitting element ED to the source electrode SE of the driving thin film transistor T2 and can be defined as an anode electrode. The first electrode connection pattern ECP1 may be formed on the upper surface 150a of the second planarization layer 150 overlapping the first electrode E1 of the light emitting device ED and the driving TFT T2 .

One side of the first electrode connection pattern ECP1 may include a first circuit contact hole CCH1 provided through the interlayer insulating layer 103 and the first planarization layer 110 and the second planarization layer 150, And is electrically connected to the source electrode SE of the driving thin film transistor T2. The other side of the second planarization layer 150 is connected to the first electrode E1 of the light emitting device ED through a first electrode contact hole ECH1 provided in the second planarization layer 150, And may be electrically connected to the first electrode E1 of the scan electrode ED. The first electrode E1 of the light emitting element ED may be electrically connected to the source electrode SE of the driving thin film transistor T2 through the first electrode connection pattern ECP1. The first electrode connection pattern ECP1 may be formed of a transparent conductive material when the LED display device is a top emission type and may be a bottom emission type when the LED display device is a bottom emission type. ≪ / RTI > Here, the transparent conductive material may be indium tin oxide (ITO), indium zinc oxide (IZO), or the like, but is not limited thereto. The light reflection conductive material may be made of the same material as the reflection pattern 130.

In addition, one side of the first electrode connection pattern ECP1 is electrically connected to the source electrode SE of the driving thin film transistor T2 through the first metal pattern 121. The first metal pattern 121 is formed together with the reflective pattern 120 so as to be electrically connected to the source electrode SE of the driving thin film transistor T2 through the first circuit contact hole CCH1. ). The first metal pattern 121 serves as an intermediate connection layer between one side of the first electrode connection pattern ECP1 and the source electrode SE of the driving thin film transistor T2, The first electrode connection pattern ECP1 prevents a contact failure which is not electrically connected to the source electrode SE of the driving TFT T2.

The second electrode connection pattern ECP2 electrically connects the second electrode E2 of the light emitting device ED and the second pixel power line PL2b and may be defined as a cathode electrode. The second electrode connection pattern ECP2 is provided on the upper surface 150a of the second planarization layer 150 overlapping with the second pixel power line PL2b while overlapping the second electrode E2 of the light emitting element ED . Here, the second electrode connection pattern ECP2 may be formed of the same material as the first electrode connection pattern ECP1.

One side of the second electrode connection pattern ECP2 may include a gate insulating layer 101 overlapping the second pixel power line PL2b, an interlayer insulating layer 103, a first planarization layer 110, 2 planarization layer 150 through the second circuit contact hole CCH2 provided through the second circuit contact hole CCH2. The other side of the second electrode connection pattern ECP2 is connected to the second electrode contact hole ECH2 provided in the second planarization layer 150 so as to overlap with the second electrode E2 of the light emitting element ED And is electrically connected to the second electrode E2 of the light emitting element ED. Accordingly, the second electrode E2 of the light emitting device ED is electrically connected to the second pixel power line PL2b through the second electrode connection pattern ECP2.

In addition, one side of the second electrode connection pattern ECP2 may be electrically connected to the second pixel power line PL2b through the second metal pattern 123. [ The second metal pattern 123 is formed together with the reflective pattern 120 so as to be electrically connected to the second pixel power line PL2b through the second circuit contact hole CCH2. ≪ / RTI > The second metal pattern 123 serves as an intermediate connection layer between one side of the second electrode connection pattern ECP2 and the second pixel power line PL2b and the second metal contact hole CCH2 And one side of the second electrode connection pattern (ECP2) serves to prevent a contact failure that is not electrically connected to the second pixel power line (PL2b).

The first electrode connection pattern ECP1 and the second electrode connection pattern ECP2 are electrically connected to the first and second circuit contact holes CCH1 and CCH2 and the first and second electrode contact holes ECH1 and ECH2 The second planarization layer 150 may be formed by a deposition process for depositing an electrode material on the second planarization layer 150 and an electrode patterning process using a photolithography process and an etching process. Accordingly, since the first electrode connection pattern ECP1 and the second electrode connection pattern ECP2 for connecting the light emitting device ED to the pixel circuit PC can be formed at the same time, And the process time for connecting the light emitting device ED and the pixel circuit PC can be greatly shortened, thereby improving the productivity of the LED display device.

The pixel isolation layer 160 defines an opening region corresponding to the light emission of the light emitting device ED. That is, the pixel isolation layer 160 is formed to cover the second planarization layer 150 excluding the opening region of the subpixel SP, the first electrode connection pattern ECP1 and the second electrode connection pattern ECP1 . The pixel isolation layer 160 may include an opening 161 for defining an opening region of the subpixel SP.

The pixel separation layer 160 is essentially blocked by the mixed color between the adjacent sub-pixels SP to reduce the black luminance of the display device so that the display device realizes real black. For this, the pixel separation layer 160 may include a light blocking material or a light absorbing material. For example, the pixel separation layer 160 may be a black matrix.

In addition, when the light emitting device ED is configured to emit white light, the sub-pixel SP may further include a color filter formed in the opening 161 of the pixel separation layer 160. [ The color filter can transmit only light having a wavelength corresponding to the sub-pixel among the white light emitted from the light emitting device ED. For example, the color filter may include a red color filter, a green color filter, or a blue color filter. Additionally, the color filter may comprise a phosphor or a quantum dot particle to increase the color gamut.

In the display device according to the present application, the concave portion 120 formed in the first planarization layer 110 minimizes misalignment generated during the transfer process of the light emitting device ED as described above, It is preferable to be formed so as to provide an effect of improving the external extraction efficiency of light emitted from the light emitting device ED, but the present invention is not limited thereto and may be omitted. The top surface 110a of the first planarization layer 110 may be substantially planar over the entire display area AA of the substrate 100 and the light emitting device ED may be formed in a substantially planar shape, May be attached to the upper surface 110a of the first flat layer 110 overlapping with the emission region of the sub pixel region defined in the subpixel SP via the bonding member 140 described above.

In addition, if the recess 120 is omitted, a reflective pattern 130 in the form of a flat plate may be provided between the light emitting device ED and the first planarization layer 110. In this case, And may be attached to the reflection pattern 130 via the member 140. The reflective pattern 130 acts as an alignment mark (or an alignment pattern) for alignment between the substrate 100 and the light emitting device ED during a transfer process of mounting on the substrate 100, ) Can be minimized during the transfer process. Alternatively, the upper surface of the reflection pattern 130 may reflect light incident from the light emitting device ED toward the first part FP of the light emitting device ED to minimize the external extraction efficiency of the light emitted from the light emitting device ED. Lt; RTI ID = 0.0 > non-planar < / RTI > For example, the non-planar structure may include a concavo-convex pattern or a micro-lens pattern.

FIG. 9 is a cross-sectional view taken along the line I-I 'shown in FIG. 2, and FIG. 10 is a cross-sectional view taken along the line II-II' shown in FIG.

9 and 10, the first mesh power line PL1 includes a first power supply line PL1a, a plurality of first pixel power lines PL1b, and a first power bridge line PL1c do. The first power supply line PL1a may be disposed in the first clearance space SA1 provided at one side of the unit pixel UP so as to be parallel to the second direction Y. [

Each of the plurality of first pixel power supply lines PL1b is disposed on one side of each of the plurality of subpixels SP so as to be parallel with the first power supply line PL1a. At this time, each of the plurality of first pixel power supply lines PL1b may be electrically separated from the first power supply line PL1a.

The first power supply bridge line PL1c is disposed in parallel with the first direction X and may intersect each of the first power supply line PL1a and each of the plurality of first pixel power supply lines PL1b. The first power supply bridge line PL1c may be electrically connected to the first power supply line PL1a and the plurality of first pixel power supply lines PL1b through the plurality of first bridge contact holes BCH1. That is, each of the plurality of first bridge contact holes BCH1 is formed at an intersection of the first power supply line PL1c and the first power supply line PL1a, and the first power supply bridge line PL1c is formed of a plurality of And may be electrically connected to the first power supply line PL1a through each of the first bridge contact holes BCH1. Each of the plurality of first bridge contact holes BCH1 is formed at an intersection of the first power supply bridge line PL1c and the first pixel power line PL1b and the first power bridge line PL1c is formed at a plurality of And may be electrically connected to each of the plurality of first pixel power supply lines PL1b through each of the first bridge contact holes BCH1.

Accordingly, the first mesh power line PL1 is connected to the first power supply line PL1a, the plurality of first pixel power lines PL1b, and the first power supply line PL1c via the plurality of subpixels SP The panel load can be reduced and the voltage drop of the first driving power source can be minimized. At this time, if the first power supply line PL1c is made of a metal material having low resistance such as copper (Cu), silver (Ag), aluminum (Al), or gold (Au) , The voltage drop of the first driving power supply can be further reduced.

The second mesh power line PL2 includes a second power supply line PL2a, a plurality of second pixel power lines PL2b, and a second power supply line PL2c. The second power supply line PL2a may be arranged in the second clearance space SA2 provided on the other side of the unit pixel UP so as to be parallel to the second direction Y. [

Each of the plurality of second pixel power supply lines PL2b is disposed on one side of each of the plurality of subpixels SP so as to be parallel with the second power supply line PL2a. At this time, each of the plurality of second pixel power supply lines PL2b may be electrically separated from the second power supply line PL2a.

The second power supply line PL2c is disposed in parallel with the first direction X and may intersect each of the second power supply line PL2a and each of the plurality of second pixel power supply lines PL2b. The second power supply bridge line PL2c may be electrically connected to the second power supply line PL2a and the plurality of second pixel power supply lines PL2b through the plurality of second bridge contact holes BCH2. That is, each of the plurality of second bridge contact holes BCH2 is formed at the intersection of the second power supply line PL2c and the second power supply line PL2a, and the second power supply line PL2c is formed at the intersection of the plurality And may be electrically connected to the second power supply line PL2a through each of the second bridge contact holes BCH2. Each of the second bridge contact holes BCH2 is formed at the intersection of the second power supply line PL2c and the second pixel power line PL2b and the second power supply line PL2c is formed at the intersection of the plurality And may be electrically connected to each of the plurality of second pixel power supply lines PL2b through each of the second bridge contact holes BCH2.

Accordingly, the second mesh power line PL2 is connected to the second power supply line PL2a, the plurality of second pixel power lines PL2b, and the second power supply line PL2c through the plurality of subpixels SP The panel load can be reduced and the voltage increase of the second driving power source can be minimized. At this time, when the second power supply line PL2c is made of a metal material having low resistance such as copper (Cu), silver (Ag), aluminum (Al), or gold (Au) , The voltage rise of the second driving power supply can be further reduced.

FIG. 11 is a plan view for explaining a recess provided in the unit pixel shown in FIG. 7, and FIG. 12 is a sectional view of III-III 'shown in FIG.

11 and 12, each of the first through third sub-pixels SP1, SP2, and SP3 constituting the first unit pixel UP1 includes a concave portion provided concave from the top surface of the first planarization layer 110, (130).

First, in each first unit pixel UP1, the second subpixel SP2 is provided at the center of the unit pixel region, the first subpixel SP1 is provided at one side of the second subpixel SP2, And the third sub-pixel SP3 may be provided on the other side of the second sub-pixel SP2.

The concave portion 130 provided in the second subpixel SP2 has a rectangular shape in a plan view and the center line CLg2 of the concave portion 130 with respect to the first horizontal axis direction X is parallel to the second subpixel SP2, Is matched with the second center line (CL2) of the second line (SP2). For example, the concave portion 130 of the second subpixel SP2 may be provided at the center of the first unit pixel UP1. The distance L between the central portion (or the central portion) of the concave portion 130 provided in the second sub-pixel SP2 and the outer surface of the substrate 100 is equal to or less than half of the reference pixel pitch P / 2).

The recess 130 provided in the first subpixel SP1 has a rectangular shape in plan view and is provided in the vicinity of the recess 130 provided in the second subpixel SP2. That is, the center line CLg1 of the concave portion 130 provided in the first subpixel SP1 with respect to the first horizontal axis direction X is shifted from the center line CL1 of the first subpixel SP1 May be provided at a position spaced toward the second sub-pixel SP2 by a distance d1.

The recess 130 provided in the third subpixel SP3 may have a rectangular shape in plan view and may be provided in the vicinity of the recess 130 provided in the second subpixel SP2. That is, the center line CLg3 of the concave portion 130 provided in the third subpixel SP3 with respect to the first horizontal axis direction X is shifted from the center line CL3 of the third subpixel SP3 Is provided at a position spaced toward the second sub-pixel SP2 by a distance d2.

Each of the first to third sub pixels SP1, SP2 and SP3 of each first unit pixel UP1 may have the same width Wa on the basis of the first horizontal axis direction X. [

In each first unit pixel UP1, the recess 130 provided in each of the first through third sub-pixels SP1, SP2, and SP3 may be provided so as to be concentrated at the center of the first unit pixel UP1 . Each first unit pixel UP1 has a first width corresponding to a set resolution and a plurality of first unit pixels UP1 has a reference pixel pitch P. Here, the reference pixel pitch P may be defined as a distance between the center portion (or the central portion) of the adjacent two first unit pixels UP1 with reference to the first horizontal axis direction X. [ In other words, the reference pixel pitch P may be defined as a distance between the same sub-pixels provided in two adjacent first unit pixels UP1 with respect to the first horizontal axis direction X. [ That is, the reference pixel pitch P may be defined as a distance between the light emitting elements ED disposed in the second sub-pixel SP2 of each of the two adjacent first unit pixels UP1. For example, the first unit pixel UP1 may be composed of a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. In this case, The distance between the concave portions 130 (or the light emitting devices ED) provided in each of the red subpixels SP1 with respect to one horizontal axis direction X, the distance between the concave portions 130 ), Or the distance between the recesses 130 provided in each of the green subpixels SP2.

In the second unit pixel UP2, the second sub-pixel SP2 is provided in the center of the unit pixel region, the first sub-pixel SP1 is provided at one side of the second sub-pixel SP2, The pixel SP3 may be provided on the other side of the second sub-pixel SP2 and adjacent to the outer side of the substrate 100. [ The outer surface of the substrate 100 may be defined as a sidewall perpendicular to an end of the front surface 100a of the substrate 100 or may be defined as an outermost surface of the substrate 100 exposed to the outside . That is, the side wall of the substrate 100 may be directly exposed to the outside, and may not be directly exposed to the outside because it is concealed by a structure such as a routing line and a protective layer. Accordingly, the outer surface of the substrate 100 may be defined as the outermost surface of the substrate 100 exposed to the outside.

The concave portion 130 provided in each of the first to third sub pixels SP1, SP2 and SP3 in each second unit pixel UP2 is the same as the concave portion of the first unit pixel UP1, A description thereof will be omitted.

In each second unit pixel UP2, each of the first and second subpixels SP1 and SP2 is adjacent to the first unit pixel UP1, and therefore, the widths of the subpixels of the first unit pixel UP1 are the same And may have a width Wa.

On the other hand, the third subpixel SP3 of each second unit pixel UP2 is provided such that the width Wa of the first and second subpixels SP1 and SP2 has a narrow width Wb. Specifically, since the recesses 130 are concentratedly formed in the central portion of the unit pixel in each second unit pixel UP2, a portion of the third subpixel SP3 adjacent to the non-display region of the substrate 100 Even if a part of the area is removed, the image quality of the image displayed on the unit pixel UP2 is not affected. Accordingly, the width Wb of the third sub-pixel SP3 with respect to the first horizontal axis direction X is set so that the light emitting device ED mounted on the third sub-pixel SP3 is the third sub- Pixel SP2 toward the second subpixel SP2 with respect to the center line CL3 of the first subpixel SP2. The maximum distance L between the second unit pixel UP2 and the outer surface of the substrate 100 is a half of the reference pixel pitch P of the plurality of first unit pixels UP1. That is, equal to or less than half of the reference pixel pitch P, for example. Therefore, as the size of the third sub-pixel SP3 of the second unit pixels UP2 adjacent to the bezel region of the substrate 100 is reduced, Lt; RTI ID = 0.0 > bezel < / RTI >

FIG. 13 is a view for explaining a multi-screen display device according to the example of the present application, and FIG. 14 is a cross-sectional view taken along the line IV-IV 'shown in FIG.

13 and 14, the multi-screen display device includes a plurality of screen modules 300-1, 300-2, 300-3, and 300-4, and a housing 400. FIG.

Each of the plurality of screen modules 300-1, 300-2, 300-3 and 300-4 is arranged in the form of N (N is a positive integer of 2 or more) * M (M is a positive integer of 2 or more) An image can be displayed or a single image can be divided and displayed. Here, each of the plurality of screen modules 300-1, 300-2, 300-3, and 300-4 includes a light emitting diode display device according to the present application shown in Figs. 1 to 12, Duplicate description will be omitted.

Each of the plurality of screen modules 300-1, 300-2, 300-3, and 300-4 includes a module connecting member 500 provided on the outer side of the outer side wall of the substrate 100, They can be attached to each other. The module connecting member 500 can implement a multi-screen display device by connecting two adjacent screen modules 300-1, 300-2, 300-3, and 300-4 arranged side by side in a lattice form. For example, the module connecting member 500 may be formed to have a relatively thin thickness in order to minimize the space between the two adjacent screen modules 300-1, 300-2, 300-3, and 300-4. Adhesive tape or double-sided tape.

According to one example, in each of the plurality of screen modules 300-1, 300-2, 300-3, and 300-4, a maximum value between the second unit pixel UP2 and the outer surface of the outer wall of the substrate 100 The distance L may be less than half (P / 2) of the reference pixel pitch P of the plurality of first unit pixels UP1. Accordingly, the maximum distance between the second unit pixels UP2 of the two adjacent screen modules coupled with each other with the module connecting member 500 interposed therebetween may have a reference pixel pitch P or less. In other words, the pixel pitch between the second unit pixels UP2 of each of the two adjacent screen modules may be equal to or smaller than the reference pixel pitch P of the first unit pixel UP1 provided in each of the screen modules. Accordingly, in the multi-screen display device, the dark region generated by the boundary provided between the plurality of screen modules 300-1, 300-2, 300-3, and 300-4 can be minimized or eliminated, It is possible to display an image with a minimum disconnection on the screen.

The housing 400 supports a plurality of screen modules 300-1, 300-2, 300-3, and 300-4 while supporting the rear edges of the plurality of screen modules 300-1, 300-2, 300-3, 300-4 may be covered. According to one example, the housing 400 includes a housing plate 410 covering the rear surface of the plurality of screen modules 300-1, 300-2, 300-3, and 300-4, And a housing side wall 430 supporting the rear edge of each of the plurality of screen modules 300-1, 300-2, 300-3, and 300-4.

According to an example, the housing plate 410 may be formed of a single body covering the entire rear surface of each of the plurality of screen modules 300-1, 300-2, 300-3, and 300-4. According to another example, the housing plate 410 may be formed of a plurality of partition plates so as to overlap the rear surfaces of the plurality of screen modules 300-1, 300-2, 300-3, and 300-4.

The housing side wall 430 is vertically installed from the upper surface of the housing plate 410 which overlaps the rear edge of each of the plurality of screen modules 300-1, 300-2, 300-3, and 300-4, 300-2, 300-3, and 300-4 may be individually supported. At this time, the side walls of the housing can support the rear edge of each of the plurality of screen modules 300-1, 300-2, 300-3, and 300-4 through the module supporting member 450. Here, the module supporting member 450 may be embodied as an elastic member, a foam pad, a double-sided tape, or the like.

Additionally, the housing 400 may include a plurality of module housings including a housing plate 410 and a housing side wall 430. Each of the plurality of module housings individually supports a plurality of screen modules 300-1, 300-2, 300-3, 300-4 while supporting the rear edges of the plurality of screen modules 300-1, 300-2, 300-3, , 300-3, and 300-4. In this case, the housing 400 may include a housing coupling member 600 provided between the plurality of module housings. The housing joining member 600 may be inserted into the gap space between adjacent module housings and secured to the housing plate 410 of each of the adjacent module housings by fastening members such as bolts or screws.

The multi-screen device according to the present exemplary embodiment includes a plurality of screen modules 300-1, 300-2, 300-3, and 300-4 including the light emitting diode display device according to the present application, 1, 300 - 2, 300 - 3, and 300 - 4 is minimized or eliminated, the image with the minimum discontinuity can be displayed on the entire screen.

15A and 15B are views showing images displayed on each of the conventional multi-screen display device and the multi-screen display device according to the present application.

15A, a conventional multi-screen display device displays an image only in a display area AA of each of a plurality of light emitting diode display devices, so that a bezel area corresponding to a front case of each of the plurality of light emitting diode display devices BA, the dark portions are generated at the boundary portion between the display devices connected to each other, and it is seen that the disconnected image is displayed on the entire screen due to the dark portion of the boundary portion.

On the other hand, referring to FIG. 15B, the multi-screen display device according to the present application has a structure in which the pixel pitch between the second unit pixels of each of two adjacent screen modules connected to each other is equal to or smaller than the reference pixel pitch of the first unit pixel It can be seen that an image in which the sense of disconnection is minimized is displayed on the entire screen as the dark area generated by the boundary between the plurality of screen modules is minimized or eliminated.

As a result, in the multi-screen display apparatus according to the present invention, even if the plurality of screen modules are connected to each other so as to have a lattice form, one image can be displayed on the entire screen with minimal discontinuity, It is possible to improve the degree of immersion of the image.

The display device according to the embodiment of the present application can be described as follows.

A light emitting diode display device according to the present application includes a substrate, a first unit pixel provided at a central region of the substrate, and a second unit pixel provided at a first edge of the substrate located at a first side of the central region, And each of the second unit pixels has a plurality of subpixels, and the second unit pixel further includes a first pad unit for applying a signal to the plurality of subpixels.

According to some embodiments of the present application, the second unit pixel may have a smaller size than the first unit pixel.

According to some embodiments of the present application, a first unit pixel includes first and second power supply lines disposed on both sides of a plurality of sub-pixels along a first direction, and a plurality of second power supply lines arranged along a second direction orthogonal to the first direction. The first power supply line connects the first power supply line and each of the plurality of subpixels, and the second power supply line connects the first power supply line and the second power supply line, 2 power supply lines and a plurality of sub-pixels, respectively.

According to some embodiments of the present application, the second unit pixel includes a second power supply line disposed on the opposite side of the first pad portion along the first direction and a second power supply line disposed on both sides of the plurality of subpixels along the second direction orthogonal to the first direction And the second power supply line may connect each of the plurality of subpixels with the second power supply line.

According to some embodiments of the present application, a light emitting diode display is provided at a second edge of a substrate located on a second side different from the first side of the central region, and a plurality of sub-pixels and a plurality of sub- And a third unit pixel having a second pad portion for the second unit pixel.

According to some embodiments of the present application, the third unit pixel may have a smaller size than the first unit pixel.

According to some embodiments of the present application, the third unit pixel includes first and second power supply lines disposed on both sides of the plurality of subpixels along a first direction, and first and second power supply lines disposed on both sides of the plurality of subpixels along a second direction orthogonal to the first direction. The first power supply line connects the first power supply line and each of the plurality of subpixels and the second power supply line connects the second power supply line to the second power supply line, The power supply line and each of the plurality of sub-pixels may be connected.

According to some embodiments of the present application, a light emitting diode display is provided at a first edge located between a first edge and a second edge of a substrate, and is provided with a plurality of sub-pixels and a plurality of sub- And a fourth unit pixel having a first pad portion and a second pad portion.

According to some embodiments of the present application, the fourth unit pixel may have a smaller size than the first, second, and third unit pixels.

According to some embodiments of the present application, the fourth unit pixel includes a second power supply line disposed on the opposite side of the first pad portion along the first direction and a second power supply line disposed on one side of the plurality of subpixels along the second direction orthogonal to the first direction And the second power supply line may connect each of the plurality of subpixels with the second power supply line.

According to some embodiments of the present application, the light emitting diode display further comprises a fifth unit pixel, provided on a third edge of the substrate located on a third side opposite the first side of the central region, and having a plurality of subpixels can do.

According to some embodiments of the present application, the fifth unit pixel may have a size smaller than the first unit pixel.

According to some embodiments of the present application, the fifth unit pixel includes a first power supply line disposed on one side of a plurality of subpixels along a first direction, and a plurality of subpixels along a second direction orthogonal to the first direction, The first power supply line may further include first and second power supply lines disposed on both sides, and the first power supply line may connect each of the plurality of subpixels with the first power supply line.

According to some embodiments of the present application, a light emitting diode display is provided at a second corner located between a second edge and a third edge of the substrate, and includes a plurality of sub-pixels and a plurality of sub- And a sixth unit pixel having two pad portions.

According to some embodiments of the present application, the sixth unit pixel may have a smaller size than the first, second, third, and fifth unit pixels.

According to some embodiments of the present application, the sixth unit pixel includes a first power supply line disposed on one side of the plurality of subpixels along a first direction, and a second power supply line disposed on the opposite side of the second pad unit along a second direction orthogonal to the first direction And the first power supply bridge line may connect each of the plurality of subpixels with the first power supply line.

According to some embodiments of the present application, the light emitting diode display further comprises a seventh unit pixel provided at the fourth edge of the substrate located on the fourth side opposite the second side of the central region and having a plurality of subpixels can do.

According to some embodiments of the present application, the seventh unit pixel may have a size smaller than the first unit pixel.

According to some embodiments of the present application, the seventh unit pixel includes first and second power supply lines disposed on both sides of a plurality of sub-pixels along a first direction, and a plurality of second power supply lines arranged along a second direction orthogonal to the first direction. Wherein the first power supply bridge line connects the first power supply line and each of the plurality of subpixels and the second power supply bridge line connects the first power supply line and the second power supply line, 2 power supply lines and a plurality of sub-pixels, respectively.

According to some embodiments of the present application, a light emitting diode display is provided at a third corner located between a first edge and a fourth edge of the substrate and includes a plurality of sub-pixels and a plurality of sub- And an eighth unit pixel having one pad portion.

According to some embodiments of the present application, the eighth unit pixel may have a size smaller than the first, second, third, fifth, and seventh unit pixels.

According to some embodiments of the present application, the eighth unit pixel includes a second power supply line disposed on the opposite side of the first pad portion along the first direction and a second power supply line disposed on one side of the plurality of subpixels along the second direction orthogonal to the first direction And the second power supply line may connect each of the plurality of subpixels with the second power supply line.

According to some embodiments of the present application, the light emitting diode display may further include a ninth unit pixel provided at a fourth corner located between the third edge and the fourth edge of the substrate, the ninth unit pixel having a plurality of subpixels.

According to some embodiments of the present application, the ninth unit pixel may have a size smaller than the first, second, third, fifth, and seventh unit pixels.

According to some embodiments of the present application, the ninth unit pixel includes a first power supply line disposed on one side of a plurality of subpixels along a first direction and a plurality of subpixels along a second direction orthogonal to the first direction, The first power supply bridge line may connect the first power supply line and each of the plurality of subpixels.

A multi-screen display device according to the present application includes a plurality of screen modules each having a light emitting diode display device and a plurality of module connecting members connecting the plurality of screen modules with each other, the light emitting diode display device including a substrate, And a second unit pixel provided at a first edge of the substrate located on a first side of the central region, wherein each of the first unit pixel and the second unit pixel has a plurality of subpixels, The unit pixel may further include a first pad portion for applying a signal to the plurality of subpixels.

According to some embodiments of the present application, the maximum distance between the unit pixels of each of the two screen modules adjacent to each other with the module connecting member therebetween is less than the reference pixel pitch of the first unit pixel, and the reference pixel pitch is the distance between the adjacent two first unit pixels As shown in FIG.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the scope of the present application is to be defined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present application.

10: Light emitting diode display device 100: substrate
300: Screen module 400: Housing
500: module connecting member 600: housing connecting member

Claims (27)

Board;
A first unit pixel arranged in a central region of the substrate; And
And a second unit pixel provided at a first edge of the substrate, the second unit pixel being located at a first side of the central region,
Wherein each of the first unit pixel and the second unit pixel has a plurality of subpixels,
Wherein the second unit pixel further comprises a first pad portion for applying a signal to the plurality of subpixels. The method according to claim 1,
Wherein the second unit pixel has a smaller size than the first unit pixel. The method according to claim 1,
The first unit pixel includes:
First and second power supply lines disposed on both sides of the plurality of sub-pixels along a first direction; And
Further comprising first and second power supply bridge lines disposed on both sides of the plurality of sub-pixels along a second direction orthogonal to the first direction,
Wherein the first power supply bridge line couples the first power supply line and each of the plurality of subpixels and the second power supply bridge line connects each of the plurality of subpixels with the second power supply line, Light emitting diode display. The method according to claim 1,
Wherein the second unit pixel comprises:
A second power supply line disposed on the opposite side of the first pad portion along the first direction; And
Further comprising first and second power supply bridge lines disposed on both sides of the plurality of sub-pixels along a second direction orthogonal to the first direction,
And the second power supply bridge line connects the second power supply line and each of the plurality of subpixels. The method according to claim 1,
A third unit having a plurality of subpixels and a second pad portion for signal application to the plurality of subpixels, the third unit being provided at a second edge of the substrate located on a second side different from the first side of the central region, And further comprising a pixel. 6. The method of claim 5,
Wherein the third unit pixel has a smaller size than the first unit pixel. 6. The method of claim 5,
Wherein the third unit pixel comprises:
First and second power supply lines disposed on both sides of the plurality of sub-pixels along a first direction; And
Further comprising first and second power supply bridge lines disposed on opposite sides of the second pad portion along a second direction orthogonal to the first direction,
Wherein the first power supply bridge line couples the first power supply line and each of the plurality of subpixels and the second power supply bridge line connects each of the plurality of subpixels with the second power supply line, Light emitting diode display. 6. The method of claim 5,
And a second pad portion provided at a first edge located between the first edge and the second edge of the substrate and having a first pad portion and a second pad portion for signal application to the plurality of sub pixels and the plurality of sub pixels, And further comprising four unit pixels. 9. The method of claim 8,
Wherein the fourth unit pixel has a smaller size than the first unit pixel, the second unit pixel and the third unit pixel. 9. The method of claim 8,
The fourth unit pixel includes:
A second power supply line disposed on the opposite side of the first pad portion along the first direction; And
Further comprising first and second power supply bridge lines disposed on one side of the plurality of sub pixels along a second direction orthogonal to the first direction,
And the second power supply bridge line connects the second power supply line and each of the plurality of subpixels. 6. The method of claim 5,
And a fifth unit pixel provided at a third edge of the substrate located on a third side opposite to the first side of the central region and having the plurality of subpixels. 12. The method of claim 11,
And the fifth unit pixel has a smaller size than the first unit pixel. 12. The method of claim 11,
The fifth unit pixel includes:
A first power supply line disposed on one side of the plurality of sub pixels along a first direction; And
Further comprising first and second power supply bridge lines disposed on both sides of the plurality of sub-pixels along a second direction orthogonal to the first direction,
Wherein the first power supply bridge line connects the first power supply line and each of the plurality of subpixels. 12. The method of claim 11,
And a sixth unit pixel provided at a second corner located between the second edge and the third edge of the substrate and having a second pad portion for signal application to the plurality of subpixels and the plurality of subpixels The light emitting diode display device. 15. The method of claim 14,
Wherein the sixth unit pixel has a smaller size than the first, second, third, and fifth unit pixels. 15. The method of claim 14,
The sixth unit pixel includes:
A first power supply line disposed on one side of the plurality of sub pixels along a first direction; And
Further comprising first and second power supply bridge lines disposed on opposite sides of the second pad portion along a second direction orthogonal to the first direction,
Wherein the first power supply bridge line connects the first power supply line and each of the plurality of subpixels. 12. The method of claim 11,
And a seventh unit pixel provided at a fourth edge of the substrate located on a fourth side opposite to the second side of the central region and having the plurality of subpixels. 18. The method of claim 17,
Wherein the seventh unit pixel has a smaller size than the first unit pixel. 18. The method of claim 17,
The seventh unit pixel includes:
First and second power supply lines disposed on both sides of the plurality of sub-pixels along a first direction; And
Further comprising first and second power supply bridge lines disposed on one side of the plurality of sub pixels along a second direction orthogonal to the first direction,
Wherein the first power supply bridge line couples the first power supply line and each of the plurality of subpixels and the second power supply bridge line connects each of the plurality of subpixels with the second power supply line, Light emitting diode display. 18. The method of claim 17,
And an eighth unit pixel provided at a third corner located between the first edge and the fourth edge of the substrate and having a first pad portion for signal application to the plurality of subpixels and the plurality of subpixels The light emitting diode display device. 21. The method of claim 20,
Wherein the eighth unit pixel has a smaller size than the first, second, third, fifth, and seventh unit pixels. 21. The method of claim 20,
The eighth unit pixel includes:
A second power supply line disposed on the opposite side of the first pad portion along the first direction; And
Further comprising first and second power supply bridge lines disposed on one side of the plurality of sub pixels along a second direction orthogonal to the first direction,
And the second power supply bridge line connects the second power supply line and each of the plurality of subpixels. 18. The method of claim 17,
And a ninth unit pixel provided at a fourth corner located between the third edge and the fourth edge of the substrate, the ninth unit pixel having the plurality of subpixels. 24. The method of claim 23,
Wherein the ninth unit pixel has a smaller size than the first, second, third, fifth, and seventh unit pixels. 24. The method of claim 23,
The ninth unit pixel includes:
A first power supply line disposed on one side of the plurality of sub pixels along a first direction; And
Further comprising first and second power supply bridge lines disposed on one side of the plurality of sub pixels along a second direction orthogonal to the first direction,
Wherein the first power supply bridge line connects the first power supply line and each of the plurality of subpixels. A plurality of screen modules; And
And a plurality of module connecting members for connecting the plurality of screen modules to each other,
Wherein each of the plurality of screen modules has the light emitting diode display device according to any one of claims 1 to 25. 27. The method of claim 26,
The maximum distance between the unit pixels of each of the two screen modules adjacent to each other with the module connecting member therebetween is less than the reference pixel pitch of the first unit pixel,
Wherein the reference pixel pitch is a distance between center portions of two adjacent first unit pixels.

Images