KR20140098406A

KR20140098406A - Liquid crystal display device and driving method thereof

Info

Publication number: KR20140098406A
Application number: KR1020130010984A
Authority: KR
Inventors: 장재혁; 이윤길; 최수진
Original assignee: 엘지디스플레이 주식회사
Priority date: 2013-01-31
Filing date: 2013-01-31
Publication date: 2014-08-08
Also published as: KR102007775B1

Abstract

The present invention relates to a liquid crystal display device, and in particular, to a liquid crystal display device and a method for driving the same, capable of differently setting output periods of three data voltages inputted to a distribution unit which is connected to one output channel of a main driver and three data lines. For this purpose, the liquid crystal display device according to the present invention comprises: a panel in which pixels are formed on intersection regions of gate lines and data lines; a main driver for converting image data to data voltages, dividing one horizontal period into a plurality of sub horizontal periods having different periods, outputting one data voltage with respect to each of the sub horizontal periods through one output channel, and outputting a plurality of selection signals having pulse widths corresponding to the sub horizontal periods; and a distribution unit for switching the data voltages inputted from the one output channel at each of the sub horizontal periods according to the selection signals, and sequentially outputting the inputted data voltages to the different data lines formed on the panel.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display (LCD)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device composed of a panel made of low temperature polysilicon (LTPS) and a driving method thereof.

Flat panel displays (FPDs) are used in various types of electronic products including mobile phones, tablet PCs, and notebook computers. The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), and an organic electroluminescence display (OLED). Recently, an electrophoretic display device EPD: ELECTROPHORETIC DISPLAY) is also widely used.

Among flat panel display devices, liquid crystal display devices are most widely commercialized at present because of advantages of mass production technology, ease of driving means, and realization of high image quality.

FIG. 1 is a waveform diagram showing various waveforms applied to a conventional low-temperature polysilicon (LTPS) type liquid crystal display device, and FIG. 2 is a graph showing the holding time and luminance of data voltages applied to a conventional low- Reduction rate in the case of the present invention.

The liquid crystal display includes a panel and a main driver.

The panel is divided into a display area in which an image is output and a non-display area in which no image is output.

In the liquid crystal display device, the main driver supplies a data voltage to each pixel formed on the panel, drives the liquid crystal of each pixel, and the image is expressed by a change in light transmittance of the liquid crystal.

In the panel, a thin film transistor which is a switching element for driving liquid crystal constituting each pixel is formed. As the thin film transistor, an amorphous thin film transistor using amorphous silicon and a polysilicon thin film transistor using low temperature poly-silicon (LTPS) are used.

Since the polysilicon thin film transistor has higher charge mobility than the amorphous silicon, the polysilicon thin film transistor is suitable for a high-resolution display device requiring a fast response speed.

A data distribution section connected to the main driver is formed in a non-display area of the panel made of the polysilicon thin film transistor using the low temperature polysilicon (LTPS). The data distributor distributes the data voltages supplied from the main driver to one of three data lines through one connection line.

To this end, the data distributor may include three switching transistors connected to the connection line and the data line, and the three switching transistors may be sequentially turned on by three selection signals to supply a data voltage to the corresponding data line do.

That is, each of the three switching transistors sequentially supplies the R, G, and B data voltages to the data lines when the gate is turned on by the selection signal.

Here, since the pulse widths of the three selection signals are constant, the ON time of the switching transistor is set to one timing. That is, since the pulse widths PSWWA of the three selection signals MUX1, MUX2, and MUX3 are the same in FIG. 1, the ON times of the three switching transistors turned on by the three selection signals are one Timing.

On the other hand, in the liquid crystal display device, in order to prevent deterioration of the liquid crystal caused by applying an electric field in one direction to the liquid crystal for a long time, a frame inversion method, a line inversion method, (Column Inversion) or Dot Inversion (Dot Inversion).

Among them, the column inversion method is a method in which the polarity is changed for each column (vertical line), and the polarity of the R, G and B data is inverted in the version in which the column is a version.

In the low temperature polysilicon type liquid crystal display device configured as described above, since R, G, and B pixels are formed in each column, when the column inversion method is applied, data output to the R, G, and B pixels The voltage is reversed.

In this case, the holding timing of the green data voltage is shortened due to the polarity inversion of the R, G, B data voltages.

For example, as shown in FIG. 1, the pulse widths PSWWA of three selection signals MUX1, MUX2, and MUX3 that are sequentially output during one horizontal period are the same, the interval PSWGA between select signals, The holding time GO of the green data voltage output to the data line by the second selection signal MUX2 between the first selection signal MUX1 and the third selection signal MUX3 is the same as the red data voltage Is relatively short in comparison with the holding time (RO) of the blue data voltage and the holding time (BO) of the blue data voltage.

That is, in the low temperature polysilicon type liquid crystal display device driven by the column inversion method, the polarity of the data voltages output to the adjacent red, green, and blue pixels is changed. In this case, the polarities of the red data voltage and the blue data voltage are the same, but the green data voltage has a polarity opposite to that of the red data voltage and the blue data voltage.

Therefore, as shown in FIG. 1, in consideration of the period GR to be changed to the ground and the period P required for polarity conversion, during the period in which the data voltage is actually output while the selection signal is turned on, The period during which the data voltage G is output is relatively short. That is, in the case of the green between the polarities of different polarities, the data holding time of the data voltage for a short time compared to the actual input (Source Holding Time) due to the rising / falling (falling) I have.

Particularly, green has the greatest influence on luminance as shown in Fig. That is, the luminance reduction amount in the case where the holding time of the green data voltage decreases is smaller than the ratio of the luminance reduction due to the reduction of the holding time of the red data voltage and the blue data voltage.

In other words, the green data voltage is not sufficiently charged to the pixels as the holding time of the green data voltage, which has the greatest influence on the luminance, is shortened. As a result, Are falling compared to red and green.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a liquid crystal display device capable of differently setting an output period of three data voltages input to a distributing unit connected to one output channel of a main driver, , A liquid crystal display device and a driving method thereof.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a panel having pixels formed at intersections of gate lines and data lines; And outputs one data voltage for each of the sub horizontal periods through one output channel, and the sub horizontal periods are divided into a plurality of sub horizontal periods having one horizontal period and a plurality of sub horizontal periods having different periods, A main driver for outputting a plurality of selection signals having a pulse width corresponding to each of the plurality of selection signals; And a distributor for switching the data voltages input for each of the sub horizontal periods from the one output channel according to the selection signals and sequentially outputting the data voltages to the different data lines formed on the panel.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, including: converting image data into data voltages, dividing one horizontal period into a plurality of sub-horizontal periods having different periods, Outputting a plurality of selection signals having a pulse width corresponding to each of the sub-horizontal periods, outputting one data voltage for each of the sub-horizontal periods; And switching the data voltages input for each of the sub horizontal periods from the one output channel according to the selection signals and sequentially outputting the data voltages to different data lines formed on the panel.

According to the present invention, in a high-resolution panel driven by a column-version method and an LTPS method, the charging time of the data voltage can be sufficiently secured. That is, since the charging time of the data voltage can be sufficiently secured, it is possible to secure a holding time margin due to the polarity reversal of the data voltage.

In particular, since the holding time margin of the green data voltage having the polarity opposite to the polarity of the red data voltage and the blue data voltage can be secured, the luminance of white is lower than that of the conventional liquid crystal display device 4%.

That is, as the holding time of the data voltage decreases, the holding time of the green data voltage, in which the luminance decreasing rate is the largest, can be prolonged, so that the luminance of the image as a whole can be improved. .

In other words, after indirectly checking the effect of the present invention after eliminating the polarity change of the data driver output and setting the margin of holding time (Holding Time) to the maximum (Max) And an average improvement of about 4%.

1 is a waveform diagram showing various waveforms applied to a conventional low temperature polysilicon (LTPS) type liquid crystal display;
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a low-temperature polysilicon type liquid crystal display device.
3 is a block diagram schematically showing an embodiment of a liquid crystal display device according to the present invention.
4 is a block diagram of a data driver applied to a liquid crystal display device according to an embodiment of the present invention.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device.
6 is a waveform diagram showing various waveforms applied to a liquid crystal display device according to the present invention;

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a schematic view of a liquid crystal display device according to an embodiment of the present invention, FIG. 4 is a diagram illustrating a data driver applied to a liquid crystal display device according to an embodiment of the present invention, And FIG. 6 is a waveform diagram showing various waveforms applied to the liquid crystal display device according to the present invention. Referring to FIG.

2, the liquid crystal display device according to the present invention includes a panel 100 in which pixels are formed at intersecting regions of gate lines GL1 to GLg and data lines DL1 to DLd, And outputs one data voltage for each of the sub-horizontal periods through one output channel 350. The data voltages are divided into a plurality of sub-horizontal periods having one horizontal period (1H) A main driver 500 for outputting a plurality of selection signals MUX1, MUX2 and MUX3 having a pulse width corresponding to each of the sub horizontal periods, And a distributor 600 for switching input data voltages according to the selection signals MUX1, MUX2, and MUX3 and sequentially outputting the data voltages to different data lines formed in the panel 100 .

First, the panel 100 includes a lower substrate and an upper substrate bonded together with a liquid crystal layer (not shown) interposed therebetween.

The lower substrate is formed with a plurality of pixels provided by intersection of d data lines DL1 to DLd and g gate lines GL1 to GLg and sequentially drives the data lines and the gate lines The main driver 500 is mounted.

The pixels are formed in a display area 110 of the panel 100 and the main driver 500 is formed in a non-display area 120 of the panel 100. [

One pixel is referred to as a red subpixel (hereinafter, simply referred to as a 'red pixel'), a green subpixel (hereinafter, simply referred to as a 'green pixel') and a blue subpixel ).

Each of the plurality of pixels is formed between a neighboring gate line and a thin film transistor connected to one adjacent data line, a plurality of pixel electrodes (pixel electrodes) connected to the thin film transistors, and a plurality of pixel electrodes, And a plurality of common electrodes (not shown) supplied with a common voltage.

The semiconductor layer of the thin film transistor applied to the liquid crystal display according to the present invention is formed of polysilicon having a high electron mobility (~ 10 cm 2 / Vsec or more) by low temperature poly-Si (LTPS) do. In the case where the semiconductor layer of the thin film transistor T is primarily formed of amorphous silicon (a-Si), the semiconductor layer of the thin film transistor T is secondarily subjected to a crystallization process using a local laser or heat treatment As shown in FIG.

The present invention can be applied to a panel in which the semiconductor layer of the thin film transistor is formed of amorphous silicon, and particularly to a panel made of low temperature poly-silicon (LTPS).

The liquid crystal is driven according to a difference voltage between a data voltage supplied to the pixel electrode through the thin film transistor and a common voltage supplied to the common electrode, The transmittance is adjusted.

A storage capacitor SC is formed in a region where the pixel electrode and the common electrode overlap. The storage capacitor SC maintains the data voltage charged in the liquid crystal LC for a predetermined period of time.

Next, the main driver 500 receives input image data and timing signals from an external system, rearranges the input image data according to the panel 100, and generates a timing controller A data driver 300 for converting the image data into data voltages and outputting the data voltages, and a gate driver 400 for sequentially outputting a scan signal to the gate line according to a gate control signal generated from the timing controller 400 And a gate driver (200).

The gate driver 200, the data driver 300 and the timing controller 400 constituting the main driver 500 may be constituted by one integrated circuit (IC) as shown in FIG. 3 However, the gate driver 200 or the timing controller 400 may be configured separately from the main driver 200.

For example, the gate driver 200 may be configured independently of the main driver 500. In this case, the main driver 500 may include one or more integrated circuits (IC) . In addition, the gate driver 200 may be a gate-in-panel (GIP) type device formed directly on the panel.

In addition, the timing controller 400 may be connected to the main driver 200 through a flexible substrate (FPC) or the like while the timing controller 400 is mounted on a main board (not shown).

That is, the main driver 500 may further perform the functions of the timing controller 400 and the gate driver 200, centering on the function of the data driver 300 that outputs the data voltage.

Hereinafter, for convenience of explanation, the present invention will be described by way of example in which the main driver 500 includes both the data driver 300, the gate driver 200, and the timing controller 400. [

First, the gate driver 200 of the main driver 500 sequentially applies a gate-on voltage (VDD) to each of the g gate lines (GL1 to GLg) using a gate control signal transmitted from the timing controller 400, And outputs the scan signal.

Here, the gate-on voltage refers to a voltage capable of turning on the switching thin film transistor connected to the gate lines. The voltage capable of turning off the switching thin film transistor is referred to as a gate off signal, and the gate on signal and the gate off signal are generically referred to as a scan signal.

When the thin film transistor is of the N type, the gate on signal is a high level voltage and the gate off signal is a low level voltage. When the thin film transistor is of the P type, the gate on signal is a low level voltage and the gate off signal is a high level voltage.

The timing controller 400 of the main driver 500 generates a gate control signal for controlling the operation timing of the gate driver 200 using the timing signal input from the external system And a data control signal DCS for controlling the operation timing of the data driver 300 and generates image data RGB to be transmitted to the data driver 300. [

To this end, the timing controller 400 includes a receiver for receiving input image data and timing signals from the external system, a control signal generator 420 for generating various control signals, And outputting the control signals and the image data. The data sorting unit may include a data sorting unit for sorting the plurality of image data and outputting the rearranged image data, and an output unit for outputting the control signals and the image data.

That is, the timing controller 400 rearranges the input image data input from the external system according to the structure and characteristics of the panel 100, and outputs the rearranged image data to the data driver 300, Lt; / RTI > Such a function can be executed in the data arrangement section.

The timing controller 400 generates a data control signal DCS for controlling the data driver 300 and a gate control signal for controlling the gate driver 200 using the timing signals transmitted from the external system (GCS), and transmits the control signals to the data driver 300 and the gate driver 200. This function can be executed by the control signal generator 420. [

The data control signals generated by the control signal generator 420 include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE and a polarity control signal POL .

The gate control signals GCS generated by the control signal generator include a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a gate start signal VST, a gate clock GCLK, And the like.

Particularly, the control signal generator 420 generates a polarity control signal POL for causing the two data voltages continuously output from the data driver 300 to have different polarities, and supplies the polarity control signal POL to the data driver 300 ).

Therefore, when there are three data voltages outputted for one horizontal period in one output channel 350 of the data driver 300, if the first data voltage outputted firstly has a positive polarity, The third data voltage having a negative polarity and the third data voltage having a third polarity having a positive polarity. That is, the control signal generator 420 generates a polarity control signal POL for changing the polarity of the data voltages according to a column-by-column version scheme.

In addition, when the data voltages output during one horizontal period are three in one output channel 350 of the data driver 300, the control signal generator 420 generates a control signal having a polarity different from that of the two data voltages And the second sub-horizontal period is longer than the first sub-horizontal period and the third sub-horizontal period in which the two data voltages are output, and outputs the source output enable signal SOE to the data driver (300).

4, the data driver 300 outputs the data voltage in accordance with the source output enable signal SOE, so that the data voltage is output in the form as shown in FIG. 6, The magnitude of the data voltage output from the data driver 300 must be varied. Therefore, the control signal generator corresponds to the first sub-horizontal period corresponding to the pulse width PSWW1 of the first selection signal MUX1 and the pulse width PSWW2 of the second selection signal MUX2 shown in Fig. And a third sub-horizontal period corresponding to the pulse width PSWW3 of the third selection signal MUX3 to the data driver 300 send.

Here, each of the first sub-horizontal period, the second sub-horizontal period, and the third sub-horizontal periods may be equal to or greater than a period corresponding to the corresponding pulse width.

5, since the output periods of the three data voltages output to the three data lines in the distributor 600 are different from each other, The first sub-horizontal period, the second sub-horizontal period, and the third sub-horizontal period for outputting the first sub-horizontal period, the second sub-horizontal period, and the third sub- To this end, the control signal generator 420 may have a different sub-horizontal period so that the data driver 300 may sequentially output different data voltages to the distributor 600 for different periods of time Generates a source output enable signal (SOE), and transmits it to the data driver (300).

As described above, the control signal generator 420 includes a first selection signal MUX1 having a pulse width corresponding to the first sub-horizontal period, a second selection signal MUX2 having a pulse width corresponding to the second sub- A second selection signal MUX2, and a third selection signal MUX3 having a pulse width corresponding to the third sub-horizontal period.

That is, the timing controller 400 generates the source output enable signal SOE having different sub-horizontal periods and the polarity control signal POL for changing the polarity of the data voltage and transmits the signal to the data driver 300 And generates selection signals MUX1, MUX2, and MUX3 having a pulse width corresponding to the sub horizontal periods, and transmits the generated selection signals to the distribution unit 600. FIG.

The data driver 300 of the main driver 500 converts the digital image data transmitted from the timing controller 400 into a data voltage and supplies the data voltage to one horizontal period 1H to which a scan signal is supplied to the gate line. And supplies data voltages of one horizontal line to the data lines.

That is, the data driver 300 converts the image data into the data voltage using the gamma voltages supplied from the gamma voltage generator (not shown), and outputs the data voltage to the data line. The data driver includes a shift register unit 310, a latch unit 320, a digital-analog converter (DAC) 330, and an output buffer 340.

The shift register unit 310 generates a sampling signal using data control signals (SSC, SSP, etc.) received from the timing controller 400.

The latch unit 320 latches the digital image data Data sequentially received from the timing controller 400 and simultaneously outputs the latched digital image data Data to the digital-to-analog converter (DAC) 330 .

The digital-to-analog converter 330 converts the image data transmitted from the latch unit 320 into a positive or negative data voltage and outputs the same. That is, the digital-analog converter 330 converts the image data into a positive or negative data voltage (data signal) using the polarity control signal POL transmitted from the timing controller 400, Lines.

Hereinafter, for convenience of explanation, the first data voltage to the third data voltage are sequentially output during one horizontal period (1H), the first data voltage and the third data voltage have a positive polarity, And the second data voltage has a negative polarity.

Here, the one horizontal period (1H) is a period during which the first data voltage to the third data voltage are outputted. As shown in FIG. 6, the horizontal period (1H) is a period during which the scan signals GLCL (Gate-on voltage) of the high-level voltage (gate-on voltage).

The output buffer 340 outputs the positive or negative data voltage transmitted from the digital-analog converter to the data line DL of the panel according to the source output enable signal SOE transmitted from the timing controller. .

At this time, the output buffer 340 outputs the first data voltage, the second data voltage, and the second data voltage in the first sub-horizontal period, the second sub-horizontal period and the third sub-horizontal period of the source output enable signal SOE. The data voltage, and the third data voltage.

Here, the second sub-horizontal period in which a second data voltage having a polarity different from the polarity of the first data voltage and the third data voltage is output may include a first sub-horizontal period during which the first data voltage is output, And is longer than the third sub-horizontal period in which the data voltage is output.

The output buffer 340 is connected to the distribution unit 600 through one output channel 350. Accordingly, the first data voltage to the third data voltage are sequentially output to the distributor 600 through the output channel 350 during one horizontal period (1H), and the period during which each data voltage is output is , And corresponds to the first sub-horizontal period to the third sub-horizontal period.

That is, the data driver 300 sequentially applies the first to third data voltages during the first horizontal period to the third horizontal period during one horizontal period (1H) as shown in FIG. 6 And the first sub-horizontal period to the third sub-horizontal period correspond to the pulse widths PSWW1 to PSWW3 of the first to third selection signals MUX1 to MUX3, respectively.

Lastly, the distributor 600 includes at least one or more switching devices 610 as shown in FIG. The number of the switching devices 610 constituting the data distributor 400 may be variously set according to the size of the liquid crystal display panel 100 and the number of output channels of the data driver 300.

Each of the switches 610 is connected to three data lines formed in the liquid crystal display panel 100. [ The first data line among the three data lines is connected to the red pixel R as shown in FIG. 5, the second data line is connected to the green pixel G, Is connected to the blue pixel (B).

The above-described configuration assumes that one unit pixel forming the panel 100 is composed of red pixels, green pixels, and blue pixels.

Each of the switches 610 is connected to one output channel 350 formed in the data driver 300 or the main driver 500 as shown in FIG.

Each of the switches 610 includes a first switch TR1 connected to the one output channel 350 and the first data line and turned on according to the first selection signal MUX1 of the selection signals, A second switch TR2 connected to the one output channel 350 and the second data line and turned on according to a second selection signal MUX2 of the selection signals, And a third switch TR3 connected to the third data line and turned on according to the third selection signal MUX3 of the selection signals, Is formed between the first data line connected to the red pixel and the third data line connected to the blue pixel.

Therefore, the first data voltage outputted through the first switch TR1 is a red data voltage, the second data voltage outputted through the second switch TR2 is a green data voltage, And the third data voltage output through the third transistor TR3 is a blue data voltage.

Here, the polarity of the first data voltage output to the first data line through the first switch TR1 and the polarity of the first data voltage output to the third data line MUX3 according to the first selection signal MUX1, The polarity of the third data voltage output to the third data line through the switch TR3 is controlled according to the polarity of the third data voltage, which is output to the second data line through the second switch TR2 according to the second selection signal MUX2. 2 polarity of the data voltage.

The pulse width of the second selection signal MUX2 is formed to be larger than the pulse width of the first selection signal MUX1 and the pulse width of the third selection signal MUX3 have.

Hereinafter, a liquid crystal display device driving method according to the present invention constituted as described above will be described. The content of the following description overlapping with that described above will be briefly described or omitted.

A method of driving a liquid crystal display according to the present invention includes converting image data into data voltages, dividing one horizontal period into a plurality of sub-horizontal periods having different periods, outputting one And outputting a plurality of selection signals having a pulse width corresponding to each of the sub horizontal periods and outputting the data voltages input for each of the sub horizontal periods from the one output channel, Switching according to the selection signals, and sequentially outputting the data to different data lines formed on the panel.

The timing controller 400 of the main driver 500 generates the source output enable signal SOE and transmits the generated source enable signal SOE to the data driver 300 to generate the selection signals MUX1 to MUX3 To the distribution unit.

Next, the data driver 300 outputs three data voltages during a horizontal period corresponding to each of the pulse widths of the selection signals, using the source output enable signal SOE. Hereinafter, the present invention will be described by assuming that 121 clocks (CLK) are outputted during one horizontal period.

Finally, the distributor 600 sequentially outputs the three data voltages to corresponding data lines according to the selection signals.

The first selection signal MUX1 is switched to a high level after the first delay time PSWT corresponding to 10 CLK after the start of one horizontal period and is output as the first pulse width PSWW1 corresponding to 15 CLK. Accordingly, the first switch TR1 is turned on, and the first data voltage RED is output to the first data line. Thus, the first data voltage may be charged to the pixel for a time corresponding to about 25 CLK.

The second selection signal MUX2 is output as the second pulse width PSWW2 corresponding to 30CLK after the second delay time PSWG1 corresponding to 10CLK after the output of the first selection signal MUX1. Accordingly, the second switch TR2 is turned on, and the second data voltage RED is output to the second data line. Thus, the second data voltage may be charged to the pixel for a time corresponding to about 30 CLK.

The third selection signal MUX3 is output as a third pulse width PSWW3 corresponding to 25CLK after the third delay time PSWG2 corresponding to 15CLK after the output of the second selection signal MUX2. Accordingly, the third switch TR3 is turned on and the third data voltage BLUE is output to the third data line. In Fig. 6, each of SNT1 and SNT2 may include a ground signal and a polarity switching signal.

As described above, the present invention sets the timings (pulse widths) of each of the three selection signals MUX1 to MUX3 capable of switching three switches to be different from each other, So that the reduction in luminance can be minimized.

That is, the present invention increases the output time of the green data voltage having a polarity different from the polarity of the red data voltage and the blue data voltage, output during the output period of the red data voltage and the blue data voltage, Green holding time margin), it is possible to solve the luminance lowering problem caused by the shortage of the holding time of the green data voltage in the conventional liquid crystal display device.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: panel 200: gate driver
300: Data driver 400: Timing controller
500: main driver 600: distribution unit

Claims

A panel in which pixels are formed for each intersection region of the gate lines and the data lines;
And outputs one data voltage for each of the sub horizontal periods through one output channel, and the sub horizontal periods are divided into a plurality of sub horizontal periods having one horizontal period and a plurality of sub horizontal periods having different periods, A main driver for outputting a plurality of selection signals having a pulse width corresponding to each of the plurality of selection signals; And
And a distributor for switching the data voltages input for each of the sub horizontal periods from the one output channel according to the selection signals and sequentially outputting the data voltages to the different data lines formed on the panel, Device.

The method according to claim 1,
Wherein the two data voltages continuously output from the main driver have different polarities.

3. The method of claim 2,
When the data voltages are three, the second sub-horizontal period in which a data voltage having a polarity different from the polarity of the two data voltages is output is a first sub-horizontal period in which the two data voltages are output, Wherein the liquid crystal display panel is longer than the liquid crystal display panel.

The method of claim 3,
The selection signals,
A first selection signal having a pulse width corresponding to the first sub-horizontal period;
A second selection signal having a pulse width corresponding to the second sub-horizontal period; And
And a third selection signal having a pulse width corresponding to the third sub-horizontal period.

The method according to claim 1,
Wherein the distributing unit includes at least one switching unit,
The switching device includes:
A first switch connected to the one output channel and the first data line and turned on according to a first one of the selection signals;
A second switch connected to the one output channel and the second data line and turned on in response to a second selection signal of the selection signals; And
And a third switch connected to the one output channel and the third data line and turned on according to a third one of the selection signals,
And the second data line is formed between the first data line and the third data line.

6. The method of claim 5,
A polarity of a first data voltage output to the first data line through the first switch in accordance with the first selection signal and a polarity of a first data voltage output to the third data line through the third switch in accordance with the third selection signal And the polarity of the third data voltage is different from the polarity of the second data voltage output to the second data line through the second switch in accordance with the second selection signal.

6. The method of claim 5,
Wherein a pulse width of the second selection signal is larger than a pulse width of the first selection signal and a pulse width of the third selection signal.

6. The method of claim 5,
Wherein the first data voltage output through the first switch is a red data voltage, the second data voltage output through the second switch is a green data voltage, and the third data And the voltage is a blue data voltage.

And outputs one data voltage for each of the sub horizontal periods through one output channel, and the sub horizontal periods are divided into a plurality of sub horizontal periods having one horizontal period and a plurality of sub horizontal periods having different periods, Outputting a plurality of selection signals having a pulse width corresponding to each of the plurality of selection signals; And
And switching the data voltages input for each of the sub horizontal periods from the one output channel according to the selection signals and sequentially outputting the data voltages to different data lines formed on the panel, Driving method.

10. The method of claim 9,
When the data voltages are three, the second sub-horizontal period in which a data voltage having a polarity different from the polarity of the two data voltages is output is a first sub-horizontal period in which the two data voltages are output, And the pulse width of the second selection signal corresponding to the second sub-horizontal period is longer than the pulse width of the first selection signal corresponding to the first sub-horizontal period and the pulse width of the third selection signal corresponding to the third sub- Wherein the pulse width of the signal is larger than the pulse width of the signal.