JP2002318566A - Liquid crystal driving circuit and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the steady-state current of an output amplifier, for realizing a low power consumption of a liquid crystal display. SOLUTION: A gradation voltage can be applied to an odd number-th terminal and an even number-th terminal during a horizontal period with a single output amplifier circuit by dividing the horizontal period into a 1st period and a 2nd period by a horizontal dividing signal, selecting the gradation voltage corresponding to an odd number-th terminal and an even number-th terminal adjacent to a data driver by a selection circuit and connecting the voltage to the output amplifier, and switching the voltage to the odd number-th terminal or the even number-th terminal by an output terminal switching circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving system for displaying a liquid crystal display and a liquid crystal driving circuit, and more particularly to a liquid crystal driver circuit for applying a driving voltage to a liquid crystal panel.

[0002]

2. Description of the Related Art In a conventional liquid crystal display device, since 1996 S
ID DIgest (p247-250) "An 8-bit
As described in “Digital Data Driver for Color TFT-LCDs,” the data driver generates a grayscale voltage from the input reference voltage using a DAC circuit, selects the liquid crystal application voltage corresponding to the display data, and outputs it. The output was buffered by an amplifier circuit. That is, an output amplifier circuit is provided corresponding to the resolution of the liquid crystal panel. However, since the amplifier circuit consumes power due to the flow of a steady current corresponding to the power supply voltage, the amplifier circuit occupies most of the power consumed inside the drive circuit.

As described above, in the conventional data driver, no consideration has been given to reducing power consumption by reducing the steady-state current of the amplifier circuit.

[0004]

The liquid crystal display is
Because of its thin and lightweight features, it is used as a display device for various OA devices such as notebook personal computers. Furthermore, liquid crystal displays are available for mobile phones, electronic organizers, PDAs (Personal D
digital assistant) and portable information devices such as portable terminals. In such portable information devices, reducing power consumption is an important issue in order to enable long-term use. Therefore, low power consumption is an important issue for liquid crystal displays.

A conventional data driver has a configuration in which an output amplifier circuit is provided for each terminal. The steady-state current flowing in the amplifier circuit cannot be reduced to a certain value or less because a current necessary to secure a stable operation with respect to a drive current variation, a load capacitance variation, and a manufacturing variation flows. Since each terminal has an output amplifier circuit, it has an amplifier circuit corresponding to the number of resolutions of the liquid crystal display driven by the data driver, and it is difficult to reduce power consumption.

According to the present invention, the steady current of the output amplifier circuit can be reduced, and the power consumption of the liquid crystal display can be reduced.

[0007]

In order to solve the above-mentioned problem, a horizontal period is divided into a first period and a second period by a horizontal division signal, and a gray scale corresponding to an odd-numbered terminal and an even-numbered terminal adjacent to a data driver. Select the voltage with the selection circuit,
By connecting to an output amplifier circuit and switching to an odd-numbered terminal or an even-numbered terminal by an output terminal switching circuit, a grayscale voltage is output to the odd-numbered terminal in the first period,
The even-numbered terminals are in a high impedance state without being driven. Conversely, in the second period, the grayscale voltage is output to the even-numbered terminals, and the odd-numbered terminals are not driven and are in a high impedance state. A single output amplifier circuit can apply a gradation voltage to odd-numbered terminals and even-numbered terminals during a horizontal period.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a configuration diagram of a liquid crystal panel drive circuit to which the present invention is applied, and a 160 × R
A liquid crystal panel of GB × 160 is converted to 64 gradations for each of RGB, 262
The configuration of a liquid crystal display for displaying 144 colors is shown. 101 is a data driver for applying a gradation voltage corresponding to display data to the liquid crystal panel, 102 is a scan driver for sequentially scanning the liquid crystal panel, 103 is a horizontal resolution of 160 ×
RGB, liquid crystal panel with vertical resolution of 160 lines, 104
, A controller for controlling the control signals and display data of the data driver 101 and the scanning driver 102; 105, a power supply circuit for generating a gradation reference voltage; 106, a display signal group transferred from the system device; 118, a display memory circuit Reference numeral 119 denotes a memory control bus. 107 is an AC polarity signal (M) indicating the AC polarity, and 108 is the controller 1
A data synchronization clock (CL2) for transferring the display data 110 from the data driver 04 to the data driver 101, and a data valid signal (E) 109 indicating the beginning of the valid period of the display data 110
IO), 110 is display data of a total of 18 bits each of 6 bits of RGB, 111 is a data horizontal synchronization signal (CL1) indicating a horizontal period of the data driver 101, and 112 is a horizontal division indicating a timing of dividing the horizontal period into two periods. A signal (CL1B), 113 denotes a gray scale reference voltage serving as a reference of a gray scale voltage generated by the power supply circuit 105, and 114 denotes a frame synchronizing signal (FLM) for controlling the scanning driver 102 and a scanning horizontal signal (CL3). Scan synchronization signal, 115
Is a common electrode power supply (VCOM) for applying a voltage of a common electrode of the liquid crystal panel 103, 480 liquid crystal application electrodes output from the data driver 101, 160 scanning electrodes driven by the scanning driver 102, 120 Is a shift register for generating a latch signal for sequentially latching the display data 110 in synchronization with the data synchronization clock 108, 121 is a latch signal corresponding to each pixel generated by the shift register 120, 122 is 6 bits for each pixel, 480
A latch circuit for pixels, 123 is display data held in the latch circuit 122, and 124 is a data horizontal synchronization signal 111.
, A latch circuit for simultaneously latching the display data 123 for all pixels; 125, display data held in the latch circuit 124; 126, a control circuit for generating a control signal 127 for switching the selection circuit 128 and the switching circuit 136; A selection circuit for selecting the display data of the odd-numbered pixel and the even-numbered pixel, 129 is the display data selected by the selection circuit 128, 130 is a gradation voltage generation circuit that generates a voltage of 64 gradations from the gradation reference voltage 113, 131 is a gradation voltage of 64 voltage levels, 132 is a selection circuit for selecting a gradation voltage corresponding to the display data 129 from the gradation voltage 131, 133 is a gradation voltage selected by the selection circuit 132, 1
Reference numeral 34 denotes a buffer for the gradation voltage 133 and
, A switching circuit 135 for switching the output voltage 135 between the odd-numbered terminal and the even-numbered terminal. FIG. 2 is a diagram showing a line inversion AC drive, FIG. 3 is a diagram showing a VCOM (common electrode) AC drive, FIG. 4 is a diagram showing a drive timing of a liquid crystal display, FIG. FIG. 6 is a diagram showing the relationship between the output terminal of the data driver, the AC polarity signal, and the liquid crystal applied voltage.

In this embodiment, as shown in FIG. 2, the AC polarity (positive polarity is indicated by + and negative polarity is indicated by-) is inverted for each line, and a line inversion AC operation in which the same line has the same polarity is performed. . Also, as shown in FIG. 3, VCOM AC driving is performed in which a VCOM electrode (common electrode) for holding a voltage of the liquid crystal panel is turned into an AC in synchronization with a gradation voltage.

Next, these display operations will be described.
In FIG. 1, a controller 104 receives a display signal group 106 from a system device (CPU or the like) not shown, and
The display data to be displayed on the liquid crystal panel 103 is written to the display memory 118 via the memory control bus 119. Then, the display data written in the display memory 118 is read out in synchronization with the display frame period, and is output together with the timing signals of the data driver 101 and the scanning driver 102 for driving the liquid crystal. In the controller 104, R
6 bits for each of RGB total 1 for RGB 64 gradation display
8-bit display data 110, data synchronous clock 10
8. The display data is transferred to the data driver 101 using the data valid signal 109, and the data driver 101
The display data is sequentially taken in by RGB one pixel by the data synchronous clock 108. The timing of data capture will be described with reference to FIGS. Data synchronization clock 10
The controller 104 outputs a data valid signal 109 to the display data 110 transferred in synchronization with the display data 8 at the timing when the display data becomes valid, and the data driver 101 starts taking in the display data. Data driver 101
Captures display data for each pixel of RGB, and completes capture of display data for 480 outputs in 160 clocks. As a result, one line of display data is transferred to the latch circuit 1.
Take in to 22. Next, all the display data of one line of the data latch circuit 122 are simultaneously transmitted to the data horizontal synchronization signal 11.
At 1, the data is latched by the data latch circuit 124. By performing this data capturing operation every horizontal period, the display data of each line can be sequentially captured. Latch circuit 12
The display data 125 held at No. 4 is selected by the selection circuit 128 between display data corresponding to adjacent odd-numbered terminals and even-numbered terminals. 64-level gray scale voltage 13 corresponding to 64 gray scales generated by the gray scale voltage generation circuit 130
The selection circuit 132 selects a one-level grayscale voltage corresponding to the display data 129 selected from No. 1. The selected gradation voltage 133 is buffered and output by the output amplifier circuit 134, and is switched by the switching circuit 136 to the odd-numbered terminal or the even-numbered terminal. This operation will be described with reference to FIGS. As shown in FIG. 5, the horizontal period is divided into a first period and a second period by a horizontal division signal 112, and in the first period, a gray scale voltage is output to an odd-numbered terminal.
The even-numbered terminals are in a high impedance state without being driven. Conversely, in the second period, the grayscale voltage is output to the even-numbered terminals, and the odd-numbered terminals are not driven and are in a high impedance state. That is, by switching the selection circuit 128 and the switching circuit 136 to the odd-numbered terminal or the even-numbered terminal with the switching signal 127, one output amplifier circuit 134 is provided for each of the odd-numbered terminal and the even-numbered terminal during the horizontal period. A voltage can be applied. This relationship is summarized as shown in FIG. 6, and can be realized by controlling the switching signal 127 by the control circuit 126. The AC polarity of the gray scale voltage is determined by an AC polarity signal 107 by the power supply circuit 105.
This is realized by switching the gradation reference voltage 113.

At this time, the scanning driver 102 selects the first gate line in synchronization with the scanning horizontal synchronization signal CL3 at the timing of the frame synchronization signal FLM generated by the controller 104, and synchronizes with the scanning horizontal synchronization signal CL3. Then, the second and third gate lines are sequentially selected. 1 in succession with 160 clocks of scanning horizontal synchronization signal CL3
When the 60th line is selected and the next frame synchronization signal FLM becomes valid, the gate line of the first line is selected. By repeating the operation of selecting 160 lines in the frame cycle in this manner, a line-sequential selection operation is performed and the data driver 10
1 outputs the grayscale drive voltage 116 to the data line of the liquid crystal panel 103, thereby realizing display corresponding to the display data.

As described above, in this embodiment, the output amplifier circuit of the data driver can be realized with one configuration for two output terminals, and the number of amplifier circuits can be reduced to half. For this reason, the steady current of the amplifier circuit of the liquid crystal display can be reduced, and low power consumption can be realized.

In this embodiment, the number of output terminals of the data driver is 480. However, the present invention is not limited to this, and the same effect can be obtained by setting the number of output terminals in accordance with the resolution of the liquid crystal panel. . For example, horizontal resolution 240 × RG
B, a liquid crystal panel having a vertical resolution of 320 and a number of output terminals of 240
Similarly, when driving with three data drivers, the number of amplifier circuits can be reduced to half, and low power consumption can be realized.

Next, a second embodiment of the present invention will be described with reference to FIG.
4 to FIG. 4 and FIG. 7 to FIG. In the second embodiment, the line inversion AC drive and the VCOM (common electrode) AC drive shown in FIGS. 2 and 3 are performed as in the first embodiment, and the horizontal period is divided into three periods. different.

FIG. 7 is a configuration diagram of a liquid crystal panel drive circuit to which the present invention is applied, and shows a configuration of a liquid crystal display in a case where a 160 × RGB × 160 liquid crystal panel displays 262144 colors of 64 gradations of RGB. Reference numeral 701 denotes a data driver for applying a gradation voltage corresponding to display data to the liquid crystal panel, 702 a scan driver for sequentially scanning the liquid crystal panel, 703 a horizontal resolution of 160 × RGB, and a vertical resolution of 1
A liquid crystal panel of 60 lines, 704 is a data driver 70
1, a controller for controlling a control signal and display data of the scan driver 702, a power supply circuit 705 for generating a gradation reference voltage, a display signal group 706 transferred from a system device, a display memory circuit 718, and a display memory circuit 719 It is a memory control bus. Reference numeral 707 denotes an AC polarity signal (M) indicating the AC polarity, reference numeral 708 denotes a data synchronization clock (CL2) for transferring display data 710 from the controller 704 to the data driver 701, and reference numeral 709 denotes data validity indicating the beginning of the validity period of the display data 710. Signal (EIO), 710 is RG
B, a total of 18 bits of display data, a total of 18 bits, 711 is a data horizontal synchronization signal (CL1) indicating a horizontal period of the data driver 701, 712 is a horizontal division signal (CL1B) indicating a timing of dividing the horizontal period into three periods, 713
Denotes a gray scale reference voltage which is a reference of a gray scale voltage generated by the power supply circuit 705, 714 denotes a frame synchronization signal (FLM) for controlling the scanning driver 702, and a scanning synchronization signal collectively indicating a scanning horizontal signal (CL3). A common electrode power supply (VCOM) 7 for applying a voltage of the common electrode of the liquid crystal panel 703;
Reference numeral 16 denotes 480 liquid crystal application electrodes output from the data driver 701, 717 denotes 160 scanning electrodes driven by the scanning driver 702, and 720 denotes a latch signal for sequentially latching display data 710 in synchronization with the data synchronization clock 708. , 721 is a latch signal corresponding to each pixel generated by the shift register 720, 7
Reference numeral 22 denotes a 6-bit pixel, a latch circuit for 480 pixels, 7
23, display data held in the latch circuit 722;
Reference numeral 4 denotes a latch circuit for simultaneously latching display data 723 with all pixels by a data horizontal synchronizing signal 711; 725, display data held in a latch circuit 724;
8. A control circuit for generating a control signal 727 for switching the switching circuit 736. A latch circuit 728 has a (3n-2) -th terminal, a (3n-1) -th terminal, and a (3n) -th terminal (n = 3n) for every three pixels. , 729 is a display data selected by the selection circuit 728, 730 is a grayscale voltage generation circuit that generates 64 grayscale voltages from the grayscale reference voltage 713, 731 is a gradation voltage of 64 voltage levels, 732 is a selection circuit for selecting a gradation voltage corresponding to the display data 729 from the gradation voltage 731,
733 is a gradation voltage selected by the selection circuit 732, 734 is an output amplifier circuit for buffering the gradation voltage 733 and driving the liquid crystal panel 703, 735 is an output voltage of the output amplifier circuit, and 736 is an output voltage 735 every three terminals. (3n-2)
This is a switching circuit that switches between the (3n−1) th terminal and the (3n) th terminal (n = 1, 2, 3,...).

FIG. 8 shows the timing of the voltage applied to the liquid crystal. FIG. 9 shows the output terminal of the data driver and the AC polarity signal.
FIG. 4 is a diagram showing a relationship between liquid crystal applied voltages.

In this embodiment, as shown in FIG. 2, the AC polarity (positive polarity is indicated by + and negative polarity is indicated by-) is inverted for each line, and a line inversion AC operation in which the same line has the same polarity is performed. . Also, as shown in FIG. 3, VCOM AC driving is performed in which a VCOM electrode (common electrode) for holding a voltage of the liquid crystal panel is turned into an AC in synchronization with a gradation voltage.

Next, these display operations will be described.
7, a controller 704 receives a display signal group 706 from a system device (CPU or the like) not shown, and
The display data to be displayed on the liquid crystal panel 703 is written to the display memory 718 via the memory control bus 719. Then, the display data written in the display memory 718 is read out in synchronization with the display frame period, and is output together with the timing signals of the data driver 701 and the scanning driver 702 for driving the liquid crystal. In the controller 704, R
6 bits for each of RGB total 1 for RGB 64 gradation display
8-bit display data 710, data synchronous clock 70
8. The display data is transferred to the data driver 701 using the data valid signal 709.
The display data is read in one by one for each RGB pixel by the data synchronous clock 708. The data fetch operation of the second embodiment is the same as that of the first embodiment, and the timing of this data fetch will be described with reference to FIGS. Display data 710 transferred in synchronization with the data synchronization clock 708
The controller 704 outputs a data valid signal 709 at the timing when the display data becomes valid, and the data driver 701 starts taking in the display data. The data driver 701 captures the display data for each pixel of RGB, and completes the capture of the display data for 480 outputs in 160 clocks. Thus, one line of display data is taken into the latch circuit 722. Next, all the display data of one line of the data latch circuit 722 are simultaneously latched in the data latch circuit 724 by the data horizontal synchronization signal 711. By performing this data capturing operation every horizontal period, the display data of each line can be sequentially captured. The display data 725 held in the latch circuit 724 is
A selection circuit 7 between display data corresponding to three adjacent terminals
28. 64 levels of gradation voltage 731 corresponding to 64 gradations generated by the gradation voltage generation circuit 730
The selection circuit 732 selects a one-level grayscale voltage corresponding to the display data 729 selected from. The selected gradation voltage 733 is buffered and output by the output amplifier circuit 734, and the switching circuit 736 outputs the (3n-2) th terminal, the (3n-1) th terminal, and the (3n) th terminal (n
= 1, 2, 3,...). This operation will be described with reference to FIGS. As shown in FIG. 8, the horizontal period is divided into a first period, a second period, and a third period by a horizontal division signal 712. In the first period, a gray scale voltage is output to the (3n-2) th terminal, and (3n) The -1) th terminal and the (3n) th terminal are in a high impedance state without being driven.
In the second period, the grayscale voltage is output to the (3n-1) th terminal, and the (3n-2) th terminal and the (3n) th terminal are in a high impedance state without being driven. In the third period,
The grayscale voltage is output to the (3n) th terminal, and the (3n-2) th terminal and the (3n-1) th terminal are put into a high impedance state without being driven. In other words, by switching the selection circuit 728 and the switching circuit 736 to the (3n-2) -th terminal, the (3n-1) -th terminal, and the (3n) -th terminal, which are the three adjacent pixels, by the switching signal 727, the output amplifier circuit 734 And a gray scale voltage can be applied to the (3n-2) th terminal, the (3n-1) th terminal, and the (3n) th terminal during the horizontal period. This relationship is summarized as shown in FIG. 9, and is realized by controlling the switching signal 727 by the control circuit 726. Note that the AC polarity of the gray scale voltage is realized by switching the gray scale reference voltage 713 by the AC polarity signal 707 in the power supply circuit 705. Also,
In the case where the configuration of the liquid crystal panel is an RGB vertical stripe structure in which red pixels, blue pixels, and green pixels are vertically arranged as shown in FIG. 20, the (3n-2) th terminal is a red pixel, (3
The (n-1) th terminal corresponds to a blue pixel, and the (3n) th terminal corresponds to a green pixel.

At this time, the scanning driver 702 selects the first gate line in synchronization with the scanning horizontal synchronization signal CL3 at the timing of the frame synchronization signal FLM generated by the controller 704, and synchronizes with the scanning horizontal synchronization signal CL3. Then, the second and third gate lines are sequentially selected. 1 in succession with 160 clocks of scanning horizontal synchronization signal CL3
When the 60th line is selected and the next frame synchronization signal FLM becomes valid, the gate line of the first line is selected. By repeating the operation of selecting 160 lines in the frame cycle in this manner, a line-sequential selection operation is performed, and the data driver 70
1 outputs the grayscale drive voltage 716 to the data line of the liquid crystal panel 703, thereby realizing display corresponding to the display data.

As described above, in the present embodiment, the output amplifier circuit of the data driver can be realized with one configuration for every three output terminals, and the number of amplifier circuits can be reduced to ３. For this reason, the steady current of the amplifier circuit of the liquid crystal display can be reduced, and low power consumption can be realized.

In this embodiment, the number of output terminals of the data driver is 480. However, the present invention is not limited to this, and the same effect can be obtained by setting the number of output terminals according to the resolution of the liquid crystal panel. . For example, horizontal resolution 240 × RG
B, a liquid crystal panel having a vertical resolution of 320 and a number of output terminals of 240
Similarly, when driving with three data drivers, the number of amplifier circuits can be reduced to 1/3 and low power consumption can be realized.

Next, a third embodiment of the present invention will be described with reference to FIG.
Description will be made from 0 to FIG. 10 and 11 are diagrams showing dot inversion AC driving.

FIG. 12 is a configuration diagram of a liquid crystal panel driving circuit to which the present invention is applied, and shows a configuration of a liquid crystal display when a 160 × RGB × 160 liquid crystal panel displays 262144 colors of 64 gradations of RGB. Reference numeral 801 denotes a data driver for applying a gradation voltage corresponding to display data to the liquid crystal panel, 802 a scan driver for sequentially scanning the liquid crystal panel, 803 a horizontal resolution of 160 × RGB, and a vertical resolution of 1
A 60-line liquid crystal panel, 804 is a data driver 80
1. A controller for controlling a control signal and display data of the scan driver 802, a power supply circuit 805 for generating a gradation reference voltage, a display signal group 806 transferred from a system device, a display memory circuit 818, and a display memory circuit 819 It is a memory control bus. 807 is an AC polarity signal (M) indicating the polarity of AC, 808 is a data synchronization clock (CL2) for transferring display data 810 from the controller 804 to the data driver 801, and 809 is data valid indicating the beginning of the valid period of the display data 810 Signal (EIO), 810 is RG
B, display data of a total of 18 bits each of 6 bits, 811 is a data horizontal synchronization signal (CL1) indicating a horizontal period of the data driver 801, 812 is a horizontal division signal (CL1B) indicating a timing of dividing the horizontal period into two periods, 813
A is a positive gradation reference voltage which is a reference of the positive gradation voltage generated by the power supply circuit 805, 813B is a negative gradation reference voltage which is a reference of the negative gradation voltage generated by the power circuit 805, and 814 is A frame synchronization signal (FLM) for controlling the scanning driver 802 and a scanning synchronization signal collectively indicating a scanning horizontal signal (CL3), 815 is a common electrode power supply (VCOM) for applying a voltage of a common electrode of the liquid crystal panel 803, and 816 is a data driver 480 liquid crystal application electrodes 817 output from 801 are driven by a scan driver 802.
0 scan electrodes; 820, a shift register for generating a latch signal for sequentially latching display data 810 in synchronization with a data synchronization clock 808; 821, a shift register 8;
20, a latch signal corresponding to each pixel generated in 20, 822 is a 6-bit pixel, a latch circuit for 480 pixels, 823 is display data held in the latch circuit 822, 824 is a data horizontal synchronizing signal 811 and the display data 823 is A latch circuit for simultaneously latching all pixels 825 is a latch circuit 824
826 are control signals 827A and 82 for switching the selection circuit 828 and the switching circuit 836.
7B, 840A, 840B, 840C, and 840D are generated by the control circuit 828.
3) A selection circuit for selecting display data of the (4n-2) th pixel, (4n-1) th pixel, and (4n) th pixel (n = 1, 2, 3,...), And 829 is a selection circuit 828
The display data 830A is a positive gradation voltage generation circuit that generates a 64 gradation voltage from the positive gradation reference voltage 813A, and the display data 830B is a 64 gradation voltage that is generated from the negative gradation reference voltage 813B. Negative gradation voltage generation circuit, 8
31A is a positive gradation voltage of 64 voltage levels, 831B is a negative gradation voltage of 64 voltage levels, 832A is a selection circuit for selecting a gradation voltage corresponding to display data 829 from the positive gradation voltage 831A, and 832B is Negative gradation voltage 83
A selection circuit for selecting a gradation voltage corresponding to the display data 829 from 1B; 833, a gradation voltage selected by the selection circuits 832A and 832B; 834, an output amplifier circuit for buffering the gradation voltage 833 and driving the liquid crystal panel 803 In HAM
P drives a positive polarity gray scale voltage, and LAMP has a configuration of an amplifier circuit which drives a negative polarity gray scale voltage. 835 is an output voltage of the output amplifier circuit, and 836 is an output voltage 835 of the (4n-3) th terminal, the (4n-2) th terminal and the (4n
-1) th terminal and (4n) th terminal (n = 1, 2, 3,.
..).

FIG. 13 is a diagram showing the drive timing of the liquid crystal display, FIG. 14 is a diagram showing the timing of the liquid crystal applied voltage, and FIG. 15 is a diagram showing the relationship between the output terminal of the data driver, the AC polarity signal, and the liquid crystal applied voltage. .

In this embodiment, as shown in FIG. 10, the AC polarity (positive polarity is indicated by + and negative polarity is indicated by-) is inverted for each adjacent terminal and each adjacent line, and the dot inversion where the polarity of the adjacent pixel is inverted. Perform AC operation. Further, as shown in FIG. 11, the voltage of the VCOM electrode (common electrode) for holding the voltage of the liquid crystal panel is kept constant, and the gradation voltage is set to a positive potential or a negative alternating polarity with a high potential and a low potential with respect to the VCOM electrode voltage. An AC drive is performed by applying a potential voltage.

Next, these display operations will be described.
12, a controller 804 receives a display signal group 806 from a system device (CPU or the like) not shown, and writes display data to be displayed on a liquid crystal panel 803 to a display memory 818 via a memory control bus 819. Then, the display data written to the display memory 818 is
The data is read out in synchronization with the display frame period and output together with the timing signals of the data driver 801 and the scanning driver 802 for driving the liquid crystal. In the controller 804,
In order to perform 64 gradation display of RGB, display data 810 of a total of 18 bits for each of 6 bits for RGB, data synchronous clock 8
08, the display data is transferred to the data driver 801 using the data valid signal 809, and the data driver 801 sequentially takes in the display data for each RGB pixel by the data synchronous clock 808. The data fetch timing will be described with reference to FIGS. The display data 810 transferred in synchronization with the data synchronization clock 808 is
When the display data becomes valid, the controller 80
4 outputs a data valid signal 809 and the data driver 8
01 starts capturing display data. The data driver 801 captures display data for each pixel of RGB and outputs
The capture of display data for 480 outputs is completed in 60 clocks. Thus, one line of display data is taken into the latch circuit 822. Next, the data latch circuit 822
Are simultaneously latched in the data latch circuit 824 by the data horizontal synchronization signal 811. By performing this data capturing operation every horizontal period, the display data of each line can be sequentially captured. The display data 825 held in the latch circuit 824 includes four adjacent terminals (4n−3) th terminal, (4n−2) th terminal, (4n−1) th terminal, and (4n) th terminal (n = 1). ,
2, 3,...).
8 selected. 1 corresponding to the display data 829 selected from the 64 levels of positive polarity gradation voltage 831A corresponding to 64 gradations generated by the gradation voltage generation circuit 830A.
The gradation voltage of the level is selected by the selection circuit 832A, and 6 corresponding to the 64 gradations generated by the gradation voltage generation circuit 830B.
The selection circuit 832B selects one-level gradation voltage corresponding to the display data 829 selected from the four-level positive polarity gradation voltage 831B. The selected gradation voltage 833 is buffered and output by the output amplifier circuit 834, but is connected to four terminals (4n−
3) The terminal is switched to the (4n-2) th terminal, the (4n-1) th terminal, and the (4n) th terminal. This operation will be described with reference to FIGS. As shown in FIG. 14, the horizontal period is divided into a first period and a second period by a horizontal division signal 812, and in the first period, the (4n-3) th terminal and the (4n-2) th terminal have inverted AC polarities. A positive gradation voltage and a negative gradation voltage are output, and the (4n-1) th terminal and the (4n) th terminal are put into a high impedance state without being driven. Conversely, in the second period, the positive and negative gray-scale voltages whose AC polarities are inverted are output to the (4n-1) th terminal and the (4n) th terminal, and the (4n-3) th terminal is connected to the (4n-3) th terminal. The (4n-2) th terminal is set in a high impedance state without being driven. In other words, the selection circuit 828 has four pixels adjacent to each other with the switching signals 827A and 827B (4n
-3) th pixel and (4n-2) th pixel and (4n-1)
Switch the display data of the pixel and the (4n) th pixel,
In synchronization with this, the switching circuit 836 switches the switching signal 8
By switching the four terminals (4n-3), (4n-2), (4n-1) and (4n) which are four terminals adjacent at 40A, 840B, 840C and 840D, the output amplifier HVAMP and LVA of circuit 834
The gradation voltage can be applied to each of the four output terminals by the two amplifier circuits of MP. This relationship is summarized as shown in FIG. 15, in which the control circuit 826 switches the switching signals 827A and 827B and the switching signals 840A and 840.
This is realized by controlling B, 840C, and 840D.

At this time, the scanning driver 802 selects the first gate line in synchronization with the scanning horizontal synchronization signal CL3 at the timing of the frame synchronization signal FLM generated by the controller 804, and synchronizes with the scanning horizontal synchronization signal CL3. Then, the second and third gate lines are sequentially selected. 1 in succession with 160 clocks of scanning horizontal synchronization signal CL3
When the 60th line is selected and the next frame synchronization signal FLM becomes valid, the gate line of the first line is selected. By repeating the operation of selecting 160 lines in the frame cycle in this manner, a line-sequential selection operation is performed, and the data driver 80
1 outputs the grayscale drive voltage 816 to the data line of the liquid crystal panel 803, thereby realizing display corresponding to the display data.

As described above, in the present embodiment, the output amplifier circuit of the data driver can be realized with the configuration having two output terminals at four output terminals, and the number of amplifier circuits can be reduced to half. For this reason, the steady current of the amplifier circuit of the liquid crystal display can be reduced, and low power consumption can be realized.

In this embodiment, the number of output terminals of the data driver is 480. However, the present invention is not limited to this, and the same effect can be obtained by setting the number of output terminals in accordance with the resolution of the liquid crystal panel. . For example, horizontal resolution 240 × RG
B, a liquid crystal panel having a vertical resolution of 320 and a number of output terminals of 240
Similarly, when driving with three data drivers, the number of amplifier circuits can be reduced to half, and low power consumption can be realized.

Next, a fourth embodiment of the present invention will be described with reference to FIG. 2, FIG. 3, FIG. 5, FIG. 6, and FIG. The fourth embodiment is different from the first embodiment in that common inversion driving is performed and gradation display is realized using a 64-gradation data driver having a built-in display memory. FIG.
FIG. 1 is a configuration diagram of a liquid crystal panel driving circuit to which the present invention is applied.
The configuration of a liquid crystal display in the case of performing 4-gradation, 262144-color display is shown. 201 is the CPU of the system device, 2
02 is a system memory, 203 is a system bus containing control signals and data, 204 is a CPU bus, and 205 is a memory bus. A data driver 901 has a built-in display memory and has 160 × RGB = 480 outputs.
Built-in display memory for lines. Reference numerals 206 and 207 denote a data bus and a control signal group with the data driver 901, 208 a command control circuit for controlling an interface with the system bus 203, 209 a control signal group, and 21.
0 is a data bus, 211 is a memory control circuit for controlling the display memory 214 incorporated in the data driver 901, 21
2 is a data address of the display memory circuit 214, 219 is a word address, and 213 is a data bus. Reference numeral 215 denotes an oscillation circuit that generates a clock serving as a reference for display timing, 216 denotes a display reference clock, 217 denotes a display control circuit that controls display timing, 218 denotes a CPU access signal indicating an access from the CPU 201 to the display memory 214, and 220 denotes a CPU access signal. A scan counter 221 for generating a word address of a display line is a word address selector 221 for switching between the CPU 201 and a word address of a display line.
Is a word address selection signal, and 223 is a word line decoder for selecting a word line. 902, a scan driver for sequentially scanning the liquid crystal panel; 903, a horizontal resolution of 160 × R
A liquid crystal panel having a GB and a vertical resolution of 160 lines, a power supply circuit 905 for generating a gradation reference voltage, an AC polarity signal (M) 907 indicating an AC polarity, and a data driver 9 for 911
A data horizontal synchronization signal (CL1) indicating a horizontal period of 01,
Reference numeral 913 denotes a gray scale reference voltage serving as a reference of the gray scale voltage generated by the power supply circuit 905, 914 denotes a frame synchronization signal (FLM) for controlling the scanning driver 902, and a scanning horizontal signal (CL).
A scan synchronization signal 915 collectively indicates a common electrode power supply (VCO) 915 for applying a voltage of the common electrode of the liquid crystal panel 903.
M) and 916 are 480 liquid crystal application electrodes output from the data driver 901, and 917 is the scanning driver 102
923 scanning electrodes driven by the display memory 923
14 is a 6-bit × 480 pixel 1-line display data bus; 924 is a latch circuit that latches display data 923 simultaneously for all pixels with a data horizontal synchronization signal 911;
25 is the display data held in the latch circuit 924, 92
8 is a selection circuit for selecting display data of odd-numbered pixels and even-numbered pixels of the latch circuit 924, and 929 is a selection circuit 92
8, the display data 930 is a gradation reference voltage 913
Voltage generation circuit for generating a voltage of 64 gradations from
1 is a gradation voltage of 64 voltage levels, 932 is a gradation voltage 93
A selection circuit for selecting a gradation voltage corresponding to display data 929 from 1; 933, a gradation voltage selected by the selection circuit 932; 934, an output amplifier circuit for buffering the gradation voltage 933 to drive the liquid crystal panel 903; Is an output voltage of the output amplifier circuit, and 936 is a switching circuit for switching the output voltage 935 between the odd-numbered terminal and the even-numbered terminal.

FIGS. 17 and 18 are timing charts showing write access and read access timings of the data driver of the CPU.

As in the first embodiment, in this embodiment, FIG.
As shown in (1), the AC polarity (positive polarity is indicated by + and negative polarity is indicated by-) is inverted for each line, and a line inversion AC operation is performed in which the same line has the same polarity. Also, as shown in FIG. 3, a VCOM electrode (common electrode) for holding the voltage of the liquid crystal panel
VCOM AC drive in which AC is driven in synchronization with the gradation voltage. Next, these display operations will be described. In FIG. 16, the CPU 201 writes display data to the display memory 214 incorporated in the data driver 901. The CPU 201 transmits the data 206 and the control signal group 207 via the system bus 203 to the data driver 90.
1 and a chip select signal CS, a write signal WR, a read signal RD, 16 as shown in FIGS.
A command is transferred to the data driver 901 based on the bit data D15 to D0, and write control and read control of the display memory are performed. For example, when writing display data to the display memory 214, the CPU 201 transfers the display memory address write command to the data driver 901, transfers the address, and then transfers the display data write command to transfer the display data. I do. In the data driver 901, the command control circuit 208 transfers a control signal group 209 to the memory control circuit 211 and the address of the display memory via the data bus 210 in response to the display memory address write command. Correspondingly, the memory control circuit 211 controls the write data address 212 and the word address 219 of the display memory 214 to write the display data.
By performing this operation for each address of the display memory, data of one screen can be written to the display memory 214. The display data of the display memory 214 is stored in the oscillation circuit 215
From the display reference clock 216 generated by the display control circuit 2
17, the scan counter 220 generates a display word address of the display line, the word address selection circuit 221 selects the display word address in the display period, and the word line decoder 223.
Selects the word line of the line to be displayed. Then, the display data 923 of the display memory 214 is simultaneously latched by the data latch circuit 924 by the data horizontal synchronization signal 911 for one line of 480 outputs. By performing this data capturing operation every horizontal period, display data of each line can be sequentially captured from the display memory circuit 214.
The display data 925 held in the latch circuit 924 is selected by the selection circuit 928 between display data corresponding to the adjacent odd-numbered terminal and even-numbered terminal. The selection circuit 932 selects one-level gradation voltage corresponding to the selected display data 929 from the 64-level gradation voltage 931 corresponding to the 64 gradations generated by the gradation voltage generation circuit 930. The selected gradation voltage 933 is output to the output amplifier circuit 934.
, And is switched by the switching circuit 936 to the odd-numbered terminal or the even-numbered terminal.
This operation is similar to that of the first embodiment, and will be described with reference to FIGS. As shown in FIG. 5, the horizontal period is divided horizontally into a first period and a second period. In the first period, the grayscale voltage is output to the odd-numbered terminals, and the even-numbered terminals are in a high impedance state without being driven. I do. Conversely, in the second period,
The grayscale voltage is output to the even-numbered terminals, and the odd-numbered terminals are set in a high impedance state without being driven. In other words, the selection circuit 928 and the switching circuit 936 switch the switching signal 927
By switching to the odd-numbered terminal or the even-numbered terminal, the output amplifier circuit 934 can apply a gradation voltage to the odd-numbered terminal and the even-numbered terminal during the horizontal period with one output amplifier circuit 934. This relationship is summarized as shown in FIG. 6, and is realized by controlling the switching signal 927 by the display control circuit 217. The AC polarity of the gray scale voltage is determined by the AC polarity signal 907 in the power supply circuit 905 and the gray scale reference voltage 9.
13 is realized.

At this time, the scanning driver 902 selects the first gate line in synchronization with the scanning horizontal synchronization signal CL3 at the timing of the frame synchronization signal FLM generated by the display control circuit 217, and selects the scanning horizontal synchronization signal CL3. , The second and third gate lines are sequentially selected. 1 in succession with 160 clocks of scanning horizontal synchronization signal CL3
When the 60th line is selected and the next frame synchronization signal FLM becomes valid, the gate line of the first line is selected. By repeating the operation of selecting 160 lines in the frame cycle in this manner, a line-sequential selection operation is performed, and the data driver 90
1 outputs the gradation drive voltage 916 to the data line of the liquid crystal panel 903, and realizes display corresponding to the display data.

As described above, in this embodiment, the output amplifier circuit of the data driver can be realized with one configuration for two output terminals, and the number of amplifier circuits can be reduced to half. For this reason, the steady current of the amplifier circuit of the liquid crystal display can be reduced, and low power consumption can be realized. Further, by incorporating a display memory in the data driver, power consumption due to transfer of display data can be reduced.

In this embodiment, the number of output terminals of the data driver is 480. However, the present invention is not limited to this, and the same effect can be obtained by setting the number of output terminals in accordance with the resolution of the liquid crystal panel. . For example, horizontal resolution 240 × RG
B, a liquid crystal panel having a vertical resolution of 320 and a number of output terminals of 240
Similarly, when driving with three data drivers, the number of amplifier circuits can be reduced to half, and low power consumption can be realized.

In the present embodiment in which the display memory is built in the data driver, the connection is switched between the adjacent odd-numbered terminals and the even-numbered terminals. However, the connection is switched between the adjacent three terminals shown in the second embodiment. The configuration and the configuration in which the connection is switched by four adjacent terminals corresponding to the dot inversion driving shown in the third embodiment can be easily achieved, and the same effect can be obtained.

A display memory as shown in FIG.
A data drive circuit, a scan drive circuit, and a power supply circuit can be easily built in a one-chip LSI.
Similar effects can be obtained.

[0038]

According to the present invention, since the number of output amplifier circuits of the data driver can be reduced, the steady-state current of the amplifier circuit can be reduced and the power consumption of the liquid crystal display can be reduced. Further, the chip size can be reduced by reducing the number of amplifier circuits of the data driver, and cost reduction can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a liquid crystal display device to which the present invention is applied.

FIG. 2 is a diagram showing line inversion driving.

FIG. 3 is a timing chart of line inversion driving.

FIG. 4 is a diagram showing driving timing of a liquid crystal display.

FIG. 5 is a diagram showing output timing of a liquid crystal gradation voltage.

FIG. 6 is a diagram illustrating a relationship between an output terminal and a liquid crystal gradation voltage.

FIG. 7 is a block diagram of an embodiment of a liquid crystal display device to which the present invention is applied.

FIG. 8 is a diagram showing the output timing of a liquid crystal gradation voltage.

FIG. 9 is a diagram showing a relationship between an output terminal and a liquid crystal gradation voltage.

FIG. 10 is a diagram showing dot inversion driving.

FIG. 11 is a timing chart of dot inversion driving.

FIG. 12 is a block diagram of one embodiment of a liquid crystal display device to which the present invention is applied.

FIG. 13 is a diagram showing driving timing of a liquid crystal display.

FIG. 14 is a diagram showing output timing of a liquid crystal gradation voltage.

FIG. 15 is a diagram showing a relationship between an output terminal and a liquid crystal gradation voltage.

FIG. 16 is a block diagram of one embodiment of a liquid crystal display device to which the present invention is applied.

FIG. 17 is a diagram showing the timing of CPU write access.

FIG. 18 is a diagram showing the timing of CPU read access.

FIG. 19 is a block diagram of a liquid crystal display device using a one-chip driver LSI.

FIG. 20 is a configuration diagram of a liquid crystal panel vertical stripe pixel.

[Explanation of symbols]

101: Data driver, 102: Scan driver, 10
Reference numeral 3 denotes a liquid crystal panel having a horizontal resolution of 160 × RGB and vertical resolution of 160 lines; 104 a controller; 105 a power supply circuit for generating a gradation reference voltage; 106 a display signal group transferred from a system device; 118 a display memory circuit 119: a memory control bus, 107: an AC polarity signal (M) indicating the AC polarity, 108: a data synchronous clock (CL2) for transferring the display data 110 from the controller 104 to the data driver 101, 109: display data 1
10 data valid signal (EI) indicating the beginning of the valid period.
O), 110: display data, 111: data horizontal synchronizing signal (CL1), 112: horizontal division signal (CL1B), 113 indicating the timing of dividing the horizontal period into two periods
.., A gray scale reference voltage serving as a reference for the gray scale voltage generated by the power supply circuit 105, 114, a scanning synchronization signal, 115, a common electrode power supply (VCOM), 116, a liquid crystal application electrode, 117, a scanning electrode, 120, a shift register, 121 ... latch signal,
122: latch circuit, 124: latch circuit, 126: control circuit, 128: selection circuit, 129: display data, 13
0: gradation voltage generation circuit, 131: gradation voltage of 64 voltage levels, 132: selection circuit, 133: gradation voltage, 134 ...
Output amplifier circuit, 136 ... Switching circuit.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 623 G09G 3/20 623B 623F 623G 623V 641 641C (72) Inventor Sumiku Oishi Aso, Kawasaki-shi, Kanagawa 1099 Ozenji-ku, Hitachi, Ltd.System Development Laboratory, Hitachi, Ltd. (72) Inventor Makoto Kimura 5-2-1, Josuihoncho, Kodaira-shi, Tokyo In the Semiconductor Group, Hitachi, Ltd. (72) Inventor Hirofumi Koshi, Chiba 3300 Hayano Mobara-shi F-term in Hitachi Display Group (reference) 2H092 GA23 JA24 NA25 NA26 NA27 NA29 PA06 2H093 NA31 NA43 NC01 NC16 NC22 NC26 NC34 NC50 ND06 ND39 ND42 ND49 ND54 5C006 AA22 AC24 AC26 AC27 AF42 AF43 AF71 BC03 BC12 BF02 BF03 BF04 BF15 BF24 BF25 BF43 FA01 FA43 FA47 FA51 5C080 AA10 BB05 CC03 DD22 DD26 DD27 EE29 EE30 FF11 JJ02 JJ04

Claims (11)

[Claims] 1. A liquid crystal panel having a pixel portion in which a plurality of scanning lines and a plurality of data lines are arranged in a matrix, and a plurality of liquid crystal display data corresponding to the liquid crystal display data, the liquid crystal display data of each pixel being held in a latch circuit. LCD gradation voltage,
A data driver circuit for outputting to the data line by a plurality of amplifier circuits from a plurality of output terminals; a head line signal being fetched by a scanning line signal, and sequentially giving a scanning instruction signal to the scanning line to apply a liquid crystal gradation voltage; A scan driver circuit for selecting the scan line to be applied and a liquid crystal for converting a display control signal and display data supplied from a system device into a liquid crystal control signal and liquid crystal display data for driving the data driver circuit and the scan driver circuit. In the liquid crystal display device including a control circuit, the data driver circuit divides a horizontal period, which is a time when one scanning line is selected, into N (N is a natural number, and divides one divided period into a sub-horizontal period). ), The plurality of output terminals are divided into N groups, and the output destination of the amplifier circuit is switched every sub-horizontal period. The liquid crystal display device and outputs a liquid crystal gray scale voltage for each between the output terminals of each group to the data line by the amplifier circuit. 2. The liquid crystal display device according to claim 1, wherein the data driver circuit divides a horizontal period, which is a time when one scanning line is selected, into two (a divided one period is a sub-horizontal period). ), The plurality of output terminals are divided into two groups, the output destination of the amplifier circuit is switched every sub-horizontal period, and the output terminals of each group are connected to the data lines by the amplifier circuit every two horizontal sub-horizontal periods. A liquid crystal display device outputting a liquid crystal gradation voltage. 3. The liquid crystal display device according to claim 1, wherein the data driver circuit divides a horizontal period, which is a time when one scanning line is selected, into three (a divided one period is a sub-horizontal period). ), The plurality of output terminals are divided into three groups, the output destination of the amplifier circuit is switched every sub-horizontal period, and the output terminal of each group is connected to the data line by the amplifier circuit every three horizontal sub-horizontal periods. A liquid crystal display device characterized by outputting a liquid crystal gradation voltage to the liquid crystal display. 4. The liquid crystal display device according to claim 3, wherein the liquid crystal panel has a vertical stripe structure in which red, green, and blue pixels are aligned in a vertical direction, and the data driver circuit includes one scanning line. The horizontal period, which is the selected time, is divided into three (the divided one period is referred to as a sub-horizontal period).
The amplifier circuit is divided into three groups corresponding to green and blue pixels, and the output destination of the amplifier circuit is switched for each sub-horizontal period.
A liquid crystal display device, wherein a liquid crystal gradation voltage is output to a data line by the amplifier circuit from output terminals of three groups of a green pixel group and a blue pixel group. 5. A liquid crystal panel having a pixel portion in which a plurality of scanning lines and a plurality of data lines are arranged in a matrix, and a scanning instruction signal is sequentially given to the scanning line by receiving a head line signal by a scanning line signal; A scanning driver circuit for selecting the scanning line to which a liquid crystal gradation voltage is applied and a display memory for holding liquid crystal display data are incorporated, and 1 is read from the display memory in synchronization with a horizontal period in which the scanning line is selected.
A liquid crystal device comprising: a data driver circuit which holds liquid crystal display data of a line in a latch circuit and outputs a plurality of liquid crystal gradation voltages corresponding to the liquid crystal display data to the data line from a plurality of output terminals by a plurality of amplifier circuits. In the display device, the data driver circuit divides a horizontal period, which is a time during which one scanning line is selected, into N (N is a natural number, and one divided period is a sub-horizontal period). Are divided into N groups, the output destination of the amplifier circuit is switched every sub-horizontal period, and the liquid crystal gray scale voltage is applied to the data line by the amplifier circuit from the output terminal of each group every N horizontal periods. A liquid crystal display device, which outputs the following. 6. The liquid crystal display device according to claim 5, wherein the data driver circuit divides a horizontal period, which is a time when one scanning line is selected, into two (the divided one period is a sub-horizontal period). ), The plurality of output terminals are divided into two groups, the output destination of the amplifier circuit is switched every sub-horizontal period, and the output terminals of each group are connected to the data lines by the amplifier circuit every two horizontal sub-horizontal periods. A liquid crystal display device outputting a liquid crystal gradation voltage. 7. The liquid crystal display device according to claim 5, wherein the data driver circuit divides a horizontal period, which is a time when one scanning line is selected, into three (the divided one period is a sub-horizontal period). ), The plurality of output terminals are divided into three groups, the output destination of the amplifier circuit is switched every sub-horizontal period, and the output terminal of each group is connected to the data line by the amplifier circuit every three horizontal sub-horizontal periods. A liquid crystal display device characterized by outputting a liquid crystal gradation voltage to the liquid crystal display. 8. The liquid crystal display device according to claim 7, wherein the liquid crystal panel has a vertical stripe structure in which red, green, and blue pixels are arranged in a vertical direction, and the data driver circuit includes one of the scanning lines. The horizontal period, which is the selected time, is divided into three (the divided one period is referred to as a sub-horizontal period).
The amplifier circuit is divided into three groups corresponding to green and blue pixels, and the output destination of the amplifier circuit is switched for each sub-horizontal period.
A liquid crystal display device, wherein a liquid crystal gradation voltage is output to a data line by the amplifier circuit from output terminals of three groups of a green pixel group and a blue pixel group. 9. A liquid crystal panel having a pixel portion in which a plurality of scanning lines and a plurality of data lines are arranged in a matrix, and a plurality of liquid crystal display data corresponding to the liquid crystal display data, the liquid crystal display data of each pixel being held in a latch circuit. LCD gradation voltage,
A data driver circuit for outputting to the data line by a plurality of amplifier circuits from a plurality of output terminals; a head line signal being fetched by a scanning line signal, and sequentially giving a scanning instruction signal to the scanning line to apply a liquid crystal gradation voltage; A scan driver circuit for selecting the scan line to be applied and a liquid crystal for converting a display control signal and display data supplied from a system device into a liquid crystal control signal and liquid crystal display data for driving the data driver circuit and the scan driver circuit. In the liquid crystal display device including a control circuit, the data driver circuit divides a horizontal period, which is a time during which one scanning line is selected, into two (one divided period is referred to as a sub-horizontal period). (4n-3) th terminal, (4n-2) th terminal, (4n-1) th terminal, and (4n) th terminal (n
1, 2, 3,...) Are connected to the (4n−2) th terminal and the (4n−
1) terminal group, (4n-1) th terminal and (4
n) The terminal group is divided into two groups, that is, the above-mentioned amplifier circuit is composed of two terminals with four terminals adjacent to each other in the preceding period, and the output destination of the amplifier circuit is switched every sub-horizontal period.
A liquid crystal display device, wherein a liquid crystal gradation voltage is output to a data line by the amplifier circuit from an output terminal of each group for each sub-horizontal period. 10. Receiving liquid crystal display data corresponding to a plurality of pixels, outputting a liquid crystal gradation voltage from a plurality of output terminals according to a horizontal period signal, and forming a plurality of scanning lines and a plurality of data lines in a matrix. In a data driver LSI for driving a liquid crystal panel having an arrayed pixel portion, a liquid crystal display data holding circuit corresponding to the number of output terminals, a data selection circuit for selecting output data of the liquid crystal display data holding circuit, and a floor for generating a gray scale voltage A gradation voltage generation circuit, a gradation voltage selection circuit for selecting a gradation voltage corresponding to liquid crystal display data,
An output amplifier circuit for buffer-amplifying the gradation voltage; and a switching circuit for switching connection of the output amplifier circuit to an output terminal. The horizontal period is divided into N (N is a natural number, and one divided period is defined as a sub-horizontal period). ), The plurality of output terminals are divided into N groups, and the output data of the liquid crystal display data holding circuit is switched and selected by the data selection circuit for each sub-horizontal period, and is input to the grayscale voltage selection circuit. A data driver LSI characterized in that a gradation voltage selected by a voltage selection circuit is amplified by an output amplifier circuit, and a connection circuit is switched by a switching circuit every sub-horizontal period to output a liquid crystal gradation voltage from a plurality of terminals. 11. The data driver LSI according to claim 10, wherein the liquid crystal panel has a vertical stripe structure in which red, green, and blue pixels are arranged in a vertical direction, and divides a horizontal period into three (a divided one period is a sub-period). The output terminals are divided into three groups corresponding to red, green, and blue pixels, and the output data of the liquid crystal display data holding circuit is switched and selected by the data selection circuit for each sub-horizontal period. Then, the grayscale voltage is input to the grayscale voltage selection circuit, the grayscale voltage selected by the grayscale voltage selection circuit is amplified by the output amplifier circuit, and a red pixel group, a green pixel group,
A data driver LSI characterized in that a connection destination is switched to output terminals of three groups of blue pixel groups to output a liquid crystal gradation voltage from a plurality of terminals.