JP2001174788A - Liquid crystal display device and driving method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device and a driving method thereof permitting remarkable reduction in power consumption for display. SOLUTION: As address signals of pixel parts with varying display data, i.e., interface signals including display data signals, active scanning line signals for selecting scanning lines are applied to an electrode common to the pixels corresponding to the addresses in the vertical direction by using, for example, SRAM interface signals. Moreover, to the drain electrodes, a voltage level is applied, which is referred to the same potential as the active and inactive potential of the scanning line signals to be applied to the same pixel. Moreover, to store display states according to the display data of the selected pixels, a control signal at a voltage level of a pulse width according thereto is applied to the gate electrodes corresponding to the addresses in the horizontal direction. In such a manner, it is possible to select only the pixel parts with varying display data and rewrite the display data, and to reduce the number of liquid crystal cells to be applied with the voltages when displaying an image with less varying display data like a still picture, and thereby it can realize a low power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device and a method of driving the same, and more particularly, to a liquid crystal display device using a liquid crystal cell having a memory function and a method of driving the same.

[0002]

2. Description of the Related Art A memory capable of storing two states of a bright state (transmittance, large) and a dark state (transmittance, small), that is, a state in which two different voltages are applied, as two display states. As a liquid crystal material having a function, for example,
Ferroelectric liquid crystal materials are known. A liquid crystal display using a ferroelectric liquid crystal is capable of displaying images with high quality without flicker without deterioration in contrast even when the number of scanning lines is increased. In addition, a liquid crystal display using a ferroelectric liquid crystal has a higher switching speed than an STN or TN liquid crystal, can prevent blurring of an image at the time of rewriting, and does not require an alternating control signal for display control. It is not necessary to always refresh the entire screen. For this reason, liquid crystal displays using ferroelectric liquid crystals are
It is suitable for use in improving responsiveness in mouse operation and window operation, which is essential for applications, and for displaying moving images. As a conventional technique relating to a driving method of a liquid crystal display (liquid crystal display device) using a ferroelectric liquid crystal as a liquid crystal cell, for example, "Color liquid crystal display" edited by Shunsuke Kobayashi (industrial book), p.
13 and the like are known.

FIG. 2 is a view for explaining the pixel structure of a liquid crystal display according to the prior art. The prior art will be described below with reference to FIG. 2, reference numeral 101 denotes a data signal driving circuit, 103 denotes a scanning line signal driving circuit, and 11 to 11.
33 is a liquid crystal cell.

The liquid crystal display according to the prior art shown in FIG. 2 has a simple matrix type panel structure, and liquid crystal cells 11 to 33 are formed at intersections of horizontal scanning lines and vertical data signal lines, respectively. It is configured. This display is driven by applying a potential difference between a scanning voltage applied to the scanning lines from the scanning signal driving circuit 103 and a data voltage applied to the data signal lines from the data signal driving circuit 101 to the liquid crystal cell. When this potential difference is positive and exceeds a certain threshold voltage, the liquid crystal cell becomes a bright state,
The state is stored. The dark state can be stored in the liquid crystal cell by applying a voltage having a polarity opposite to that of storing the bright state and exceeding a certain threshold voltage.

As one of the driving methods of the liquid crystal display having the above-mentioned structure, there is a method of "refresh scanning" in which the entire screen is always written at a constant speed. In this method, the scanning signal driving circuit 103 applies a selection voltage for selecting a scanning line for writing a display, and the data signal driving circuit 101 applies a selection voltage to each liquid crystal cell so as to correspond to the display data of the selected scanning line. The data voltage is applied to write data to the liquid crystal cell on one scanning line. The scanning signal driving circuit 103 sequentially selects the scanning lines and repeats this operation, whereby it is possible to perform writing on the entire screen.

[0006]

A liquid crystal display device using a liquid crystal cell having a memory function according to the prior art described above is one in which display is performed by driving scanning lines in a line-sequential manner. The data voltage corresponding to the display data is applied to the liquid crystal cell at the ratio of. For this reason, in the above-described liquid crystal display device according to the related art, even when a pattern in which display data such as a still image does not change is displayed for a long time, extra power is consumed due to repeated application of voltage. have.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a liquid crystal display device and a driving method thereof capable of remarkably reducing power consumption for display.

[0008]

According to the present invention, an object of the present invention is to provide a liquid crystal display device using a liquid crystal cell having a memory function, wherein one of two substrates disposed opposite to each other with a liquid crystal layer interposed therebetween. A liquid crystal cell having a plurality of common electrodes and a gate electrode orthogonal to each other on the inner surface, a plurality of drain electrodes parallel to the common electrode, and further having a memory function at an intersection of the common electrode and the gate electrode. A liquid crystal panel connected to the gate electrode and the drain electrode and having a switching element for controlling the liquid crystal cell via a common electrode; a data signal driving circuit for driving the gate electrode; and a scanning signal for driving the common electrode A drive circuit; and a voltage level selection circuit for driving the drain electrode, wherein the display state changes as display information in accordance with display data. It said address signal indicating the vertical address of the liquid crystal cell, an address signal indicating the horizontal address, and, using the display data indicating the display state, and the data signal driving circuit and the scanning signal driving circuit is that,
One of the liquid crystal cells is selected based on the address, and the voltage level selection circuit outputs a voltage signal to enable the display state of the liquid crystal cell to be changed to the drain electrode. This is achieved by changing the display state of the liquid crystal cell.

It is another object of the present invention to control one of the liquid crystal cells by the data signal drive circuit, the scan signal drive circuit, and the voltage level selection circuit, and to control the scan signal drive circuit to specify an address in the vertical direction. An active signal of a scanning line signal is applied to a common electrode corresponding to a signal, and the data signal driving circuit applies a scanning signal to a gate electrode corresponding to an address signal indicating an address in the horizontal direction to display data of a selected liquid crystal cell. A voltage level control signal having a pulse width controlled so that the switching element is turned off in the first half or the second half of the active period of the scan line signal applied to the same liquid crystal cell so as to store a corresponding display state. And the voltage level selection circuit applies the same potential as the active and inactive potentials of the scan line signal. As a reference potential, in the first half and the second half of the active period of the scan line signal, a voltage level having an on-level and an off level is achieved by carrying out by applying to said drain electrode.

Another object of the present invention is to provide a liquid crystal display device using a liquid crystal cell having a memory function, wherein a plurality of substrates orthogonal to each other are provided on one inner surface of two substrates arranged to face each other via a liquid crystal layer. It has a first gate electrode and a drain electrode commonly connected to all of the plurality of pixels, has a plurality of second gate electrodes parallel to the drain electrode, and has the all pixels on the inner surface of the other substrate. A liquid crystal cell having a common common electrode, having a memory function at an intersection of the first gate electrode and the drain electrode, and a first switching element connected to the first gate electrode and the drain electrode; A liquid crystal panel having a second switching element connected to the first switching element and the second gate electrode and controlling the liquid crystal cell via a common electrode; and the first gate electrode. A data signal driving circuit for moving the scanning signal drive circuit for driving the drain electrode, the second
A voltage level generating circuit for driving the gate electrode of
As display information, an address signal indicating a vertical address of the liquid crystal cell whose display state changes according to display data, an address signal indicating a horizontal address,
And using the display data indicating the display state, the data signal driving circuit and the scanning signal driving circuit select one of the liquid crystal cells based on the address, and the voltage level generating circuit changes the display state of the liquid crystal cell. This is achieved by outputting a changeable voltage signal to the drain electrode, thereby changing the display state of the liquid crystal cell at the position where the display state has changed.

It is another object of the present invention to control one of the liquid crystal cells by the data signal drive circuit, the scan signal drive circuit, and the voltage level selection circuit, and to control the scan signal drive circuit to specify the address in the vertical direction. An active signal of a scan line signal is applied to a second gate electrode corresponding to a signal, and the data signal driving circuit applies a selected liquid crystal cell to a gate electrode corresponding to an address signal designating the horizontal address. A voltage whose pulse width is controlled so that the switching element is turned off in the first half or the second half of the active period of the scan line signal applied to the same liquid crystal cell so as to store a display state according to display data. A level control signal is applied, and the voltage level generating circuit adjusts the active and inactive potentials of the scanning line signal. As a reference potential the potential, in the first half and the second half of the active period of the scan line signal, a voltage level having an on-level and an off level is achieved by carrying out by applying to said drain electrode.

Further, the object is that the display information is a signal corresponding to a refresh scan for storing a display state in all liquid crystal cells in accordance with display data for one frame at a certain period. An address signal indicating a vertical address of the liquid crystal cell whose display state changes according to display data, an address signal indicating a horizontal address, and information converted into display data indicating a display state, or a CPU. This is achieved by the SRAM interface signal which is an interface signal between the SRAM and the SRAM, and the liquid crystal cell having the memory function is a liquid crystal cell formed of a ferroelectric liquid crystal.

More specifically, the present invention relates to a liquid crystal display device comprising: a plurality of common electrodes and a gate electrode which are orthogonal to each other; To form a plurality of drain electrodes parallel to
A liquid crystal cell having a memory function and a switching element are formed at the intersection, and all the switching elements are formed of, for example, a thin film transistor. The drain of the thin film transistor is connected to the drain electrode. A voltage level that determines the state of the cell is applied, and the source of the thin film transistor is connected to one of the liquid crystal cells. The opposite side of the liquid crystal cell is connected to a common electrode. A scan line signal for selecting one of the scan lines is applied, the gate of the thin film transistor is connected to the gate electrode, and the gate electrode selects any of the liquid crystal cells from liquid crystal cells arranged in a horizontal direction, A flat panel to which a voltage level control signal for controlling a voltage level applied to the liquid crystal cell is applied. A display, wherein the thin film transistor, the potential difference between the voltage applied to the gate electrode and the common electrode becomes the the on state exceeds a certain predetermined value,
A liquid crystal display device in which the liquid crystal cell is turned off when the value is smaller than the specified value and the liquid crystal cell is applied with a potential difference between voltages applied to the drain electrode and the common electrode when the thin film transistor is turned on. A signal indicating a vertical address of the liquid crystal cell, a signal indicating a horizontal address, and display data corresponding to a display state are used as interface signals between the system and the liquid crystal display device. The display state is changed by turning on only the thin film transistor connected to the liquid crystal cell whose display state changes according to the display state.

Further, according to the present invention, the display control of the liquid crystal display device for changing the display state is performed by turning on only the thin film transistor connected to the liquid crystal cell whose display state changes according to the display data. Applying a scan line signal active indicating a scan line to a common electrode of a liquid crystal cell corresponding to a signal indicating a vertical address, and applying a scan line signal applied to the same liquid crystal cell to a drain electrode. The same potential as the potential of the scan line signal is used as the reference potential, and a voltage level having an on level and an off level is applied in the first half and the second half of the active period of the scanning line signal, and the signal for specifying the address in the horizontal direction is applied. The same liquid crystal is stored in the gate electrode of the corresponding liquid crystal cell so that the display state corresponding to the display data of the selected liquid crystal cell is stored. The first half of the active period of the scan line signal applied to Le, or, as the thin film transistor is turned off later, and performs by applying a voltage level control signal having a controlled pulse width.

Further, according to the present invention, a drain electrode and a first gate electrode which are common to all of a plurality of pixels which are orthogonal to each other are provided on one inner surface of two substrates disposed to face each other with a liquid crystal layer interposed therebetween.
And a plurality of second gate electrodes parallel to the drain electrode, a common electrode common to all pixels is formed on the inner surface of the other substrate, and all pixels have two switching elements and a liquid crystal having a memory function. And two switching elements of the pixel are, for example, a first thin film transistor and a second thin film transistor, a gate of the first thin film transistor is connected to a first gate electrode, and a drain of the first thin film transistor is A drain electrode common to all pixels is connected, a source of the first thin film transistor is connected to a drain of the second thin film transistor,
The gate of the thin film transistor is connected to the second gate electrode, the drain of the second thin film transistor is connected to the common electrode via the liquid crystal cell, and a voltage level that determines the state of the liquid crystal cell is applied to the drain electrode. A scanning line signal for selecting one scanning line from a plurality of scanning lines arranged in the vertical direction is applied to the gate electrode, and a first gate electrode is selected from liquid crystal cells arranged in the horizontal direction.
An arbitrary liquid crystal cell is selected, a voltage level control signal for controlling a voltage level applied to the liquid crystal cell is applied, an active voltage is applied to a gate of the first thin film transistor by a first gate electrode, and a second thin film transistor is applied. When an active voltage is applied to the gate of the first thin film transistor by the second gate electrode, the first thin film transistor and the second thin film transistor are turned on, and the first thin film transistor and the second thin film transistor are turned on.
When the thin film transistor is turned on at the same time, the liquid crystal cell is a liquid crystal display device to which a potential difference between voltages applied to a drain electrode and a common electrode is applied, and a vertical address of the liquid crystal cell whose display state changes according to display data. , A signal indicating a horizontal address, and display data corresponding to the display state are used as interface signals between the system and the liquid crystal display device, and the display state changes according to the display data. The display state is changed by simultaneously turning on only the first thin film transistor and the second thin film transistor connected to the liquid crystal cell.

Further, according to the present invention, the display state is changed by simultaneously turning on only the first thin film transistor and the second thin film transistor connected to the liquid crystal cell whose display state changes according to display data. The display of the liquid crystal display device is controlled by applying an active scan line signal indicating a scan line to a second gate electrode of a pixel corresponding to a signal indicating a vertical address, and applying a scan line signal of a scan line signal to a drain electrode. In the first half and the second half of the active period, a voltage level having an ON level and an OFF level is applied, and a display corresponding to the display data of the selected pixel is applied to the first gate electrode of the pixel corresponding to the horizontal address. In order to memorize the state, the first thin film transistor is provided in the first half or the second half of the active period of the scan line signal applied to the same pixel. There so turned off, and applying a voltage level control signal having a controlled pulse width.

Further, the present invention is characterized in that, for example, a liquid crystal cell composed of a ferroelectric liquid crystal is used as the liquid crystal cell having the memory function.

The present invention also acts as a central control, performs calculations, logic, and determination of effectiveness, and provides input devices, output devices,
And a central processing unit that transmits signals to and from the storage device, a storage device used for storing commands and data, an input device for inputting information to the information device, and from the inside of the information device to the outside. In an information device including a liquid crystal display device including an output device for outputting information, a liquid crystal display device having the above-described configuration is used as the liquid crystal display device.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a liquid crystal display and a method of driving the same according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram for explaining a pixel structure of the liquid crystal display device according to the first embodiment of the present invention, FIG. 3 is a timing chart for explaining a driving method of the liquid crystal display device shown in FIG.
4 is a block diagram showing the configuration of the scanning signal driving circuit in FIG. 1, FIG. 5 is a timing chart illustrating the operation of the scanning signal driving circuit shown in FIG. 4, and FIG. 6 shows the configuration of the data signal driving circuit in FIG. FIG. 7 is a block diagram, and FIG. 7 is a timing chart for explaining the operation of the data signal drive circuit shown in FIG. 1, 4 and 6, reference numeral 102 denotes a voltage level selection circuit; 104, a voltage level generation circuit;
1, 601 and 602 are latch circuits, 402 is a control signal generator, 403 and 604 are output channel selectors, 40
Reference numerals 4 and 605 denote output control circuits, 405 and 606 denote output buffers, 603 denotes a data pulse conversion circuit, and other symbols are the same as those in FIG.

The liquid crystal display device according to the first embodiment of the present invention shown in FIG. 1 includes a liquid crystal cell having a memory function, for example, a liquid crystal cell using a ferroelectric liquid crystal material, and a switching element, for example, an N-type. It is configured to have pixels composed of MOS transistors. In each MOS transistor, the gate is connected to the gate electrode of the vertical pixel common gate, the drain is connected to the drain electrode common to the horizontal direction, and the source is connected to the common pixel of the horizontal pixel on the opposite side via the liquid crystal cell. Are connected. A voltage level control signal (Vx1, Vx2,...) Output from the data signal drive circuit 101 is output to the gate electrode, and a voltage level signal (Vd1, Vd2,...) Output from the voltage level selection circuit 102 is output to the drain electrode. .), The common electrode is provided with the scanning line signals (Vy1, Vy2,
・ ・) Is applied.

On the other hand, the peripheral circuits include a data signal driving circuit 101 for outputting a voltage level control signal, a voltage level selecting circuit 102 for outputting a voltage level, a scanning signal driving circuit 103 for outputting a scanning line signal, And a voltage level generating circuit 104 that outputs a voltage waveform (Vlev) as a reference. Further, the voltage level selection circuits 102 (voltage level selection circuits 1 to n) are provided in the same number as the scanning lines corresponding to the scanning lines, and are selected by the scanning line signals.

As the interface signal 105 between the liquid crystal display device and the system shown in FIG. 1, a signal indicating a vertical address of a pixel whose display state changes according to display data and a horizontal address are indicated. signal,
And an interface signal containing display data. This interface signal is, for example, an SRAM interface signal between a CPU and a general-purpose SRAM.
It may be an interface signal. The SRAM interface signal transferred from the system includes an address signal indicating a display position in the horizontal direction and the vertical direction, a display data signal, and a drawing access signal, and is transferred to the data signal driving circuit 101 and the scanning signal driving circuit 103. Is done. The control signal and the latch signal 106 generated by the scanning signal driving circuit are transferred to the data signal driving circuit 101 and the voltage level generating circuit 104.

Next, a data signal driving circuit 101, a voltage level selection circuit 102, a scanning signal driving circuit 103, and
The operation of voltage level generating circuit 104 will be described with reference to the timing chart shown in FIG.

The SR used in the first embodiment of the present invention
The AM interface signal is shown in FIG.
As shown as (x direction) and AD (y direction), only when there is a change in the display data, the position (address) of the liquid crystal cell having the change in the display data and the display data to be written in the liquid crystal cell are shown. It is a signal to have. The position of the liquid crystal cell whose display data is changed is determined by the horizontal address AD (x
Direction) and a vertical address AD (y direction). The signal of the SRAM interface shown in FIG. 3 is a signal for rewriting the third liquid crystal cell in the horizontal direction and the fourth liquid crystal cell in the vertical direction to display data 0. Hereinafter, the operation in this case will be described.

When the scanning signal drive circuit 103 shown in FIG. 1 receives a signal of the vertical address AD (y direction),
The scanning line signal V applied to the fourth scanning line in the vertical direction
y4 is output as a “low” level for a certain period. During the period when the scanning line signal Vy4 is at the “low” level,
The SRAM interface signal is equal to the period required to transfer data of one liquid crystal cell, and
The timing of changing to the “low” level is synchronized with the rise of the control signal 106 generated by the scanning signal drive circuit 103. At this time, the scanning signal driving circuit 103
Outputs a "high" level scanning line signal to all scanning lines other than those specified by the vertical address AD (y direction).

The data signal drive circuit 101 sets the voltage level control signal Vx applied to the drain electrode corresponding to the horizontal address AD (x direction) transferred from the system to the "high" level. Output. For example, in this case, since the horizontal address AD (x direction) is “3”, the voltage level control signal Vx3 is output as “high” level. The timing when the voltage level control signal changes to the “high” level is synchronized with the rise of the control signal 106 output from the scanning signal driving circuit 103, and the timing when the scanning line signal Vy4 output from the scanning signal driving circuit 103 falls Is the same as At this time, the data signal drive circuit 101 outputs a voltage level control signal other than the voltage control signal Vx3 specified by the address AD (x direction) as a “low” level. During a period in which the data signal driving circuit 101 applies a “high” level voltage to the voltage control signal Vx3, the display data (DA
TA), and the voltage level Vd4 at the timing when the voltage level control signal Vx3 falls causes the liquid crystal cell 34 having a memory function (not shown in FIG. 1, but below the liquid crystal cell 33 in FIG. 1). The state of the positioned liquid crystal cell) will be determined.

The voltage level Vd4 to be applied to the drain electrode of the pixel 34 is the voltage output from the voltage level generating circuit 104 when Vy4, which is a select signal to the voltage level selecting circuit 4, is low. Output level Vlev. The voltage level Vlev generated by the voltage level generation circuit 104 is based on the control signal 106 output from the scanning signal driving circuit 103, and is set to a value within the period in which the scanning line signal Vy4 output from the scanning signal driving circuit 103 is at the "low" level. For example, a voltage waveform in which the first half is at a “low” level and the second half is at a “high” level is generated and output to the voltage level selection circuit 102. On the other hand, the other voltage level selection circuits 1, 2, 3, 5,...
Since Vy2, Vy3, Vy5,... Are at the "high" level, the voltage level Vlev of the voltage level generation circuit 104 is not selected, and the "high" level voltage is changed to the voltage level (Vd1, Vd1).
d2, Vd3, Vd5,...).

In the case of a ferroelectric liquid crystal as a liquid crystal cell having a memory function used in the embodiment of the present invention, when a positive voltage exceeding a certain threshold voltage is applied, a bright state is stored and a certain threshold voltage is stored. When a negative voltage exceeding the voltage is applied, the dark state is stored. Therefore, the first "low" period of the voltage level Vlev output from the voltage level generation circuit 104 corresponds to the display data DATA "0",
This is a voltage level for storing a dark state, and the latter “high” period corresponds to the display data DATA′1 ”and is a voltage level for storing a bright state.

In the example described, the voltage level control signal Vx3 output from the data signal drive circuit 101 corresponds to the display data DATA '0', so that the voltage level control signal Vx3 is applied so that a negative voltage is applied to the liquid crystal cell. Since Vx3 falls during the "low" period of Vd4, it is controlled to the "high" level and output during the toff period. Also, the display data DATA
Is "1", the scan line signal Vy of the scan signal drive circuit is at the "low" level and the voltage level Vd is at the voltage level during the "high" period so that a positive voltage is applied to the liquid crystal cell. The control signal Vx changes from “high” level to “low”
A 'high' level is output to the voltage level control signal Vx only for the period of ton so that it falls to the level.

The operation of the data signal driving circuit 101, the voltage level selection circuit 102, the scanning signal driving circuit 103, and the voltage level generating circuit 104 as described above causes the common of the NMOS transistors connected to the liquid crystal cell 34 to operate. The low level of the scan line signal Vy4 output from the scan signal drive circuit 103 is applied to the electrode.
Further, since the “high” level of the voltage level control signal Vx3 output from the data signal drive circuit 101 is applied to the gate electrode, the NMOS transistor is turned on, and the voltage level Vd4 output from the voltage level selection circuit 4 is output. Is applied to the liquid crystal cell 34. After the toff period, the voltage level control signal Vx3 changes to the “low” level, so that the NMOS transistor is turned off. Therefore, the voltage finally applied to the liquid crystal cell 34 becomes a negative voltage Voff exceeding a certain threshold voltage, and the dark state (transmittance, small) is stored in the liquid crystal cell 34. .

Similarly, the next SRAM interface signals are AD (x direction) '7', AD (y direction) '2',
And, since the display data '1' is transferred,
The low level of the scanning line signal Vy2 output from the scanning signal driving circuit 103 is applied to the common electrode of the NMOS transistor connected to the liquid crystal cell 72. In addition, since the voltage level control signal Vx7 output from the data signal drive circuit 101 is applied to the gate electrode at the “high” level, the NMOS transistor is turned on and the voltage level output from the voltage level selection circuit 2 is output. Vd2 is applied to the liquid crystal cell 72. In this case, since the display data DATA is “1”, after the period of ton,
The voltage level control signal Vx7 changes to 'low' level,
The NMOS transistor is turned off. Therefore, the voltage finally applied to the liquid crystal cell 72 becomes a positive voltage Von exceeding a certain threshold voltage, and the liquid crystal cell 72 stores a bright state (transmittance, large). .

As described above, by using the address signal AD and the data signal DATA, which are transferred as the SRAM interface signal, it is possible to perform the NMO only on the portion of the entire screen where the display is rewritten, instead of the refresh scan.
It can be selected by the S transistor and can be rewritten.

Next, the configuration and operation of the scanning signal driving circuit 103 will be described with reference to FIGS.

As shown in FIG. 4, the scanning signal driving circuit 10
3 is a latch circuit 401, a control signal generator 402, an output channel selector 403, an output control circuit 404, and
An output buffer 405 is provided.

The scanning signal drive circuit 103 configured as described above includes a vertical address signal AD (y direction) included in the SRAM interface signal, an access signal CS as a drawing access signal, and a write enable signal WE. Are input at the timing shown in FIG. As for the input signal, the address signal and the data signal when the access signal CS is at the “low” level are valid data. Also, the write enable signal WE is 1
In the period in which the address data of one pixel is transferred, it is at the “low” level for a certain period. The drawing access signal (CS, WE) is input to the control signal generation unit 402,
The control signal generator 402 generates and outputs a latch signal and a control signal at the timing shown in FIG. The latch signals are CS and WE, which are drawing access signals.
By taking the NOR logic of the above, it can be easily generated. Further, the control signal shifts the latch signal, and the rising edge of the control signal causes the display data DAT to rise.
A is a signal that allows A to be latched.

Vertical address signal AD (y direction)
Is input to the latch circuit 401 and the control signal generation unit 40
2 is latched at the timing of the rising edge of the latch signal output. The address signal ADY held by the latch circuit 401 is input to the output channel selector 403, and the output channel selector 403 connects one terminal corresponding to ADY in synchronization with the rise of the control signal output from the control signal generation unit 402. A selection signal is output to one of the terminals B1 to Bn so as to make a selection. The output control circuit 404
In response to the selection signal output by the output channel selector 403, a signal of low level is output to a terminal corresponding to the address ADY in the vertical direction in synchronization with the rise of the control signal for a certain period. The period during which the output control circuit 404 outputs the “low” level is adjusted so as to be the same as the period during which the SRAM interface signal outputs the address signal for one pixel. Then, finally, the output buffer 405 adjusts the output of the output control circuit to the potentials of the “high” level and the “low” level of the scanning line signal, and outputs the potentials to the output terminals Vy1 to Vyn.

Next, the configuration and operation of the data signal drive circuit 101 will be described with reference to FIGS.

As shown in FIG. 6, the data signal driving circuit 1
Reference numeral 01 includes latch circuits 601 and 602, a data pulse conversion circuit 603, an output channel selector 604, an output control circuit 605, and an output buffer 606.

The data signal drive circuit 101 configured as described above includes a horizontal address signal AD (x direction) and display data DATA included in the SRAM interface signal, and a latch signal output by the scan signal drive circuit 103. , Control signals are input at the timing shown in FIG. The horizontal address signal AD (x direction) is input to the latch circuit 601 and is latched by the latch circuit 601 at the timing of the rising edge of the latch signal. The address signal ADX held by the latch circuit 601 is input to the output channel selector 604,
Reference numeral 4 outputs a selection signal to one of the terminals A1 to An so as to select one terminal corresponding to ADX in synchronization with the rise of the control signal.

The latch circuit 602 latches the display data DATA in synchronization with the rise of the control signal. The display data D held by the latch circuit 602 is input to the data pulse conversion circuit 603. The data pulse conversion circuit 603 rises to the “high” level in synchronization with the rise of the control signal, and outputs the “high” level only for the period of toff when the display data D is “0”. In the case of ', a signal which becomes'high' level only for the period of ton is output. The output control circuit 605 supplies an output pin corresponding to the address signal D to one of the selection signals A1 to An output from the output channel selector 604,
Outputting the signal generated by the data pulse conversion circuit 603;
A low-level signal is output to the other output pins. Finally, the output buffer 606 adjusts the output of the output control circuit 605 to the “high” level and the “low” level of the voltage level control signal, and outputs V
x1 to Vxn signals are output.

As described above, the liquid crystal display device according to the first embodiment of the present invention uses the SRAM interface signal and has the structure of the liquid crystal display device using the liquid crystal cell having a memory function as shown in FIG. By doing
Instead of a method in which the entire screen is rewritten and displayed at a fixed cycle as in the case of refresh scanning, a liquid crystal display device that rewrites only a portion requiring rewriting can be easily realized. Thus, the first embodiment of the present invention described above does not rewrite the entire screen by refresh scanning, but selects only a portion where the display data changes and writes the changed display data to display a still image or the like. When a display pattern in which data hardly changes is displayed, the number of pixels to which a voltage is applied can be greatly reduced, and low power consumption can be realized.

In the first embodiment of the present invention described above, the waveform of the voltage level Vlev is rectangular, but the present invention is not limited to this, and the voltage level Vle
v and the time of the “high” level of the voltage level control signal Vx
By adjusting ton and toff, when the MOS transistor is finally turned off, there is no problem if the liquid crystal cell having the memory function is adjusted so that it can clarify which state is stored. Can be applied. In the embodiment of the present invention, a ferroelectric liquid crystal is used as a liquid crystal cell having a memory function.
The present invention provides a similar liquid crystal display device using another liquid crystal cell having a memory function by adjusting the voltage level Vlev and the time "ton" and toff of the "high" level of the voltage level control signal Vx. It is also possible to configure.

The above-described liquid crystal display device according to the first embodiment of the present invention can be manufactured by using an amorphous silicon TFT which is currently widely used. In order to enhance the performance, it is also possible to use a low-temperature polysilicon TFT capable of integrally forming a peripheral circuit and a pixel.

FIG. 8 is a view for explaining the pixel structure of the liquid crystal display device according to the second embodiment of the present invention, and FIG. 9 is a view for explaining the second embodiment of the present invention.
10 is a timing chart illustrating an interface signal from the system in the embodiment, FIG. 10 is a block diagram illustrating a configuration of the conversion circuit in FIG. 8, and FIG. 11 is a timing chart illustrating the operation of the conversion circuit illustrated in FIG. A liquid crystal display according to a second embodiment of the present invention will be described with reference to FIGS. 8 and 1
At 0, 802 is a conversion circuit, 1001 and 1002 are counter circuits, 1003 is an inversion circuit, and 1004 to 100
Reference numeral 6 denotes a latch circuit, 1007 denotes an adder, and other symbols are the same as those in the first embodiment.

The liquid crystal display device according to the second embodiment of the present invention uses the C signal as an interface signal from the system.
A refresh scanning signal widely used in a display device such as an RT is used, and in this case, rewriting is performed only in a pixel portion where display data changes. Therefore, in the liquid crystal display device according to the second embodiment of the present invention, as shown in FIG. 8, the interface signal 801 corresponding to the refresh scan transferred from the system is changed by the conversion circuit 802 to the pixel whose display data changes. Horizontal address signal AD (x direction), vertical address signal AD (y direction), data signal DA
It is configured and realized so as to be converted into TA and drawing access signals (CS and WE). Therefore, the liquid crystal display device according to the second embodiment of the present invention shown in FIG. 8 receives the interface signal 801 based on the refresh scanning signal as described above, and converts the interface signal 801 into data corresponding to the changed pixel by the conversion circuit 802. Since the signal processing can be performed as in the case of the first embodiment of the present invention described above, the configuration may be the same. Therefore, only the operation of the interface signal 801 and the conversion circuit 802 will be described below.

The interface signal 802 from the system used in the second embodiment of the present invention shown in FIG.
The vertical synchronizing signal V that becomes effective once every frame period
SYNC (not shown), a horizontal synchronizing signal HSYNC that is enabled once in one scanning period, and a display timing signal DTM that is at a “high” level during a period in which display data is effective.
G, display data DATA, and clock signal DCLK
Which is an interface signal used in a display device that requires normal refresh scanning. The display data change signal DCH, which is another interface signal used in the second embodiment of the present invention, has a high level when the display data of a certain pixel is different from the display data of the previous frame. Signal. For example, the display data change signal DCH is stored in the memory of the system when the display data of one frame previously transferred is stored in the memory of the system and the display data of the next frame is transferred. Compared with the displayed data,
If the display data change signal DCH is different, the display data change signal DCH is output as a “high” level.

Next, the configuration and operation of the conversion circuit 802 will be described with reference to FIGS.

The conversion circuit 802, as shown in FIG.
For example, counter circuits 1001 and 1002, inverting circuit 1
003, latch circuits 1004, 1005, 1006, adder 1007, and drawing access signal generator 1008
Consists of

In the conversion circuit 802 shown in FIG. 10, the counter circuit 1001 is reset to “0” when the vertical synchronizing signal VSYNC becomes “high” level, and is synchronized with the rising of the display timing signal DTMG.
The disp timing signal DTMG is counted up. Therefore, the output of the counter circuit 1001 shown in FIG.
The count data YCNT shown in FIG.
ATA indicates the vertical address of the pixel being transferred. The latch circuit 1004 is a counter circuit 1
By latching the count data YCNT of 001 at the rising edge of the display data change signal DCH, the vertical address AD (y direction) of the pixel portion where the display data changes can be output.

On the other hand, the counter circuit 1002 uses the horizontal synchronization signal HSYNC as a reset signal and
It is reset to '0' at the falling edge of CLK. Thereafter, the counter circuit 1002 uses the display timing signal DTMG as a count enable signal, and counts up the clock signal DCLK in synchronization with the fall of the clock signal DCLK while DTMG is at the “high” level. Therefore, data obtained by adding “1” to the count data XCNT of the counter circuit 1002 by the adder 1007 indicates the horizontal address of the pixel to which the display data is currently being transferred. Therefore, the latch circuit 1005 outputs the counter data X of the counter circuit 1002 in synchronization with the rise of the display data change signal DCH.
By latching the CNT, the adder 1007 can control the horizontal address AD of the pixel portion where the display data changes.
(X direction) can be output.

The latch circuit 1006 uses the display data change signal DCH as a latch enable signal,
The display data DATA is latched in synchronization with the fall of the clock signal DCLK during the period when H is at the “high” level. Thus, the conversion circuit 802 shown in FIG. 10 can output the address signal of the pixel portion where the display data changes, and can also output the changed display data CDATA at the same time. Further, the drawing access signal generator 100
Reference numeral 8 denotes an access signal CS as a drawing access signal and a write enable signal WE from the display data change signal DCH.
Generate The access signal CS is a signal obtained by inverting the display data change signal DCH, and the period during which the signal is at a “low” level is a period necessary for the system to transfer display data for one pixel (for example, the period of the clock signal DCLK). ). The write enable signal WE is a signal having a timing such that the width of the “low” level is shorter than the access signal CS and the display data CDATA output from the conversion circuit 802 can be latched at the rise of the write enable signal WE.

As described above, the liquid crystal display device according to the second embodiment of the present invention includes the conversion circuit 802 having the configuration shown in FIG. , SR
It can be converted into an address signal of the pixel section corresponding to the AM interface signal, display data, and a drawing access signal.

Thus, in the liquid crystal display device according to the second embodiment of the present invention, even if the interface signal is from a system corresponding to the refresh scan, the entire screen is displayed at a certain period as in the case of the refresh scan. It is not necessary to rewrite and display, it is possible to rewrite only the part that needs rewriting, and when displaying an image such as a still image with little change in display data, the number of pixels to which voltage is applied is greatly increased. Thus, power consumption can be reduced.

FIG. 12 is a diagram for explaining the pixel structure of the liquid crystal display device according to the third embodiment of the present invention, and FIG. 13 is a timing chart for explaining the driving method of the liquid crystal display device shown in FIG. The configuration and operation of the liquid crystal display device according to the third embodiment of the present invention will be described with reference to FIGS. The reference numerals in FIG. 12 are the same as those in FIG.

In the liquid crystal display device according to the third embodiment of the present invention, as shown in FIG.
For example, the first MOS transistor has a gate connected to a first gate electrode common to pixels in the vertical direction, a drain connected to a drain electrode for applying a voltage level common to all pixels, and a source connected to the second MOS transistor. Connected to drain. The gate of the second MOS transistor is connected to a second gate electrode common to pixels in the horizontal direction, and the source is common to all pixels via a liquid crystal cell having a memory function, for example, a liquid crystal cell using a ferroelectric liquid crystal. Connected to common electrode.

The liquid crystal display device according to the third embodiment of the present invention provides an interface signal including a pixel address signal, a display data signal, and a drawing access signal, as an interface signal from the system, for example, an SRAM. Interface signals are used. Therefore, the data signal driving circuit 10 which is a peripheral circuit
1. The scanning signal driving circuit 103 and the voltage level generating circuit 104 are the data signal driving circuit 101, the scanning signal driving circuit 103, and the data signal driving circuit 103 described in the first embodiment of the present invention.
The operation is substantially the same as the operation of voltage level generating circuit 104, and the description is omitted here. However, the voltage level generating circuit 104 included in the liquid crystal display device shown in FIG. 12 according to the third embodiment of the present invention outputs the common voltage Vcom together with the voltage level Vlev. Further, the scanning signal driving circuit 103 includes:
A scan line which has the opposite polarity and has a 'high' level when a scan line is selected in order to apply an on-voltage as a scan line signal Vy to the gate of the second MOS transistor connected to the second gate electrode when the scan line is selected. Signal is being output.

Referring to FIG. 13 for explaining the operation of the liquid crystal display device according to the third embodiment of the present invention, the address signals transferred from the system are AD (x direction) '3', AD
(Y direction) It is assumed to be '4'. First, the scanning signal driving circuit 103 applies Vy4 to the second gate electrode in accordance with the address.
Is applied. Thus, the second MOS transistor on the fourth scanning line in the vertical direction is turned on. Further, the data signal driving circuit 101 applies Vx3 to the first gate electrode corresponding to the address. As a result, the first MOS transistor on the third column in the horizontal direction is turned on.

The address signal AD (x
Direction) and AD (y direction), the first and second MOS transistors are turned on only in the pixel portion corresponding to the pixel direction, and the voltage level Vlev generated by the voltage level generation circuit 104 is applied only to the liquid crystal cell 34. Become. At this time, since the display data of the pixel portion including the liquid crystal cell 34 is “0”,
The data signal driving circuit 101 includes a voltage level control signal Vx3
Of the liquid crystal cell 34 at the timing when the first MOS transistor is turned off.
Is adjusted so as to be a voltage Voff of negative polarity. As a result, the liquid crystal cell 34 stores a dark state (transmittance, small) corresponding to the display data '0'.

Further, since the display data of the pixel portion including the liquid crystal cell 72 is “1”, in this case, the data signal drive circuit 101 sets the period of the “high” level of the voltage level control signal Vx7 to ton, At the timing when one MOS transistor is turned off, the voltage applied to the liquid crystal cell 72 is adjusted to be a positive voltage Von. As a result, the liquid crystal cell 72 stores a bright state (transmittance, large) corresponding to the display data '1'.

As described above, the liquid crystal display device according to the third embodiment of the present invention uses the SRAM interface signal and employs a liquid crystal cell having a memory function as shown in FIG. By doing so, it is possible to easily realize a liquid crystal display device that rewrites only the parts that need to be rewritten, instead of the method of rewriting the entire screen at a certain cycle and displaying as in the case of refresh scanning. Becomes Thus, in the third embodiment of the present invention described above, instead of rewriting the entire screen by refresh scanning, it is only necessary to select only the portion where the display data changes and write the changed display data. When a display pattern in which the display data hardly changes is displayed, the number of pixels to which a voltage is applied can be greatly reduced, and power consumption can be reduced.

Further, in the liquid crystal display device according to the third embodiment of the present invention, by using the conversion circuit 802 described in the second embodiment of the present invention, the interface signal from the system can correspond to the refresh scan. Even when a signal is used, a liquid crystal display device in which only a pixel portion that needs rewriting can be rewritten can be easily realized.

In the third embodiment of the present invention, as in the case of the first embodiment of the present invention, the waveform of the voltage level Vlev is rectangular, but the present invention is not limited to this. However, by adjusting the time ton and toff of the "high" level of the voltage level Vlev and the voltage level control signal Vx, when the MOS transistor is finally turned off, the liquid crystal cell having the memory function can be controlled. It can be applied without any problem if it is adjusted so as to clarify whether to store the state. In the embodiments of the present invention, the ferroelectric liquid crystal is used as the liquid crystal cell having the memory function. However, the present invention is applied to the case where the above-described voltage level Vlev and the high-level time of the voltage level control signal Vx are used. By adjusting ton, toff, and the like, it becomes possible to configure a similar liquid crystal display device using another liquid crystal cell having a memory function.

The above-described liquid crystal display device according to the third embodiment of the present invention can be manufactured using an amorphous silicon TFT which is widely used at present. In order to enhance the performance, it is also possible to use a low-temperature polysilicon TFT capable of integrally forming a peripheral circuit and a pixel.

FIG. 14 is a block diagram showing the configuration of an information device configured using the liquid crystal display device according to the above-described embodiment of the present invention, which will be described below. FIG.
In 140, 1401 is an information device having a liquid crystal display device, 1402 is a liquid crystal display device, 1403 is a central processing unit, 1404 is an input device, 1405 is a storage device, 140
6 is an output device, and 1407 is a power supply device.

An information device 1401 shown in FIG. 14 is a liquid crystal display device according to the first to third embodiments of the present invention, that is,
This is an information device including a liquid crystal display device capable of realizing rewriting of only a pixel portion where display data changes. The information device 1401 is, for example, a computer, and includes a liquid crystal display device 1402 according to the first to third embodiments of the present invention described above, a central processing unit 1403 mutually connected via a system bus, and an input device. Device 1404, storage device 1405, output device 1406, and power supply circuit 14
07.

The central processing unit 1403 acts as a central control unit, makes calculations, logics, and execution decisions, and controls signal transmission between the input unit 1404, the output unit 1406, and the storage unit 1405. I do. The storage device 1405 is used for storing commands and data, and the input device 1404 is a keyboard, a mouse, and the like, and inputs necessary information to a computer. The input information may be data or a program. The output device 1406 may be an auxiliary storage device such as a printer, a magnetic tape, or a magnetic disk. The output device 1406 may write internal data of a computer to a printer or store the data in an auxiliary storage device, such as a magnetic tape or a magnetic disk. I do. The power supply circuit 1407 is
Power is supplied to the liquid crystal display device 1402 and other components of the information device 1401 that require power.

In the information device 1401 described above, the central processing unit 1403 includes a signal indicating a horizontal address, a signal indicating a vertical address of a pixel portion where display data changes, and display data such as a general-purpose SRAM. The display is controlled by inputting the interface signal to the liquid crystal display device 1402 described in the first embodiment of the present invention or the third embodiment of the present invention. Can be performed.

In the information device 1401 described above,
An interface signal corresponding to the refresh scan output by the output device 1406, for example, a display data signal, and a horizontal synchronization signal that is enabled once in one horizontal period, and is enabled once in one frame period. By inputting an interface signal including a vertical synchronization signal, a clock signal, and a display timing signal indicating a range of valid display data to the liquid crystal display device 1402 described as the second embodiment of the present invention, It is possible to realize an information device with reduced power consumption.

The information device configured as shown in FIG. 14 includes the liquid crystal display device described above as the display device according to the first to third embodiments of the present invention, thereby reducing the power consumption of the information device. A large effect can be obtained by applying the present invention to a portable information terminal device such as a notebook personal computer or an electronic organizer, which further requires lower power consumption among information devices.

[0071]

As described above, according to the present invention, in a liquid crystal display device using a liquid crystal cell having a memory function, as an interface signal from a system, an address signal of a pixel portion where display data changes and a display data are displayed. By using signals and interface signals including drawing access signals, it is only necessary to select the pixels that need rewriting and rewrite the display.Therefore, when displaying a still image or an image with many still parts, a voltage must be applied. The number of pixels that must be reduced can be significantly reduced, and low power consumption can be realized.

Further, according to the present invention, even if the interface signal transferred from the system is a signal corresponding to the refresh scan, the display data change signal DCH and those signals are converted into the address signal corresponding to the SRAM interface signal, By using a conversion circuit for converting a display data signal and a drawing access signal, it is possible to select only pixels that need rewriting and drive to rewrite display, thereby realizing low power consumption.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a pixel structure of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a pixel structure of a conventional liquid crystal display.

FIG. 3 is a timing chart illustrating a driving method of the liquid crystal display device shown in FIG.

FIG. 4 is a block diagram illustrating a configuration of a scanning signal driving circuit in FIG. 1;

FIG. 5 is a timing chart illustrating an operation of the scanning signal drive circuit shown in FIG.

FIG. 6 is a block diagram illustrating a configuration of a data signal driving circuit in FIG. 1;

FIG. 7 is a timing chart illustrating the operation of the data signal drive circuit shown in FIG.

FIG. 8 is a diagram illustrating a pixel structure of a liquid crystal display according to a second embodiment of the present invention.

FIG. 9 is a timing chart illustrating interface signals from a system according to a second embodiment of the present invention.

FIG. 10 is a block diagram illustrating a configuration of a conversion circuit in FIG. 8;

FIG. 11 is a timing chart illustrating the operation of the conversion circuit shown in FIG.

FIG. 12 is a diagram illustrating a pixel structure of a liquid crystal display according to a third embodiment of the present invention.

13 is a timing chart illustrating a driving method of the liquid crystal display device shown in FIG.

FIG. 14 is a block diagram illustrating a configuration of an information device configured using the liquid crystal display device according to the embodiment of the present invention.

[Explanation of symbols]

11 to 33 liquid crystal cell 101 data signal drive circuit 102 voltage level selection circuit 103 scan line signal drive circuit 104 voltage level generation circuit 401, 601, 602, 1004 to 1006 latch circuit 402 control signal generation unit 403, 604 output channel selector 404, 605 Output control circuit 405, 606 Output buffer 603 Data pulse conversion circuit 802 Conversion circuit 1001, 1002 Counter circuit 1003 Inversion circuit 1007 Adder 1401 Information equipment 1402 Liquid crystal display device 1403 Central processing unit 1404 Input device 1405 Storage device 1406 Output device

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G09G 3/36 G02F 1/137 510 (72) Inventor Yasuyuki Kudo 1099 Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Hitachi, Ltd. System Development Laboratory (72) Inventor Toshio Miyazawa 3300 Hayano, Mobara-shi, Chiba Hitachi, Ltd. Display Group (72) Inventor Yoshiro Mikami 1-1-1, Omika-cho, Hitachi City, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. Within Hitachi Research Laboratory (72) Inventor Hajime Akimoto 1-280 Koigakubo, Kokubunji-shi, Tokyo F-term (reference) 2H088 EA13 JA17 MA10 MA20 2H093 NA15 NA16 NC02 NC11 NC32 ND39 NF17 5C006 AA02 AF31 AF44 AF52 BA11 BB16 BC03 BC12 BC20 BF04 BF16 BF22 BF24 BF26 BF27 BF28 BF43 FA47 5C080 AA10 BB05 DD26 EE17 FF11 JJ02 JJ04 5C094 AA22 BA03 BA09 BA49 CA19 EA03 EA04 EA07 GA10

Claims (6)

[Claims] In a liquid crystal display device using a liquid crystal cell having a memory function, a plurality of common electrodes and gates orthogonal to each other are formed on one inner surface of two substrates arranged to face each other with a liquid crystal layer interposed therebetween. Having an electrode, and having a plurality of drain electrodes parallel to the common electrode,
A liquid crystal panel having a memory function at the intersection of a common electrode and a gate electrode, and a liquid crystal panel having a switching element connected to the gate electrode and the drain electrode and controlling the liquid crystal cell via a common electrode; and driving the gate electrode A data signal driving circuit, a scanning signal driving circuit for driving the common electrode, and a voltage level selection circuit for driving the drain electrode, wherein the liquid crystal cell changes a display state according to display data as display information. Using an address signal indicating a vertical address, an address signal indicating a horizontal address, and display data indicating a display state, the data signal driving circuit and the scanning signal driving circuit use a liquid crystal based on the address. Selecting one of the cells, and the voltage level selection circuit enables the display state of the liquid crystal cell to be changed By outputting a pressure signal to the drain electrode, a liquid crystal display device characterized by changing the display state of the liquid crystal cell in a position where the display state has changed. 2. The control of one of the liquid crystal cells by the data signal drive circuit, the scan signal drive circuit, and the voltage level selection circuit corresponds to the scan signal drive circuit corresponding to an address signal designating the address in the vertical direction. An active signal of a scanning line signal is applied to a common electrode, and the data signal driving circuit applies a display state according to display data of a selected liquid crystal cell to a gate electrode corresponding to an address signal indicating the horizontal address. So that the switching element is turned off in the first half or the second half of the active period of the scan line signal applied to the same liquid crystal cell, so that a voltage level control signal with a controlled pulse width is applied, The voltage level selection circuit, the same potential as the active and inactive potential of the scan line signal as a reference potential, 2. The method according to claim 1, wherein the driving is performed by applying a voltage level having an on level and an off level to the drain electrode in the first half and the second half of the active period of the scan line signal. . 3. A liquid crystal display device using a liquid crystal cell having a memory function, wherein a plurality of first gates orthogonal to each other are provided on one inner surface of two substrates arranged to face each other with a liquid crystal layer interposed therebetween. An electrode and a drain electrode commonly connected to all of the plurality of pixels; a plurality of second gate electrodes parallel to the drain electrode; and a common electrode common to all pixels on the inner surface of the other substrate. A liquid crystal cell having a memory function at an intersection of the first gate electrode and the drain electrode, a first switching element connected to the first gate electrode and the drain electrode, and a first switching element A liquid crystal panel having a second switching element connected to the second gate electrode and controlling the liquid crystal cell via a common electrode, and a data signal for driving the first gate electrode A driving circuit, a scanning signal driving circuit for driving the drain electrode, and a voltage level generating circuit for driving the second gate electrode;
An address signal indicating a vertical address of the liquid crystal cell whose display state changes in accordance with display data, an address signal indicating a horizontal address, and display data indicating a display state; The scanning signal driving circuit is one of the liquid crystal cells based on the address.
The voltage level generating circuit changes the display state of the liquid crystal cell at the position where the display state has changed by outputting a voltage signal enabling the change of the display state of the liquid crystal cell to the drain electrode. A liquid crystal display device characterized by the above-mentioned. 4. The control of one of the liquid crystal cells by the data signal drive circuit, the scan signal drive circuit, and the voltage level selection circuit, wherein the scan signal drive circuit corresponds to an address signal designating the address in the vertical direction. An active signal of a scanning line signal is applied to a second gate electrode, and the data signal driving circuit applies a scanning signal to a gate electrode corresponding to an address signal indicating a horizontal address in accordance with display data of a liquid crystal cell to be selected. To remember the display state
A voltage level control signal with a controlled pulse width is applied so that the switching element is turned off in the first half or the second half of the active period of the scan line signal applied to the same liquid crystal cell, and the voltage level generation circuit Applying a voltage level having an on level and an off level to the drain electrode during the first half and the second half of the active period of the scan line signal, using the same potential as the active and inactive potentials of the scan line signal as a reference potential. 4. The method according to claim 3, wherein the driving is performed. 5. The display information includes a signal corresponding to a refresh scan for storing a display state in all liquid crystal cells in accordance with display data for one frame at a certain cycle, according to the display data. An address signal indicating a vertical address of the liquid crystal cell whose display state changes, an address signal indicating a horizontal address, and information converted to display data indicating a display state, or a CPU.
4. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is an SRAM interface signal which is an interface signal between the SRAM and the SRAM. 6. The liquid crystal cell having a memory function,
6. The liquid crystal display device according to claim 1, wherein the liquid crystal cell is a liquid crystal cell composed of a ferroelectric liquid crystal.