JPH09329807A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption by writing operation for a pixel which does not require write-in by selectively driving each one or every pixel block constituted of plural pixels out of the pixels arranged in a matrix state. SOLUTION: Out of the pixels (liquid crystal cells) arranged in matrix form, an on-voltage is applied to each address line by a row address line driving circuit 12 and a pixel block address line driving circuit 13. In such a case, a picture signal from a pixel signal conductor 20 can be impressed only on the pixel where switching elements SW1 and SW2 are simultaneously turned on. In this device, a pixel block address line 22 is simultaneously applied to the switching element SW2 of every pixel in the pixel block per block unit to make it in an on-state, so that plural pixel blocks are optionally selected and the pixel of the block is controlled to be driven.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device for image display, in which a plurality of pixels are arranged in a matrix and each pixel is driven to perform display.

[0002]

2. Description of the Related Art Liquid crystal display devices are thin and lightweight and can be driven at a low voltage, and are therefore widely used in wristwatches, calculators, word processors, personal computers, small game machines and the like. Recently, the need for a pen input electronic notebook has increased, and the demand for a portable terminal (PDA) has expanded.

On the other hand, when it becomes necessary to display a plurality of images on the same screen as the progress of multimedia, it becomes necessary for a liquid crystal display device to have a large screen and high definition, and the amount of information increases. The driving frequency becomes high. Therefore, along with this, it becomes necessary to develop an IC capable of higher speed operation.

Further, as the driving frequency becomes higher, the increase in power consumption generally becomes a problem, and even if it is considered that the portable terminal (PDA) is driven by a battery, the power consumption is reduced in order to reduce the size and weight. Will be required, of course.

As a driving method of the liquid crystal display device for reducing the power consumption, for example, a technique disclosed in Japanese Patent Laid-Open No. 3-271795 has been proposed. The driving method disclosed in this publication will be referred to as a multi-field driving method here.

Conventionally, when writing an image signal in pixels arranged in a matrix, as shown in FIG. 13, a plurality of address lines arranged in the row direction are sequentially scanned from the top, and the scanned addresses are scanned. All the switching elements in one horizontal line connected to the line are turned on, and the signal from the signal line is written in the pixel electrode. In this case, the switching elements in the same row connected to the same address line are turned on, and a desired signal must be given to all the pixels arranged in the same row.

That is, when displaying the same image in the previous field and the next field, the same image signal must be supplied to the signal line. However, when it is necessary to invert the polarity as a method of driving the liquid crystal, even when the same image is displayed, the image signal whose polarity is inverted is added to the counter voltage. However, even in this case, the driving frequency can be further reduced as long as the liquid crystal does not deteriorate. Also in the multi-field driving, since one frame is composed of a plurality of sub-fields, the driving frequency is divided by the number of sub-fields for one pixel, and the speed is reduced. Also,
This greatly reduces power consumption.

On the other hand, when the display screen of the liquid crystal display device is arbitrarily divided into windows, a window is partially displayed, a moving image is displayed in this window, and a still image is displayed outside the window. For the address line provided with the pixel for displaying the area corresponding to the portion, it is necessary to increase the driving frequency originally in order to display the moving image.

However, when the conventional multi-field driving method is used, the driving frequency is lowered in the pixels for displaying a moving image, so that the occurrence of the afterimage phenomenon due to the lowered driving frequency cannot be avoided.

In recent years, the liquid crystal display device has been reduced in power consumption by lowering the driving voltage and reducing the driving frequency. Further, as a structure capable of lowering the power consumption, each pixel is A structure provided with a memory has been proposed (JP-A-58-196582 or JP-A-3).
-77922). By adopting this technique, for a still image, once a display signal is transmitted to each pixel, then that pixel may be constantly displayed by the signal held in the memory of that pixel. for that reason,
Theoretically, the power consumption is only the power consumption for polarity reversal, so that the power consumption of a still image is approaching "0" without limit.

However, in recent years, with the progress of multimedia,
The need for displaying moving images is increasing, and moreover, since the moving images are images in which pixel information changes sequentially at a high speed, even if each pixel has a memory, that memory has a high frequency. Therefore, it becomes necessary to rewrite the pixel signal. If the pixels are rewritten at such a high frequency as described above, the electric power will be significantly consumed as in the conventional case.

FIG. 1 is a schematic circuit configuration example of a liquid crystal display device.
4 shows. FIG. 14A is a block diagram showing the configuration of the main part of the liquid crystal display device. The liquid crystal display device is shown in FIG.
As shown in FIG. 1, the liquid crystal display panel 10, the signal line drive circuit 11, the gate line drive circuit 12, and the buffer circuit 13
And a common drive circuit 14 and a control signal generation circuit 15.

As shown in FIG. 14 (b), the liquid crystal display panel 10 has a plurality of minute liquid crystal display cells CEL arranged in a matrix, and each row unit is a row driving row. The scanning lines La1 and La2 to Lam are arranged, and the pixel signal lines Lb1 and Lb2 to Lbn are arranged in units of columns. In each liquid crystal display cell CEL, the switch SW is driven by the corresponding row scanning line, and the pixel SW is driven. Pixel signals from the signal lines are applied to the corresponding liquid crystal display cells CEL to display pixels.

The liquid crystal display cell CEL changes the pixel density according to the potential by applying a potential difference between the potential applied from the pixel signal line and the common power source (common power source) VCOM potential.

The common power supply VCOM is a power supply having a common potential, which is generated by the common drive circuit 14. The control signal generation circuit 15 generates various control signals necessary for the display operation and gives them to the respective parts so that the necessary operations can be performed. A switch SW is provided corresponding to each liquid crystal display cell CEL, and each switch SW is composed of a TFT (thin film transistor), and its gate terminal is a row scanning line La1 (to La2) of a corresponding row. To Lam), and on / off is controlled by a signal of the row scanning line. Further, each switch SW has a pixel signal line L of a corresponding column.
The source-drain is connected between b1 (-Lb2-Lbn) and the liquid crystal display cell CEL so that the output of the signal line drive circuit 11 can be applied to the liquid crystal display cell CEL.

The gate line drive circuit 12 sequentially supplies the row scanning line L.
This is for applying a drive signal to a1 and La2 to Lam to provide a signal to the gate of the TFT which constitutes the switch SW of each liquid crystal display cell in units of rows to drive control the switch SW.

In such a configuration, the gate line drive circuit 12 has all the row scanning lines La1 and La2 to La2 arranged in the vertical direction.
The gate line drive signals are set to G1 and G in the time period for scanning am
2, G3 to Gm in order.

Gate line drive signals G1, G2, G3, ... G
The output terminal of m corresponds to the row and the corresponding row scanning lines La1 and La2.
To Lam, and therefore, in the row scanning line in which the gate line driving signal is generated, each switch SW of the liquid crystal cells connected to that row is on / off controlled. In this way, the gate line driving circuit 12 sequentially scans each row scanning line.

On the other hand, the image signal is given to the signal line drive circuit 11 via the buffer circuit 13, and the signal line drive circuit 11 is supplied.
In order to control the state of each pixel of the row being scanned corresponding to the image signal in response to the scanning of the row scanning line, the display signal of each pixel of the row being scanned is output corresponding to each pixel. The display signals are output to the pixel signal lines Lb1 and Lb2 to Lbn arranged corresponding to the pixel positions.

In the liquid crystal panel as shown in FIG. 14B, by turning on the signal of the row scanning line, each SW of the liquid crystal cell corresponding to the row is turned on, and at the same time, from the signal line drive circuit 11 described above. By providing a display signal corresponding to each pixel of the row being scanned by such control, the display signal corresponding to the content of the display image is input through the pixel signal lines Lb1, Lb2 to Lbn, and the common drive circuit 14 A voltage having a potential difference from the applied common voltage is applied to the liquid crystal cell CEL to display pixels.

Now, let us consider what factors determine the power consumption of the drive circuit (module circuit) of the liquid crystal display device. Note that the power consumption of the bias current flowing in DC is not included in the power consumption of the module circuit.

The drive circuit of the liquid crystal display device is basically divided into a signal line drive circuit, a buffer circuit, a control signal generation circuit, a common drive circuit and a gate line drive circuit as described above. Hereinafter, each will be described in detail.

[I] Signal line drive circuit The signal line drive circuit is a drive IC for driving the signal line and can be classified into a digital type and an analog type.
Since the A image is digital, the power consumption will be examined for a digital system with good matching.

The digital driving IC is basically a shift register for determining a signal sampling time, a latch circuit for latching a digital signal, a D / A conversion circuit for converting the latched digital signal into an analog signal, and a signal. It consists of an output buffer that drives a line.

Here, the factors that determine the power consumption are the latch circuit and the output buffer, so only these two are considered.
The maximum power consumption Pl of the latch circuit is expressed by the following formula, where C _{l is the} input equivalent capacitance of the image signal, C _{CK is the} input equivalent capacitance of the sampling clock, f _s is the image sampling frequency, and V _l is the latch circuit power supply voltage. become that way.

[0026] _{P l = (C l + 2C} CK) * f s / 2 * V 2 ... (1) maximum power consumption P _ob output buffers, a signal line capacitance C _ss, the horizontal driving frequency f _h, horizontal The number of pixels is represented by N _h , and the signal line voltage is represented by V _ss as follows.

[0027] _{P ob = N h * C ss} * f h * V s 2/2 ... (2) [ii] Buffer circuit buffer circuit, signal lines and a noise removal and waveform shaping by receiving a digital signal of the input This is a part that supplies a stable signal to the drive circuit, and although it may be omitted, it is basically necessary, so consider it. The maximum power consumption P _b of the buffer circuit is C equivalent to the input equivalent capacity of the circuit related to the clock f _s.
bc , the equivalent input capacitance of the circuit relating to the image signal are represented by C _bp , and the power supply voltage of the buffer circuit is represented by V _b .

P _b = (2C _bc + C _bp ) * f _s / 2 * V _b (3) [iii] Control signal generation circuit The control signal generation circuit is basically a gate array, and an internal Although the frequencies are different, the power consumption mainly related to the image sampling clock f _s is considered to be an important factor. The maximum power consumption P _ga of the entire gate array is C _gac which is the equivalent internal capacitance of the circuit regarding the clock f _s, and C which is the input equivalent capacitance of the circuit regarding the image signal.
_{The gap} and the power supply voltage of the gate array are represented by V _ga as follows.

[0029] _{P ga = (2C gac + C} gap) * f s / 2 * V ga 2 ... (4) [iv] common drive circuit common drive circuit is a dispute for driving the common capacitance C _c, the common drive The maximum power consumption P _c of the circuit is as follows, where f _{c is} the drive frequency of the common and V _c is the power supply voltage of the common drive circuit. In the case of common inversion,
The common drive frequency f _c is half the horizontal drive frequency f _h .

P _c = C _c * f _c * V _c ² (5) [v] Gate line drive circuit The gate line drive circuit is for driving the capacitance C _g of the gate line. The maximum power consumption P _g is
The drive frequency of the gate line is represented by f _g , and the power supply voltage of the gate line drive circuit is represented by V _g as follows. The drive frequency f _g of the gate line is usually the horizontal drive frequency f _h .

P _g = C _g * f _h * V _g (6) [vi] Power consumption P _{all of the} entire circuit From the above, the power consumption P _{all of the} entire circuit is as follows.

[0032] _{P all = P l + P ob} + P b + P ga + P c + P g = (C l + 2C CK) * f s / 2 * V l 2 -N h * C s * f h * V s 2/2 + ( _{2C bc + C bp) * f} s / 2 * V b 2 + (2C gac + C gap) * f s / 2 * V ga 2 + C c * f c * V c 2 + C g * f h * V g ( here , And the common voltage is N _h * C _ss >> C _g , P _all = (C _l + 2C _CK + 2C _bc + C _bp + 2C _gac + C _gap ) * (f _s / 2) * V ² tens N _h * C _{ss * {f h / 2)} * V 2 = P al l (C, f, V) ... (7) , and the power supply voltage V of the digital system and the capacitance C and the driving frequency f (clock frequency of the horizontal frequency and the image) Is a function of. Here, the capacitance C is determined by the device structure, and the voltage V is determined by the IC and liquid crystal panel structure such as the process and the VT characteristic of the liquid crystal. However, the frequency f
Is determined by the system and image quality such as the horizontal scanning frequency of the image and flicker characteristics, and can be lowered by the driving method.

Next, the factors that determine the power consumption of the liquid crystal panel will be examined. As shown in FIG. 14, the liquid crystal panel basically has pixel signal lines and row scanning lines (gate lines).
The image signal and the scanning signal are respectively transmitted by and the pixels are displayed. At this time, the capacitance C of the pixel signal line and the row scanning line
_In order to drive _sig and C _g , C _sigf V ² and C, respectively
The power of _gf V ² is consumed. This power consumption does not directly contribute to the display of the liquid crystal cell CEL and is therefore a loss.

To reduce this, it is necessary to reduce the capacitance C, frequency f, and voltage V. Then, if it is a still image, the frequency f can be set to “0”, but if it is a moving image,
Normally, this cannot be set to "0", and since the display density of each liquid crystal cell CEL frequently changes in the case of a complicated image, there is a problem that the driving power for that also increases. .

Previously proposed LCD with pixel memory
Is for holding the display signal obtained through the switch SW in the pixel memory and using the contents of this memory for display of the pixel. If it is a technology that has the effect of reducing static power consumption, when it is used for video display, of course,
It is necessary to increase the driving frequency f, which increases the overall power consumption.

[0036]

As described above, in the conventional liquid crystal display device, a liquid crystal display device with a pixel memory that can hold a display signal of a display image for each pixel is used for still image display. In addition, although the effect of reducing the driving frequency f and the static power consumption can be expected, there is a problem that such a power consumption reducing effect cannot be expected when displaying a moving image.

In particular, as in recent years, with the spread of multimedia, moving image display is an essential requirement, and liquid crystal display devices include notebook personal computers, handy terminals, mobile TVs, mobile phones, electronic organizers, and game machines. Since it is often used in portable devices such as the above, the problem of power consumption is one of the major problems that must be solved.

Therefore, it is an object of the present invention to significantly reduce the power consumption due to the writing operation to the pixels which do not need to be written among the pixels arranged in a matrix.

Another object of the present invention is to significantly reduce the power consumption due to the writing operation to the pixels which do not need to be written among the pixels arranged in a matrix. Another object of the present invention is to reduce the number of address lines by changing the array configuration in a display system in which individual pixels or pixel blocks each including a plurality of pixels are selectively driven.

Further, according to the present invention, by arranging the column address line drive circuit and the signal line driver on the same side with respect to the display surface, it becomes possible to further narrow the frame when the size of the display device becomes a problem. The purpose is to ensure a large display area.

Further, according to the present invention, in the case of a liquid crystal material which requires polarity reversal, if there is a brightness difference due to the writing polarity and flicker occurs due to it, the polarity is made different between adjacent pixels to compensate for the flicker. , Aim to improve the image quality. Further, in the present invention, the clock to the signal line driver can be stopped or the speed of the pixel which is not rewritten can be stopped, so that the power consumption in the signal line driver can be reduced.

[0042]

According to the present invention, a plurality of pixels arranged in a matrix in a display region, at least two or more switching elements for each pixel, and an image signal supplied to each pixel. Signal line to
A signal line driver that supplies an image signal to the signal line, at least two or more address lines that control a write operation to the one pixel, and an address line drive circuit that supplies a scanning signal to the plurality of address lines. The basic configuration is to selectively drive each pixel or a pixel block including a plurality of pixels in accordance with the scanning signal.

First, according to the present invention, a plurality of pixels arranged in a matrix form at least two pixels in one pixel.
One or more switching elements and scanning lines (gate lines) for controlling the switching elements are provided, and by applying an ON voltage to the switching elements from the scanning lines, an image is output from the signal line. A signal is applied.

As a result, arbitrary selection can be performed for each individual pixel or for each pixel block including a plurality of pixels. Secondly, according to the present invention, a plurality of pixels arranged in a matrix have at least two switching elements and at least one rectifying element in one pixel,
Scanning lines are provided to control the switching elements. An ON voltage is applied to the switching elements from the scanning lines, and the pixel electrode potential can be changed according to the voltage relationship applied to the rectifying element.

Thirdly, according to the present invention, a plurality of pixels arranged in a matrix form two switching elements, two rectifying elements, and a common image signal for each pixel. Signal line driver, a signal line driver for supplying an image signal to the signal line, and the switching element
In the first and second switching elements having different scanning lines for applying N or OFF voltage and an address line driving circuit for voltage supply, the first switching element of the first switching element The gate electrode is connected to the address line, the gate electrode of the second switching element is connected to a gate line different from the gate line, and
And a source electrode of the second switching element is connected to the signal line, a drain electrode of the first switching element is connected to the first rectifying element, and a drain electrode of the second switching element is connected to the second rectifying element. By connecting and connecting the other end of each rectifying element to the pixel electrode together, it is possible to perform writing selection and control of the image signal to be applied in pixel units. As a result, writing control can be performed in pixel units.

Fourthly, according to the present invention, a plurality of pixels arranged in a matrix in the display area are provided with a plurality of signal lines for transmitting image signals to the pixels and a signal for supplying the image signals to the signal lines. A line driver, a plurality of address lines that are orthogonal to each other for selecting a lost pixel, a column address line drive circuit that supplies a scanning signal to the plurality of address lines arranged in the column direction, and a column address line drive circuit arranged in the row direction. A row address line driving circuit for supplying a scanning signal to the plurality of address lines, and changing the lengths of the column address lines and the signal lines in a display system that enables selective scanning for each pixel. Thus, for example, when the space between the signal line pad section and the column address line pad section cannot be maintained in one horizontal row, the position of the pad section is not set in one horizontal row, so that the column address line drive circuit Signal line driver is arranged on the same side with respect to the display surface, characterized in that mounted on the same table carrier back cage on.

Fifthly, according to the present invention, the polarities of writing are the same between adjacent pixels or not, so that the polarities of the adjacent pixels are inverted when the brightness of the pixels is different due to the different polarities. Therefore, it is characterized in that flicker is compensated.

Sixth, according to the present invention, the clock is converted in accordance with the address of the pixel to be rewritten in the display system in which the image data for one line is stored and then the image signals are collectively output to the signal line. The feature is that the clock is stopped when the frequency of the clock is lowered or the rewriting is not performed.

According to the first aspect of the present invention, it is possible to selectively drive individual pixels arranged in a matrix or a pixel block including a plurality of pixels.
As a result, pixels or pixel blocks to be rewritten can be selected in one frame and pixels or pixel blocks not to be rewritten can be selected. Therefore, there is no need to output a signal to each pixel that does not need to be rewritten, and power consumption is reduced. Can be reduced. For example, in a display method in which a window is displayed, when a moving image and a still image need to be displayed on the same screen at the same time, a pixel for displaying a moving image and a pixel for displaying a still image can be selectively driven separately. For the displayed pixels, the driving frequency can be lowered to a region where the deterioration of the image quality is not visually recognized due to the visual characteristics, and the power consumption can be significantly reduced.

According to the second aspect of the present invention, for pixels arranged in a matrix, a rectifying element is provided in each pixel and is arranged between the signal line and the pixel electrode, thereby switching between the signal line and the pixel. Even when the element is turned on, the writing operation to the pixel can be controlled by the voltage relationship between the signal line potential and the pixel electrode potential. As a result, for example, the scanning lines are turned on for the pixels arranged in the column direction as in the past.
Even when a voltage is applied and selected all at once, the rectifying element causes a non-conduction state depending on the voltage applied to the signal line, so that signal writing to the pixel electrode can be prevented. . Therefore, the selective writing operation can be performed even between pixels arranged on the same scanning line. In this case, for the pixel to be rewritten, the operation of resetting the image signal of the previous field is required, and therefore, a means for making the pixel electrode and the counter electrode potential coincide with each other through another switching element provided in the pixel is used. You can also

According to the third aspect of the present invention, one pixel has two switching elements and two rectifying elements, and the scanning lines for controlling the switching elements are arranged in the pixels arranged in the column direction. Two scanning lines are arranged, the phases selected by the scanning lines are made different, and the writing and erasing operations to the pixels can be controlled by the voltage relationship between the signal line potential and the pixel electrode potential. In this case, the rectifying elements are arranged so that the conducting directions are opposite to each other. This allows
For example, even when the ON voltage is applied to the scanning lines with respect to the pixels arranged in the column direction as in the conventional case and the pixels are collectively selected, depending on the voltage applied to the signal line, the rectifying element causes non-conduction. Therefore, it is possible to prevent signal writing and erasing on the pixel electrode.
Further, in this case, since the two scanning lines are arranged only in the column direction, it is possible to implement by only the row address line driving circuit or to adopt a panel configuration in which each row address line driving circuit can be installed on one side, so that the driver is The frame size does not increase due to the increase.

According to the fourth aspect of the present invention, by changing the lengths of the column address lines and the signal lines, the pad portions provided in the column address lines and the pad portions provided in the signal lines are provided in different stages. Since the pitch between the pad portions can be increased by arranging the pad portions on the same side with respect to the display surface, the wiring from the signal line driver and the wiring of the row address line driving circuit You can contact them without overlapping. Accordingly, the signal line driver that drives the pixel signal line and the column address line drive circuit that drives the column address line can be arranged on the same side with respect to the display surface, and the frame size due to the increase in the number of drivers does not increase.

According to the fifth aspect of the present invention, when the luminance difference of pixels due to the different writing polarities appears as flicker, the polarities can be made different between adjacent pixels, so that the flicker is compensated. be able to. In this case, as is well known in multi-field driving, it is possible to invert the polarity in units of a plurality of pixel blocks without inverting the polarity for each adjacent pixel, or invert over a plurality of fields. The image quality can be sufficiently maintained by keeping the spatial frequency characteristics out of the visible region.

According to the sixth aspect of the present invention, when there is a pixel which is not rewritten to the pixel, the clock to the signal line is stopped, or the clock frequency is lowered according to the address of the pixel to be rewritten. Therefore, the power consumption by the clock in the signal line driver and the power consumption for shifting the image data can be reduced.

[0055]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to specific examples. First, a liquid crystal display device of a system in which arbitrary driving is performed for each individual pixel or for each pixel block including a plurality of pixels among a plurality of pixels arranged in a matrix will be described.

(First Specific Example) The first specific example is an image display liquid crystal display device having a structure in which a plurality of pixels are arranged in a matrix, and among a plurality of pixels, each individual pixel or a plurality of pixels. In order to reduce the power consumption, arbitrary driving is performed for each pixel block including

FIG. 1A is a block diagram showing the configuration of the main part of the liquid crystal display device according to the first embodiment of the present invention.
(B) shows a cell configuration of a liquid crystal panel for selecting each pixel. The liquid crystal display device of this example is shown in FIG.
As shown in (a), a liquid crystal display panel 10, a signal line driver 11, a row address line drive circuit 12, a row pixel counter circuit 14, a row address line signal generation circuit 15,
The pixel block address line drive circuit 13, the pixel block counter circuit 16, and the pixel block address line signal generation circuit 17 are provided.

FIG. 1B shows the cell structure of the liquid crystal panel for selecting each pixel. FIG.
A processing method in the row address line drive circuit 12 is shown in (a).

Here, the signal line driver 11 receives the input image signal, and in response to the scanning of the row address line, the state of each pixel in the row being scanned is controlled during the scanning so as to control the state of each pixel. The display signal of each pixel in the row is output corresponding to each pixel, and each display signal is output to the pixel signal line 20 arranged corresponding to each pixel position.

The liquid crystal display panel 10 is a liquid crystal panel for image display in which a plurality of pixels are arranged in a matrix. The liquid crystal display panel 10 has a plurality of wirings extending in the row direction as shown in FIG. Row address line 21 and a plurality of pixel signal lines 20 extending in the column direction,
It is arranged respectively. The region surrounded by the row address line 21 and the pixel signal line 20 constitutes a liquid crystal cell CEL which is an individual pixel.

Each liquid crystal cell CEL comprises a first switching element SW1 composed of a TFT (thin film) transistor, a second switching element SW2 also composed of a TFT transistor, a liquid crystal C _LC and a capacitor C _s . In this specific example, the screen is divided into a plurality of areas and the driving is performed in each area unit.

The gate of the first switching element SW1 is connected to the row address line 21 corresponding to the coordinate position of the liquid crystal cell CEL, and the source-drain is connected to the signal line 20 corresponding to the coordinate position of the liquid crystal cell CEL. And the driving electrode of the liquid crystal C _LC via the source-drain of the second switching element SW2. The liquid crystal has a structure in which a liquid crystal material is sandwiched between a drive electrode and a counter electrode facing the drive electrode, and the liquid crystal C _LC has the same structure.
Therefore, the common potential V _com can be applied to the counter electrode, and the auxiliary capacitance C _s is interposed between the drive electrode side and the counter electrode side of the liquid crystal C _LC .

The gate of the second switching element SW2 is connected to the pixel block address line 22 of the block to which the liquid crystal cell CEL belongs. Further, the pixel block address line 22 is wired in the block unit.

The row address line drive circuit 12 is for generating a signal for driving the row address line, and the row address line drive circuit 12 has output terminals corresponding to a plurality of row address lines 21. The row address lines 21 are sequentially connected to the output terminal so that a row address signal can be applied.

The row pixel counter circuit 14 is a counter for managing row pixel positions so that an image is displayed in correspondence with frame display control of a moving image. In the row pixel counter circuit 14, the liquid crystal display panel is used. A start signal S3 is issued every time (normally, one frame) required to drive all the address lines corresponding to the pixels arranged in rows among the 10 pixels arranged in matrix.
As a result, a signal (row address signal) is individually output from each of the output terminals in such a manner that each output terminal makes one round in order during the period of one frame.

The row address signal generation circuit 15 is a circuit for generating a row address signal which allows all rows to be sequentially selected one by one during the position frame period at a timing corresponding to the frame display control. Row address signal generating circuit 15 issues a row address signal A1 for selectively scanning the address lines arranged for the row.

Here, the processing method in the row address signal generation circuit 15 in this example is a multi-field driving method in which one frame (one frame image) is divided into a plurality of sub-fields to lower the driving frequency. The scanning is performed only on the row address line having the pixel to be selected, as applied in (1). Since the multi-field driving method is a well-known technique, its detailed description is omitted here.

The row address line driving circuit 12 has a start signal S3 from the row pixel counter circuit 14, a row address signal A1 from the pixel block counter circuit 16, and an address signal A from the pixel block address signal generating circuit 17.
2 and a drive signal is generated to drive each row of pixels of the matrix configuration of the liquid crystal panel in order in the period of 1 frame from this, and in order to be able to implement this, this row address line The drive circuit 12 has a built-in shift register, and shifts the start signal S3 in the row direction every horizontal period. Row address line VA
Signals to 1, VA2 to VAE are performed by a logical product of the start signal S3 and the row address signal.

FIG. 2B shows a processing method in the pixel block address line drive circuit 13. Here, in the pixel block counter circuit 16, the start signal S4 is generated every time (normally one horizontal time) required to drive all the address lines corresponding to the pixels arranged in block units.
Is emitted. Pixel block address signal generation circuit 17
In this case, a pixel block address signal A2, which is a signal for selectively scanning an address line arranged in a pixel block unit to be selected, is issued.

Any processing method may be used in the pixel block address signal generation circuit 17, but since one horizontal image (image for one horizontal line) is divided into a plurality of blocks, the driving frequency Is low. The pixel block address line drive circuit 13 incorporates a shift register, a data memory corresponding to each address line, and a multiplexer, and shifts the start signal S4 to obtain the logic of the pixel block address signal A2. The result of the product is recorded in the data memory. In the data memory, pixel block address lines BA1, BA
Information for selecting the output of the gate voltage to 2 to BAE is recorded, and the output of the gate voltage is controlled by the multiplexer.

FIG. 1B shows a cell structure of the liquid crystal display panel 10 for selecting each pixel. As described above, the basic cell configuration includes the liquid crystal CLc, the auxiliary capacitance Cs, and the switching elements SW1 and SW2. Then, the switching element SW1 is connected to the row address line 2
1 and the switching element SW2 is connected to the pixel block address line 22.

When an ON voltage is applied from the row address line drive circuit 12 via the row address line 21, the switching element SW1 whose gate is connected to the row address line 21 is in the ON state. When an ON voltage is applied from the pixel block address line drive circuit 13 via the pixel block address line 22, the switching element SW2 whose gate is connected to the pixel block address line 22 is in the ON state. become.

As a result, of the plurality of pixels (liquid crystal cells), the row address line drive circuit 12 and the pixel block address line drive circuit 13 apply an ON voltage to each address line, thereby switching element SW1. The image signal from the pixel signal line 20 can be applied only to the pixels whose switching element SW2 is turned on at the same time. The pixel block address line 22 is applied to the switching elements SW2 of all the pixels in the block at the same time in a block unit of the pixel so as to be turned on.
It is possible to perform control such that a plurality of pixel blocks are arbitrarily selected for each pixel block and the pixels of the block are made drivable.

Then, for the pixel in which the switching element SW1 and the switching element SW2 are simultaneously turned on (ON), when the image signal from the pixel signal line 20 is applied, the pixel of the pixel is passed through these switching elements SW1 and SW2. The image signal is applied to and held in the capacitor C _s , and the held image signal is applied to the liquid crystal C _s , and thereafter, the liquid crystal is held by the image signal held in the capacitor C _s until rewriting is performed. C _s drives the liquid crystal C _LC to be used for display.

Therefore, of the plurality of pixel blocks, only the block whose display content needs to be rewritten can be driven, and the other blocks are not driven, so that the moving image display can be performed with low power consumption. Can be implemented.

FIG. 3 shows an example of the operation in the case where one block is made up of three pixels in the vertical and horizontal directions. FIG. 3A shows the signal waveform of each part in this example. Further, FIG. 3B shows the address of each pixel and
(C) and (d) show (b) in the signal waveform in (a) above.
The switching result for each pixel in is shown.

In the figure, the pixel address Pxi, yj indicates the pixel at the Xi-th row and the Yj-th column in the matrix of the X-th row and the Y-th column.
Corresponds to the row address, and Yj corresponds to the column address. As a result, pixel switching is controlled by the logical product of the row address VA and the column address BA.

Further, in this example, a pixel block having 3 pixels in each of the vertical and horizontal directions is described, but the method of dividing the block may or may not be the same in each block. Can be arbitrarily determined in block units. Furthermore, as an advantage of block selection, MP standardized as a moving image compression transmission method is used.
Good matching with EG1 and MPEG2 can be mentioned.

That is, in the MPEG technique, an image is 8 × 8.
Or 16 × 16 (16 × 8) block, etc.
The determination of "present" or "absent" of motion and the compression process are performed in block units such as 8x8 or 16x16 (16x8). Therefore, even if the information can be selected in the unit of pixel, the transmitted information is in the unit of block, so that the information cannot be effectively used. Therefore, it is desirable to divide the blocks into blocks according to the size of the blocks to be transmitted.
Further, since the address line can be provided for each block, the number of address lines in the panel can be reduced by forming the block in a plurality of columns.

As a result, as shown in FIG. 4, it is possible to prevent the number of drivers from increasing by providing the row address line drive circuit with the same function as the pixel block address line drive circuit.

As described above, in the first concrete example, a plurality of pixels arranged in a matrix are divided into blocks, and drive control can be performed for each block to operate the blocks in which the image needs to be rewritten. The other components are configured so as not to operate, so that low power consumption can be achieved.

In a liquid crystal display device in which a capacitor C _s , which is a memory holding unit for storing an image signal, is provided for each pixel, only the pixels that need to be rewritten are rewritten to the contents of the given image signal. Next, an example of achieving low power consumption by doing so will be described as a second specific example.

(Second Specific Example) In the second specific example, a plurality of pixels arranged in a matrix have at least two switching elements and at least one rectifying element in one pixel, Scanning lines are provided to control the switching elements, and an ON voltage is applied to the switching elements from the scanning lines so that the pixel electrode potential can be changed by the voltage relationship applied to the rectifying element. It is a thing.

Here, with respect to the pixels arranged in a matrix, a rectifying element is provided in the pixel and is arranged between the signal line and the pixel electrode, so that the switching element between the signal line and the pixel is turned on. Even in such a case, the writing operation to the pixel can be controlled by the voltage relationship between the signal line potential and the pixel electrode potential. As a result, for example, when the ON voltage is applied to the scanning lines with respect to the pixels arranged in the column direction as in the conventional case, and the pixels are collectively selected, depending on the voltage applied to the signal line, the Since the conductive state is established, signal writing to the pixel electrode can be prevented. By doing so, the selective writing operation can be performed even between the pixels arranged on the same scanning line, and the power consumption is reduced.

Details will be described. In the second specific example, among a plurality of pixels arranged in a matrix, a reset pulse is applied to each pixel or each pixel block including a plurality of pixels, and then an arbitrary pixel is arranged to the pixels arranged in the row direction. The selective driving is performed, and the configuration as shown in FIG. 5 is adopted.

FIG. 5 shows the structure of the main part of a liquid crystal display device according to the second embodiment of the present invention. The liquid crystal display device of this embodiment has a structure in which a plurality of pixels are arranged in a matrix as shown in the drawing. Liquid crystal display panel 50, signal line driver 51, row address line drive circuit 52, row pixel counter circuit 54, row address line signal generation circuit 55, reset signal line drive circuit 53, and reset counter circuit 56.
And a reset signal generation circuit 57.

FIG. 5B shows a cell structure of a liquid crystal panel for selecting each pixel. The basic cell structure includes a liquid crystal C _LC , an auxiliary capacitance C _s , switching elements SW1 and SW2, and a rectifying element D1.

The switching element SW1 has its gate connected to the row address line 58 corresponding to the self pixel in the row address line 58 provided for each row, and is also provided for each column from the signal line driver 51. The pixel signal line corresponding to the self pixel in the pixel signal line and the anode side of the diode D1 are connected between the source and drain of the switching element SW1. The cathode side of the diode D1 is connected to the drive electrode of the liquid crystal C _LC .

The liquid crystal has a structure in which a liquid crystal material is sandwiched between a drive electrode and a counter electrode facing the drive electrode, and the liquid crystal C _LC has the same structure. Therefore, the common potential V
_{In addition} to enabling the application of _com , the auxiliary capacitance C _s is interposed between the drive electrode side and the counter electrode side of the liquid crystal C _LC .

The switching element SW2 has its gate side connected to the reset signal line 59 corresponding to the self pixel of the reset signal line 59 provided for each column.
The source-drain of the switching element SW2 is connected between the cathode side of the diode D1 and the reset pulse T _RS terminal for applying the reset pulse V _rs .

With this configuration, the ON (ON) voltage is applied to the reset signal line from the reset signal line drive circuit 53, so that the pixel electrode potential of the pixel in which the switching element SW2 is ON (ON) is It becomes V _rs . In this case, the pixel electrode potential V _rs is set to be equal to or lower than the minimum signal voltage Vmin to be given as the pixel electrode potential.

Next, the row address line drive circuit 52 selects the row address lines in a line-sequential manner. The voltage applied to the pixel signal line here is the pixel to be rewritten (usually, the pixel to which the reset pulse is applied). Regarding the image signal Vsig according to the image data, the voltage Vof at which the rectifying element D1 becomes non-conducting for the pixels which are not rewritten.
f is applied.

That is, the signal line driver 51 outputs the image signal Vsig according to the image data for the pixel to be rewritten (usually a pixel to which a reset pulse is applied) to the pixel signal line, and the rewriting is not performed. For the pixel, a voltage of Voff level is output. This V
The off-level voltage is a voltage at which the rectifying element D1 becomes non-conductive.

Here, the relationship of each voltage is, for example, Voff ≦ Vrs ≦ Vmin ≦ Vsig (1).

Therefore, in the switching element SW1 to which the ON signal is given from the row address line, the diode D1 is turned on or off depending on the voltage of the image data given from the pixel signal line. A reset signal is supplied from the reset signal line drive circuit 53 to the pixel to be rewritten, and the switching element SW2 of the pixel to which the reset signal is supplied is turned on and the reset pulse T _{RS is applied.} The reset voltage V _rs from the terminal is applied to the auxiliary capacitance C _{s of the} pixel, and the auxiliary capacitance C _s
s becomes the reset voltage V _rs .

With such a configuration, the image data is given to the diode D1 via the switching element SW1 which is in the ON state, whereby the content (voltage level) of the image data and the auxiliary capacitance C _{s of the} pixel. The diode D1 becomes conductive / non-conductive in accordance with the holding voltage of. As a result, with respect to the pixel that needs to be written, the diode D1 is turned on, pixel data is given to the auxiliary capacitance C _s of the pixel, held there, and provided for pixel display of the liquid crystal C _LC . In addition, since the diode D1 is non-conducting in a pixel that does not need to be rewritten, no current flows in the auxiliary capacitance C _s, and power consumption can be reduced accordingly.

When it is necessary to rewrite the entire surface, a reset pulse is applied to the target pixel. Since the auxiliary capacitance C _s of the pixel to which the reset pulse is applied is the reset voltage V _rs , it is necessary to newly write. By applying image data to the diode D1 via the switching element SW1 which is in the ON state, the diode D1 becomes conductive / non-conductive according to the content (voltage level) of the image data. It will be possible to rewrite to correspond to the data.

Note that the pixel information to be rewritten can be configured to output image information from a frame memory or the like provided separately. Further, it is desirable to define an area that is frequently rewritten on the display screen and use this specific example in that area.

As described above, with respect to the pixels arranged in a matrix, a rectifying element (diode) is provided in each pixel,
By arranging this between the pixel signal line and the pixel electrode of the liquid crystal, the switching element between the pixel signal line and the pixel is turned on.
Even in the case of the state, the writing operation to the pixel can be controlled by the voltage relationship between the signal line potential and the pixel electrode potential. Thereby, for example, even when the ON voltage is applied to the scanning lines with respect to the pixels arranged in the column direction and the pixels are collectively selected, depending on the voltage applied to the pixel signal line, the rectifying element may Since the non-conduction state is set, it is possible to prevent the signal writing to the pixel electrode. Therefore, the selective writing operation can be performed even between pixels arranged on the same scanning line. In this case, since the pixel to be rewritten needs to reset the image signal of the previous field, the potential of the auxiliary capacitance is set to the reset potential via another switching element provided in the pixel, and thereby the liquid crystal cell of the liquid crystal cell is reset. The potentials of the pixel electrode and the counter electrode were made to match.

With such a configuration, it is possible to minimize rewriting and achieve low power consumption. Next, there are two switching elements and two rectifying elements in one pixel.
Two scanning lines for controlling the switching elements are provided for the pixels arranged in the column direction, and the phases selected by the scanning lines are made different.
An example in which the writing and erasing operations to the pixel can be controlled by the voltage relationship between the signal line potential and the pixel electrode potential will be described as a third specific example.

(Third Concrete Example) In the third concrete example, a reset pulse is applied to each individual pixel or each pixel block consisting of a plurality of pixels among a plurality of pixels arranged in a matrix. It is for optional driving. FIG. 6A is a block diagram showing a configuration of a main part of a liquid crystal display device according to a third example of the present invention, and FIG. 6B is a diagram showing a rough cell configuration of each liquid crystal cell. As shown in FIG. 6, the liquid crystal display device of this specific example has a liquid crystal display panel 60, a signal line driver 61, a row address line drive circuit 62, a row pixel counter circuit 64, and a row address line signal generation circuit 65. And.

FIG. 6B shows the cell structure of the liquid crystal panel for selecting each pixel. The basic cell structure is the liquid crystal C _LC , the auxiliary capacitance C _s, and the switching element SW1. And SW2 and rectifying elements D1 and D2, the switching element SW1 has its gate connected to the row address line 66, and the switching element SW2 has its gate connected to the reset signal line 67. Storage capacitance C _s is Yes connected between the drive electrode and the counter electrode of the liquid crystal C _LC, and the pixel position corresponding pixel signal lines and the liquid crystal C _LC
The source-drain of the switching element SW1 is connected via the rectifying element D1 connected in the forward direction to the drive electrode of the switching element, and the source-drain of the switching element SW2 is connected between the source-drain of the switching element SW2 connected in the reverse direction. Connected

In addition to the pixel data corresponding to the image, the signal line driver 61 also receives a reset signal having a voltage level of V _rs ,
A non-rewriting signal having a voltage level of V _ns can be output. By applying an ON voltage to the row address line 67 from the row address line drive circuit 62,
Among the pixels in which the switching element SW2 is turned on, the pixel to be rewritten is V
_A reset signal of _rs is generated and applied, and a non-rewriting signal of V _ns is generated and applied to a pixel that is not rewritten.

Therefore, by applying an ON (ON) voltage to the row address line 67 from the row address line drive circuit 62, among the pixels in which the switching element SW2 is ON (ON), the pixel to be rewritten is selected. As a result, a reset signal of V _rs can be applied from the pixel signal line, and a non-rewriting signal of V _ns can be applied to pixels that are not rewritten.

In this case, V _rs is set to the minimum signal voltage V _min or less to be applied as the pixel electrode potential, and V _ns is set to the maximum signal voltage V _max or more to be applied as the pixel electrode potential. Next, an ON voltage is applied to the row address line 66, and an image signal (pixel data) V _sig is applied from the pixel signal line to the pixel to be rewritten among the pixels in which the switching element SW1 is turned ON. Further, V _rs is applied to the pixels that are not rewritten.

The respective voltage relationships are, for example, V _rs ≤V _min ≤V _sig ≤V _max ≤V _ns (2). In this case, regarding the row address lines 65 and 66,
The wiring may be from the same row address line drive circuit or may be from another row address line drive circuit.

As described above, one pixel has two switching elements and two rectifying elements, and two scanning lines for controlling the switching elements are arranged for the pixels arranged in the column direction. Thus, the phases selected by the scanning lines are made different, and the writing and erasing operations to the pixels can be controlled by the voltage relationship between the signal line potential and the pixel electrode potential. In this case, the rectifying elements are arranged so that the conducting directions thereof are opposite to each other, whereby an ON voltage is applied to the scanning lines with respect to pixels arranged in the column direction as in the conventional case, for example. Even when selected, the rectifying element causes a non-conduction state depending on the voltage applied to the signal line, so that it is possible to prevent signal writing and erasing to the pixel electrode.
Low power consumption can be achieved. Also, in this case, 2
Since the scanning lines of the book are arranged only in the column direction, it can be implemented only by the row address line drive circuit, or each row address line drive circuit can be installed on one side. Can be prevented from increasing.

A signal line driver for driving the pixel signal line,
Another example in which the column address line driving circuit for driving the column address lines can be arranged on the same side with respect to the display surface to prevent the frame size from increasing due to the increase in the number of drivers will be described below.

(Fourth Concrete Example) A fourth concrete example is a display device having column address lines and column address drive circuits arranged in the column direction, in which a signal line driver and the column address line drive circuit are provided. It is arranged on the same side with respect to the display surface.

FIG. 7A is a diagram showing the array configuration of the panel peripheral portion of the liquid crystal display device according to the fourth embodiment of the present invention. 70 is a pixel signal line, 71 is a column address line, and 72 is a pixel signal. Line pads and 73 are column address line pads. The liquid crystal display device of this specific example includes a plurality of pixel signal lines for transmitting image signals to the pixels, a signal line driver for supplying image signals to the pixel signal lines, and row addresses orthogonal to each other for selecting each pixel. A line and column address line, a row address line drive circuit that supplies a scanning signal to the plurality of address lines arranged in the row direction, and a scanning signal to the plurality of address lines arranged in the column direction. In a display system having a column address line drive circuit and enabling selective scanning for each pixel, the column address line drive circuit and the signal line driver are arranged on the same side with respect to the display surface.

Therefore, as shown in FIG. 7A, for example, by changing the lengths of the column address line 71 and the pixel signal line 70, the pad 72 of the pixel signal line and the pad 73 of the column address line are separated from each other. It is possible to have a configuration with different stages (not in a single horizontal row).

FIG. 7B shows a contact portion between the pad and the tab wiring 75. The pad and the tab wiring 75 are electrically connected through, for example, the anisotropic conductive film 74. As described above, by using the anisotropic conductive film, the signal line driver and the column address line driving circuit can be mounted on the same tape carrier. The area will not increase.

FIG. 7C shows a structure in the case where the signal line driver and the column address line drive circuit are the same tape carrier package in this example. Next, in the liquid crystal display panel, when the difference in pixel brightness due to different writing polarities of pixels appears as flicker, the polarities can be made different between adjacent pixels and flicker can be compensated. This example will be described as a fifth specific example.

(Fifth Concrete Example) In the fifth concrete example, in a liquid crystal display device in which a plurality of pixels are arranged in a matrix, by reversing the writing polarities between adjacent pixels, the polarities are different and the luminance of the pixels is changed. This is to compensate for flicker that occurs when the values are different.

FIG. 8 shows a cell structure of a liquid crystal panel for selecting each pixel. The basic cell structure is
Similar to the first specific example, the liquid crystal C _LC and the auxiliary capacitance C _s
And the switching element SW1 is connected to the row address line 81, and the switching element SW2 is connected to the pixel block address line 82.

In this case, the pixel block has pixels arranged on different signal lines as one block. This allows
From each address line drive circuit 12, each address line 8
ON voltage is applied to the switching element S
Image signals are applied from the pixel signal lines 83 and 84 to pixels in which W1 and SW2 are turned on at the same time, but in this specific example, the image signals having different polarities are applied to the signal lines 83 and 84. Is applied.

Further, among the pixels of the selected pixel block, the number of pixels in which writing is performed in + (positive polarity) and −
It is desirable that the number is approximately the same as the number of pixels written in (negative polarity). Further, it is preferable that the method of reversing the polarity is switched every few frames.

As described above, in this specific example, the polarities of writing are the same between adjacent pixels or not the same, so that the polarities are inverted between adjacent pixels when the brightness of the pixels is different due to the different polarities. West,
This is characterized by compensating for flicker. In the case where the luminance difference of pixels due to different writing polarities appears as flicker, the polarities can be made different between adjacent pixels in this specific example, so flicker can be compensated.

In this case, as is well known in the multi-field driving, the polarity is not inverted for each adjacent pixel, but the polarity is inverted in a unit of a plurality of pixel blocks, or the inversion is performed over a plurality of fields. It is also possible to maintain the image quality sufficiently by not entering the visible region in the spatiotemporal frequency characteristic of vision.

Next, a technique for reducing the frequency of the operation clock will be described as a sixth specific example. (Sixth Specific Example) A sixth specific example is characterized in that when one row includes pixels to be rewritten and pixels to be not rewritten, the clock is converted according to the address of the image signal. To do.

FIG. 9 shows the signal waveform of each part according to the sixth example of the present invention. The signal line driver 11, which receives the image signal and outputs the pixel data to the pixel signal line, includes the image data Q which is an image signal, a clock CK, and an addressing signal A.
Enter D and. At that time, in this specific example, the clock CK
Is not continuous occurrence, but is shown in FIG. 9 in which a stop period is provided.

As for the image data Q, as shown in FIG. 9, the image data for the pixel to be rewritten is Qs, and the image data for the pixel not to be rewritten is Q _ns . Further, STH is a start pulse, and the signal line driver 1
1 is provided with a shift register that shifts by the clock CK to shift image data. This STH is a start pulse for instructing the first shift register in the signal line driver 11 to start inputting image data. Becomes

The signal line driver 11 in this example starts inputting image data to the shift register after inputting a start pulse. However, since the clock CK is controlled by the address signal AD, the number of shifts of the image data Q is also controlled. Will be done. However, in this case, the image data of the pixel to be rewritten must be input to the signal line driver 11 from the control circuit in synchronization with STH. Here, although not shown, the control circuit controls the center of control of the liquid crystal display device.

Also, in the case where a pixel to be rewritten and a pixel to be rewritten are not included between pixels in one image line, the image data having the largest number of shifts among the image data in the same row is STH. The signal line driver may be input in synchronism with.

As described above, according to this example, when there is a pixel for which rewriting to the pixel is not present, the clock to the signal line is stopped or the clock frequency is adjusted according to the address of the pixel to be rewritten. Therefore, the power consumption by the clock in the signal line driver and the power consumption for shifting the image data can be reduced.

FIG. 10 is a signal waveform diagram of each part according to another specific example for lowering the clock frequency. In this specific example, image data for pixels for which one frame of rewriting is performed is serially input to the signal line driver in synchronization with a start pulse STV for instructing the start of image input of one frame, regardless of the write line. Let it start.

In this case, the image data can be input only while the clock is being input. However, the output from the control panel is converted according to the address signal, and the image data for one line does not necessarily have to be sent in block units. Further, in this case, it is possible to reduce the speed according to the display image without stopping the clock.

Although the present invention has been described with reference to the illustrated specific examples, the row address lines and the column address lines may be interchanged.
The method of arranging the switching element and the rectifying element can be changed, and the present invention is not limited to each specific example, and various modifications can be carried out without departing from the scope of the invention.

Next, it is possible to arbitrarily select each pixel, and to transmit a display signal only to a portion to be rewritten and to transmit a display signal to a portion which is not to be rewritten. In the case of a device, an example in which the power consumed by a transmission signal can be significantly reduced will be described as a seventh specific example.

(Seventh Concrete Example) FIG. 11 shows the configuration of the seventh concrete example, and FIG. 12 shows a drive timing chart. In FIG. 11, both _Vth of the TFT transistors Tr1 and Tr2, which are switching elements, are set to 4 [V]. V _gl
Is a selection signal, ON is 5 [V], OFF
(Off) is 0 [V]. A selection signal is input to V _s1 for a certain time and a pixel signal is input for a certain time. At the time of the selection signal, ON is 10 [V] and OFF is 5 [V].
Further, it changes from 0 to -4 [V] at the time of pixel signal. In the case of AC driving, the driving voltage is 2 [V].

The timing chart of FIG. 12A shows the pixel (1,
The case where 1) is selected and written is shown. First, V _g1 and V _s1 are simultaneously selected. That is, V _g1 is 5 [V] and V _s1 is 10 [V].

At this time, Tr1 is turned on, and the selection signal 5 [V] is written in V _p1 . Next, V
_{When s1} is changed to -4 [V] which is an image signal, Tr1
Turns off and the selection signal is held. An image signal is written through Tr2 during this hold period. Next, the selection of V _g1 is completed, the voltage is _lowered to 0 [V], and
_{When s1} is returned to the range of selection signal 5-10 [V], Tr1 becomes O
The N state is set, and the non-selection signal is written as V _p1 .

After that, since V _g1 is not in the selected state until the next selection period, the voltage of −4 [V] written in the pixel is held until the next selection period starts. That is,
As long as V _s1 is selected or not, and V _g1 is non-selected, the non-selection signal is written as a pixel selection signal during Tr1 during the selection signal period. Therefore, the capacitance C provided for holding the pixel selection signal is used. _{Since p1} has a level that can be held only while the pixel signal is input to V _s1 ,
In some cases, only floating capacitance is sufficient, so it is not necessary to provide it in particular, and the image signal is 0 to
Since it changes only up to -4 [V], it does not turn on because it does not exceed 4 [V] which is _Vth of Tr2.

That is, even with the same signal line V _s1 , the selection signal and the image signal can be separated by changing the signal level. Further, in order to reduce the power consumption, after the non-selection signal power S is output, the same level (non-selection signal level: 5 [V] here) is output even for the image signal, and V
You can also set the level so that the _s1 signal itself does not change. Further, if it takes a long time to turn off, it may cause crosstalk. To prevent this, as shown in FIG. 00A (b), a slight overshoot is set to V _g1 when turning off. It is also possible to have it.

In the specific example described above, the n-channel T
Although the case where the FT is used is shown, the present invention can be applied even if the p channel is used. In addition, this specific example
One pixel selection has been described, but a block (for example, 8
This also includes the case of selecting every (× 8 pixels or 16 × 16 pixels). MPEG2 will be used in the future for moving image transmission, but this compression processing is performed in block units. Therefore, if the display is also performed in block units, the compatibility is better and the MPEG information is easier to use.

As described above, since it is possible to arbitrarily select each pixel, it is not necessary to transmit the display signal only to the portion to be rewritten and the display signal to the portion not to be rewritten, so that the memory function is provided somewhere. In the liquid crystal display device that has the power consumption, power consumed by a transmission signal can be significantly reduced.

As described above in detail, according to the seventh specific example, it is possible to arbitrarily select each pixel without newly providing a signal line for selecting in the column direction, and to move only a moving part. By rewriting, power consumption can be significantly reduced even for moving images. Further, since the signal line driver can be used both for driving the pixel voltage and for selecting, it is possible to dispose separate drivers on both sides.
Since it can be placed on one side, the liquid crystal panel can have a narrow frame structure. Further, the power supply voltage is reduced by making the signal line driver different for the time-division selection signal and the time of the image signal, and it is possible to use the low-voltage low-cost driver.

[0138]

According to the present invention, since it is possible to selectively drive each pixel arranged in a matrix or each pixel block composed of a plurality of pixels, a signal is output to each pixel which does not need rewriting. Power consumption can be reduced significantly. Further, since the address line is connected to each block, the capacity of the address line is reduced, and power consumption can be reduced accordingly. Further, according to the present invention, since the rewriting can be controlled for the pixel which is not rewritten by the potential relationship between the pixel electrode potential and the signal line electrode potential, the rewriting can be controlled for each pixel which does not need rewriting. , It becomes unnecessary to output a signal, and the power consumption can be greatly reduced. Further, according to the present invention, since the pixel block address line driving circuit is not required, or the signal line driver and the pixel block address line driving circuit can be arranged on the same side with respect to the display surface, a panel structure can be adopted. If the liquid crystal display device has the same display screen area, the size of the liquid crystal module can be reduced. Further, according to the present invention, since the pixels having different polarities can be written in substantially the same number in the pixel block, the image quality can be improved without causing flicker.
Further, according to the present invention, the clock to the signal line driver can be stopped or slowed down, so that the power consumption of the signal line driver can be significantly reduced.

Further, according to the present invention, since it is possible to arbitrarily select each pixel, it is not necessary to transmit the display signal only to the portion to be rewritten and to transmit the display signal to the portion not to be rewritten. In the liquid crystal display device having the above-mentioned somewhere, the power consumed by the transmission signal can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the present invention and is a diagram showing a main configuration of a liquid crystal display device according to a first example of the present invention and a cell configuration of the liquid crystal panel.

2 is a diagram for explaining the present invention, showing a signal processing mode in a row address line drive circuit and a pixel block address line drive circuit in the device of FIG. 1. FIG.

3 is a diagram for explaining the present invention, which is a diagram showing a signal waveform diagram of each part and a pixel selection state in the device of FIG. 1. FIG.

FIG. 4 is a diagram showing an example of a pixel block configuration in the same specific example.

FIG. 5 is a diagram for explaining the present invention and is a diagram showing a main configuration of a liquid crystal display device according to a second specific example of the present invention and a cell configuration of the liquid crystal panel.

FIG. 6 is a diagram for explaining the present invention, showing a main configuration of a liquid crystal display device according to a third example of the present invention and a cell configuration of the liquid crystal panel.

FIG. 7 is a diagram for explaining the present invention and is a diagram showing a wiring configuration of a liquid crystal display device according to a fourth example of the present invention.

FIG. 8 is a diagram for explaining the present invention and is a diagram showing a cell configuration of a liquid crystal panel of a liquid crystal display device according to a fifth example of the present invention.

FIG. 9 is a diagram for explaining the present invention and is a diagram showing signal waveform diagrams of respective parts of the liquid crystal display device according to the sixth example of the present invention.

FIG. 10 is a diagram for explaining the present invention and is a diagram showing signal waveform diagrams of respective parts of the liquid crystal display device according to the sixth specific example of the present invention.

FIG. 11 is a diagram for explaining the present invention, showing the configuration of a seventh example of the present invention.

FIG. 12 is a diagram for explaining the present invention, showing a drive timing in a seventh example of the present invention.

FIG. 13 is a diagram showing a main part configuration of a conventional liquid crystal display device and a cell configuration of the liquid crystal panel.

FIG. 14 is a diagram showing a conventional example.

[Explanation of symbols]

10, 50, 60 ... Liquid crystal display panel 11, 51, 61 ... Signal line driver 12, 52, 62 ... Row address line drive circuit 14, 54, 64 ... Row pixel counter circuit 15, 55, 65 ... Row address line signal generation Circuit 13 ... Pixel block address line drive circuit 16 ... Pixel block counter circuit 17 ... Pixel block address line signal generation circuit 53 ... Reset signal line drive circuit 56 ... Reset counter circuit 57 ... Reset signal generation circuit SW1, SW2 ... Switching element D1, D2 ... rectifying element C _LC ... liquid crystal C _s ... auxiliary capacitor.

Claims (4)

[Claims] 1. A plurality of pixels are arranged in a matrix in a display area, and a gate line for selecting a row position and a pixel signal line for giving individual pixel information in a column direction are provided and are provided by these gate lines. A liquid crystal display device using a liquid crystal display panel that selects each pixel by a signal, and performs pixel display based on the pixel information given to the selected pixel, and is provided for each pixel and corresponds to each pixel. A first switching element that operates according to a signal from the gate line, a block selection unit that divides each pixel into blocks, and a block that collectively selects the pixels divided into blocks, and each pixel Provided for each block, operating in pixels corresponding to the block selected by the block selecting means, and operating by the first switching element. A liquid crystal display device comprising: a second switching element that obtains pixel information for a pixel and provides the pixel display. 2. A plurality of pixels are arranged in a matrix in a display area, and a gate line for selecting a row position and a pixel signal line for giving individual pixel information in a column direction are provided to be provided by these gate lines. A liquid crystal display device using a liquid crystal display panel in which each pixel is selected by a signal, and pixel display is performed based on pixel information given to the selected pixel, which is provided for each pixel and corresponds to each pixel. A first switching element that operates by a signal from the gate line, a rectifying element that passes pixel information for the own pixel given through the first switching element according to a level, and is used for pixel display, and obtains information. Second for pixel display
A liquid crystal display device comprising: 3. A plurality of pixels are arranged in a matrix in a display area, and a gate line for selecting a row position and a pixel signal line for giving individual pixel information in a column direction are provided and are provided by these gate lines. A liquid crystal using a liquid crystal display panel in which each pixel is selected by a signal, pixel information given to the selected pixel is held in a holding unit provided corresponding to the pixel, and pixel display driving is performed by the held pixel information. In the display device, a second gate line that selects the same row position as the gate line at a different timing from the gate line that selects the row position; and the gate line provided for each pixel and corresponding to each pixel. A first switching element that operates by a signal from the pixel and pixel display information for the own pixel that is given through the first switching element A first rectifying element that is passed through according to a signal level of information to be used for pixel display; and a first rectifying element that is provided for each pixel and that operates by a signal from the second gate line corresponding to each pixel A liquid crystal display comprising: a second switching element; and a second rectifying element which discharges and disappears in accordance with the signal level of the pixel display information held by the holding means when the second switching element operates. apparatus. 4. A gate line related to vertical selection and a signal line related to horizontal selection, which are arranged substantially orthogonal to each other, a pixel arranged at a portion where the gate line and the signal line intersect, and the pixel are selected. An active matrix liquid crystal display device including a switch element for: a liquid crystal display device, wherein a signal for selecting the pixel and an image signal are applied to at least the signal line or the gate line in a time division manner.