JP4665291B2 - Active matrix display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an active matrix display device. More specifically, the present invention relates to a driving technique for writing image signals in units of blocks.
[0002]
[Prior art]
An active matrix display device such as a liquid crystal display (LCD) is a next-generation display that replaces the CRT, but the image signal input method is the same one-dimensional format as the CRT. That is, image data is written on the liquid crystal panel by one line (one scanning line) as a raster signal. One-dimensional input is certainly the best way to view narrowband transmission images such as terrestrial broadcasts such as NTSC and analog VTRs.
[0003]
[Problems to be solved by the invention]
However, when wide-band transmission digital compressed images such as satellite broadcasting and DVD are widely used as signal sources, these compressed images are encoded in block units of m × n (m and n are natural numbers of 2 or more). In order to display the encoded compressed image, it is necessary to decode it into a one-dimensional format. However, in order to decode an image signal compressed in an m × n two-dimensional format into a one-dimensional format, a frame memory is required, so it cannot be said that the signal processing efficiency is good. Therefore, it is considered preferable that the next-generation display input method is not limited to a one-dimensional format. In other words, a method in which input can be performed as it is in m × n block units is more efficient. Nevertheless, at present, the two-dimensional input format of the active matrix display device has not been established, which is a problem to be solved. In addition, next-generation displays are required to reduce power consumption in addition to being thinner and lighter. For this purpose, it is effective to reduce the speed of the clock used for data transfer. However, in response to this, the one-dimensional input format has a limit in reducing the data transfer rate. Thus, for the next generation display, the conventional one-dimensional signal input method is not necessarily optimal, and there is a problem of realizing a more efficient block input format. Hereinafter, the MPEG technology will be briefly described with reference to this example.
[0004]
FIG. 11 schematically shows the process of MPEG image data processing. An input signal such as a video signal is first compressed by the MPEG encoder 11. This compression is performed in units of blocks of 8 rows × 8 columns. That is, 8 × 8 = 64 dots of image data is made into one block and compressed by pixel thinning or bit thinning. The MPEG compressed data is transmitted through the packetizing / bitstreaming circuit 12. The reception set side includes an MPEG decoder 13 and decompresses compressed data to obtain uncompressed raster signal data. At this time, in order to convert the two-dimensional data expanded in block units into a one-dimensional raster signal, a large-capacity frame memory 16 is required.
[0005]
FIG. 12 schematically shows raster signal data for one horizontal period assigned to one scanning line. The data transfer clock CK1 has a frequency of 25 MHz, for example.
[0006]
FIG. 13 schematically shows an active matrix display device which is an example of a conventional reception set. The raster signal data shown in FIG. 12 is converted into an analog signal by the DA converter 13x and then input to the active matrix display device. As shown in the figure, this display device includes pixels 3 formed in a matrix using a pair of substrates 4 and 5 facing each other, scanning lines X provided corresponding to the rows of the pixels 3, and columns of pixels. Corresponding signal lines Y are provided. In the conventional configuration, the pixel 3 is formed on one substrate 4, and the opposite substrate (common electrode) 8 a is formed on the other substrate 5 over the entire surface. Further, the row driving circuit 14 and the column driving circuit 15 are provided integrally with or separately from the pair of substrates 4 and 5 described above. The row driving circuit 14 includes a shift register and the like, and is connected to each scanning line X to select the pixels 3 for each row. The column driving circuit 15 is connected to each signal line Y and writes an image signal to the pixels 3 in the selected row. In the illustrated example, the column drive circuit 15 basically writes the image signal input from the DA converter 13x to each pixel 3 in a dot-sequential manner for one row selected by the row drive circuit 14. .
[0007]
In some cases, a plurality (n) may be simultaneously written in the pixels arranged in the selected row. This is a so-called multi-pixel simultaneous driving method, but it is a simultaneous multi-pixel writing to one selected row. FIG. 14 shows an example of the image signal supplied from the DA converter 13x to the column drive circuit 15 in this case. As shown in the figure, n data 1 to data n are supplied to the column drive circuit 15 in parallel corresponding to the number n of pixels to be simultaneously written. In this case, the image signal transfer clock CK2 is lowered to CK1 / n. However, since it is basically a one-dimensional writing method, a large-capacity frame memory is required when decompressing the original compressed image.
[0008]
FIG. 15 is a schematic diagram showing an active matrix display device of a line sequential drive system. Portions corresponding to those of the conventional dot sequential drive type display device shown in FIG. 13 are denoted by corresponding reference numerals. In the line sequential driving method, the input raster signal data is directly input to the column driving circuit 15. The multiplexed raster signal data is processed by the demultiplexer of the column drive circuit 15, latched in units of rows, and analogized by the DA converter. On the other hand, the row driving circuit 14 selects the row 3 of pixels in a line sequential manner. The column driving circuit 15 writes the latched and DA-converted image signal to all the pixels in one selected row at once. This is a typical one-dimensional input method.
[0009]
FIG. 16 is a waveform diagram schematically showing analog signal data output from the DA converter of the column drive circuit 15 shown in FIG. In line sequential driving, image data for one row is output to the panel side in synchronization with line sequential scanning on the row driving circuit 14 side in units of one horizontal period (1H).
[0010]
[Means for Solving the Problems]
An object of the present invention is to provide an active matrix display device that enables a two-dimensional input method in view of the above-described problem of the one-dimensional input method. In order to achieve this objective, the following measures were taken. That is, pixels formed in a matrix using a pair of substrates facing each other; Said A scanning line provided corresponding to a row of pixels; Said Connect to each scanning line and the signal line provided corresponding to the pixel column Said A row driving circuit for selecting pixels for each row, and each row connected to each signal line Said In an active matrix display device including a column driving circuit for writing image signals to pixels, an odd number of rows Said Pixel And even row counter electrode Is assigned to one board, The counter electrode of the odd row and the Even row Said Pixels are assigned to the other substrate, and the row driving circuit includes: A first row driving circuit for driving the one substrate, and a second behavior driving circuit for driving the other substrate, wherein the first row driving circuit and the second row driving circuit are respectively By driving Pixel Said Odd lines and Said Even number rows are selected simultaneously, and the column drive circuit A first column driving circuit for driving the one substrate; and a second column driving circuit for driving the other substrate; and the first column driving circuit and the second column driving circuit By driving each, Selected at the same time Said Odd lines and Said Even rows Said Each pixel Said An image signal is written. Specifically, the above First Row drive circuit And the second row driving circuit At least two Said Odd lines And the second row drive circuit is at least Two Said Even rows Select at least A total of four Said Select rows of pixels simultaneously, the signal line is Said Four are provided together for the column of pixels, two of which are Said Placed on one board, the remaining two Said Arranged on the other substrate, First Column drive circuit And the second column driving circuit Are summarized in the four Said Belonging to four rows selected simultaneously via signal lines Said Each pixel Said Write image signal. In this case, First Column drive circuit And the second column driving circuit Has at least sixteen rows belonging to four rows Said For signal lines all at once Said Apply image signal to 16 pixels in 4 rows and 4 columns selected at the same time. Said Write image signal.
[0011]
The present invention also provides pixels formed in a matrix using a pair of substrates opposed to each other; Said A scanning line provided corresponding to a row of pixels; Said Connect to each scanning line and the signal line provided corresponding to the pixel column Said A row driving circuit for selecting pixels for each row, and each row connected to each signal line Said In an active matrix display device including a column driving circuit for writing image signals to pixels, one or more rows are combined into one set Said Odd set of pixels And even pairs of counter electrodes that combine one or more rows Is assigned to one board, The odd number of the counter electrodes and the even number of the pixels are Assigned to the other board, the signal line is Said A plurality of pixels are provided together for a pixel column. Said The same number as the number of lines in the odd set Said Placed on one substrate, Said The remaining number is the same as the number of rows in the even set. Said On the other board, The row drive circuit includes a first row drive circuit that drives the one substrate and a second behavior drive circuit that drives the other substrate, and the first row drive circuit and the second row drive circuit By simultaneously driving the row driving circuits, the pixels belonging to the odd group and the even group are simultaneously selected, The column driving circuit includes: A first column driving circuit for driving the one substrate; and a second column driving circuit for driving the other substrate, wherein the first column driving circuit and the second column driving circuit are By driving each, It was compiled into multiple lines for each row Said Selected simultaneously via signal line Said Odd group and Said Multiple belonging to an even set Said Each pixel Said An image signal is written.
[0012]
The present invention further includes pixels formed in a matrix using a pair of substrates facing each other; Said A scanning line provided corresponding to a row of pixels; Said Connect to each scanning line and the signal line provided corresponding to the pixel column Said A row driving circuit for selecting pixels for each row, and each row connected to each signal line Said Pixel Picture In an active matrix display device comprising a column driving circuit for writing image signals, The pixels are alternately assigned to one substrate and the other substrate every predetermined number of rows, and the counter electrodes are alternately assigned to the other substrate and the one substrate every predetermined number of rows. The substrate has a first row driving circuit and a first column driving circuit for driving the one substrate, and the other substrate has a second row driving circuit and a first row driving circuit for driving the other substrate. Two column drive circuits, Supplied in blocks of M rows and N columns (M and N are natural numbers of 2 or more) Said The image signal is sequentially processed in blocks of m rows and n columns (m and n are natural numbers of 2 or more). The first Column drive circuit And the second column driving circuit In Alternately Including signal processing circuit to be supplied Only The above First Row drive circuit And the second row driving circuit Is Said Select m rows of pixels simultaneously, First Column drive circuit And the second column driving circuit Belongs to n columns Said For signal lines all at once Said Apply image signal, m rows and n columns Said Batch to pixel Said An image signal is written. Preferably, the signal processing circuit is encoded in advance in units of M rows and N columns. Said The image signal corresponds to the pixels of M rows and N columns. Said Decode into an image signal. Further, the signal processing circuit has m = M and n = N. Said Performs sequential processing of image signals. Alternatively, the signal processing circuit has at least m as a divisor of M. Said Performs sequential processing of image signals.
[0013]
In the present invention, two means are combined to realize a two-dimensional input method. First, pixel portions and common electrode portions facing the pixel portions are alternately provided in units of rows on both of the two substrates. Here, the pixel portion and the common electrode portion may be arranged every other row or every two to several rows. In the two substrates, pixel rows are alternately arranged, and at least two rows can be simultaneously selected. As a result, two lines of pixel portions are provided on the upper and lower substrates, but the number of pixels can be divided into two as is, so that the number of signal lines is equivalently doubled. Accordingly, it is possible to simultaneously write image signals to two pixels arranged in the column direction with respect to two simultaneously selected rows. Thus, the number of pixels that can be turned on simultaneously is doubled by the first means. Second, on each substrate, at least two signal lines are provided for one of the pixel columns arranged vertically. The two signal lines are alternately connected one by one from the vertical pixel column. Further, two scanning lines are bundled. As a result, signals can be written to two of the vertically aligned pixel columns for the two selected rows. By this second means, the number of pixels that can be lit simultaneously is increased at least twice. Therefore, if the first structure and the second structure are combined, the number of pixels that can be lit simultaneously can be increased at least four times.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic diagram showing a basic concept of an active matrix display device according to the present invention. The panel 1 includes pixels formed in a matrix using a pair of substrates facing each other. The panel 1 is composed of a block 2 including a plurality of pixels. Each block 2 includes, for example, 4 × 4 = 16 pixels 3. The present invention is characterized in that image signals are simultaneously written in units of the block 2. In the example shown in the figure, the pixel 3 in 4 rows and 4 columns is set as one block, and image data in a two-dimensional format corresponding to this is written at once. Since the original digital compressed image to be written to the panel 1 is established in units of blocks, according to this method, it is possible to directly decode the compressed form and write it to the panel 1, thereby improving the signal processing efficiency. it can.
[0015]
FIG. 2 schematically shows a conventional multiple pixel simultaneous writing method. As shown in the figure, in this conventional method, 16 image data arranged in a one-dimensional manner are simultaneously written in the block 2 having 1 row and 16 columns as a unit. However, since the 1-row, 16-column one-dimensional block has a different arrangement from the 4-row, 4-column two-dimensional block adopted as the compression mode, after the compressed data is decoded, the 4-row, 4-column block configuration is 1 It is necessary to rewrite the block configuration with 16 rows and 16 columns, which complicates signal processing and requires a large-capacity frame memory to once decompress compressed data.
[0016]
FIG. 3 is a schematic diagram showing a general configuration of the conventional active matrix panel shown in FIG. One substrate 4 is provided with scanning lines X arranged in a row, signal lines Y arranged in a column, and pixels 3 arranged in a matrix at the intersection of both. Each pixel 3 includes a pixel electrode 6 and a switching element 7. The switching element 7 is made of a thin film transistor, for example, and has a gate electrode connected to the scanning line X, a source electrode connected to the signal line Y, and a drain electrode connected to the pixel electrode 6. On the other substrate 5, a counter electrode 8a (common electrode) is formed on the entire surface. The substrate 4 and the substrate 5 are bonded to each other, and liquid crystal is sealed between them as an electro-optical material, for example.
[0017]
FIG. 4 is a schematic plan view showing a specific configuration of the active matrix panel according to the present invention shown in FIG. For easy understanding, parts corresponding to those of the conventional panel shown in FIG. In the conventional panel shown in FIG. 3, all the pixels are formed on one substrate 4 and only the counter electrode is formed on the other substrate 5, and the roles of both substrates are completely separated. On the other hand, the panel according to the present invention shown in FIG. 4 is characterized in that a pixel region and a counter electrode region are mixed in each substrate on a row basis. That is, the even-numbered pixels 3 are assigned to one substrate 4a, and the odd-numbered pixels 3 are assigned to the other substrate 4b. Here, a row driving circuit (not shown) connected to each scanning line X simultaneously selects the odd and even rows of the pixels 3. For example, in the first horizontal cycle, the first row of pixels 3 formed on the substrate 4b and the second row of pixels 3 formed on the substrate 4a are simultaneously selected. On the other hand, a column drive circuit (not shown) connected to each signal line Y writes image signals to the pixels 3 in the first and second rows selected simultaneously. Accordingly, an image signal can be simultaneously written into two pixels arranged in the column direction. In practice, the row driving circuit simultaneously selects at least two odd rows and two even rows for a total of four pixel rows. That is, the first row scanning line X and the third row scanning line X formed on the substrate 4b are commonly connected, and the row scanning circuit simultaneously selects the first row and the third row. Similarly, in the substrate 4a, the scanning line X corresponding to the second row and the scanning line X corresponding to the fourth row are connected in common, and the row driving circuit selects the second and fourth rows simultaneously. Therefore, the row driving circuit combines the substrates 4a and 4b and simultaneously selects the pixels in the first to fourth rows. On the other hand, four signal lines Y are collectively provided for the column of pixels. Among them, two are arranged on one substrate 4a, and the remaining two are arranged on the other substrate 4b. In this case, the column drive circuit writes image signals to the four pixels 3 belonging to the four rows selected simultaneously via the four signal lines Y. Further, the column driving circuit applies image signals to the 16 signal lines Y belonging to at least 4 columns all at once, so that the image signals are collectively applied to 16 pixels in 4 rows and 4 columns selected simultaneously. Can be written. In the above description, the horizontal direction of the screen is the row and the vertical direction is the column, but the horizontal direction of the screen may be the column and the vertical direction may be the row.
[0018]
The structure shown in FIG. 4 will be described in a more easy-to-understand manner by breaking it down into two configurations. FIG. 5A schematically shows the first feature of the structure of the present invention shown in FIG. The first feature of the present invention is that pixel regions and counter electrode regions 8 are alternately provided in units of rows on both of the two glass substrates 4a and 4b sandwiching the liquid crystal. In this example, the pixel portion and the counter electrode region 8 are arranged every other row, but may be arranged every two to several rows. In the two substrates 4a and 4b, pixel rows are arranged in a staggered manner, and when the odd and even rows adjacent to each other are selected at the same time, two pixels arranged in the vertical direction in the apparent column direction can be driven simultaneously. The row width assigned to the pixel portion and the row width assigned to the counter electrode region 8 may be equal or unequal. In the illustrated example, odd-numbered rows are allocated to one substrate 4b, and even-numbered rows are allocated to the other substrate 4a. As a result, when the pixel portion is viewed as a whole panel, two systems are provided. However, since the number of pixels is allocated to two substrates as is conventionally, the number of signal lines Y is equivalently doubled when viewed as the entire panel. Increased. If the signal line Y formed on one substrate 4a and the signal line Y formed on the other substrate 4b are positioned so as to overlap in the substrate thickness direction with respect to the same column, the aperture ratio of the pixel does not decrease. With such a configuration, the number of pixels that can be lit simultaneously increases at least twice.
[0019]
The second feature is that n signal lines are provided per pixel column on each substrate as shown in FIG. n is a natural number of 2 or more, and n = 2 in the illustrated example. Then, n signal lines are alternately connected from the vertical pixel column to n pixels one by one. In the illustrated example, the first pixel is connected to one signal line Y, the third pixel is connected to the other signal line Y, and the fifth pixel is connected to one signal line Y again. Yes. Further, n scanning lines X are bundled. In the illustrated case, the scanning lines X are bundled two by two. With this structure, it is possible to simultaneously light n pixels along a vertical column while simultaneously selecting n scanning lines X on the panel. In the illustrated example, since n = 2, the first-stage pixel and the third-stage pixel can be driven simultaneously.
[0020]
By combining the two structures shown in (A) and (B) above, for example, in the case of a dot-sequential writing display, m × n pixels (m and n are arbitrary natural numbers) can be lit in blocks. Further, even in an active matrix liquid crystal display of a line sequential writing type, n rows × all columns can be simultaneously written, and both the dot sequential method and the line sequential method can cope with two-dimensional signal input.
[0021]
In the example shown in FIGS. 4 and 5, pixels are allocated to both substrates every other row, but the present invention is not limited to this. As described above, it may be allocated every two to several lines. When allocating a plurality of rows as a unit, the row width of the pixel portion and the row width of the counter electrode region are not necessarily equal. If they are not equal, more pixels are formed on one substrate and the number of pixels on the remaining substrate is reduced. As described above, the display device according to the present invention has a general configuration in which an odd group of pixels in which one or more rows are combined into one set is assigned to one substrate, and one or more rows are combined into one set. An even set of combined pixels is assigned to the other substrate. A plurality of signal lines Y are provided together for the column of pixels 3, and the same number as the number of rows included in the odd set is arranged on one substrate, and the same number as the number of rows included in the even number set remains. Are arranged on the other substrate. The column driving circuit writes image signals to a plurality of pixels belonging to the odd-numbered group and the even-numbered group selected at the same time via signal lines grouped into a plurality for each column.
[0022]
FIG. 6 is a diagram schematically illustrating compression processing in units of 4 rows × 4 columns. An input signal digitized in advance by an AD converter (not shown) or the like is compressed by a method such as pixel thinning or bit thinning for each block of 4 rows × 4 columns. The compressed signal is processed by the packetization / bitstreaming circuit 12 and then transmitted to the reception set.
[0023]
FIG. 7 schematically shows a signal transmitted from the signal source of FIG. Data is sent for each field (1F), and the transfer clock is represented by CK1.
[0024]
FIG. 8 shows an example of a reception set for displaying an image signal transmitted from the signal source of FIG. 6, and basically uses the panel shown in FIGS. 4 and 5. That is, the pixel portion and the counter electrode are formed on the pair of substrates 4a and 4b in units of rows. Note that the receiving set may be formed integrally on a single substrate. main As a TFT region in the figure. The portion where the counter electrode is formed is represented as a counter region. The TFT regions formed on the substrate 4a are odd rows, the TFT regions formed on the substrate 4b are even rows, and both are arranged alternately. The TFT region formed on the substrate 4a is connected to the row drive circuit 14a via the scanning line X. Further, two signal lines Y are provided for each pixel column included in each TFT region, and a column drive circuit 15a is connected to these signal lines Y. Similarly, the pixels formed on the substrate 4b are driven by the row driving circuit 14b and the column driving circuit 15b. The compressed data supplied from the signal source shown in FIG. 6 is decompressed and analogized by the decoder / DA converter 13. The image signal developed for each block of 4 rows × 4 columns is directly distributed to the column drive circuits 15a and 15b. Since the column drive circuits 15a and 15b can write the image signal on the panel while maintaining the two-dimensional format of the image signal, there is no need to rearrange the image signals to the one-dimensional format as in the prior art, and the frame memory can be omitted.
[0025]
FIG. 9 schematically shows signals supplied from the decoder / DA converter 13 shown in FIG. 8 to the column drive circuits 15a and 15b. Since the decoder / DA converter 13 shown in FIG. 8 processes data in units of 4 rows × 4 columns = 16 pixels, the output is 16 pieces of data 11 to 44 as shown in FIG. The signals are sent in parallel to the column drive circuits 15a and 15b via the output lines. The transfer clock is CK3 = CK1 / (4 × 4). Pixels arranged in a matrix on the panel are divided into blocks of 4 rows × 4 columns. In any pixel block, data 11 is sequentially written according to the transfer clock CK3 to the pixel located in the first row and the first column. Further, the data 44 of FIG. 9 is written to the pixel located in the fourth row and the fourth column of each block.
[0026]
FIG. 10 shows an embodiment in which data compressed in units of blocks of 8 rows × 8 columns is displayed according to, for example, the MPEG standard. However, the reception set side basically has the configuration shown in FIG. 8, and sequentially performs processing in units of 4 rows × 4 columns. Therefore, in the embodiment of FIG. 10, the decoder / DA converter 13 expands the block data of 8 rows × 8 columns, and then processes the block data into 4 rows × 4 rows of block data and sends them to the column drive circuits 15a and 15b. ing. For this reason, the decoder / DA converter 13 requires the frame memory 16. However, the capacity of the frame memory 16 can be reduced as compared with the case where the data in the two-dimensional format is converted into the data in the one-dimensional format.
[0027]
As shown in FIGS. 8 and 10, the active matrix display device according to the present invention is provided corresponding to pixels formed in a matrix using a pair of substrates 4a and 4b facing each other, and the rows of pixels. A panel having scanning lines X and signal lines Y provided corresponding to the pixel columns is used. Further, it is provided with row driving circuits 14a and 14b, column driving circuits 15a and 15b, and a decoder / DA converter 13 (signal processing circuit) which are built in or externally attached to the panel. The row driving circuits 14a and 14b are connected to each scanning line X and select a pixel for each row. In addition, the signal processing circuit 13 converts the image signal encoded in units of blocks of M rows and N columns (M and N are natural numbers of 2 or more) in advance into M rows and N columns. Column To an image signal corresponding to the pixel. The column drive circuits 15a and 15b are connected to the signal lines Y and write image signals to the pixels in the selected row. As a feature of the present invention, the signal processing circuit 13 sequentially processes an image signal decoded in units of M rows and N columns in units of blocks of m rows and n columns (m and n are natural numbers of 2 or more). To the column drive circuits 15a and 15b. In this case, the row driving circuits 14a and 14b simultaneously select m pixel rows. The column drive circuits 15a and 15b apply image signals all at once to the signal lines Y belonging to n columns, and write the image signals to pixels in m rows and n columns at a time. In the embodiment of FIG. 8, the signal processing circuit 13 performs sequential processing of image signals with m = M = 4 and n = N = 4. In the embodiment of FIG. 10, the signal processing circuit 13 performs sequential processing of image signals with m being a divisor of M. That is, m = 4 for M = 8.
[0028]
【The invention's effect】
As described above, according to the present invention, the display can be lit in block units, and the image signal input method can be handled from the conventional one-dimensional format to the two-dimensional format, so that the digitized compressed image data is decoded within the display interface. This makes it possible to omit the frame memory and the like necessary for conversion to the conventional one-dimensional format. Further, since the number of pixels that are turned on at the same time increases, the operation speed of the display can be reduced, and an operation margin can be secured for high-speed display with a frame rate of 120 Hz or higher. The field high-speed display in which the refresh rate reaches 120 Hz or more is used for, for example, color display by the field sequential method and image quality improvement of moving images by the subfield technology. In addition, since data can be directly received and decoded / written together at the time of serial transfer after block compression, the data transfer rate to the display can be reduced, and power consumption can be reduced. That is, since the transfer clock frequency is reduced and the circuit size is also reduced, power consumption can be reduced accordingly.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a basic concept of an active matrix display device according to the present invention.
FIG. 2 is a schematic diagram showing a conventional method.
FIG. 3 is a schematic plan view showing a conventional display panel.
FIG. 4 is a schematic plan view showing an embodiment of a display panel according to the present invention.
FIG. 5 is a schematic plan view showing the structure of a display panel according to the present invention.
FIG. 6 is a schematic block diagram illustrating a signal source of a compressed image.
7 is a schematic diagram showing a signal output from the signal source shown in FIG. 6. FIG.
FIG. 8 is a block diagram showing an example of an active matrix display device according to the present invention.
FIG. 9 is a waveform diagram for explaining the operation of the active matrix display device shown in FIG. 8;
FIG. 10 is a block diagram showing another example of an active matrix display device according to the present invention.
FIG. 11 is a block diagram showing a signal processing system according to a conventional MPEG standard.
12 is a waveform chart for explaining the operation of the circuit shown in FIG.
FIG. 13 is a block diagram showing an example of a conventional active matrix display device.
14 is a waveform diagram for explaining the operation of the active matrix display device shown in FIG. 13; FIG.
FIG. 15 is a block diagram showing another example of a conventional active matrix display device.
16 is a waveform diagram for explaining the operation of the active matrix display device shown in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Panel, 2 ... Block, 3 ... Pixel, 4a ... Substrate, 4b ... Substrate, 6 ... Pixel electrode, 7 ... Switching element, 8 ... Counter electrode Area, 13 ... decoder / DA converter, 14a ... row drive circuit, 14b ... row drive circuit, 15a ... column drive circuit, 15b ... column drive circuit, X ... scanning line, Y ... Signal line

Claims (8)

And pixels formed in a matrix by using a pair of substrates facing each other, the scanning line provided in correspondence with rows of the pixels, and signal lines arranged corresponding to the columns of the pixels, each scan line a row driving circuit for selecting the pixels in each row are connected, in an active matrix display device comprising a column driver circuit for writing an image signal to the pixel of the selected row is connected to each signal line,
Assigned counter electrode of the pixel and the even rows of the odd rows on one substrate, the pixels of the even rows and the counter electrode of the odd-numbered rows are assigned to the other substrate,
The row drive circuit includes a first row drive circuit that drives the one substrate and a second behavior drive circuit that drives the other substrate, and the first row drive circuit and the second row drive circuit the row driving circuit by driving each selects the odd-numbered rows and the even rows of the pixels at the same time,
The column driving circuit includes a first column driving circuit for driving the one substrate and a second column driving circuit for driving the other substrate, and the first column driving circuit and the first column driving circuit the second column drive circuits to be driven respectively, the active matrix display device characterized by writing each said image signal to the pixel of the odd row and the even row are selected simultaneously. The first row driving circuit selects the odd row of at least two, the second row driver circuit selects the even rows of at least two rows of the pixels of a total of at least four At the same time,
The signal line is provided with collectively four for the columns of the pixels, of which two are arranged on the one substrate and the remaining two are arranged on the other substrate,
The first column driving circuit and the second column driving circuit via the signal line summarized in four said writes each of the image signals to the pixels belonging to the four rows selected simultaneously The active matrix display device according to claim 1. The first column driving circuit and the second row drive circuit, by applying the image signals simultaneously for at least four of the sixteen pieces of the signal lines which belong to the column, four lines simultaneously selected 3. The active matrix display device according to claim 2, wherein the image signal is written in a batch to 16 pixels in four rows. And pixels formed in a matrix by using a pair of substrates facing each other, the scanning line provided in correspondence with rows of the pixels, and signal lines arranged corresponding to the columns of the pixels, each scan line a row driving circuit for selecting the pixels in each row are connected, in an active matrix display device comprising a column driver circuit for writing an image signal to the pixel of the selected row is connected to each signal line,
Even number of sets of one or more of the odd sets of the pixels as a tuple row and one or more counter electrodes as a tuple row is assigned to one of the substrates, the said odd set of the counter electrode An even number of the pixels are assigned to the other substrate;
The signal line is provided with a plurality of collectively for the column of the pixel, of which the same number as the number of rows in the odd set disposed on one substrate, the number of rows included in the even group the same remaining number are arranged on the other substrate and,
The row drive circuit includes a first row drive circuit that drives the one substrate and a second behavior drive circuit that drives the other substrate, and the first row drive circuit and the second row drive circuit By simultaneously driving the row driving circuits, the pixels belonging to the odd group and the even group are simultaneously selected,
The column driving circuit includes a first column driving circuit for driving the one substrate and a second column driving circuit for driving the other substrate, and the first column driving circuit and the first column driving circuit the second column drive circuits to be driven respectively, via the signal lines are grouped into a plurality of each column simultaneously selected the odd sets and each of the image signals to the plurality of pixels belonging to the even set An active matrix display device. And pixels formed in a matrix by using a pair of substrates facing each other, the scanning line provided in correspondence with rows of the pixels, and signal lines arranged corresponding to the columns of the pixels, each scan line a row driving circuit for selecting the pixels in each row are connected, in an active matrix display device comprising a column driver circuit for writing images signal to the pixel of the selected row is connected to each signal line,
The pixels are alternately assigned to one substrate and the other substrate for each predetermined number of rows, and the counter electrodes are alternately assigned to the other substrate and the one substrate for each predetermined number of rows,
The one substrate has a first row driving circuit and a first column driving circuit for driving the one substrate,
The other substrate has a second row driving circuit and a second column driving circuit for driving the other substrate,
It said sequentially processed in blocks of M rows and N columns (M and N is a natural number of 2 or more) the image signal to m rows and n columns (m and n is a natural number of 2 or more) the block is supplied as a unit of the look including a signal processing circuit for supplying alternately to the first row driving circuit and the second column driving circuit,
Wherein the first row driver circuit and the second row drive circuit selects the rows of the pixels to the m simultaneous,
The first column driving circuit and the second row drive circuit, by applying the image signals simultaneously to the signal line belonging to the column of the n, the bulk to the pixels of m rows and n columns An active matrix display device for writing an image signal. It said signal processing circuit is active according to claim 5, characterized in that for decoding the image signal that has been encoded blocks of pre-M rows and N columns as a unit in the image signal corresponding to the pixels of M rows and N columns Matrix display device. Said signal processing circuit, an active matrix display device according to claim 5, wherein the processed serially the image signals as m = M and n = N. The signal processing circuit includes at least m active matrix display device according to claim 5, wherein the processed serially in the image signal as a divisor of M.

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