JPH06161385A - Active matrix display device - Google Patents

Abstract

PURPOSE:To provide the active matrix display device which provides excellent display quality on a large area and high definition screen and makes an accurate gradational display without depending upon the number of gradations. CONSTITUTION:This active matrix display device is equipped with plural parallel column-directional lines 1, plural row directional lines 2 crossing the lines 1 at right angles, many display pixels 3 connected to the intersections of the lines 1 and 2, and many select lines 4 connected to the display pixels 3 respectively; when each display pixel 3 is placed in display operation, a select voltage is supplied to the lines 1 and 2 at the same time, a gradation voltage for gradation level display is supplied to select lines 4 connected to respective display pixels 3 for displaying the same gradation level at the same time to display the respective pixels 3 selectively at the same time. Further, the gradation voltages are supplied by gradation levels to the select lines 4 corresponding to the gradation levels in order on a time-division basis, so that the gradation voltages for all gradation levels are supplied on the time-division basis in a one-frame period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display type active matrix display device, and more particularly, when a large-area screen or a high-definition screen is displayed by giving a margin to a selection time of display pixels in one frame period. Also relates to an active matrix display device capable of improving display image quality.

[0002]

2. Description of the Related Art Conventionally, a known active matrix display device, in particular, an active matrix liquid crystal display device, has a plurality of scanning lines arranged in parallel with each other, and a plurality of signal lines arranged in insulation orthogonal to each of the scanning lines. It is composed of a large number of display pixels respectively connected and arranged at the intersections of the scanning lines and the respective signal lines, and a common line connected to the respective display pixels, and each of the display pixels is usually connected to a scanning line to which a gate corresponds. A thin film transistor (TFT) whose drain is connected to the corresponding signal line;
It includes a source of FT and a liquid crystal element connected between the common lines. Each display pixel is selected by applying a scan pulse through the scan line and turning on the corresponding TFT, and the display signal is written through the signal line. In this case, the scanning pulse supplied to each display pixel is normally applied in a state where the timing is sequentially shifted from the first scanning line to the last scanning line. The larger the screen becomes and the finer the screen becomes, the larger the total number of scanning lines becomes, and if one frame time is unchanged, the number of scanning lines is inversely proportional to the number of scanning lines. The application time (scanning pulse width) of the scanning pulse, that is, the driving time of each display pixel is shortened. Therefore, in order to configure a liquid crystal display device having a large area and high definition screen, it is necessary to write a signal to a display pixel within a short pixel selection time and maintain the display content for a long time until the next frame. .

As a known liquid crystal display device that has tried to solve the above-mentioned problems, for example, Japanese Patent Laid-Open No. 7792/1993 has been proposed.
The means disclosed in No. 2 is known.

FIG. 8 shows an example of the known liquid crystal display device, and is a circuit configuration diagram showing a configuration portion related to one display pixel in the liquid crystal display device.

In FIG. 8, 50 and 51 are scanning lines,
52 and 53 are signal lines, 54 is a first thin film transistor (TFT), 55 is a voltage storage capacitor, and 56 is a second
Thin film transistor (TFT), 57 is a liquid crystal element, 5
Reference numerals 8 and 59 are AC power supply lines (common lines), and 60 is a ground line.

The first TFT 54, the voltage storage capacitor 55, the second TFT 56, and the liquid crystal element 57 constitute one display pixel. In this case, the gate of the first TFT 54 scans. The drain is connected to the line 50, the drain is connected to the signal line 52, the source is connected to the gate of the second TFT 56, and the voltage storage capacitor 55 is connected between the gate of the second TFT 56 and the ground line 60. The drain of the second TFT 56 is the AC power supply line 5
9, the source is connected to one end of the liquid crystal element 57, and the other end of the liquid crystal element 57 is connected to the AC power supply line 58. The first TFT 54 and the voltage storage capacitor 5
5 functions as a sampling and holding circuit, and the second TFT 55 functions as a buffer transistor.

The known liquid crystal display device having the above structure operates as described below.

Now, at a certain timing, when a scan pulse is applied to the scan line 50 and a signal voltage is applied to the signal line 52, the first TFT 54 becomes conductive and a voltage corresponding to the signal voltage is stored in the voltage storage capacitor 55. Accumulated in. Further, when the signal voltage is charged in the voltage storage capacitor 55, the second TFT 56 is brought into a conducting state, but the conducting state depends on the magnitude of the signal voltage, and its drain-source impedance is , Depending on the state of conduction. That is, when the signal voltage is maximum, the impedance is minimum, and conversely,
When the signal voltage is minimum, the impedance is maximum, and when the signal voltage is at an intermediate value, the impedance is also at an intermediate value. On the other hand, the liquid crystal element 57 is connected in series to the drain / source passage of the second TFT 56, and an AC voltage is supplied to both ends of these series connection circuits. This AC voltage is the impedance of the liquid crystal element 57 and the second TFT 56. Since the voltage is divided by the impedance of the liquid crystal element 57, the magnitude of the voltage of the AC voltage applied across the liquid crystal element 57 is determined by the value of the impedance of the second TFT 56, and the liquid crystal element 57 is included. In the display pixel, display with brightness corresponding to the magnitude of the voltage of the AC voltage applied across the liquid crystal element 57 is performed.

Thus, the known liquid crystal display device is
Since the signal voltage of the signal line 52 is stored in the voltage storage capacitor 55, even if the conduction time of the first TFT 54 is short, the liquid crystal element 57 surely corresponding to the magnitude of the signal voltage can be obtained.
It is possible to charge the battery and to store and hold the signal voltage with almost no loss for a relatively long period.

[0010]

In the known liquid crystal display device, the conduction time of the first TFT 54, that is, the scanning pulse width or the pixel selection time can be selected to be relatively short. Also in this case, if the total number of scanning lines is increased in order to configure a liquid crystal display device having a large area and high definition screen, it is necessary to further shorten the pixel selection time. In that case, the voltage storage capacitor 55
It is clear that the display quality is remarkably deteriorated because the signal voltage to the battery is not sufficiently charged and a difference between the signal voltage and the charging voltage occurs, and naturally, the known liquid crystal display device cannot cope with it. I have a problem.

Further, in various liquid crystal display devices including the known liquid crystal display device, in order to increase the number of display colors (the number of display gradations), the magnitude of the signal voltage applied to the signal line is set to the liquid crystal. From the threshold voltage of the element to the range of its saturation voltage, it is necessary to perform fine control according to the number of gradations, but in order to perform this control, all the elements in the display panel of the liquid crystal display device are required. It is necessary to apply a signal voltage to the display pixel with high accuracy, and for that purpose, it is necessary to sequentially switch the signal voltage of each signal line at each pixel selection time.
However, since each signal line has its wiring resistance, wiring capacitance, etc., there is a concern that the magnitude of the signal voltage may change or the voltage waveform may be deformed due to them, and the number of display colors ( When the number of display gradations) is increased,
There is also a problem that an accurate color number display cannot be performed.

The present invention eliminates these problems, and its purpose is to obtain good display quality even in a large-area and high-definition screen, and to provide accurate display even if the gradation level during display is increased. An object of the present invention is to provide an active matrix display device capable of displaying various gradations.

[0013]

In order to achieve the above-mentioned object, the present invention provides a plurality of column-direction lines arranged in parallel with each other, and a plurality of row-direction lines insulated and orthogonally arranged in the column-direction lines. A plurality of display pixels respectively connected and arranged at intersections of the respective column-direction lines and respective row-direction lines; and a plurality of selection lines respectively connected to the plurality of display pixels, wherein the plurality of display pixels are display elements. Each display pixel including a charge holding means and a display element driving means, and simultaneously supplying a selection voltage to each column direction line and each row direction line and displaying one same gradation level when displaying the plurality of display pixels. A grayscale voltage for displaying the grayscale level is simultaneously supplied to the selected line connected to the display line, so that each of the display pixels is selectively and simultaneously displayed. For each gradation level, the gradation lines are sequentially supplied to the selected line corresponding to the gradation level in a time-divisional manner, and the gradation voltage is supplied in a time-divisional manner for all the gradation levels within one frame period. Equipped with means.

[0014]

According to the above-mentioned means, a large number of display pixels connected and arranged at the intersections of the respective column-direction lines and the respective row-direction lines are not selected by the scanning pulse applied to each column-direction (scanning) line. Rather, when displaying a large number of display pixels, the display pixels that display the same gradation level,
A gradation voltage for displaying the gradation level is simultaneously supplied, the display pixel is selected by the supply of the gradation voltage, and the gradation level is displayed in the selected display pixel.

The gradation voltage is supplied to each display pixel in a time-divisional manner for each gradation level to be displayed, and the gradation voltage corresponding to all the gradation levels to be displayed is supplied. One cycle is made within one frame period.

As described above, the selection of a large number of display pixels in one frame period does not depend on the scanning pulses sequentially supplied to the scanning lines, but only on the number of gradation levels to be displayed by these display pixels. In this case, since the pixel selection time based on the number of gradation levels can be considerably longer than the pixel selection time based on the total number of scanning lines, it is preferable even in a large area and high definition screen. Image quality can be displayed, and moreover, accurate display corresponding to each gradation level can be performed.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a schematic configuration diagram showing a main part of an embodiment of an active matrix display device according to the present invention.

In FIG. 1, 1-1, 1-2, ...
..., 1-m is a column direction line, 2-1, 2-2, ...
..., 2-n are row-direction lines, 3-11, 3-12, ...
... 3-1n, 3-21, 3-22, ..., 3
-Mn is a display pixel, 4-1, 4-2, ...
n is a common line, 5-11, 5-12, ...
-1n, 5-21, 5-22, ..., 5-mn is a selection line, 6 is a column direction line selection means, 7 is a row direction line selection means, 8 is a common voltage supply means, and 9 is a gradation voltage. Supply means 10 is a control unit.

Then, the column-direction lines 1-1 to 1-
m and the row-direction lines 2-1 to 2-n are arranged in parallel at equal intervals, and the column-direction lines 1-1 to 1
-M and each row direction line 2-1 to 2-n are orthogonally arranged in the insulated state. One end of each column direction line 1-1 to 1-m is connected to the column direction line selection means 6, and one end of each row direction line 2-1 to 2-n is connected to the row direction line selection means 7. . Display pixels 3-11 to 3-mn are connected and arranged at the intersections of the column-direction lines 1-1 to 1-m and the row-direction lines 2-1 to 2-n, respectively. A matrix display panel is formed by arranging 3-11 to 3-mn in the column direction and n in the row direction. The common lines 4-1 to 4-n respectively extend in the row direction, and one ends thereof are commonly connected in the common voltage supply means 8. The common line 4-1 is commonly connected to the m display pixels 3-11 to 3-m1 arranged in the row direction, and the other common lines 4-2 to 4-n also correspond in a similar manner. It is commonly connected to the display pixels. Each of the selection lines 5-11 to 5-mn extends in the row direction, and one end of each of the selection lines 5-11 to 5-mn corresponds to the corresponding display pixel 3-11.
To 3-mn, and the other ends thereof are individually connected to the gradation voltage supply means 9. Further, the control section 10 is connected to the column direction line selection means 6, the row direction line selection means 7, the common voltage supply means 8, and the gradation voltage supply means 9, respectively, and controls these means 6 to 9 individually. I have to.

Continuing with FIG. 2, one display pixel, eg,
It is a circuit block diagram which shows an example of a structure of the display pixel 3-11.

In FIG. 2, 11 is a first thin film transistor (TFT), 12 is a second thin film transistor (TF).
T), 13 are capacitors, 14 is a liquid crystal element, and other components that are the same as those shown in FIG. 1 are denoted by the same reference numerals.

In the first TFT 11, the gate is in the column direction line 1-1 and the drain is in the row direction line 2-1.
The source is connected to the gate of the second TFT 12, and the drain of the second TFT 12 is connected to the common line 4-.
1, the source is connected to one end of the liquid crystal element 14, respectively. One end of the capacitor 13 is connected to the gate of the second TFT 12, the other end is connected to the common line 4-1, and the other end of the liquid crystal element 14 is connected to the selection line 5-11.
In this case, the first TFT 11 and the capacitor 13 serve as charge holding means, and the second TFT 12 serves as the display element (liquid crystal element) 1.
The liquid crystal element 14 and the liquid crystal element 14 constitute a display element.

Further, FIG. 3 is an example of a display on the matrix display panel of the present embodiment and a display explanatory view showing a display state of each display pixel at that time, where (a) is a display example and (b) is a display example. To (e) are display states of respective display pixels, (f)
Indicates the state of each gradation level.

In the example of FIG. 3, for simplification of description, the matrix display panel shown in FIG. 1 has five display pixels in each of the column direction and the row direction, and a total of 25 display pixels 3-11 to 25. 3-15, 3-21 to 3-25, ...
..., 3-51 to 3-55 (5 × 5 pixel matrix display panel), and
At the time of displaying each display pixel, four gradation levels,
,, shall be displayed.

The operation of this embodiment will be described below with reference to FIGS. 2 and 3.

First, in the first one frame period, the control section 10 controls the column direction line selection means 6, the row direction line selection means 7, and the common voltage supply means 8 from the column direction line selection means 6. Five column direction lines 1-1 to 1
-5, at the same time, a selection voltage is applied from the row-direction line selection means 7 to the five row-direction lines 2-1 to 2-5, respectively, and the common voltage supply means 8 is applied to the common line 4-1.
The common voltage is applied to 4 to 4-5. In this case, the display pixels 3-11 to 3-55, for example, the display pixel 3-1.
1, the column-direction line 1-1 and the row-direction line 2
The application of the selection voltage to -1 brings the first TFT 11 into the conducting state, and the application of the common voltage to the common line 4-1 brings the selection voltage of the row-direction line 2-1 into the conducting state. The capacitor 13 is charged through the capacitor to drive the second TFT 12 in a conductive state. In addition,
The application of the selection voltage and the application of the common voltage are continued until the end of the one frame period, during which the first T
The FT 11 and the second TFT 12 maintain the conductive state, and the charging voltage of the capacitor 13 is also maintained.

On the other hand, within this one frame period, the control unit 1
Based on the control of 0, the gradation voltage applying means 9 selects the selection line 5-11 at a predetermined timing, and the third gradation for displaying the gradation level through the selection line 5-11. If a voltage is applied, the liquid crystal element 14
Is charged by the third gradation voltage through the second TFT 12 in the conductive state, and the liquid crystal element 14 is driven by the charging so as to display a gradation level. Then, the supply of the third gradation voltage to the selection line 5-11 is stopped together with the supply of the fourth gradation voltage for displaying the next gradation level, for example, the gradation level. However, because the supply of the third gradation voltage is stopped, the impedance of the liquid crystal element 14 on the side of the selection line 5-11 becomes extremely high. This state is maintained until a gradation voltage of any gradation level is supplied to the display pixel 14.
At -11, the gradation level is continuously displayed.

Also, the next frame period is almost the same as the above-mentioned operation, but the display pixel 3-
The gray scale voltage supplied to the liquid crystal element 14 of 11 is not necessarily the one to which the third gray scale voltage is supplied again. For example, the fourth gray scale voltage for displaying the gray scale level is supplied. The supply timing is different from that in the previous frame period. When the fourth gradation voltage is supplied to the liquid crystal element 14 of the display pixel 3-11, the display of the gradation level is continuously performed in the display pixel 3-11.

Subsequently, in the 5 × 5 pixel matrix display panel, in the case of displaying a predetermined content by 4 gradation levels or more, here, as shown in FIG.
For example, the case where a display including the katakana "hi" is included is as follows. However, in this case, the order of the gradation voltages supplied via any of the selection lines 5-11 to 5-55 in the one frame period is the first for displaying the gradation level first. Second gray scale voltage for the display of the next gray scale level
, The third gradation voltage for displaying the gradation level, and the last is the fourth gradation voltage for displaying the gradation level.

First, within the first ¼ period of one frame period, a plurality of display pixels for displaying a gradation level are displayed in the gradation voltage applying means 9 under the control of the control section 10 here. Select lines 5-12, 5-22, 5-32 to 5-connected to the pixels 3-12, 3-22, 3-32 to 3-52, 3-42, 3-52 to 3-55.
52, 5-42, 5-52 to 5-55 are selected, and the selected selection lines 5-12, 5-22, 5-3 are selected.
2 to 5-52, 5-42, 5-52 to 5-55, and the display pixels 3-12, 3-22, 3-32 to 3-52, 3-42, 3-52 to 3- described above. The first grayscale voltage is supplied to 55, whereby the display pixel 3-
12, 3-22, 3-32 to 3-52, 3-42, 3
At -52 to 3-55, gradation levels are displayed at the same time, and this display is continued until the next frame period as described above.

Then, the second 1 in the one frame period
Within the / 4 period, a plurality of display pixels, which are the display pixels 3-13 to 3-1 in this case, are displayed by the gradation voltage applying unit 9 under the control of the control unit 10 in the same manner.
5, select line 5-connected to 3-23 to 3-25
13 to 5-15, 5-23 to 5-25 are selected,
These selected selection lines 5-13 to 5-15, 5
A second grayscale voltage is supplied to the display pixels 3-13 to 3-15 and 3-23 to 3-25 via −23 to 5-25, and thereby the display pixels 3-13 to 3-1.
In 5 and 3-23 to 3-25, gradation level display is simultaneously performed, and this display is continued until the next frame period.

Then, the third 1 in the one frame period
Within the / 4 period, a plurality of display pixels, which are the display pixels 3-11 and 3-2 in this case, are displayed in the gradation voltage applying unit 9 under the control of the control unit 10 in the same manner.
Select lines 5-11, 5-21, 5-31, 5-41, 5-5 connected to 1, 3-31, 3-41, 3-51
1 is selected, and these selected selection lines 5-11,
The display pixels 3-11, 3-21, 3-31, 3-41, 3 through 5-21, 5-31, 5-41, 5-51.
A third grayscale voltage is supplied to -51, which causes the display pixels 3-11, 3-21, 3-31, 3-41, 3-.
In 51, the gradation level is displayed at the same time,
This display is also maintained until the next frame period.

Finally, the fourth 1 in the one frame period
Within the / 4 period, a plurality of display pixels, here, display pixels 3-43 to 3-4, which display a gradation level in the gradation voltage applying means 9 are also controlled by the control unit 10.
The selection lines 5-43 to 5-45 connected to the 5 are selected, and the selected selection lines 5-43 to 5-4 are selected.
A fourth gray scale voltage is supplied to the display pixels 3-43 to 3-45 via the display pixel 3-43.
3 to 45, gradation levels are displayed at the same time, and this display is also maintained until the next frame period.
A display including a katakana "hi" character as shown in FIG.

The display operation within the next frame period is also
The display operation is almost the same as that described above. Similarly, a plurality of display pixels for displaying four gray scale levels or the like are sequentially selected within the frame period, and the selected display pixels are sequentially subjected to the first display. Further, the fourth gradation voltage is supplied, and the display having the required number of gradations (the number of colors) and the content of the required form is performed.

Next, FIG. 4 is a voltage waveform showing an example of the temporal history of the first to fourth gray scale voltages applied from the gray scale voltage applying means 9 to the selection lines 5-11 to 5-55. FIG. 4 is an example applied to the 5 × 5 pixel matrix display panel shown in FIG.

In FIG. 4, the vertical axis represents the voltage levels V1 to V4 of the first to fourth gradation voltages, and the horizontal axis represents time.

FIG. 5 is an operation characteristic diagram showing the relationship between the voltage applied to the liquid crystal element and the display brightness of the liquid crystal element, where the vertical axis is the display brightness and the horizontal axis is the applied voltage.

As shown in FIG. 5, in the liquid crystal element, display between four levels of display brightness (gradation level) or more is set by dividing the threshold value and the saturation level at substantially equal intervals. To achieve this, four applied voltages V as shown
1, V2, V3, V4 may be selected, and these voltages V1, V2, V3, V4 become the first to fourth gradation voltages V1, V2, V3, V4 in the gradation voltage applying means 9. To be selected.

Further, as shown in FIG. 4, when the liquid crystal element is driven by alternating current, the first to fourth gradation voltages V1 to V are applied.
4 should be substantially reversed in polarity.
To the fourth gradation voltages V1 to V4 are supplied for one cycle,
In the next cycle, the negative first to fourth gradation voltages (-V
1) to (-V4) are supplied, and the first to fourth gray scale voltages V1 to V4 having a positive polarity are supplied again in the next cycle. The polarities of the voltages V1 to V4 may be reversed.

The time course of the gray scale voltage applied from the gray scale voltage applying means 9 to each of the selection lines 5-11 to 5-55 is gradually increased or decreased stepwise as described above. Not only the thing but various forms can be used.

Here, FIG. 6 is a voltage waveform diagram showing an example of some forms of the time course of the gradation voltage.

In FIG. 6, (a) shows the case of displaying at two gradation levels, in which the first and second gradation voltages in the on / off state are used. (B) is a case of displaying a continuously changing multi-gradation level, in which case a gradation voltage (triangular waveform gradation voltage) that continuously increases or decreases is used. It can be adapted to analog driving such as (TV). (C) shows a case of displaying a multi-gradation level (non-uniformity between levels) that varies in a stepwise manner, in which case multi-step gradation voltages with nonuniform increase or decrease ratios are used, The non-linear characteristic based on the voltage dependency of the transmittance of the liquid crystal element can be corrected so as to be equidistantly viewed. (D) is a case of performing multi-gradation level display in which the selection order of the gradation levels is arbitrary. At this time, multi-step gradation voltages whose application order does not depend on the gradation levels are used. In addition, (a),
In the cases (b) and (c), the polarity of the gradation voltage is periodically inverted, but in the case (d), the polarity of the gradation voltage is also inverted arbitrarily. In the case of (d), since the polarity of the gradation voltage is random for each display pixel, it is possible to reduce flicker on the screen display such as flicker.

As described above, according to this embodiment, the pixel selection time of each display pixel 3-11 to 3-mn per frame in the liquid crystal display device is the scanning line (corresponding to the column direction line of this embodiment). ) Of the display pixels 3-11 to 3-mn to be displayed (the number of colors), and in the normal state, the total number of scanning lines is Since the number of gradations (the number of colors) is considerably smaller than that of the other, even if the matrix display panel of the liquid crystal display device has a large area and high definition, pixel selection in each display pixel 3-11 to 3-mn It is possible to take a long time, and thereby a display image with good display quality can be obtained.

By the way, when 256 is selected as the actual number of gradations and a frequency within the range of 25 to 50 Hz is selected as the liquid crystal AC drive frequency at which the screen flicker is not recognized in the liquid crystal display device, the pixel selection time is , For example, it becomes 78.1 μs, and the conventional device of this type (640
The pixel selection time of a matrix display panel (× 480 pixels), for example, 41.7 μs, is about 1.9 times longer.

Next, FIG. 7 shows one display pixel, for example,
It is a circuit block diagram which shows the other example of a structure of the display pixel 3-11, (a) is an example which omitted the common line 4-1, (b) omits the common line 4-1 and is the 1st TFT11. Is also an example omitting.

In FIG. 7, 15 is a series resistance,
In addition, the same components as those shown in FIGS. 1 and 2 are designated by the same reference numerals.

In the above example (a), the second
Connect the drain of the TFT 12 of to the scan line 1-1,
One end of the capacitor 13 is connected to the adjacent scan line 1-2. In addition, in the above (b), the first TFT1
Instead of 1, resistor 15 is used, in which case resistor 1
5 has one end on the row direction line 2-1 and the other end on the second TFT.
It is connected to 12 gates. At the same time, the second T
The drain of the FT 12 and one end of the capacitor 13 are connected to the scan line 1-1, respectively.

The operation of the embodiment in which the display pixels shown in the examples (a) and (b) are used for the display pixels 3-11 to 3-mn in FIG. 1 has already been described (FIGS. 1 and 2). Since the operation is the same as that of the embodiment (shown in FIG. 2), further description of the operation will be omitted.

However, in the case of the embodiment using the display pixel shown in the example of (a), only the display pixel 3-11 will be described. The common line 4-1 and the scanning line 1-
1 or 1-2 is also used, and the second TFT 12 is actually used.
By simplifying the circuit configuration of the portion related to, the yield and reliability of the matrix display panel are improved. Further, in the case of the embodiment using the display pixel shown in the example of (b), the effective value of the voltage applied to the capacitor 13 is different between the selected display pixel and the non-selected display pixel. The second applied voltage to the selected display pixel
Of the second TF of the selected display pixel by setting the applied voltage of the non-selected display pixel lower than the threshold voltage of the second TFT 12 of the second TF.
By setting only T12 to be in the conductive state, the same operation as that of the above-described embodiment (shown in FIGS. 1 and 2) can be performed.

As another embodiment, it is possible to use an electroluminescence (EL) element instead of the liquid crystal element 14 to form an active matrix EL display panel as a whole. In the case of this example, zinc sulfide (ZnS), calcium sulfide (CaS), and strontium sulfide (SrS) are used as a matrix on the substrate on which the first and second TFTs 11 and 12 are formed, and manganese (M
n), cerium (Ce), europium (Eu) and other transition metals or rare earths are added to the light emitting layer, and an insulating film made of yttrium oxide, silicon oxide, aluminum oxide or tantalum pentoxide is formed on one or both sides of the light emitting layer. ,
Finally, if the counter electrode is formed, an EL element can be constructed.

In the case of this example, the first and second TFs are
As T11 and T12, those having a withstand voltage of 100 V or more are required, and silicon (Si) as an active layer
Besides, the TFT using a II-VI group compound such as cadmium selenide (CdSe) is applicable.

[0053]

As described above, according to the present invention, the pixel selection time of each display pixel 3-11 to 3-mn per frame in the active matrix display device is
Since it is determined by the number of gradations (the number of colors) to be displayed in the display pixels 3-11 to 3-mn,
Even if the matrix display panel of the active matrix display device has a large area and high definition, each display pixel 3-
There is an effect that it is possible to lengthen the pixel selection time in 11 to 3-mn, thereby obtaining a display image with good display quality.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a main part of an embodiment of an active matrix display device according to the present invention.

FIG. 2 is a circuit configuration diagram showing an example of the configuration of one display pixel.

3A and 3B are a display explanatory view showing an example of display on the matrix display panel shown in the embodiment of FIG. 1 and a display state of each display pixel at that time.

FIG. 4 is a voltage waveform diagram showing an example of a temporal history of first to fourth gray scale voltages applied from a gray scale voltage applying means to each selection line.

FIG. 5 is an operating characteristic diagram showing the relationship between the voltage applied to the liquid crystal element and the display brightness of the liquid crystal element.

FIG. 6 is a voltage waveform diagram showing an example of some forms of the time course of the gradation voltage.

FIG. 7 is a circuit configuration diagram showing another example of the configuration of one display pixel.

FIG. 8 is an example of a circuit configuration diagram showing a configuration portion related to one display pixel of a known liquid crystal display device.

[Explanation of symbols]

1-1, 1-2, ..., 1-m column direction lines 2-1, 2-2, ..., 2-n row direction lines 3-11, 3-12 ,. 1n, 3-2
1, 3-22, ..., 3-mn Display pixels 4-1, 4-2, ..., 4-n Common lines 5-11, 5-12, ..., 5-1n, 5- Two
1, 5-22, ..., 5-mn selection line 6 column direction line selection means 7 row direction line selection means 8 common voltage supply means 9 gray scale voltage supply means 10 control section 11 first thin film transistor (TFT) 12 Second thin film transistor (TFT) 13 Capacitor 14 Liquid crystal element 15 Resistor

Claims (8)

[Claims] 1. A plurality of column-direction lines arranged in parallel with each other, a plurality of row-direction lines arranged orthogonally to the column-direction lines in an insulating manner, and connected and arranged at intersections of each column-direction line and each row-direction line. A plurality of display pixels and a plurality of selection lines respectively connected to the plurality of display pixels, each of the plurality of display pixels including a display element, a charge holding unit, and a display element driving unit are provided. When a pixel is displayed, a selection voltage is supplied to each column direction line and each row direction line at the same time, and the gradation level is displayed on the selection line connected to each display pixel that displays one and the same gradation level. The gradation voltages to be performed are simultaneously supplied so that the respective display pixels are selectively displayed at the same time, and the gradation voltage corresponds to the gradation level for each gradation level. An active matrix display device characterized in that the grayscale voltages are sequentially supplied to selected lines in a time-divisional manner and the grayscale voltages are supplied in a time-divisional manner for all grayscale levels within one frame period. 2. The active matrix display device according to claim 1, wherein the display element is a liquid crystal element. 3. The active matrix display device according to claim 1, wherein the display element is an electroluminescence (EL) element. 4. The active matrix display device according to claim 1, wherein the charge holding means includes a first thin film transistor (TFT) and a capacitor. 5. The active matrix display device according to claim 1, wherein the display element driving means comprises a second thin film transistor (TFT). 6. The active matrix display device according to claim 5, wherein a common line is provided to the plurality of display pixels, and the common line is connected to one end of the second thin film transistor (TFT). 7. The active matrix display device according to claim 1, wherein the gray scale voltage waveform supplied to the select line sequentially rises or falls stepwise within the one frame period. . 8. The active matrix display device according to claim 1, wherein the gray scale voltage waveform supplied to the select line sequentially rises or falls linearly during the one frame period. .