JP2005321745A - Display device and driving method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem; since there is a limit to the operation of a high temperature polysilicon TFT in a three-board system projection type liquid crystal display device using high temperature polysilicon, not only the whole system is increased in costs, but a liquid crystal panel is also increased in costs, since demand for higher brightness in recent years increases, and on the other hand, when a block sequential driving system is adopted, TFTs are produced separately for a pixel array part and a peripheral circuitry part. <P>SOLUTION: In the three-board system projection type liquid crystal display device 10 using high temperature polysilicon, a circuitry part for performing impedance conversion (buffering) of an analog video signal after D-A conversion is configured of two stages comprising LCD drivers 13R, 13G, 13B operating at a high speed of 1MHz or higher, and analog drivers 14R, 14G, 14B operating at a low speed of 1MHz or lower. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device and a driving method of the display device, and in particular, an electro-optic element and pixels including the electro-optic element are two-dimensionally arranged in a matrix and wired for each column of the matrix-like pixel array. The present invention relates to a display device configured to output a pixel signal through a signal line and a method for driving the display device.

  In recent years, the LCD TV market has expanded rapidly, and with the start of digital high-definition broadcasting in December 2003, LCD TVs are expected to become increasingly popular. This liquid crystal television includes a three-plate projection type using high-temperature polysilicon and a direct view type using amorphous silicon.

  Both the three-plate projection type and the direct-view type liquid crystal televisions are currently commercialized with a resolution of about 1280 × 720 and gradations of 6 to 8 bits, and are standard specifications for high definition (HD) televisions. The resolution is less than 1920 × 1080 (full HD specification) and gradation of 10 bits. Further, even when the input video signal is as low as 6 bits, if the number of gradations at the time of display is not increased, gradation deterioration is perceived in terms of image quality. Yes.

In the general three-plate projection type liquid crystal display device using high-temperature polysilicon shown in FIG. 20, the mobility of the high-temperature polysilicon TFT (Thin Film Transistor) is as large as 100 cm ² / V · s, and it is ON / OFF. Since the ratio can be sufficiently large, not only a pixel array portion in which pixels are arranged in a matrix but also a circuit portion for driving a signal line can be integrally formed on a glass substrate. Therefore, driving is performed by a block sequential driving method in which a plurality of signal lines are made into blocks (units), and analog video signals are sequentially sampled (simultaneous sampling of a plurality of dots) for each block.

  Specifically, the signal control unit 101 that processes and controls the digital video signal, and the digital video signal transferred from the signal control unit 101 is converted into an analog video signal (D / A conversion), and then the impedance is converted. An analog video signal is supplied to the R (red), G (green), and B (blue) liquid crystal panels 103R, 103G, and 103B by the LCD driver 102 having a function of converting (buffering), while these liquid crystal panels An analog video signal is sequentially sampled for each block by a shift register (not shown) provided in 103R, 103G, and 103B and supplied to a plurality of signal lines in the block. Simultaneous sampling of a plurality of dots written simultaneously is performed (see, for example, Patent Document 1).

JP-A-8-286640

  By the way, as shown in FIG. 21, the frequency of the dot (pixel) clock at a field frequency of 60 Hz with a graphics display standard higher than SVGA (Super Video Graphics Array) resolution increases as the resolution increases. Full-HD) reaches 160 MHz.

  However, in the three-plate projection type liquid crystal display device according to the above conventional example, high-temperature polysilicon can only operate at about 6 MHz. Therefore, when driving a full HD with a dot clock of 160 MHz, 24 (≦ 160 MHz / 6 MHz) pixels (dots) need to be simultaneously sampled by 24 dots, and 24 analog video signals input to each of the liquid crystal panels 103R, 103G, and 103B are required. As a result, the number of LCD drivers 102 is four per panel (when the number of outputs per LCD driver is six), which is a total of twelve, which increases the cost of the entire system.

  Further, in the three-plate projection type liquid crystal display device, with the recent increase in luminance of the light source, further reduction in the OFF current of the pixel TFT during light irradiation is required. However, since the reduction of the OFF current causes a decrease in mobility, it becomes difficult to normally operate the peripheral circuit integrally formed on the glass substrate. As a countermeasure against this, there is a method in which TFTs are separately formed in the pixel array portion and the peripheral circuit portion, but the number of steps increases and the cost increases. On the other hand, there is a method of reducing the W / L (channel width / channel length) of the pixel TFT and extending the writing time, but if the dot clock is 160 MHz full HD and block sequential driving is performed, the shift register circuit It is not possible to take a sufficient time for writing to the pixels in the last stage.

  As is apparent from the above description, in the conventional three-plate projection type liquid crystal display device using high-temperature polysilicon, the operation of the high-temperature polysilicon TFT is limited, which not only increases the cost of the entire system. However, as the demand for higher luminance has been increasing in recent years, when the block sequential driving method is adopted, it is necessary to make TFTs separately for the pixel array portion and the peripheral circuit portion, which increases the cost of the liquid crystal panel. .

  In addition, since the threshold variation of TFTs using polysilicon is as large as ± 0.5 V, not only multi-level display of 8 bits or more is difficult, but also the mobility is as low as 100 cm 2 / V · s. A liquid crystal display device with a dot clock of 40 MHz or higher cannot be driven.

  The present invention has been made in view of the above problems, and the object of the present invention is to realize a multi-pixel display with a multi-gradation of 8 bits or more and a dot clock of 40 MHz or more at low cost. And a driving method of the display device.

  In order to achieve the above object, in the present invention, pixels including electro-optic elements are two-dimensionally arranged in a matrix, and a signal line is wired for each column of the matrix-like pixel arrangement, and a pixel array unit and a digital In a display device comprising a digital / analog conversion means for converting a video signal into an analog video signal, the analog video signal output from the digital / analog conversion means is impedance-converted at a first operating speed, and Further, an impedance-converted analog video signal is further subjected to impedance conversion at a second operation speed lower than the first operation speed and supplied to the signal line.

  In the display device having the above-described configuration, the analog video signal output from the digital / analog converter is impedance-converted between the first circuit portion for impedance conversion at the first operation speed and the signal line of the pixel array portion. By interposing a second circuit portion that performs impedance conversion at a second operation speed slower than the operation speed of, for example, in a display device using a high-temperature polysilicon TFT having a limit in operation, block sequential (simultaneous sampling of a plurality of dots) ) Driving is possible without taking the drive. Thereby, the number of first circuit portions (drivers) can be reduced.

  According to the present invention, since the number of drivers can be reduced, the cost of the entire system can be reduced, and line-sequential driving can be performed, so that the pixel writing time can be extended. Therefore, the image quality can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration of a display device according to the first embodiment of the present invention. In this embodiment, for example, a three-plate projection type liquid crystal display device using high-temperature polysilicon adopting a full HD (dot clock; 160 MHz) driving method with a gradation of 10 bits and a resolution of 1920 × 1080 is given as an application example. Specific examples thereof will be described.

  As shown in FIG. 1, the three-plate projection type liquid crystal display device 10 according to the present embodiment is in addition to R (red), G (green), and B (blue) liquid crystal panels (display panels) 11R, 11G, and 11B. The liquid crystal panels 11R, 11G, and 11B have one system of signal control unit 12, three systems of LCD drivers 13R, 13G, and 13B, and analog drivers 14R, 14G, and 14B, respectively.

  FIG. 2 shows an example of the configuration of the liquid crystal panels 11R, 11G, and 11B. The liquid crystal panels 11R, 11G, and 11B have a configuration in which two transparent insulating substrates, for example, glass substrates are disposed to face each other with a predetermined gap, and a liquid crystal material is sealed between the two glass substrates. Pixels 21 are two-dimensionally arranged in a matrix on one glass substrate of the liquid crystal panels 11R, 11G, and 11B to form a pixel array unit 24. In the pixel array section 24, scanning lines 22-1 to 22-m are wired for each row with respect to a pixel array of m rows and n columns, and signal lines 23-1 to 23-n are wired for each column. Yes.

  FIG. 3 shows an example of the circuit configuration of the pixel 21. The pixel 21 includes a pixel transistor, for example, a TFT (Thin Film Transistor) 211, a liquid crystal cell 212 having a pixel electrode connected to the drain electrode of the TFT 211, and a storage capacitor having one electrode connected to the drain electrode of the TFT 211. 213. Here, the liquid crystal cell 21 means a liquid crystal capacitance generated between a pixel electrode and a counter electrode formed opposite to the pixel electrode. As the TFT 211, a polysilicon TFT having high mobility is used.

  The TFT 211 has a gate electrode connected to the scanning line 22 (22-1 to 22-m) and a source electrode connected to the signal line 23 (23-1 to 23-n). For example, the counter electrode of the liquid crystal cell 212 and the other electrode of the storage capacitor 213 are connected to the common line 27 in common for each pixel. A common voltage (a common electrode voltage) Vcom for driving the common electrode is applied to the common electrode of the liquid crystal cell 212 via the common line 27.

  On the same glass substrate as the pixel array unit 24, vertical drive circuits 25A and 25B are arranged on the left and right sides of the pixel array unit 24, for example, and a selector circuit 26 is arranged on the pixel array unit 24, for example. Yes. Here, the vertical drive circuits 25A and 25B are arranged on both the left and right sides of the pixel array unit 24. However, it is possible to adopt a configuration in which one vertical drive circuit 25 is arranged only on one of the left and right sides of the pixel array unit 24. is there. The vertical drive circuits 25A and 25B and the selector circuit 26 are also manufactured using polysilicon TFTs. On the other hand, a color filter (not shown) of each color (R, G, B) is provided for each pixel 21 on the other glass substrate of the liquid crystal panels 11R, 11G, 11B.

  The two vertical drive circuits 25A and 25B are configured by a shift register or the like. In these vertical drive circuits 25A and 25B, each shift register starts a shift operation in response to the vertical start pulse VST, and the vertical start pulse VST is converted into a vertical clock pulse VCK (generally, clock pulses having opposite phases to each other). By sequentially shifting in synchronization with (VCK, VCKX), the transfer pulses transferred at each transfer stage are sequentially output as scan pulses V1 to Vm. The scanning pulses V1 to Vm are sequentially applied to the scanning lines 22-1 to 22-m to select the pixels 21 in units of rows.

  The selector circuit 26 is configured by, for example, the number n of horizontal pixels, that is, the number k (= n / 2) of the switch circuits SW1 to SWk which is half the number n of the signal lines 23-1 to 23-n. These switch circuits SW1 to SWk are configured to have one input and two outputs, and k video signal input lines 28- for inputting analog video signals from the analog drivers 14R, 14G, and 14B to the liquid crystal panels 11R, 11G, and 11B. 1-28-k is connected to the input terminal, and one of the signal lines 23-1 to 23-n is connected to the odd signal lines 23-1, 23-3,. The other output terminals are connected to the even signal lines 23-2, 23-4,..., 23-n.

  Accordingly, the switch circuits SW1 to SWk connect the odd signal lines 23-1, 23-3,..., 23-n-1 and the even signal lines 23-2, 23-4,. By selecting, the analog video signals input by the video signal input lines 28-1 to 28-k are input to the pixels 21 in the row selected by the vertical scanning by the vertical drive circuits 25A and 25B. Writing is performed twice, divided into pixels and even-numbered pixels. Hereinafter, such driving is referred to as pseudo-sequential driving for line-sequential driving in which analog video signals are simultaneously written to all the pixels 21 in the selected row.

  Here, the analog video signals are selectively transmitted to the odd signal lines 23-1, 23-3,..., 23-n-1 and the even signal lines 23-2, 23-4,. An example of pseudo-line sequential driving by selecting two signal lines for supplying a signal is described as an example, but the present invention is not limited to pseudo-line sequential driving by selecting two signal lines, and analog video is selectively applied to four signal lines. 4 signal line selection for supplying signals, 6 signal line selection for selectively supplying analog video signals to 6 signal lines, and an analog video signal for selectively supplying 8 signal lines It is also possible to adopt pseudo line sequential driving by selecting eight signal lines.

  Further, as shown in FIG. 4, an analog video signal is input to the liquid crystal panels 11R, 11G, and 11B through n video signal input lines 28-1 to 28-n without selecting a signal line by the selector circuit 26. At the same time, the n video signal input lines 28-1 to 28-n and the n signal lines 23-1 to 23-n are directly connected, and directly from the video signal input lines 28-1 to 28-n. It is also possible to adopt complete line sequential driving in which analog video signals are input to the signal lines 23-1 to 23-n and the analog video signals are simultaneously written to the pixels 21 in the selected row.

  In FIG. 1 again, the signal control unit 12 performs processing for dividing the input digital video signals R, G, and B into, for example, an odd pixel and an even pixel every horizontal period, and the like. Various timing pulses for driving and controlling the LCD drivers 13R, 13G, 13B and the analog drivers 14R, 14G, 14B are generated based on the horizontal synchronization signal HSYNC, the vertical synchronization signal VSYNC, and the master clock CLK.

  The LCD drivers 13R, 13G, and 13B have a D / A (digital / analog) conversion function for converting a digital video signal transferred from the signal control unit 12 into an analog video signal, and also perform impedance conversion (buffering). Has function. The analog drivers 14R, 14G, and 14B are made of high-mobility transistors such as single crystal silicon, and have a function of sample-holding analog video signals supplied from the LCD drivers 13R, 13G, and 13B and performing impedance conversion again. ing.

  FIG. 5 shows characteristics for each output number of the LCD drivers 13R, 13G, and 13B with respect to the resolution with respect to the transfer speed (transfer frequency) from the LCD drivers 13R, 13G, and 13B to the analog drivers 14R, 14G, and 14B. As is apparent from this characteristic diagram, the number of outputs of the LCD drivers 13R, 13G, and 13B is determined so that the transfer frequency from the LCD drivers 13R, 13G, and 13B to the analog drivers 14R, 14G, and 14B is 1 MHz or more. Is desirable.

  FIG. 6 shows characteristics of the transfer speed (transfer frequency) from the analog drivers 14R, 14G, and 14B to the liquid crystal panels 11R, 11G, and 11B for each selected number of signal lines with respect to the resolution. As is apparent from this characteristic diagram, the transfer frequency from the analog drivers 14R, 14G, and 14B to the liquid crystal panels 11R, 11G, and 11B depends on the number of signal lines 23-1 to 23-n, but is 1 MHz. It is desirable to set as follows.

  In the three-plate projection type liquid crystal display device 10 using the high-temperature polysilicon according to the first embodiment having the above-described configuration, a circuit portion for impedance-converting (buffering) an analog video signal after D / A conversion is provided. LCD drivers 13R, 13G, and 13B that operate at a high operating speed (operating frequency) of 1 MHz, for example, and a second operating speed that is lower than the first operating speed, for example, an analog driver that operates at a low speed of 1 MHz or less. It is characterized by a two-stage configuration of 14R, 14G, and 14B. Thereby, the following effects can be obtained.

  That is, by interposing the analog drivers 14R, 14G, and 14B operating at low speed between the LCD drivers 13R, 13G, and 13B operating at high speed and the liquid crystal panels 11R, 11G, and 11B, the operation is limited to about 6 MHz. A liquid crystal display device using polysilicon TFTs can be driven by line sequential driving (including pseudo line sequential driving) without adopting block sequential (simultaneous sampling of multiple dots) driving. This means that the number of LCD drivers 13R, 13G, and 13B can be reduced.

  More specifically, the conventional high-temperature polysilicon can only operate at about 6 MHz and requires four LCD drivers (6 outputs x 4 = 24 outputs), whereas high movement of single crystal silicon or the like. Since the analog drivers 14R, 14G, and 14B manufactured with the same number of transistors can operate even when the drive frequency is 20 MHz or more, the number of LCD drivers per analog driver can be reduced to one (6 outputs). As a result, even if the analog drivers 14R, 14G, and 14B are inserted, it is only necessary to provide two drivers for each of the liquid crystal panels 11R, 11G, and 11B, for a total of six, thereby reducing the cost of the entire system. Can do.

  In addition, since line-sequential driving (including pseudo-line sequential driving) is possible, writing time to the storage capacitor 213 (see FIG. 3) of the pixel 21 can be increased, so that image quality can be improved. Can do. Further, since the W / L of the TFT 211 of the pixel 21 can be narrowed and there is no sampling circuit that operates at high speed on the glass substrate, the low-speed peripheral circuit section (vertical drive circuits 25A and 25B) and the pixel array section There is no need to make TFTs separately. Therefore, the liquid crystal panels 11R, 11G, and 11B can be provided at a low cost.

  In mounting the LCD drivers 13R, 13G, and 13B and the analog drivers 14R, 14G, and 14B, in the three-plate projection type liquid crystal display device, the LCD drivers 13R, 13G, and 13B have as few as 100 or fewer output pins. For this reason, the analog drivers 14R, 14G, and 14B are mounted on a PCB (Printed Circuit Board) board and have a large number of output pins, so it is desirable to mount them on COF (Chip On Film) or COG (Chip On Glass).

  However, the LCD drivers 13R, 13G, and 13B and the analog drivers 14R, 14G, and 14B can be both COF or COG mounted. When an LCD analog driver having an LCD driver function and an analog driver function on a single chip is configured, one chip may be COF or COG mounted.

  Hereinafter, specific examples of the LCD driver 13 (13R, 13G, 13B) and the analog driver 14 (14R, 14G, 14B) in the three-plate projection type liquid crystal display device 10 using high-temperature polysilicon according to the first embodiment will be described. The configuration will be described with some examples.

(Example 1)
FIG. 7 is a block diagram illustrating configurations of the LCD driver 13 and the analog driver 14 according to Example 1 of the first embodiment.

  In FIG. 7, the LCD driver 13 includes a sample hold circuit 131, a D / A converter circuit 132, and an analog buffer circuit 133 with an AC function. The sample hold circuit 131 samples and holds the digital video signal DS transferred from the signal control unit 12 in synchronization with the clock CK in response to the start pulse SP. The D / A converter circuit 132 converts the digital video signal sampled and held by the sample hold circuit 131 into an analog video signal and outputs the analog video signal. The analog buffer circuit 133 with an AC function performs impedance conversion (buffering) on the analog video signal output from the D / A converter circuit 132 and changes the polarity of the analog video signal to, for example, 1H (H is a horizontal period). ) To invert the video signal.

  The analog driver 14 is composed of an analog sample hold circuit 141 and an analog buffer circuit 142. The analog sample hold circuit 141 samples and holds the analog video signal transferred from the LCD driver 13 in synchronization with the clock ACK having a lower speed (frequency) than the clock CK in response to the start pulse ASP. The analog buffer circuit 142 performs impedance conversion (buffering) on the analog video signal output from the analog sample and hold circuit 141 and then transfers it to the liquid crystal panel 11.

  Thus, by providing the analog driver 14 operating at a lower speed than the LCD driver 13 between the LCD driver 13 and the liquid crystal panel 11, as described above, line sequential driving (including pseudo line sequential driving) is performed. In addition, the number of LCD drivers 13 can be greatly reduced, so that the circuit configuration of the entire system can be simplified and the cost can be reduced accordingly. Further, since the line sequential driving is possible, it is possible to take a long time for writing to the pixel 21, thereby making it possible to narrow down the W / L of the TFT 211 of the pixel 21, and the vertical drive circuits 25A and 25B and the pixel array. Since it is not necessary to make separate TFTs in the portion 24, it is possible to contribute to cost reduction of the liquid crystal panel 11.

  Further, as a modification of the first embodiment, as shown in FIG. 8, the LCD driver 13 and the analog driver 14 can be integrated into one chip and configured as an LCD analog driver 15 having both functions of the LCD driver and the analog driver. It is. Thus, by making the LCD driver 13 and the analog driver 14 into one chip, the cost of the entire system can be further reduced.

(Example 2)
FIG. 9 is a block diagram showing the configuration of the LCD driver 13, the analog driver 14, and the liquid crystal panel 11 according to Example 2 of the first embodiment. In FIG. 9, the same parts as those in FIG. Show.

  In the first embodiment, the analog buffer circuit 133 of the LCD driver 13 performs AC conversion for reversing the polarity of the analog video signal. In the second embodiment, the analog buffer circuit 133A of the LCD driver 13 is used. Only has an impedance conversion function, and the analog buffer circuit 142A operating at a low speed of the analog driver 14 has an alternating function for polarity inversion of the analog video signal, that is, the analog buffer circuit 142A has an addition function, for example. The analog buffer circuit having the configuration is adopted.

  By adopting such a configuration, in addition to the operational effects of the first embodiment, the following operational effects can be obtained. That is, the LCD driver 13 is not provided with an AC function for polarity inversion, so that the sample hold circuit 131, the D / A converter circuit 132, and the analog buffer circuit 133A of the LCD driver 13 are manufactured by a low withstand voltage process. Since the chip of the LCD driver 13 can be further reduced, the cost of the entire system can be further reduced.

  Incidentally, the analog driver 14 is a circuit portion that directly drives the liquid crystal panel 11 and is a circuit portion that handles an analog video signal that is originally converted into an alternating current, and thus is manufactured by a high withstand voltage process. Therefore, even if the analog buffer 142A of the analog driver 14 has an alternating function for polarity inversion, it does not become negative in the process.

  Further, as a modification of the second embodiment, as shown in FIG. 10, the LCD driver 13 and the analog driver 14 can be integrated into one chip and configured as an LCD analog driver 15 having both functions of the LCD driver and the analog driver. It is. Thus, by making the LCD driver 13 and the analog driver 14 into one chip, the cost of the entire system can be further reduced.

  By the way, various power supply voltages, for example, a power supply voltage VDD and a power supply voltage such as a common voltage Vcom for driving the counter electrode of the liquid crystal cell 212 are applied to the liquid crystal panel 11 from the outside of the panel. Here, as in the first embodiment (FIG. 7) and the second embodiment (FIG. 9), the common voltage Vcom is generated in the liquid crystal display device having the system configuration in which the LCD driver 13 and the analog driver 14 are mounted on different chips. The Vcom generation circuit is mounted on the analog driver 14 mounted with COF or COG, and the common voltage Vcom is applied from the analog driver 14 to the liquid crystal panel 11 via, for example, a flexible substrate (not shown). There are concerns about the following problems.

  Generally, when a power supply system including the power supply voltage VDD is input to the liquid crystal panel 11 from a power supply unit (not shown) different from the analog driver 14 via the flexible substrate, the end of the flexible substrate is On the other hand, the common voltage Vcom is input using the terminal pin inside the power supply system from the analog driver 14 while the terminal pin is used for input. Further, on the liquid crystal panel 11, the common line 27 (see FIG. 3) that transmits the common voltage Vcom is arranged along the periphery of the liquid crystal panel 11 so that the common line 27 has a role of shielding against static electricity or the like. That is, a method of wiring the outermost peripheral portion of the liquid crystal panel 11 is employed.

  As a result, the common voltage Vcom input to the liquid crystal panel 11 using the terminal pins inside the terminal pins on the flexible substrate of the power supply system such as the power supply voltage VDD becomes the power supply voltage VDD immediately after the input on the liquid crystal panel 11. Thus, it is led to the common line 27 that is wired to the outermost peripheral portion of the liquid crystal panel 11 beyond the power source line. That is, the power supply line such as the power supply voltage VDD and the common line 27 always intersect on the liquid crystal panel 11. As a result, since the wiring resistance of the power supply line such as the power supply voltage VDD or the common line 27 is increased, there is a concern that image quality defects such as lateral crosstalk may occur. The third embodiment described below is made in consideration of this point.

(Example 3)
FIG. 11 is a block diagram showing configurations of the LCD driver 13, the analog driver 14, and the liquid crystal panel 11 according to Example 3 of the first embodiment. In FIG. 11, the same parts as those in FIG. Show.

  In FIG. 11, a Vcom generation circuit 134 that generates a common voltage Vcom is mounted on the LCD driver 13 in addition to the sample hold circuit 131, the D / A converter 132, and the analog buffer circuit 133. The common voltage Vcom generated by the Vcom generation circuit 134 is input into the liquid crystal panel 11 via, for example, the outermost terminal pin of a flexible substrate (not shown).

  The common voltage Vcom input into the liquid crystal panel 11 is given to the common line 27 wired along the periphery of the liquid crystal panel 11 via the contact portion 28, and the liquid crystal cell 212 is connected via the common line 27. The common electrode is applied to the counter electrode. The common line 27 has a role of shielding against static electricity or the like by being wired in the outermost peripheral portion of the liquid crystal panel 11.

  On the other hand, each voltage of the power supply system, for example, the power supply voltage VDD, is inputted into the liquid crystal panel 11 from a power supply unit (not shown) through terminal pins inside the common voltage Vcom of the flexible substrate. The power supply voltage VDD input into the liquid crystal panel 11 is supplied to circuit units such as the vertical drive circuits 25A and 25B by a power supply line 29 wired inside the common line 27.

  As described above, in the liquid crystal display device having the system configuration in which the LCD driver 13 and the analog driver 14 are mounted on different chips, the Vcom generation circuit 134 that generates the common voltage Vcom is replaced with an analog buffer circuit that is a first impedance conversion unit. The common voltage Vcom is mounted on the same chip as 133, that is, on the LCD driver 13, and the common voltage Vcom is directly supplied from the LCD driver 13 to the liquid crystal panel 11 without going through the analog driver 14, whereby the common voltage Vcom is supplied to the power supply on the flexible substrate. Input can be made into the liquid crystal panel 11 using terminal pins outside the system terminal pins.

  Thereby, on the liquid crystal panel 11, it is possible to avoid the common line 27 wired in the outermost peripheral portion of the liquid crystal panel 11 from intersecting with the power supply line 29. An increase in the wiring resistance of the line 29 can be suppressed, and the wiring resistance of the common line 27 or the power supply line 29 can be reduced. As a result, it is possible to reduce image quality defects such as lateral crosstalk caused by an increase in the wiring resistance of the common line 27 or the power supply line 29, so that the image quality can be improved.

  However, the intersection of the common line 27 and the power supply line 29 on the liquid crystal panel 11 can be avoided, but the common line 27 and the power supply line 29 intersect on a drive board (not shown) on which the LCD driver 13 and the like are mounted. It will be. However, unlike the intersection on the liquid crystal panel 11, the lead wiring can be formed by, for example, copper wiring on the drive board, and the wiring resistance of the lead wiring is low. Therefore, the lead wiring for the common voltage Vcom, the power supply voltage VDD, etc. There is no problem even if the power supply wiring crosses.

  In the third embodiment, the analog buffer circuit 133 in the LCD driver 13 is applied to the system configuration of the first embodiment (the LCD driver 13 has a medium breakdown voltage, for example, 16 V or less) having an AC function for polarity inversion. However, since the voltage (common voltage Vcom) output from the Vcom generation circuit 134 is the unipolar maximum voltage (for example, 7.5 V) of the analog video signal, the analog in the analog driver 14 The buffer circuit 142A can be similarly applied to the system configuration of the second embodiment (the LCD driver 13 has a low breakdown voltage, for example, 8 V or less) having an AC function for polarity inversion.

  In the third embodiment, the common voltage Vcom is directly supplied from the LCD driver 13 to the liquid crystal panel 11 without using the analog driver 14. However, the common voltage Vcom is not necessarily directly supplied, for example, an external Vcom buffer (not shown). ) May be supplied to the liquid crystal panel 11. In this case as well, the analog driver 14 is supplied.

  In each of the above-described embodiments and modifications thereof, the selector circuit 26 is mounted on the liquid crystal panel 11, and pseudo line sequential by 2-signal line selection (or 4-signal line selection, 6-signal line selection, 8-signal line selection, etc.) is performed. Although the case where the present invention is applied to a driving liquid crystal display device has been described as an example, as shown in FIG. 4, an analog video signal input from the outside of the panel is not selected in the selected row without selecting a signal line by the selector circuit 26. The present invention can be similarly applied to a liquid crystal display device that is completely line-sequentially written to each pixel at the same time.

  However, the configuration in which the selector circuit 26 is mounted on the liquid crystal panel 11 can reduce the number of analog buffer circuits (impedance conversion circuits) corresponding to the number of the video signal input lines 28-1 to 28 -k. Since the chip can be made smaller, the cost of the entire system can be further reduced. In this case, if the number of selected signal lines is increased, the operation of the impedance conversion circuit unit that should be operated at a lower speed becomes faster, so the number of selected signal lines is the maximum even when the operation of the impedance conversion circuit unit is maximum. It is desirable to set it to be 1 MHz or less.

  In each of the above-described embodiments and modifications thereof, AC conversion for polarity inversion is performed by the analog buffer circuit 133 at the previous stage or the analog buffer circuit 142A at the subsequent stage. However, the polarity is inverted by the D / A converter circuit 132. It is also possible to adopt a configuration in which the exchange is performed.

[Second Embodiment]
FIG. 12 is a block diagram showing a configuration of a display device according to the second embodiment of the present invention. In this embodiment, for example, a direct-view liquid crystal display device using amorphous silicon that employs a full HD (dot clock; 160 MHz) driving method with a gradation of 10 bits and a resolution of 1920 × 1080 is taken as an application example. A specific embodiment will be described.

  As shown in FIG. 12, in addition to the liquid crystal panel 31, the direct view liquid crystal display device 30 according to the present embodiment includes a signal control unit 32 and y gate drivers 33-1 to 33-y as vertical driving means. And x LCD analog drivers (source drivers) 34-1 to 34-x as horizontal driving means.

  The liquid crystal panel 31 has a configuration in which two transparent insulating substrates, for example, glass substrates are arranged to face each other with a predetermined gap, and a liquid crystal material is sealed between the two glass substrates, as shown in FIG. Similarly to the pixel array unit 24, on the one glass substrate, for example, the pixels having the circuit configuration shown in FIG. And a pixel array section 35 in which signal lines are wired for each column. As the pixel transistor, an amorphous silicon TFT is used.

  The signal control unit 32 processes and controls the digital video signal. The gate drivers 33-1 to 33-y are configured by a shift register or the like, and sequentially select each pixel of the pixel array unit 35 in units of rows. The LCD analog drivers 34-1 to 34-x D / A convert the digital video signal transferred from the signal control unit 32, and perform impedance conversion (buffering) on the analog video signal after the D / A conversion. After the above processing is performed, the gate drivers 33-1 to 33-y write all the pixels in the selected row of the pixel array unit 35 all at once (line-sequential driving).

  Thus, in the direct-view type liquid crystal display device 30 using amorphous silicon, the mobility of the amorphous silicon TFT is as small as 0.1 cm 2 / V · s, and the ON / OFF ratio of the TFT cannot be sufficiently obtained. LCD analog drivers 34-1 to 34-x for driving the TFT are not only difficult to manufacture on the glass substrate, but also the writing time of the pixel TFT needs to be sufficiently long. Line-sequential driving capable of securing time over one horizontal period is performed.

  By the way, the conventional direct-view type liquid crystal display device using amorphous silicon has one D / A conversion circuit part and one analog buffer part for each signal line of the pixel array part 35. It was. For this reason, in order to be able to be applied to full HD where multi-gradation such as 10 bits is required, since the circuit scale of each D / A conversion circuit unit is increased, an LCD analog driver (source driver) The cost of 34-1 to 34-x increases.

  In view of this point, in the direct-view liquid crystal display device 30 using amorphous silicon according to the present embodiment, the LCD analog drivers 34-1 to 34-x are connected to an impedance conversion unit (analog buffer unit) of the previous stage that operates at high speed. ) And a two-stage configuration of the subsequent impedance conversion section operating at a low speed. By adopting such a two-stage configuration, the number of D / A conversion circuit units provided in the previous stage of the impedance conversion circuit unit operating at high speed is reduced, and the impedance of the subsequent stage operating at low speed is reduced. A configuration supplemented by a conversion circuit unit can be employed. Thereby, since the circuit scale of the whole D / A conversion circuit part can be reduced, the cost reduction of the whole system can be achieved.

  Further, since the occupied area of the entire D / A conversion circuit unit can be reduced along with the reduction of the number of D / A conversion circuit units, the circuit scale of each D / A conversion circuit unit can be increased by the reduction amount. . This means that an increase in the circuit scale of each D / A conversion circuit unit can be allowed in order to make it applicable to full HD where multi-gradation such as 10 bits is required. That is, the gradation can be increased without increasing the scale of the entire D / A conversion circuit unit. As a result, the D / A conversion circuit unit can be shared not only for RGB colors (3 signal lines) but also for 12 signal lines at 1 MHz or higher, for example, full HD, with a gradation of 8 bits or more. Therefore, the effect of reducing the D / A conversion circuit portion in the chip area is extremely large.

  Hereinafter, specific examples of the LCD analog driver 34 (34-1 to 34-x) in the direct-view liquid crystal display device 30 using amorphous silicon according to the second embodiment will be described with some examples. To do.

(Example 1)
FIG. 13 is a block diagram showing the configuration of the LCD analog driver 34 according to Example 1 of the second embodiment. In FIG. 13, the LCD analog driver 34 includes a sample hold circuit 341, a D / A converter circuit 342, an analog buffer circuit 343 with an AC function, an analog sample hold circuit 344, and an analog buffer circuit 345.

  The sample hold circuit 341 samples and holds the digital video signal DS transferred from the signal control unit 32 in synchronization with the clock CK in response to the start pulse SP. The D / A converter circuit 342 converts the digital video signal sampled and held by the sample and hold circuit 341 into an analog video signal and outputs the analog video signal. The analog buffer circuit 343 with an AC function performs impedance conversion (buffering) on the analog video signal output from the D / A converter circuit 342, and inverts the polarity of the analog video signal every 1H, for example. Exchange video signals.

  The analog sample hold circuit 344 samples and holds the analog video signal output from the analog buffer circuit 343 with an AC function in synchronization with the clock ACK having a lower speed (frequency) than the clock CK in response to the start pulse ASP. . The analog buffer circuit 345 performs impedance conversion (buffering) on the analog video signal output from the analog sample hold circuit 344. The analog video signal output from the analog buffer circuit 345, that is, the analog video signal output from the LCD analog driver 34 is simultaneously written to each pixel in the selected row through each signal line of the pixel array unit 35 in the liquid crystal panel 31. It is.

  As described above, the impedance conversion circuit portion of the LCD analog driver 34 is connected to the analog buffer circuit 343 in the previous stage that operates at the first operating speed (operating frequency) and the second operating speed that is slower than the first operating speed. By adopting the two-stage configuration of the analog buffer circuit 345 in the subsequent stage that operates, as described above, the number of individual D / A conversion circuit sections of the D / A converter circuit 342 provided in the preceding stage of the impedance conversion circuit 343 is reduced. In addition, since the overall circuit scale of the D / A converter circuit 342 can be reduced, the chip size of the LCD analog driver 34 can be reduced, and the cost of the entire system can be reduced. Further, since the number of D / A conversion circuit units can be reduced, the circuit scale of each D / A conversion circuit unit can be increased. Therefore, the circuit scale of each D / A conversion circuit unit is increased to increase the number of gradations. be able to.

(Example 2)
FIG. 14 is a block diagram illustrating a configuration example of the LCD analog driver 34 according to the second example of the second embodiment. In FIG. 14, the same parts as those in FIG. 13 are denoted by the same reference numerals.

  In the first embodiment, the analog buffer circuit 343 in the previous stage performs AC conversion for reversing the polarity of the analog video signal. In contrast, in the second embodiment, the analog buffer circuit 343A in the previous stage simply has an impedance. An analog buffer circuit 345A having only a conversion function and having an alternating function for polarity inversion of the analog video signal is provided to the analog buffer circuit 345A operating at a low speed in the subsequent stage, that is, the analog buffer circuit 345A is an analog buffer having an addition function, for example The circuit configuration is adopted.

  By adopting such a configuration, in addition to the operational effects of the first embodiment, the following operational effects can be obtained. That is, the sample-and-hold circuit 341, the D / A converter circuit 342, and the analog buffer circuit 343A can be manufactured by a low withstand voltage process by not providing the analog buffer circuit 343A in the previous stage with an AC function for polarity inversion. Since the chip of the LCD analog driver 34 can be further reduced, the cost of the entire system can be further reduced.

  Incidentally, in the direct-view type liquid crystal display device, since the size of the liquid crystal panel 31 is large, the size of the LCD analog driver 34 (34-1 to 34-x) is small. The merit by reducing the chip size of the LCD analog driver 34 is greater than the merit by reducing the number of .about.34-x).

  As a modification of the first and second embodiments, as shown in FIGS. 15 and 16, an LCD analog driver 34, a sample hold circuit 341, a D / A converter circuit 342, and an AC machine analog buffer circuit 343 (343A) are provided. It is also possible to adopt a configuration in which the LCD driver 36 is separated from the analog driver 37 having the analog sample hold circuit 344 and the analog buffer circuit 345 (345A).

  FIG. 17 shows characteristics of the transfer speed (transfer frequency) from the LCD driver 36 to the analog driver 37 for each output number of the LCD driver 36 with respect to the resolution. As is clear from this characteristic diagram, it is desirable to determine the number of outputs of the LCD driver 36 so that the transfer frequency from the LCD driver 36 to the analog driver 37 is 1 MHz or higher.

  FIG. 18 shows characteristics of the transfer speed (transfer frequency) from the analog driver 37 to the liquid crystal panel 31 for each selected number of signal lines with respect to the resolution. Since amorphous silicon cannot provide TFT characteristics like low-temperature polysilicon, it cannot adopt a configuration for selecting a signal line like the three-plate projection type liquid crystal display device 10 using high-temperature polysilicon. However, if TFT characteristics such as low-temperature polysilicon can be obtained, a selector circuit may be provided on the liquid crystal panel 31 to select a signal line. In this case, although it depends on the number of selected signal lines, the transfer frequency from the analog driver 37 to the liquid crystal panel 31 is preferably set to 1 MHz or less.

  The setting of the transfer frequency of these analog video signals is the same as in the first and second embodiments. When applied to the first and second embodiments, the transfer frequency from the LCD driver 36 to the analog driver 37 may be read as the transfer frequency from the preceding impedance conversion unit to the subsequent impedance conversion unit. What is necessary is just to read the transfer frequency to the liquid crystal panel 31 with the transfer frequency to the liquid crystal panel 31 from the impedance conversion part of a back | latter stage.

  In each of the above-described embodiments and modifications thereof, the AC conversion for polarity inversion is performed in the analog buffer circuit 343 in the previous stage or the analog buffer circuit 345A in the subsequent stage, but the polarity inversion is performed in the D / A converter circuit 342. It is also possible to adopt a configuration in which the exchange is performed.

  Further, in the case of adopting the configuration of the modified example of the first and second embodiments, as shown in FIG. 19, a single LCD driver 36 (36-1 to 36-w) includes a plurality of analog drivers 37 (37-1). It is also possible to adopt a configuration for driving ˜37-x). According to this, since the number of LCD drivers 36 (36-1 to 36-w) can be reduced, the cost of the entire system can be further reduced.

  Next, when mounting the LCD analog driver 34 according to the first and second embodiments, the LCD analog driver 34 preferably has COF or COG mounting because of the large number of output pins. Further, when the LCD analog driver 34 is mounted separately from the LCD driver 36 and the analog driver 37 as in the modification of the first and second embodiments, the LCD driver 36 has a small number of output pins of 100 pins or less. Since the analog driver 37 is mounted on a PCB board and has a large number of output pins, it may be mounted COF or COG.

  In the second embodiment, the case where the present invention is applied to a direct-view type liquid crystal display device using amorphous silicon has been described as an example. However, the present invention is not limited to this application example, and low-temperature polysilicon is used. The present invention can be similarly applied to a conventional direct-view type liquid crystal display device. When applied to a direct-view type liquid crystal display device using low-temperature polysilicon, a selector circuit is provided on a liquid crystal panel (glass substrate) like the three-plate projection type liquid crystal display device 10 using high-temperature polysilicon. It is also possible to adopt a configuration for selecting a signal line.

  In the first and second embodiments, the case where the present invention is applied to a liquid crystal display device using a liquid crystal cell as an electro-optical element of a pixel has been described as an example. However, the present invention is limited to this application example. Instead, the present invention can be applied to all display devices that supply analog video signals to signal lines. For example, in addition to a three-plate projection type liquid crystal display device, the invention can also be applied to a two-plate projection type liquid crystal display device, a single-plate projection type liquid crystal display device, and a viewfinder (VF) used in a camcorder.

  Furthermore, the present invention can be applied to an organic EL display device using an organic EL (electroluminescence) element as an electro-optical element of a pixel. However, since the organic EL element does not require polarity inversion driving, the polarity inversion function must be removed. For this reason, the effect of cost reduction by adding an AC function for polarity reversal to a subsequent impedance converter that operates at a low speed cannot be expected, but a multi-gradation of 8 bits or more and a dot clock of 40 MHz or more. This is useful for an organic EL display device capable of displaying pixels.

1 is a block diagram showing a configuration of a three-plate projection type liquid crystal display device using high-temperature polysilicon according to a first embodiment of the present invention. It is a block diagram which shows the example of 1 structure of a liquid crystal panel. It is a circuit diagram which shows an example of the circuit structure of a pixel. It is a block diagram which shows the other structural example of a liquid crystal panel. It is a figure which shows the characteristic for every output number of the LCD driver with respect to the resolution about the transfer rate from the LCD driver in 1st Embodiment. It is a figure which shows the characteristic for every selection number of the signal line with respect to the resolution about the transfer speed from the analog driver in 1st Embodiment to a liquid crystal panel. It is a block diagram which shows the structure of the LCD driver and analog driver which concern on Example 1 of 1st Embodiment. FIG. 10 is a block diagram illustrating configurations of an LCD driver and an analog driver according to a modified example of the first embodiment. It is a block diagram which shows the structure of the LCD driver and analog driver which concern on Example 2 of 1st Embodiment. FIG. 10 is a block diagram illustrating a configuration of an LCD driver and an analog driver according to a modified example of the second embodiment. It is a block diagram which shows the structure of the LCD driver and analog driver which concern on Example 3 of 1st Embodiment. It is a block diagram which shows the structure of the direct view type liquid crystal display device using the amorphous silicon which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the structure of the LCD analog driver which concerns on Example 1 of 2nd Embodiment. It is a block diagram which shows the structure of the LCD analog driver which concerns on Example 2 of 2nd Embodiment. FIG. 10 is a block diagram illustrating a configuration of an LCD analog driver according to a modified example of the first embodiment. FIG. 10 is a block diagram illustrating a configuration of an LCD analog driver according to a modification of the second embodiment. It is a figure which shows the characteristic for every output number of the LCD driver with respect to the resolution about the transfer speed from the LCD driver in 2nd Embodiment. It is a figure which shows the characteristic for every selection number of the signal line with respect to the resolution about the transfer rate from the analog driver in 2nd Embodiment to a liquid crystal panel. FIG. 12 is a block diagram illustrating a configuration of an LCD analog driver according to another modification of the first and second embodiments. It is a block diagram which shows the structure of the liquid crystal display device of a 3 plate type projection type using general high temperature polysilicon. It is a figure which shows the relationship between resolution and a dot clock frequency.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Three-plate projection type liquid crystal display device, 11 (11R, 11G, 11B), 31 ... Liquid crystal panel, 12, 32 ... Signal control part, 13 (13R, 13G, 13B) ... LCD driver, 14 (14R, 14G, 14B) ... Analog driver, 15, 34 (34-1 to 34-x) ... LCD analog driver, 21 ... Pixel, 22 (22-1 to 22-m) ... Scanning line, 23 (23-1 to 23-n) ) ... Signal line, 24, 35 ... Pixel array section

Claims (16)

A pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix, and signal lines are wired for each column of the matrix-like pixel arrangement;
A digital / analog conversion means for converting a digital video signal into an analog video signal;
A first impedance conversion means for impedance-converting an analog video signal output from the digital / analog conversion means at a first operation speed;
Second impedance conversion means for converting an analog video signal output from the first impedance conversion means at a second operation speed lower than the first operation speed and supplying the analog video signal to the signal line; A display device comprising: The display device according to claim 1, wherein the second impedance conversion unit is made of single crystal silicon. The first impedance conversion means outputs an analog video signal subjected to impedance conversion as a unipolar signal,
The display device according to claim 1, wherein the second impedance conversion unit converts the impedance-converted analog video signal into an alternating current and outputs it as a bipolar signal. The display device according to claim 1, wherein the first impedance conversion unit and the second impedance conversion unit are mounted on the same chip. 5. The display device according to claim 4, wherein the first impedance conversion unit and the second impedance conversion unit are configured by one chip per display panel on which the pixel array unit is formed. . The display device according to claim 4, wherein the chip on which the first impedance conversion unit and the second impedance conversion unit are mounted is COF or COG mounted. The display device according to claim 1, wherein the first impedance conversion unit and the second impedance conversion unit are mounted on different chips. The said 1st impedance conversion means and the said 2nd impedance conversion means are comprised by one chip | tip per display panel in which the said pixel array part was formed. Display device. The display device in which the pixel array unit is formed, wherein the first impedance conversion unit includes one chip and the second impedance conversion unit includes a plurality of chips. 8. The display device according to 7. The electro-optic element is a liquid crystal cell;
A common voltage generating means for generating a common voltage for driving the counter electrode of the liquid crystal cell is mounted on the same chip as the first impedance converting means, and the pixel array portion is formed from the common voltage by the chip. The display device according to claim 7, wherein the display device is supplied to a display panel. The display device according to claim 10, wherein the second impedance conversion unit is made of single crystal silicon. The display device according to claim 10, wherein a common line for transmitting the common voltage supplied from the common potential generating unit is wired along a peripheral edge of the display panel. The display device according to claim 7, wherein the chip on which the second impedance conversion unit is mounted is mounted with COF or COG. The display device according to claim 13, wherein the chip on which the first impedance conversion unit is mounted is COF or COG mounted. A unit having a plurality of signal lines as a unit on the display panel on which the pixel array unit is formed, and supplying the analog video signal to the signal lines in the unit when selected. The display device according to claim 1. A pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix, and signal lines are wired for each column of the matrix-like pixel arrangement;
A driving method of a display device comprising: a digital / analog converting means for converting a digital video signal into an analog video signal,
A first step of impedance-converting an analog video signal output from the digital / analog conversion means at a first operating speed;
A second step of impedance-converting the analog video signal impedance-converted in the first step at a second operation speed lower than the first operation speed and supplying the analog video signal to the signal line. A display device driving method.

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