JPH0580722A - Multi-level driving method for liquid crystal display device, and circuit therefor - Google Patents

Abstract

PURPOSE:To provide the multi-level/multicolor signal driving circuit of the liquid crystal display device which makes a multi-level, multicolor display on a liquid crystal panel by inputting and converting digital display data which has multi-level, multicolor information into analog data, and temporary storing data of one line in the form of analog values. CONSTITUTION:The digital display data 100 are inputted in order to a shift register 102 and a latch 105 which have capacity smaller than the data capacity of one horizontal line and converted by a D/A converter 107 into the analog data, which are stored in a sample holding circuit in the form of the analog values; after data of one horizontal line are stored, a liquid crystal applied voltage corresponding to the display data is outputted to a signal line 114 through a buffer 113.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as an active matrix type liquid crystal display device, and more particularly to an image display method for converting digital display data into a corresponding voltage for multi-color / multi-gradation display. , Its device, its driving method, and its circuit.

[0002]

2. Description of the Related Art A conventional color liquid crystal display is a VDT T described in the Hitachi LCD Driver LSI Data Book (issued by the Semiconductor Division of Hitachi, Ltd. in March 1990).
An FT driver: HD66310T can be used for a signal drive circuit to form a drive circuit for a liquid crystal display. A conventional color liquid crystal display using HD66310T will be described with reference to FIGS.

FIG. 2 shows a block diagram of a conventional color liquid crystal display composed of a signal drive circuit. In this figure, 200 is display data, of which 200R is 3
Bit R data, 200G is 3 bit G data, 2
00B is 3-bit B data. Reference numeral 201 is a circuit for rearranging the display data 200, and reference numeral 202 is display data after rearrangement. Reference numeral 203 is a block diagram of a signal drive circuit configured by the HD66310T. In this conventional example, it is assumed to be configured by 640 × 3 (R, G, B) pixels in the horizontal direction. Since the number of signal lines output from the HD66310T is 160 and the number of necessary signal lines is 640 × 3 = 1920, a total of twelve HD66310T are required.
Therefore, the signal drive circuit 203 is the HD66310T.
It is a block in which 12 are collected. Rearrangement circuit 201
Has been converted into display data 202 suitable for the interface of the signal drive circuit 203. Signal drive circuit 203
Of these, 204 is a shift circuit, which fetches the display data 202 in synchronization with the fetch clock of 205. 20
A latch circuit 6 temporarily stores display data for one line in the horizontal direction, which is latched by a latch clock 207. A data decoding circuit 208 decodes the display data stored in the latch circuit 206, and supplies the decoded result to the voltage multiplexer 209. A voltage generation circuit 211 generates a 16-level liquid crystal applied voltage 214 from the input high level voltage 212 and the input low level voltage 213. The voltage multiplexer 209 converts the voltage corresponding to the display data into the 16-level liquid crystal applied voltage 21.
Select from 4 and output to the drain line 111. 11
Reference numeral 6 denotes a scan driving circuit, which controls the gate line 119 in response to an enable signal 117 for enabling the vertical first line and a clock 118 for sequentially selecting the line.
Reference numeral 120 is a color liquid crystal panel for displaying. The number of gate lines 119 depends on the number of vertical lines of the color liquid crystal panel 120.

Next, FIG. 3 shows an internal equivalent circuit of the color liquid crystal panel 120. The liquid crystal panel 120 is described as 640 × 3 (R, G, B) pixels in the horizontal direction and 480 lines in the vertical direction. 300 is one pixel unit,
In the pixel portion 300, 301 is a thin film transistor (hereinafter abbreviated as TFT), 302 is a thin film transistor.
Is a liquid crystal, 303 is a storage capacitor, and 304 is a counter electrode.
R, G, and B color filters are sequentially added to three consecutive pixels to form one pixel. For example, an R color filter is used for the pixel units 300-1-1, 300-1-2,
..., 300-1 to 480, G color filters to pixel units 300-2-1, 300-2-2, ..., 300-2-4
80, B color filters to the pixel units 300-3-1, 3
00-3-2, ..., 300-3-480, ..., 300-
1920-1, 300-1920-2, ..., 300-1
920-480.

Next, FIG. 4 shows a driving waveform of the pixel portion 300. In this figure, reference numeral 119 indicates a drive waveform of the gate line, VGH is a gate-on voltage, and VGL is a gate-off voltage. Reference numeral 111 denotes a drive waveform of the drain line, and 16 levels of drain voltage from V7 to -V7 are prepared. 304 is a counter voltage VCOM which is the voltage level of the counter electrode. Further, the drain voltage is V7 at a positive potential with respect to this counter voltage VCOM.
To V0, and −V0 to −V7 for negative potentials.

The operation of the drive circuit shown in FIG. 2 will be described.

The liquid crystal display has an R of 3 bits for each pixel.
Data 200R, G data 200G, B data 200B
Enter to display. At this time, the signal drive circuit 203
Has an input interface of 4 pixels × 3 bits, the display data 202
Sort the data into. In the signal drive circuit 203, the shift circuit 204 first synchronizes with the clock 205 in the horizontal direction 1.
The display data 202 for the line is fetched. Shift circuit 2
The latch clock 207 becomes active after the last display data for one line is captured in 04, and the data for one line is temporarily stored in the latch circuit 206 at the same time. The shift circuit 204 starts to fetch the display data of the next line again. In the latch circuit 206, the shift circuit 2
The data of the current line is stored until 04 latches all the data of the next line again. The shift circuit 204 and the latch circuit 206 sequentially repeat this. The data latched by the latch circuit 206 is decoded by the decoding circuit 208.
And is supplied to the voltage multiplexer 209 as a signal for selecting the 16-level liquid crystal application voltage 214. The voltage multiplexer 209 includes a voltage generation circuit 21.
16-level voltage 214 generated in 1 is supplied, and the voltage level corresponding to each display data is selected,
Output to the drain line 111.

The lines to be displayed among the gate lines 119 of the scan driving circuit 116 are sequentially selected in synchronization with the voltage output of the drain line 111. For example, when the voltage level for displaying the first line of the color liquid crystal panel 120 is output from each drain line 111, the clock 118 becomes active and the enable signal 117 that enables the first gate line 119-1 is activated. When activated, the first gate line is valid.
Next, when the voltage level for displaying the second line is output from each drain line 111, the clock 1
By making only 18 active, the second gate line 119-2 becomes effective. This operation is repeated in the third and subsequent lines.

Further, R data 200R and G data 200
Since each of the G and B data 200B is 3-bit data, the levels capable of gradation expression are 8 levels (2 to the power of 3). Since liquid crystal has a characteristic of being deteriorated when a direct current component is applied, it is necessary to make alternating current with a certain period. Therefore, with respect to the voltage level of the counter electrode 304 shown in FIG.
The liquid crystal application voltage 214 of a total of 16 levels is generated by the voltage generation circuit 211 so that all eight levels have positive and negative potentials.

A color liquid crystal panel 12 will be described with reference to FIGS.
The internal operation of 0 will be described based on the operations of the drain line 111 and the gate line 119. In FIG.
A gate line to be valid is selected from the gate lines 119. That is, the gate of the TFT 301 is turned on and a voltage is supplied from the drain line 111 to the drain of the TFT 301. The TFT 301 becomes conductive and the voltage level applied from the drain line 111 is changed to the liquid crystal 30.
2 and the storage capacitor 303. The liquid crystal 302, which has been twisted in advance, controls the amount of twist to be released by the application of this voltage, and controls the amount of light cutoff and light transmission to perform multicolor, multigradation display.

This operation will be described with reference to the drive waveform of FIG. When the voltage level of the gate line 119 is VGL, the gate is off, and when it is VGH, the gate is on. When the voltage level of the gate line 119 is VGH, for example,
When a positive potential voltage is applied to the counter voltage level VCOM of the counter electrode 304, a voltage level corresponding to display data among the liquid crystal applied voltages V0 to V7 is supplied to the liquid crystal 302 and the storage capacitor 303 from the drain line 111, accumulate. The actual value applied to the liquid crystal changes according to the accumulated voltage level, and it becomes possible to obtain gradations with different luminance. Then, through the color filter of each pixel section,
Realizes multiple colors and multiple gradations.

A plurality of TV TFT drivers; HD66300 described in the driver LSI data book are also used. The HD66300 has a configuration in which analog display data is input, amplified, and then output as a liquid crystal applied voltage from a signal line.

In FIG. 23, an analog type signal drive circuit for performing multi-color / multi-gradation display by inputting analog display data: H
FIG. 16 shows an internal block diagram of the D66300.

Reference numeral 2300 is analog display data, which is 2
Reference numeral 301 is a sample and hold clock, and 2302 is a sample and hold circuit. 2303 is a data line for transferring the data output from the sample hold circuit 2302, and 2304 is a buffer, which amplifies the analog data and outputs it as a liquid crystal applied voltage to the signal line 2305.

Next, the operation will be described in detail.

Since the signal drive circuit of FIG. 23 obtains the information regarding the gradation of each pixel at the voltage level of the analog display data 2300, the sample hold circuit 2302 synchronizes the analog display data 2300 with the sample hold clock 2301. Data is sequentially captured and data for 120 pixels is held at a voltage level. Sample and hold circuit 2
The signal 302 is held again until the signal for holding the sample-hold clock 2301 becomes valid again. Since the voltage level held by the sample hold circuit 2302 is output to the data line 2303, the voltage level is amplified by the buffer 2304, converted into a liquid crystal applied voltage, and output to the signal line 2305.

Further, as another conventional example, JP-A-59-2 is used.
There is a signal drive circuit described in "Liquid Crystal Display Device Drive Circuit" (Seiko Electronic Industry Co., Ltd.) in Japanese Patent Publication No. 19791. This conventional example will be described with reference to FIGS.

FIG. 24 is a block diagram of a signal drive circuit of this conventional example.

In FIG. 24, reference numeral 2400 is an input signal having a plurality of bits of logic information. 2401, 240
Reference numerals 2, 2403, 2404, 2405, and 2406 are storage circuits. 2407, 2408, and 2409 are latch signals, which store the contents of the input signal 2400. Furthermore, 2
410 is also a latch signal, and the storage circuits 2401 and 2402
The contents stored in 402 and 2403 are stored in the storage circuit 2404,
2405 and 2406 are operated to be stored. 241
1, 2412, and 2413 are storage circuits 2404 and 2 respectively.
405 and 2406 are signal lines for transferring the stored contents. 2414 is a switching circuit, and the signal line 2411,
The data transferred at 2412 and 2413 are switched.
2415 is a digital / analog conversion circuit (hereinafter, D / A
Abbreviated as converter. ). 2416 is a switching circuit, which outputs the output of the D / A converter 2415 to 2417,
The signal is distributed to one of the signal electrodes 2418 and 2419 and output. 2420 and 2421 are switching circuits 2414,
2416 selection signal. Further, 2422 is a memory circuit 2
401, 2402, 2403, 2404, 2405, 2
406, switching circuit 2404, D / A converter 24
15, a drive circuit having a circuit equivalent to the switching circuit 2416. 2423, 2424, and 2425 are latch signals equivalent to the latch signals 2407, 2408, and 2409. 2426, 2427, and 2428 are signal electrodes.

FIG. 25 is a timing chart showing the operation of the signal drive circuit shown in FIG.

Next, the operation will be described in detail.

In FIG. 25, the latch signals 2407, 2408, 2409, ... Within 1 scanning time from time t1.
Causes the contents of the input signal 2400 to be sequentially transferred to the latch 240.
1, 2402, 2403 ,. At time t2, the storage circuit 240 is activated by the latch signal 2410.
The contents of 1, 2402, and 2403 are signal lines 2411 and 24.
Storage circuits 2404 and 2405 via 12, 2413,
2406, ... The latch signals 2401, 2402, 2403, again within one scanning time from time t2.
, The contents of the input signal 2400 are sequentially stored in the storage circuit 24.
01, 2402, 2403, ... In the time interval td1, the storage circuits 2404, 2405, 240.
The output of 6 passes through the signal lines 2411, 2412, and 2413, but the signal line 2411 is selected by the switching circuit 2414 by the selection signals 2420 and 2421 and input to the D / A converter 2415. Further, the switching circuit 2416
Then, the output of the D / A converter 2415 is output to the signal electrode 2417 by the selection signals 2420 and 2421.

Further, in the time interval td2, the contents stored in the storage circuit 2405 are the switching circuits 2414, D.
It is output to the signal electrode 2418 through the / A converter 2415 and the switching circuit 2416. Similarly, time section t
At d3, the content stored in the storage circuit 2406 is output to the signal electrode 2419 through the switching circuit 2414, the D / A converter 2415, and the switching circuit 2416.

Signal electrodes 2417, 2418, 24
There are many driving circuits equivalent to the driving circuit 2422 depending on the number of signal electrodes such as 19, 2426, 2427, and 2428, and all the operations are the same.

[0025]

In the conventional signal drive circuit, in the case of the digital type configuration such as the conventional example HD66310, high-speed data processing is possible, but the circuit is increased as the number of gradations of one pixel increases. There is a problem that the scale increases. That is, since gradation control of 8 levels for one pixel is performed,
Although the bit width of the input data is 3 bits, when the bit width of the input data is doubled to 6 bits, the scale of the shift register and the latch circuit is doubled, and the scale of the decoder and the voltage multiplexer is 8. However, there is a problem in that the cost of the liquid crystal display device as a whole is increased due to the doubling.

Further, in the case of an analog type structure such as the conventional example HD66300, the gradation level becomes the voltage level of the input analog display data, and the liquid crystal applied voltage can be generated by amplifying the voltage level,
It is possible to easily realize multi-gradation such as full color. However, there is a problem that high-speed data processing is difficult because the voltage level of the analog display data to be input must be accurately maintained.

Further, in the method of generating a plurality of voltages externally and supplying them to the voltage multiplexer like the conventional example HD66310, it is easy to control the resistance ratio of the dividing circuit to the voltages of a plurality of levels, and the digital display data can be controlled. Since it is possible to generate the voltage to be applied to the liquid crystal necessary to obtain the display brightness expressed by, it was easy to set the display brightness expressed as digital display data according to the visual characteristics. ..

Furthermore, JP-A-59-21 described in the conventional example.
No. 9791 “Liquid Crystal Display Device Driving Circuit” (Seiko Denshi Kogyo Co., Ltd.), data for a plurality of pixels is
After sharing the A converter and converting to analog data,
Although the analog data is distributed to each pixel electrode, the timing at which the driving circuit outputs the analog data to the liquid crystal panel varies depending on each pixel electrode. Since the current liquid crystal display drives one horizontal line at the same time,
With the drive timing of the drive circuit, it becomes difficult to obtain a good display.

Further, in the case of displaying multi-color and multi-gradation on a color liquid crystal display, in the conventional example, the signal drive circuit is R,
Since the G and B display data are mixed regardless of each display data, the liquid crystal applied voltage supplied to the voltage multiplexer is
It is common to all R, G, and B pixels. For this reason, since the voltage level applied to each pixel cannot be controlled, the luminance characteristic of each pixel depends on the characteristic of the color filter or the like, which makes it difficult to balance the luminance of each pixel. For example, to get a halftone between black and white,
Since the same display data is input to R, G, and B from the system, the liquid crystal applied voltage is the same. Therefore,
By shifting the luminance characteristics of R, G, and B, it is possible to obtain white and black halftones with color shift.

Further, when the input image is a natural image, color correction is difficult and there is a problem that color reproducibility cannot be easily achieved.

Further, in the case of monochrome display on a normal CRT or the like, only the G data is validated for display.
At present, the liquid crystal display has no means to realize that function.

A first object of the present invention is to provide a signal driving method for a display device capable of high-speed data processing without increasing the circuit scale even if the number of gradations of one pixel increases, and the same. To provide a device.

Therefore, a second object of the present invention is to provide a signal driving method of a display device and a device therefor capable of implementing a relationship between digital display data and display brightness to be expressed according to visual characteristics.

Therefore, a third object of the present invention is to provide a signal driving method capable of simultaneously outputting analog data of one horizontal line to a signal electrode, and a circuit thereof.

A fourth object of the present invention is to provide a liquid crystal display driving method capable of color correction for each of R, G and B pixels, and a circuit thereof.

A fifth object of the present invention is to provide a liquid crystal display driving method and a circuit therefor capable of displaying a good quality even when the color display is switched to the monochrome display.

[0037]

In order to achieve the above first and third objects, the present invention has pixel portions arranged in a matrix, and each pixel portion has a switching element and a liquid crystal. In a multi-grayscale driving method of a liquid crystal display device in which light transmission is controlled by a display signal applied to the liquid crystal to display a pixel, digital display data having a capacity smaller than the number of signals output in parallel to a pixel portion is sequentially captured. , Temporarily store, convert the digital display data of this capacity into corresponding analog display data, sequentially capture a plurality of sets of the converted analog display data of this capacity, and capture the analog display data of the number of signals to be output in parallel. After that, it outputs at the same time. Further, in the present invention, the multi-gradation driving circuit of the liquid crystal display device sequentially fetches digital display data having a capacity smaller than the number of signals output in parallel to the pixel portion and temporarily stores the digital display data, and the digital display data having this capacity. A structure in which a unit for converting to corresponding analog display data and a unit for sequentially capturing a plurality of sets of the converted analog display data of this capacity, capturing the analog display data of the number of signals to be output in parallel, and simultaneously outputting the same And

Further, in the present invention, the pixel portions are arranged in a matrix, each pixel portion has a switching element and a liquid crystal, and light transmission is controlled by display data applied to the liquid crystal to display an image. In a liquid crystal display device that performs
Display data for horizontal lines is divided into N (N is an integer),
A means for sequentially fetching digital display data for 1 / N horizontal lines and temporarily storing it, a means for converting the digital display data for 1 / N horizontal lines into corresponding analog display data, and an analog for 1 / N horizontal lines A multi-gradation driving circuit having a structure in which a unit for sequentially fetching each display data and fetching one horizontal line of the analog display data and then simultaneously outputting the same to the pixel portion is used.

Furthermore, in the present invention, the pixel portions are arranged in a matrix, each pixel portion is composed of a switching element and a display portion, and a switching element is provided for each horizontal line of the pixel portion. In an image display device that applies display data to the display unit via the display unit to display a multi-gradation image, the horizontal direction of the pixel units arranged in a matrix is set to M.
(M is an integer), and the display device has M multi-gradation driving circuits arranged in the horizontal direction for applying display data for each horizontal line to each of the M-divided pixel portions, and arranged in the horizontal direction. The display data of the pixel portion, which is divided into M multi-gradation driving circuits in sequence, is divided into N (N is an integer) and 1 / (M
XN) means for sequentially fetching and temporarily storing corresponding digital display data for horizontal lines, and connected to the storage means,
Means for converting digital display data corresponding to 1 / (M × N) horizontal lines to corresponding analog display data each time it is taken in, and means connected to the converting means for taking in analog display data for 1 / M horizontal lines The M multi-gradation driving circuits have all the analog display data for 1 / M horizontal lines and then apply the horizontal display data for one horizontal line to the display pixel portion at the same time.

Further, in order to achieve the second object, in the present invention, the curve showing the relationship between the voltage applied to the liquid crystal and the brightness is approximated by a plurality of straight lines, and the curves are drawn so as to follow the loci of the plurality of straight lines. Determination means for determining which straight line the digital display data is approximated to in order to correspond the display brightness expressed by the digital display data and the voltage applied to the liquid crystal.
From the means for generating a current having a plurality of weights for each bit of the digital display data, one of the current values having a plurality of weights for each bit of the digital display data is selected by the selection means based on the result of the determination means. After that, the current value is added, converted into a voltage, and output.

Furthermore, in the present invention, a curve showing the relationship between the voltage applied to the liquid crystal and the brightness is approximated by a plurality of straight lines,
In order to match the display brightness expressed by the digital display data and the voltage applied to the liquid crystal so as to follow the trajectory of a plurality of straight lines, a judgment means for judging which straight line the digital display data is approximated, A unit for generating a current having a plurality of weights for each bit of display data and a variable voltage supplied to the current generator are used to make the weights variable, and based on the result of the determination unit, a plurality of bits are provided for each bit of the digital display data. After selecting one of the weighted current values by the selection means, the current values are added, converted into a voltage, and output.

Further, in the present invention, any one of the active matrix liquid crystal panel which constitutes each display pixel portion by the switching element and the liquid crystal, and the voltage of the n-th power level based on the inputted n-bit (n is an integer) display data. A driving method in a liquid crystal display device comprising a voltage selector for selecting whether or not and a X driving means capable of applying a selected voltage to each display pixel portion to obtain a gradation color having a display brightness of 2 n level. In the scanning time of one line in the X direction, that is, when the switching element is in the conductive state, different levels of voltage are sequentially applied to the power lines for the liquid crystal applied voltage of 2 n or less to display data. When a corresponding voltage is applied to the liquid crystal applied voltage power supply line, the selected voltage is propagated to each display pixel unit and accumulated in the liquid crystal.

Further, in order to achieve the first object, in the present invention, an active matrix liquid crystal panel which constitutes each pixel of a matrix display pixel section by a first switching element and liquid crystal, and the display pixel section. A scanning line selecting means for selecting the pixel on one horizontal line, and a voltage corresponding to the input n-bit (n is an integer) display data,
A driving device for a liquid crystal display device, comprising: an X driving unit that applies a voltage to each of the pixels selected by the scanning line selecting unit to obtain a gradation color having a display brightness of 2 n level. Is applied to the liquid crystal applied voltage power supply lines of at least 1 and up to 2 n power lines, and to the liquid crystal applied voltage power supply lines, a voltage of 2 n level is sequentially applied within the scanning time of one line in the X direction. And a means for driving the liquid crystal by propagating the voltage to each display pixel portion when the voltage corresponding to the display data is applied to the liquid crystal applied voltage power supply line, The gray scale corresponding to the display data is obtained.

In order to achieve the above fourth and fifth objects,
A liquid crystal display driving circuit according to the present invention is provided with R, G, B
In a color liquid crystal display drive circuit that controls display brightness by a voltage value applied to a liquid crystal panel having each pixel of n, R, G, and B display data of n bits are respectively generated.
Data conversion means for converting (> n) -bit display data, means for temporarily storing the m-bit display data,
Based on the means for generating a voltage of (2 m-th power) level and the temporarily stored display data, a voltage of any one of the (2 m-th power) levels is selected and output to the liquid crystal panel. And means for doing so.

The generating means and the outputting means may be replaced with digital / analog converting means for converting each of the m-bit display data into an analog signal.

The data conversion means may be configured to store the conversion constant, and the conversion constant may be read from the means for storing the conversion constant.

The data conversion means may include a plurality of data conversion circuits having different conversion contents for each of R, G and B.

There may be provided means for receiving a control signal from the outside and switching the display data bus connected to the input of the data conversion means to another display data bus.

Another liquid crystal display drive circuit according to the present invention is a color liquid crystal display drive circuit for controlling display brightness by a voltage value applied to a liquid crystal panel having R, G, B pixels. For each display data,
Means for taking in n-bit display data at any time and temporarily storing display data of a capacity that can be simultaneously output to the liquid crystal panel, and for each R, G, B display data (2 to the nth power)
Means for generating a level voltage, and for each of the R, G, and B display data, a voltage of any one of the (2 to the nth power) levels is selected based on the temporarily stored display data. And means for outputting to the liquid crystal panel.

[0050]

With respect to the first and third objects, in the present invention, a circuit for processing data, that is, a circuit for inputting data from the outside is constituted by a digital circuit to generate a signal drive circuit. The circuit that holds and outputs the data of the signal line is a mixed digital / analog circuit that is configured by an analog circuit. Regarding the digital circuit, a shift circuit or a latch circuit that converts high-speed digital display data into low-speed analog data, The digital / analog converter circuit is provided with a capacity smaller than that of the signal line output from the signal driver circuit. Further, as for the analog circuit, a sample hold circuit and a buffer circuit for sequentially storing low-speed analog data converted by the digital / analog conversion circuit are provided.

Further, with respect to this digital circuit, a shift circuit for converting high-speed digital display data into low-speed analog data, a latch circuit, and a digital / analog conversion circuit are provided for 1 / N horizontal lines. Further, with respect to this digital circuit, it is possible to integrate the digital / analog conversion circuit by configuring it with a data decoding circuit, a voltage multiplexing circuit, and a voltage dividing circuit.

As a result, the shift circuit, the latch circuit, and the digital / analog conversion circuit of the digital circuit are constructed with a capacity smaller than the capacity of the signal line output from the signal drive circuit.
It has a function of converting high-speed digital display data into voltage level of low-speed analog data.

Further, the shift circuit, the latch circuit, and the digital / analog conversion circuit of the digital circuit for 1 / N horizontal lines have the function of converting the high-speed digital display data into the voltage level of the low-speed analog data.

Furthermore, the sample-and-hold circuit of the analog circuit has a function of holding the analog data of the signal line at the voltage level for a certain period, and the buffer circuit converts the voltage level of the analog data into a liquid crystal applied voltage, It has the effect of outputting to a line.

Further, the data decoding circuit, the voltage multiplex circuit, and the voltage dividing circuit have a function of converting digital data into analog data, like the digital / analog conversion circuit.

Further, for the second purpose, the current generating means and the adding means have the function of adding the current value corresponding to each bit of the digital display data, converting it into a voltage and outputting it.

Further, the judging means for judging the digital display data and the selecting means for selecting any one of a plurality of currents per bit have a function of correcting the current value supplied to the adding means for each display data, This has the effect of approximating the curve of the relationship between the voltage applied to the liquid crystal and the brightness with a plurality of straight lines, and the function of making the relationship between the display data and the brightness according to the visual characteristics.

Furthermore, by varying the voltage supplied to the current generating circuit, it is possible to easily vary a plurality of straight lines that approximate the curve of the relationship between the voltage applied to the liquid crystal and the brightness, and the relationship between the display data and the brightness. Has the effect of making the relationship according to the visual characteristics.

Further, for the first purpose, in the present invention, X
It is possible to sequentially apply different levels of voltage to one power supply line within one scanning period in one direction, and to apply the voltage to each pixel of the liquid crystal panel only for a required voltage level application time. Further, by making it possible to set the application time of the voltage of different levels to the power supply line, it is possible to sufficiently cope with the change of the liquid crystal material, the voltage level, etc., only by changing the set value of the application time.

For the fourth purpose, the data conversion means for converting the n-bit digital data into m (> n) bits has a function of weighting the input n-bit display data. The means for generating a 2 × (2 m-th power) level voltage generates a positive / negative potential level to be applied to the liquid crystal from the processed m-bit display data inside the liquid crystal drive circuit. A voltage corresponding to m-bit display data is selected from the 2 × (2 m-th power) level voltage and output to the liquid crystal panel. Input display data amount 2 x (2 to the n-th power)
It is possible to supply a voltage level higher than the level to the liquid crystal panel, compensate for the characteristic difference of the color filter, and obtain good display quality.

Further, for the fifth purpose, means for fetching n-bit display data at any time and temporarily storing display data of a capacity capable of being simultaneously output to the liquid crystal panel,
Separating the means for generating a voltage of (n-th power of 2) level and the means for outputting to the liquid crystal panel for each display data bus of R, G, B means displaying each of R, G, B. It is possible to supply a voltage of (2 to the nth power) level for each data bus.

Further, depending on the characteristics of the display data, R,
By making it possible to change the contents of data conversion for each of the G and B display data, it is possible to perform color multicolor display with good quality even when switching to monochrome display.

The first embodiment of the present invention is shown in FIGS. 1, 5 and 6.
Will be described with reference to FIG.

FIG. 1 shows a digital / analog conversion (hereinafter referred to as Digital / Analog Converter) of the present invention.
ter: Abbreviated as DAC. ) System signal drive circuit according to an embodiment.

Reference numeral 100 denotes digital display data, which has a plurality of bit widths per pixel in order to realize multi-color / multi-gradation. In this embodiment, 6 pixels are input in parallel. 101 is a shift clock synchronized with the digital display data 100, and 102 is the digital display data 100.
Is a shift register that sequentially takes in. In this embodiment, the shift register 102 has 24 clocks corresponding to 4 shift clocks.
It is assumed that data for pixels is taken in. Reference numeral 103 is a data line output from the shift register 102. Reference numeral 104 is a latch clock, and 105 is a latch for simultaneously capturing the data for the 24 pixels. Even if the number of pixels to be input in parallel of the digital display data 100 is a plurality of pixels other than 6, the shift register 102 and the latch 1
The configuration is the same only by changing the capacity of 05. 106
Is a data line output from the latch 105. Reference numeral 107 is a DAC that converts digital data into analog data, and 108 is a data line that can simultaneously transfer analog data for 24 pixels. 109 is a sampling clock for sampling the analog data every 24 pixels, 110 is a sample hold circuit, and 111 is 240
It is a hold clock that simultaneously holds data for pixels. 112 is the output of the sample hold circuit 110
A data line for transferring data of 40 pixels, 113 is a buffer, 114 is a signal line, and the signal drive circuit of this embodiment has 240 signal lines 114. Although the number of signal lines 114 is 240 in the present embodiment, the sample-hold circuit 11 is dependent on the number of signal lines 114.
0, the configuration is the same only by changing the capacity of the buffer 113.

FIG. 5 shows a sampling clock generation circuit for generating the sampling clock 109 of the sample hold circuit 110 shown in FIG.

In FIG. 5, reference numeral 500 is a sampling clock generation circuit, which can be constituted by a shift register. Reference numeral 501 is an input enable signal, and 502 is an output enable signal.

FIG. 6 is a timing chart showing the operation of the signal drive circuit shown in FIG. In FIG. 6, (a) is a shift clock 101 and (b) is a latch clock 104, which are synchronized with the 6-pixel parallel digital display data 100-1 to 100-6 shown in (c) to (d), respectively. ..
(E) and (f) are data lines 106-1 to 106-24.
The data is updated in synchronization with the latch clock 104 in (b). (G) and (h) are obtained by converting the digital data 106-1 and 106-24 in (e) and (f) into analog data 108-1 and 108-24, and reducing the time scale. Since the signal line 114 for 240 pixels is included, the data of D1 to D240 is processed. (I), (j), and (k) show the operations of the sample and hold clocks 109-1, 109-2, and 109-10, which are sequentially valid as (i), (j), and (k). (L), (m), (n), and (o) show how sampling is performed inside the sample hold circuit 110. (P) is a hold clock 111 for synchronizing analog data of 240 pixels, and (q)
(R) is a synchronized buffer 114-1, 114-2
240 signal lines 113-1 and 11 output from 40
The operation of 3-240 is shown.

FIG. 7 shows a signal drive circuit which adopts a system in which a DAC is separated for each display data of R, G, B when color correspondence is applied to the signal drive circuit of the D / A system shown in FIG. Is shown.

In FIG. 7, 100R is R digital display data, 100G is G digital display data, and 100B is B digital display data. 102R is an R shift register, 102G is a G shift register, and 102B is B
For shift register. 103R is an R data line, 1
Reference numeral 03G is a G data line, and 103B is a B data line. 105R is an R latch, 105G is a G latch, 1
Reference numeral 05B is a B latch. 106R is a data line for R,
106G is a G data line, and 106B is a B data line. 107R is an R DAC, 107G is a G DAC, 1
07B is a DAC for B. 108R is a data line for R,
108G is a G data line, and 108B is a B data line.

The operation will be described again in detail with reference to FIG.

The shift register 102 sequentially takes in the digital display data 100 for 6 pixels in one cycle of the shift clock 101, and transfers the data for 24 pixels in 4 cycles collectively to the data line 103. The data of 24 pixels processed by the shift register 102 is latched by the latch 10.
Held at 5 simultaneously.

The state of this operation will be described with reference to FIG.
(C) and (d) are digital display data 100-1, 1
Although 00-6 is described, it is synchronized with the shift clock 101 in (a). Further, the latch clock 104 in (b) is obtained by dividing the shift clock 101 in (a) by four. By these two clocks, D1 of the digital display data 101-1 of (c) is converted to D1 of the data line 106-1 of (e), and the sequential operation is repeated.
D6 of the digital display data 101-6 in (d) is
It is converted into D24 of the data line 101-24 in (f).
Similarly, D25 of the digital display data 101-1 of (c) is replaced with D25 of the data line 106-1 of (e),
D48 of the digital display data 101-6 in (d) is
It is sequentially converted into D48 of the data line 106-24 in (f).

The DAC 107 shown in FIG. 1 repeats the operation of sequentially converting digital data for 24 pixels into analog data, and outputs the analog data to the data line 108. The digital-to-analog data is input to the sample and hold circuit 110 every 24 pixels, and is repeated 24 times after 10 times.
Data for 0 pixels is taken in.

In the conventional signal drive circuit, the shift register 102, the latch 105, and the DAC 107 required a circuit for 240 pixels, but according to the present invention, the circuit section has a circuit scale of about 1/10. Can be configured with.

Here, the sampling clock 10 is shown in FIG.
9 shows a sampling clock generation circuit 500 for generating 9. The sampling clock generation circuit 500 is a shift register that operates by receiving the enable signal 101 and the latch clock 104. That is, when the effective polarity of the enable signal 501 is set to the “high” level, the sampling clock 10 is input every time the latch clock 104 is input after the enable signal 501 becomes the “high” level.
It is effective from 9-1 to 109-10 in order. And
After enabling 109-10, enable signal 50
2 is valid.

This operation will be described with reference to FIG. (E)
The digital data 106-1 of is the analog data 108-1 of (g) described by reducing the time scale,
The digital data 106-24 in (f) is converted into the analog data 108-24 in (h). Then, the converted (g) analog data 108-1 to (h)
Analog data 108-24 are sampled every 24 pixels by the sampling clock 109-1 of (i) to the sampling clock 109-10 of (k),
The sampling data 110-1 of (l) is converted into the sampling data 110-240 of (o). still,
The (l) sampling data 110-1 to (o) sampling data 110-240 are held until the corresponding (i) sampling clock 109-1 to (j) sampling clock 109-10 become valid.
Then, when the hold clock 111 becomes valid after the data for 240 pixels has been gathered, signals from the signal line 113-1 of (q) to the signal of (r) are transmitted through the buffer 113 of FIG. 1 as shown in FIG. The liquid crystal applied voltage is output to the line 113-240.

Next, the operation of the signal drive means capable of color correction and capable of color correction in FIG. 7 will be described.

In FIG. 7, digital display data 100
Each of R, 100G, and 100B transfers two pixels in parallel, and a total of six pixels are transferred in parallel. That is, data having the same capacity as that of the signal drive circuit shown in FIG. 1 is sequentially input. The shift registers 102R, 102G, and 102B each have 8 pixels for each color, and 24 pixels in total for digital display data 1
00R, 100G, and 100B are data lines 103R and
Transfer to 103G and 103B. Then, like the signal drive circuit of FIG. 1, after capturing 24 pixels, the data is aligned by the respective data lines 106R, 106G, 106B after being latched by the respective latches 105R, 105G, 105B. Each of the DACs 107R, 107G, 107B is configured so that the weighting of each bit of the digital value of each of the data lines 106R, 106G, 106B is different, and even if the same data is input to each of the data lines 108.
The analog values appearing in R, 108G, and 108B are different. From this, color correction of each color is possible.

The operation after the sample hold circuit 110 is similar to that of the signal drive circuit shown in FIG. The signal drive circuit shown in FIGS. 1 and 7 can be integrated including the sampling clock generation circuit of FIG.

Another embodiment of the present invention will be described with reference to FIGS. 8 and 9.

FIG. 8 shows a digital signal drive circuit of the present invention.

In FIG. 8, reference numeral 800 is a decoder for decoding digital data, and 801 is a selection signal as a result of decoding. 802 and 803 are power lines, 804
Is a voltage dividing circuit as a plurality of voltage level generating means, 805
Is a multilevel liquid crystal applied voltage. Reference numeral 806 is a voltage multiplexer as a means for selecting a plurality of voltage levels according to a selection signal. Decoder 800, voltage dividing circuit 80
4 and the voltage multiplexer 809 are shown in FIGS.
It has a function corresponding to the DAC 107 in the embodiment shown in FIG.

FIG. 9 shows an embodiment in which the signal drive circuit shown in FIG. 8 is a color-compatible signal drive circuit capable of color correction.

In FIG. 9, 800R is an R decoder,
800G is a G decoder and 800B is a B decoder. 801R is an R selection signal, 801G is a G selection signal, and 801B is a B selection signal. 804R is a voltage dividing circuit for R, 804G is a voltage dividing circuit for G, and 804B is a voltage dividing circuit for B. The voltage dividing ratio can be changed according to each color. 805R is a multi-level liquid crystal applied voltage for R, 80R
5G is a multi-level liquid crystal applied voltage for G, and 805B is a multi-level liquid crystal applied voltage for B. 806R is a voltage multiplexer for R, 806G is a voltage multiplexer for G, 806B
Is a voltage multiplexer for B. Reference numeral 807R is an R data line, 807G is a G data line, and 807B is a B data line.

Decoders 800R, 800G, 800B,
The voltage dividing circuits 804R, 804G, 804B and the voltage multiplexers 806R, 806G, 806B have the same function as the above DACs 107R, 107G, 107B in combination for each color.

The operation of FIG. 8 will be described again in detail.

The operation in which the digital display data 100 appears on the data line 107 via the shift register 102 and the latch 105 is the same as the operation of the signal drive circuit shown in FIG. The decoder 800 decodes digital data of a plurality of bits of each pixel to obtain a selection signal 801. For example, in the case of realizing multi-color / multi-gradation with 3-bit data for each pixel, there are eight selection signals 801 raised to the power of 2 for each pixel, and any one of them is effective. In addition, the voltage dividing circuit 804
Then, multi-level liquid crystal application voltages 805 are generated from the power supplies 802 and 803, and when the selection signal 801 is for each pixel, eight levels of voltage are generated. Voltage multiplexer 8
At 06, the voltage level of the multi-level liquid crystal applied voltage 805 corresponding to the valid signal line in the selection signal 801 is selected and output to the data line 108.

The operation in which the voltage level of each pixel appearing on the data line 108 appears on the signal line 114 via the sample hold circuit 110 and the buffer 113 is the same as that of the signal drive circuit shown in FIG.

The operation of FIG. 9 will be described in detail.

In FIG. 9, R digital display data 10
The 0R, G digital display data 100G, and the B digital display data 100B are respectively R shift registers 102R,
G shift register 102G, B shift register 10
2B and R latches 105R, G latches 105G, B latches 105B, and respective data lines 106R, 1R
The operations appearing in 06G and 106B are similar to those of the signal drive circuit shown in FIG. Decoder 800R, 800
G and 800B are the data lines 106R, 106G, and 10
The digital data transferred by 6B is decoded and output as selection signals 801R, 801G, 801B of the voltage multiplexers 806R, 806G, 806B. Each voltage multiplexer 806R, 806G, 806B
Corresponding to the voltage dividing circuits 804R, 804G, 80
Liquid crystal applied voltage 805 of different levels generated by 4B
R, 805G, 805B are supplied and the selection signal 80
Since it is selected by 1R, 801G, 801B, even if the values of the digital display data 100R, 100G, 100B are the same, the data line 10 may be selected depending on the color characteristics.
It is possible to output different analog values to 8R, 108G, and 108B.

The voltage level of each pixel appearing on the data lines 108R, 108G and 108B is the sample hold circuit 11.
0, the operation that appears on the signal line 114 via the buffer 113 is the same as the operation of the signal drive circuit shown in FIG.
The signal drive circuit shown in FIGS. 8 and 9 can be integrated including the sampling clock generation circuit shown in FIG.

FIG. 10 shows a block diagram of a liquid crystal display device using the signal drive circuit of the present invention.

In FIG. 10, reference numeral 1000 denotes the signal drive circuit of the present invention described in FIG. 1, FIG. 7, FIG. 8, or FIG. The signal drive circuit 1000 is assumed to have the sampling clock generation circuit shown in FIG. 5 integrated therein. Reference numeral 120 denotes a color liquid crystal panel, which has a horizontal resolution of 640 dots and one dot is made up of 3 pixels each of R, G, and B, and the total number of pixels in the horizontal direction is 1920 pixels. Therefore, a total of eight signal driving means 1000 for outputting the 240 signal lines 114 are required. In the present embodiment, these eight are equivalent to M of the M multi-gradation drive circuits arranged in the horizontal direction described above. M is 8
Needless to say, it is limited to. An enable signal 1001 is connected to the adjacent signal drive circuit 1000.

Next, the operation will be described.

The digital display data 100 are all inputted to the eight signal driving means 1000-1 to 1000-8, and first, in synchronization with the shift clock 101, the first
240 pixels are input to the signal driving means 1000-1 of
Retained. 240 in the first signal drive circuit 1000-1
When the data for pixels is held, the enable signal 100
2-1 becomes effective, and the second signal drive circuit 1000-2
Works. The enable signal 1002-0 of the first signal drive circuit 1000-1 is fixed to the "high" level and is set so that the input operation can always be started from the beginning of the horizontal line data. Second and subsequent signal drive circuits 1
000 operates by inputting the “high” level of the enable signal 1002 output from the signal drive circuit 1000 in the previous stage. Then, the data for 240 pixels after the 240 pixels captured by the signal drive circuit 1000-1 are sequentially captured. The second signal drive circuit 1000-2 has 24
When the data for 0 pixels is fetched and held, the enable signal 100 is generated similarly to the first signal drive circuit 1000-1.
2-2 is made effective, and the same operation is repeated after the third signal drive circuit 1000-3.

The eighth signal drive circuit 1000-8 has 240
After the data for the pixel is fetched and held, the hold clock 111 becomes effective, and the liquid crystal applied voltage corresponding to the digital display data 100 changes from the signal lines 114-1 to 114-.
Output from a total of eight 1920 lines simultaneously. When the hold clock 111 becomes valid, each signal drive circuit 1000-1
From No. 1000 to No. 1000-8, by repeating the above operation, the operation of sequentially fetching the data of the horizontal line and outputting from the signal line 114 is repeated.

Further, the scanning circuit 116 is a circuit for sequentially scanning the scanning line 119, and when the scanning clock 118 becomes effective while the enable signal 117 is effective, the scanning line 1 becomes effective.
The top 19 lines are valid. Then, when the scan clock 118 is sequentially enabled while the enable signal 117 is disabled, the scan line 119 operates so as to be sequentially enabled from the second line. At this time, the scan clock 118 and the hold clock 1311 are synchronized clocks,
The liquid crystal applied voltage output from the signal line 114 is transferred to the desired pixel portion 300 by the scanning line 119.

The pixel section 300 includes a TFT 301 and a liquid crystal 30.
2 and a storage capacitor 303. When the scanning line 119 becomes effective, the TFT 301 is turned on, and the liquid crystal applied voltage transferred from the signal line 1314 is applied to the TFT 30.
The data is stored in the liquid crystal 302 and the storage capacitor 303 via 1.
When the next scanning line 119 becomes effective, T
The FT 301 is turned off, and the liquid crystal applied voltage is held in the liquid crystal 302 and the holding capacitor 303. The amount of light is controlled through the liquid crystal 302 according to the voltage level of the liquid crystal applied voltage to realize multicolor / multigradation display. In this embodiment, the horizontal resolution is 640 dots and 1 dot is R,
Eight signal drive circuits 1900 having 240 signal lines 1314 are used because each pixel is composed of three G and B pixels, but the number of signal drive circuits 1000 (M
The same is true even if the number) is increased or decreased.

Next, in the DAC described in the embodiment of the present invention shown in FIGS. 1 and 7, the correction means capable of implementing the display data and the luminance characteristic according to the visual characteristic will be described with reference to FIGS. , FIG. 13 will be described.

In FIG. 11, the horizontal axis represents the gradation number and the vertical axis represents the display luminance, and the gradation number-luminance characteristic according to the visual characteristic is represented by curve 1.
It is shown by 100. In this embodiment, the digital display data 100 input to the signal drive circuit shown in FIGS. 1 and 7 is described as one pixel of 4 bits. Therefore, since the number of gradations that can be expressed per pixel of the digital display data 100 is 16 (2 to the 4th power) gradations, when the digital display data 100 is the hexadecimal number F, it indicates the brightest display brightness. The gradation number indicated by the hexadecimal F data is No.
15, and the gradation number indicated by the hexadecimal E data is No1.
4, the gradation number corresponding to the intermediate display brightness in which the display brightness sequentially decreases is shown in FIG. 11, and the gradation number of hexadecimal 0, which is the data indicating the darkest display brightness, is No0. ..

It is also possible to select 16 types of brightness corresponding to each gradation number. The brightest display brightness represented by the gradation number No15 is Br15, and the gradation number No
The display brightness represented by 14 is Br14, the intermediate display brightness in which the gradation number decreases is shown in FIG. 11, and the gradation number N
The darkest display luminance represented by o0 is Br0.

FIG. 12 is a curve 12 showing the voltage-display brightness characteristics, where the horizontal axis represents the voltage applied to the liquid crystal and the vertical axis represents the display brightness.
00 is shown. By increasing the voltage applied to the liquid crystal, the display brightness has a characteristic that the display brightness is gradually darkened.

The voltage for obtaining the display brightness Br15 is V15, the voltage for obtaining the display brightness Br14 is V14, and the voltage corresponding to the intermediate display brightness at which the display brightness is lowered is shown in FIG.
And the voltage for obtaining the display brightness Br0 is V0.

Further, each of 1201, 1202, and 1203 is obtained by approximating the curve 1200 by a straight line in a certain range. The straight lines 1201, 1202, 1203 are provided in a range in which the brightness differences between adjacent display brightnesses are substantially the same and the voltage differences between the voltages corresponding to the adjacent display brightnesses are substantially the same.

FIG. 13 is a circuit diagram for processing one pixel in which a correction circuit is added to the DAC 107 described in the embodiment of the present invention shown in FIGS. 1 and 7. 1300 is a current generation circuit, 1301 is a reference power supply, 1302-1 to 1302
-8 is a reference current source, which is 8 per pixel in this embodiment.
A type of reference current is generated, and 1303 is a data line for transmitting the reference current.

Reference numeral 1304 is a judgment circuit for judging the value of the display data for one pixel transferred by the data line 106-1. Reference numerals 1305-1, 1305-2, 1305-3 are generated by the judgment circuit 1304. It is a data line for transmitting a determination signal.

Reference numeral 1306 is a current selection circuit.
-1 to 1306-6. 1
Reference numerals 307-1 and 1307-2 denote the current selection circuit 130.
6 is a data line for transmitting the selected current. 1308
Is an adder circuit, 1309 is a switch in the adder circuit 1308, and 1310 is a resistor.

Next, the outline of the correction will be described.

In FIG. 13, in order for the relationship between the display brightness and the gradation number to be the relationship shown by the curve 1100 in the figure, it is necessary to control the voltage applied to the liquid crystal corresponding to the gradation number. For example, the display brightness B expressed by the gradation number No10
In order to obtain r10, the display brightness Br1 shown in FIG.
Since the voltage applied to the liquid crystal corresponding to 0 is V10,
In the case of the display data of gradation number N010, the voltage of V10 may be controlled so that it can be applied to the liquid crystal. Similarly, to obtain the display brightness expressed by another gradation number, the desired display brightness expressed by the gradation number is obtained from FIG. 11 and applied to the corresponding liquid crystal to obtain the display brightness from FIG. It can be controlled by determining the voltage.

Here, in the curve 1200 of the relationship between the display luminance and the voltage applied to the liquid crystal in FIG. 12, it can be seen that the change in luminance with the increase in voltage does not simply decrease. That is, in the case of the display brightness in the bright range or the display brightness in the dark range, the display brightness gradually decreases as the voltage increases, and in the range of the display brightness intermediate between the display brightness in the bright range and the display brightness in the dark range. With the increase of the voltage, the decrease is rapid.

Therefore, the relationship between the display luminance and the voltage is approximated by a straight line as shown in the figure.

That is, the display brightness B in the bright display brightness range
r15 to Br12 and a voltage V15 for obtaining the display brightness
To V12 with a straight line 2101, display luminances Br11 to Br4 in the intermediate display luminance range, and straight lines 1202 with characteristics of voltages V11 to V4 for obtaining the display luminance, and display luminances Br3 to Br0 in a dark display luminance range. The characteristic of the voltages V3 to V0 for obtaining the display brightness is approximated by a straight line 1203.

The operation will be described in detail with reference to FIG.

In FIG. 13, a current generation circuit 1300.
Generates a plurality of reference currents having different weighting values and transfers the reference currents through the data line 1303. That is, it is set so that the current I1 flows through the reference current source 1302-1, and similarly, I2 is 1302-2, 1302-3 is I3, and 1 similarly.
302-4 to I4, 1302-5 to I5, 1302-6
I6 to 1302-7, I7 to 1302-7, and I8 to 1302-8.

The display data is transferred through the data line 106-1 and the data line 10 that transfers the upper 2 bits of the data is transferred.
6-1-3 and the data line 106-1-2 are connected to the determination circuit 130.
Enter in 4. In the determination circuit 1304, the data line 106
-1-3 and 106-1-2 are both "0", the data line 1305-3 is determined to be valid and "1".
When any data is “1”, the data line 1305-1 is determined to be valid and “1” is output. When any data is “1”, the data line 1305-2 is determined to be valid. Outputs "1".

When each judgment signal 1305 becomes valid, the switch 13 is selected in the current selection circuit 1306.
06-1 to 1306-6 are controlled. When 1305-1 becomes valid, the switches 1306-3 and 1306-6 become valid, and the current I3 flows through the data line 1307-1 and the current I6 flows through the data line 1307-2. Similarly 1305-2
Is enabled, the switches 1306-2 and 1306-5 are enabled, the current I2 is passed through the data line 1307-1, the current I5 is passed through the data line 1307-2, and when the switch 1306-3 is enabled, the switch 1306-1, 1306-4 becomes effective, and the current I1 flows through the data line 1307-1 and the current I4 flows through the data line 1307-2.

Then, in the adder circuit 1308, the data line 1
Switch 1 depending on the display data transferred in 06-1.
309-1, 1309-2, 1309-3, 1309-
4 performs a switching operation, and the currents supplied to the switches whose switches are turned on are added in parallel because they flow in parallel and appear on the output line 108-1. The relationship between the voltage V, the current I, and the resistance R is Ohm's law V =
Since it can be represented by IR, it is possible to obtain a current appearing in the output line 108-1 and a desired voltage with the resistor 1310.

Here, the relation between the display luminance and the voltage at which "1" appears on the data line 1305-3 is the straight line 1 shown in FIG.
It is approximated by 201, and similarly, "1" is set to the data line 1305-2.
Is displayed on the straight line 1202, the data line 1305-2
When '1' appears in the line, the line 1203 is approximated. Therefore, in order to perform the control of the straight line approximation, for example, the voltages V3 to V0 whose characteristics are approximated by the straight line 1202 are used.
Since the adjacent voltage difference is large in the range of, the current I3 selected at this time is set to be larger than I2 and I1, and the current I6 is similarly set to be larger than I5 and I4.

Further, in order to keep the voltage difference between adjacent voltages in each straight line uniform, I6≈2 × I3, I5≈2 × I2, I
It is desirable that 4≈2 × I1.

Further, when I6>I4> I5, I8≈2
XI7> V6 is set so that each current I1 to I
The absolute value of 8 can be set by the resistor 1310 and a desired voltage.

In the present embodiment, the digital display data 100 has been described with one pixel having 4 bits, but even in the case of data having 4 bits or more, the curve showing the characteristics of the gradation number and the display luminance shown in FIG. 1100, the gradation number is subdivided, the display brightness is selected, and the voltage can be determined using the curve 1200 showing the characteristics of the voltage and the display brightness shown in FIG. A current generation circuit 1300 according to the above, and a current generation circuit 1300 with a correction added by the number of straight lines approximating the curve 1200 representing the characteristics of the voltage and the display brightness, and further, a judgment circuit 1304 sets a judgment range. This can be achieved by setting and selecting the correction current by the selection circuit 1306, and by using an addition circuit having a switch according to the bit width.

Next, in the DAC described in the embodiment of the present invention shown in FIGS. 1 and 7, another embodiment of the correction means capable of implementing the characteristics of display data and brightness according to the visual characteristics. This will be described with reference to FIG.

In FIG. 14, 1400 is a power source,
1401-1, 1401-2, 1401-3 are variable resistors, and 1402-1, 1402-2, 1402-3 are data lines for transmitting current. 1403 is the DAC 10
7 is a current generation circuit in
2, 1404-3, 1404-4, 1404-5, 14
Reference numerals 04-6 are reference current sources, which are Ia, Ib, Ic, and
The currents Id, Ie, and If are generated. Other configurations are the same as the circuit diagram shown in FIG.

Next, the operation will be described.

Reference current sources 1404-1, 1404-2,
1404-3, 1404-4, 1404-5, 1404
The data line supplied to −6 is a variable resistor 1401-1,
It is connected to 1401-2 and 1401-3. Therefore, the variable resistors 1401-1, 1401-2, 1402-
By switching the resistance value of 3, the current generation circuit 14
Reference current sources 1404-1, 1404-2, 14
04-3, 1404-4, 1404-5, 1404-6
It becomes possible to change the voltage value supplied to each of the reference current sources 1404-1, 1404-2, 1404.
-3, 1404-4, 1404-5, 1404-6, the currents Ia, Ib, Ic, Id, Ie, If can be made variable. Then, the current generation circuit 14
03, the determination circuit 1304, the current selection circuit 1306, and the addition circuit 1308 perform the same operation as the circuit shown in FIG. 13, so that a voltage appears at 1308-1.

The currents Ia, Ib, Ic, Id, I
Since e and If are variable, the approximate curves 1201, 1202, 1203 shown in FIG. 21 can be realized, and the inclination of the straight line can be easily changed.

In the present embodiment, the digital display data 100 has been described with one pixel having 4 bits, but even in the case of data having 4 bits or more, the curve showing the characteristics of the gradation number and the display luminance shown in FIG. 1100, the gradation number is subdivided, the display brightness is selected, and the voltage can be determined using the curve 1200 showing the characteristics of the voltage and the display brightness shown in FIG. A current generation circuit 1300 corresponding to the above, and a voltage is supplied from the variable resistor 1401 according to the number of straight lines approximating the curve 1200 representing the characteristics of the voltage and the display luminance, and a current generation circuit 1300 with correction is added, Further, it is possible by setting a judgment range by the judgment circuit 1304, selecting the correction current by the selection circuit 1306, and using an addition circuit having a switch according to the bit width. That.

Further, in FIG. 15, the voltage dividing circuit 804 and the voltage multiplexer 806 of the signal driving circuit shown in FIG. 8 and the voltage dividing circuits 804R and 804G of the signal driving circuit shown in FIG.
804B and voltage multiplexers 806R, 806G, 8
Example 06B is described.

In FIG. 15, reference numeral 106 denotes a data line, which transfers upper f-bit and lower g-bit data.
Reference numeral 1500-1 is a high-order bit decoder,
-1 is a lower bit decoder. Reference numeral 1502 denotes a decoding result of the decoder 1500-1, which has (f squared) = k decoded signals. Reference numeral 1503 denotes the decoding result of the decoder 1500-2 (g squared) = p decoded signals. Reference numeral 1504 denotes a voltage dividing circuit, which inputs the power source 1505-1 and the power source 1505- (k + 1) and is divided by the voltage dividing resistors 1507-1 to 1507-k into the voltage line 1505-2 to the voltage line 1505- (k +).
The divided voltage is propagated to 1). 1508-1 to 15
08-k and 1509-1 to 1509-k are switching circuits composed of transistors. 1510-
1, 1510- (p + 1) are switching circuits 15 respectively.
08-1 to 1508-k and 1509-1 to 1509
It is a voltage line that propagates the voltage selected by -k.
Reference numeral 1512 denotes a voltage dividing circuit provided for each pixel, which inputs the voltage supplied from the voltage lines 1510-1 and 1510-p and is divided by the voltage dividing resistors 1513-1 to 1513-p from the voltage line 1510-1. The divided voltage is propagated to the voltage line 1505-p. 1514-1 to 1514-p are switching circuits composed of transistors.

The detailed operation will be described.

As for the data transferred on the data line 106, the upper f bits are input to the decoder 1500-1, and the lower g bits are input to the decoder 1500-2.
Either 02 or 1503 is enabled. The decode signal 1502 serves as a selection signal for the switching circuits 1508 and 1509. Each one of the decoded signals 1502 is connected to one of the switching circuits 1508 and one of the switching circuits 1509. The switches to be connected are assumed to be connected to adjacent voltage lines. That is, when the decode signal 1502 connected to the switches 1508-1 and 1509-1 becomes valid, the voltage line 1510-
The voltage propagated on the voltage line 1502-1 appears at 1, and the voltage propagated on the voltage line 1502-2 appears at the voltage line 1510-p. Here, since the voltage propagated to the voltage lines 1505-1 and 1505-2 is via the voltage dividing resistor 1507-1 in the voltage dividing circuit 1504, the voltage line 1
The voltage propagating at 505 is an adjacent voltage.

Further, switching circuits 1508 and 1509
The voltage selected by is the voltage line 1510-1 and 151
0-p propagates and is input to the voltage dividing circuit 1512.
It is further subdivided by the voltage dividing resistor and propagated to the voltage line 1510.

Here, the decode signal 1503 serves as a selection signal for the switching circuit 1514 and is connected to one of the switching circuits 1508 for each line. Then, the switch connected to the valid decode signal 1514 becomes valid, and any one of the voltages propagated on the voltage line 1510 appears on the data line 108. With such a structure, a voltage corresponding to the data 106 per pixel can be generated.

In the present embodiment, only the voltage multiplexer 107 for one pixel is described, but in the embodiment shown in FIG. 8, 24 pixels are required, so the switching circuit 150.
8, 1509 and 1514 and the voltage dividing circuit 1512 are provided for each pixel, and the voltage dividing circuit 1504 can be shared by the previous pixels. Furthermore, the same applies when the voltage multiplexer 107 has another number of pixels.

In addition, the voltage dividing resistor 151 in the voltage dividing circuit 1512.
3-1 to 1513-p have the same resistance value, and the voltage dividing resistors 1507-1 to 1507 in the voltage dividing circuit 1504.
By making − (k + 1) variable, it becomes possible to correct the voltage and luminance characteristics of the liquid crystal. That is, the data 106
Voltage lines 1510-1 and 151 depending on the value of the upper bit of
The voltage of 0-p is different, and the voltage difference is also different. However, since the voltage dividing resistors 1513-1 to 1513-p in the voltage dividing circuit 1512 have the same resistance value, linearity can be guaranteed for the voltage appearing on the voltage line 1510. Therefore, it is possible to obtain good display quality by approximating with a plurality of straight lines.

Furthermore, the voltage dividing circuit 804 and the voltage multiplexer 806 of the signal driving circuit shown in FIG. 8 and the voltage dividing circuits 804R and 804G of the signal driving circuit shown in FIG. 9 are shown in FIG.
804B and voltage multiplexers 806R, 806G, 8
Example 06B is described.

In FIG. 16, 106 is data,
1600 is a decoder. 1601 is a decoder 160
It is assumed that the decoded result of 0 has h decoded signals. Reference numeral 1602 denotes a voltage dividing resistor group, which is a voltage dividing resistor 1602.
-1-1 to 1602-1-p divide the voltage propagated on the voltage lines 1505-1 and 1505-2, and
The voltage divided by 5-1 and 1505-1-2 to 1505-1-p is propagated. Furthermore, the voltage dividing resistor 1602-2-
1 to 1602-2-p are voltage lines 1505-2 and 150
The voltage propagated in 5-3 is divided and the voltage line 1505-2
And propagate the voltage divided by 1505-2-2 to 1505-2-p. Similarly, the divided voltage is propagated to 1505- (p + 1). 1603-1-1 to 16
A switching circuit 03- (k + 1) -p is connected to the voltage lines 1505-1 to 1505- (k + 1), respectively. The selection signal of the switching circuits 1603-1-1 to 1603- (k + 1) -p becomes the decode signal 1601.

Next, the operation will be described.

The voltage divided by the voltage dividing circuit 1504 is propagated through the voltage lines 1505-1 to 1505- (p + 1) and further divided by the voltage dividing resistor group 1602.
Then, the voltage line 15 that propagates each subdivided voltage
A switching circuit 1603 is connected to 05,
A voltage is propagated to the data line 1515 when any one of the decode lines 1601 becomes valid.

In this embodiment, only the voltage multiplexer 107 per pixel is described, but in the embodiment shown in FIG. 8, 24 pixels are required, so the switching circuit 160.
3 is provided for each pixel, and the voltage dividing circuit 1504 is common to the previous pixels. Further, the voltage multiplexer 10
The same applies when 7 has another number of pixels.

Further, the resistance values of the voltage dividing resistors 1610 are set to be the same, and the voltage dividing resistors 1507 in the voltage dividing circuit 1504 are used.
By making -1 to 1507- (k + 1) variable, it becomes possible to correct the voltage and luminance characteristics of the liquid crystal. That is, the voltages of the voltages appearing on the voltage lines 1505-1 and 1505- (k + 1) are different from each other and the adjacent voltage line 1505
The voltage difference between will also be different. However, the voltage dividing resistor 160
Since 2 has the same resistance value, it is possible to obtain good display quality by approximating with a plurality of straight lines.

Next, a signal drive circuit which is capable of color correction by providing a data conversion circuit in the signal drive circuit shown in FIG. 1 of the present invention will be described with reference to FIGS. 17, 18, 19, 20 and 21. To do.

FIG. 17 shows a block diagram of a signal drive circuit using the present invention.

Reference numeral 700 is display data, and 700R is n.
Bit R data, 700G is n bit G data, 7
00B is n-bit B data. A data conversion circuit 701 converts n-bit display data into m (> n) -bit display data.

FIG. 18 shows the drive waveform of this embodiment. In this figure, reference numeral 114 denotes a drive waveform of the drain line, which is from V (2 m-1) to -V (2 m-1).
Up to 2 × (2 m-th power) level drain voltage is prepared. A counter voltage VCOM 304 is a voltage level of the counter electrode. Further, the drain voltage is set to V (2 m -1) to V0 for a positive potential and -V0 to -V (2 m -1) for a negative potential with respect to the counter voltage VCOM. Since the voltage level of the counter electrode VCOM is constant, it is called a constant VCOM drive waveform.

FIG. 19 shows the drive waveform of another example of this embodiment. In this figure, reference numeral 119 indicates a drive waveform of the gate line, VGH is a gate-on voltage, and VGL is a gate-off voltage. Reference numeral 111 denotes a drive waveform of the drain line, which is a drain voltage from V (2 m −1) to V 0 (2 m power). Reference numeral 304 denotes a drive waveform of the counter electrode, where VCOMH is a high level counter voltage and VCOML is a low level counter voltage. Also,
The drain voltage is a level from V (2 m-1) to V0 when the counter voltage VCOM is at the VCOML level, but when the counter electrode VCOM is at the VCOMH level, the drain voltage VCOMV0 is -V (2 m to the power). -1) to V
(2 m-1) means -V0. Counter electrode VCO
Since the voltage level of M is AC, it is called a VCOM AC drive waveform. According to the configuration in which the counter voltage is changed, the amplitude of the drain voltage can be reduced.

The operation of the drive circuit shown in FIG. 17 will be described.

In this embodiment, n-bit display data 700R, 700G, 700B for each pixel is input to the drive circuit. Data conversion circuit 701 for each display data of R, G, B
Then, the n-bit display data of each pixel is converted into the m-bit display data 100. In the operation of converting this data, each display data 700R, 700G, 700 to be input
Since the weighting process is performed for each B, even if the same value is input for each of R, G, and B, the drive circuits after the shift register 102 can process as different data.

The display data is converted to m bits by the data conversion circuit 701, and the level capable of expressing gradation is (2
Level). Further, since the liquid crystal has a characteristic of being deteriorated when a direct current component is applied, it is necessary to make the liquid crystal alternating with a certain period. Therefore, with respect to the voltage level of the counter electrode 304 shown in FIG. 18, in order to obtain a potential of (2 m-th power) level in both positive and negative, D
The / A converter 107 is processed.

Input display data 700R, 700
G and 700B are weighted by the data conversion circuit 701, but 2 × (2
The number of the set of voltage levels used in the liquid crystal applied voltage 115 of the (m-th power) level is 2 × (2 to the n-th power) for each pixel.
Becomes Since the selection of this set of voltage levels can be set differently for each of R, G, and B, it is possible to control the luminance for each color.

The operation will be described with reference to the VCOM constant drive waveform shown in FIG. 18 and the pixel equivalent circuit shown in FIG. When the voltage level of the gate line 119 is VGL, the gate is off, and when it is VGH, the gate is on. When the voltage level of the gate line 119 is VGH, the drain line 1
The voltage level corresponding to the display data among the liquid crystal applied voltages V0 to V (2 m-1) from 14 is supplied to and accumulated in the liquid crystal 302 and the storage capacitor 303. The effective value applied to the liquid crystal changes according to the accumulated voltage level, and it becomes possible to obtain gradations with different brightness. As described above, the selectable levels are limited to (2 to the nth power) of these levels, but the R, G, and B display data 700 to be input are input.
Even if the values of R, 700G, and 700B are the same, since the weighted values of the display data 100 are different in the data conversion circuit 701, different voltage levels can be selected for each pixel, so that good multicolor display can be achieved. Can be obtained.

Further, another example of the VCOM AC drive waveform will be described with reference to FIG. When the voltage level of the gate line 119 is VGH in the gate-on state, the drain line 114
From the drain voltages V (2 m -1) to V0, the voltage corresponding to the display data is selected. At this time, the voltage level of the counter electrode 304 is the low level counter voltage VCOML.
And Again, the voltage level of the gate line 119 is VG.
When the H gate is on, the voltage level of the counter electrode 304 is inverted and becomes the high level counter voltage VCOMH. At this time, a voltage corresponding to the display data is selected from the drain voltages V (2 m -1) to V0 on the drain line 114, but the voltage corresponding to the display data is valid due to the potential difference from the counter electrode 304. Become. That is, if the drain voltage V (2 m −1) corresponds to a certain display data when the voltage level of the counter electrode 304 is VCOML, when the voltage level of the counter electrode 304 is VCOMH,
The drain voltage V0 corresponds. Even if this drive waveform is used, the same value as the liquid crystal applied voltage effective value in the drive waveform with a constant VCOM shown in FIG. 18 can be obtained.
Good multi-color and multi-gradation display can be realized.

Next, FIG. 20 shows a block diagram of a data conversion circuit which can be rewritten at any time in the data conversion circuit 701 shown in FIG.

In this figure, 700 is display data, and of the display data 700, 700R is an n-bit R.
Data, 700G is n-bit G data,
700B is n-bit B data. 2000 is a system control signal transferred from the system. 20
01R is an R / G data selector for selecting R data 700R and G data 700G, and 2001G is G data 700
It is a G / B data selector for selecting G and B data 700B, and selects 2002 n-bit R data and 2003 n-bit B data, respectively. A control circuit 2004 receives a system control signal 2000 and receives a color / monochrome control signal 2005 and a data conversion circuit control signal 200.
6. Generate constant memory circuit control signal 2007. 200
8R is an R data conversion circuit for converting n-bit data into m-bit data, 2008G is a G data conversion circuit for converting n-bit data into m-bit data, and 2008B is a B data conversion circuit for converting n-bit data into m-bit data. Is. A constant storage circuit 2009 stores conversion constants, and supplies the conversion constants from the constant data bus 2010 to the data conversion circuits 2008R, 2008G, and 2008B. 2011R is m-bit R data, 2011G is m-bit G data, and 2011B is m-bit B data.
The data.

The operation will be described.

The system control signal 2000 is a signal indicating the characteristics of the display data 700 transferred from the system described later. For example, when the display data 700 is monochrome data, the control circuit 2004 that inputs the system control signal 2000 enables the color / monochrome control signal 2005 to be monochrome and switches the display data bus. That is, monochrome data is transferred to G data 700G, and R data 700R and B data 700B are transferred.
If no data is transferred to the R / G data selector 2
For 001R, select G data 700G and select R data 2
002, and the G / B data selector 2001B selects G data 700G and sets it as B data 2003. Even if the display data is monochrome data, the R data 7
When the same data as the G data 700G is transferred to the 00R and B data 700B, the data is converted in advance on the system side. Therefore, as in the case where the display data is color data, the R / G data selector 2001R
Selects the R data 200R as the R data of 2002, and the G / B data selector 2001B selects the B data 2
00B is selected as B data 2003.

Further, each data conversion circuit 2008R,
The 2008G and 2008B are configured so that the conversion constant can be switched at any time. The control circuit 2004 is
System control signal 2000 is input and data conversion circuit 2
The control signal 2006 for resetting the constants of 008R, 2008G, and 2008B is generated. Further, the control circuit 2004 generates a constant storage circuit control signal 2007,
It is output to the constant storage circuit 2009. For example, when the constant storage circuit 2009 is composed of a memory, the constant storage circuit control signal 2007 may be a memory address and a memory control signal. The constant storage circuit 2009 stores conversion constants of display data according to display characteristics,
By specifying the area in which the conversion constant is stored by the constant storage circuit control signal 2007, the constant data bus 2010
It becomes possible to read it out. Constant data bus 2010
The data read from the R, G, and B data conversion circuits 2008R and 20R are controlled by the control signal 2006.
It is set to 08G and 2008B. The n-bit R data 2002 is converted to m-bit R data by the data conversion circuit 2008R, the n-bit G data 700G is converted to m-bit G data by the data conversion circuit 2008G, and the n-bit B data 2003 is converted to the data conversion circuit. 20
It is converted to m-bit B data by 08B. Any of the m-bit data 2008R, 2008G, 2008
Also in B, since the data conversion is performed according to the characteristics of the display data, good image quality can be obtained.

Next, FIG. 21 shows a block diagram of a data conversion circuit which can be switched at any time.

In FIG. 21, reference numeral 700 denotes display data. Of the display data 700, 700R is an n-bit R.
Data, 700G is n-bit G data,
700B is n-bit B data. 2100 is a system control signal transferred from the system. 21
01R is an R / G data selector that selects R data 700R and G data 700G. 2101G is G data 700.
G / B data selectors for selecting G and B data 700B, and 2102R n-bit R data, 2102
B n-bit B data is selected. Reference numeral 2103 denotes a control circuit, which receives the system control signal 2100 and outputs
Monochrome control signal 2104, enable signal 2105
a, an enable signal 2105b is generated. 2106
R 2107R is an R data conversion circuit, 2106G, 21
Reference numeral 07G is a G data conversion circuit, 2106B and 2107B are B data conversion circuits. 2108R is m-bit R data, 2108G is m-bit G data, and 210
8B is m-bit B data.

Next, the operation of the data conversion circuit shown in FIG. 21 will be described.

The system control signal 2100 is a signal indicating the characteristics of the display data 700 transferred from the system described later. For example, when the display data 700 is monochrome data, the control circuit 2103 that inputs the system control signal 2100 causes the color / monochrome control signal 2 to be input.
The display data bus is switched by making the monochrome 104 effective. That is, when the monochrome data is transferred to the G data 700G and the data is not transferred to the R data 700R and the B data 700B, the R / G data selector 210
For 1R, select G data 700G and select R data 200
2R, and the G / B data selector 2101B selects G data 700G and sets it as B data 2102B. Even if the display data is monochrome data, the R data 7
When the same data as the G data 700G is transferred to the 00R and B data 700B, the data is converted in advance on the system side. Therefore, as in the case where the display data is color data, the R / G data selector 2101R
Selects the R data 700R and then the R data 2102R
Then, the G / B data selector 2101B outputs the B data 7
00B is selected as B data 2102B.

Further, on the R, G, and B display data buses, R data conversion circuits 2105R and 2106 are provided.
Data conversion circuits 2105G and 2106 for R and G data
Data conversion circuits 2105B and 2106B for G and B data
2 and a set of data conversion circuits. The control circuit 2103 selects one of the two types of enable signals 2105a and 2105b according to the characteristics of the display data.
The conversion process is enabled only for the selected one data conversion circuit, and m-bit R data 2108R, m-bit G data 2108G, and m-bit B data 2108B are generated. In this embodiment, there are only two types of R, G, and B data conversion circuits. However, when the display data has a plurality of characteristics, the number of data conversion circuits according to the characteristics is used and the enable signal is used. The same applies to providing a plurality.

Further, FIG. 22 shows a block diagram of a signal drive circuit constituted by the signal drive circuit shown in FIG. 8 and the data conversion circuit shown in FIG. 20 or 21. Regarding the operation of the data conversion circuit 701, as shown in FIG.
The operation is the same as that of the data conversion circuit shown in FIG. 21, and the operation after the shift register 102 is the same as that of the signal drive circuit shown in FIG.

In the above description of the embodiments, the signal drive circuit shown in FIGS. 1, 7, 8, 9, 17, and 21 is used as the TF.
Although it has been described as a driving circuit for a T liquid crystal display,
It goes without saying that the signal drive circuit of the present invention is generally applicable to a matrix type device which is line-sequential scanning and whose display state changes depending on the voltage value.

Furthermore, another embodiment of the present invention is shown in FIGS.
7 and FIG. 28 will be described. FIG. 26 is a block diagram of the liquid crystal display device of the present invention.

Reference numeral 2800 is display data indicating the gradation of one pixel of several bits, 2801 is a clock, 2802 is an X drive circuit, and X drive circuit 2802 is a clock 2801.
Display data 2800 in ₁ from X ₀ to X ₆₃₉ in synchronization with
Read lines. In this embodiment and the following embodiments, only one pixel of display data is handled for simplification of description, but display data of several pixels may be input at one time. 2803 is a multi-level power supply circuit, 2804 is a multi-level power supply line bus, and this multi-level power supply bus 2804
Thus, the applied voltage for multi-gradation is supplied to the X drive circuit 2802. 2805 is a timer, 2806 is a timer output bus, 2807 is a liquid crystal panel, and X drive circuit 2802
Uses a timer output bus 2806 to drive the liquid crystal panel 2807.
The application time of each voltage applied to the liquid crystal inside is defined. 11
Reference numeral 8 denotes a scan clock, and the X drive circuit 2802 synchronizes when the scan clock 118 becomes “high”,
A voltage corresponding to the display data of each pixel is output to the drain lines X ₀ to X ₆₃₉ for the time specified by the timer output 2806. Reference numeral 117 denotes an enable signal for starting display in the vertical direction. Reference numeral 116 denotes a scan drive circuit. The scan drive circuit 116 has the gate line Y ₀ when the enable signal 117 rises to "high" and the scan clock 118 rises to "high". To "high". Next, when the scan clock 118 rises to "high", the gate line Y ₀
To "low", and to the gate line Y ₁ "high".
The scan drive circuit 116 sequentially repeats this operation.

For example, 1 connected to the gate line Y
When displaying pixels for a line, the X drive circuit 2802 reads display data for one line from when the gate line Y ₀ is “high” to when Y ₁ is “high”. Then, when the scan clock 118 rises to "high", the X drive circuit supplies a voltage according to the display data to the drain lines X ₀ to X ₆₃₉ , and the scan drive circuit 116.
Makes the gate line Y ₁ "high". By this operation, one line can be displayed. By repeating this operation from the gate lines Y ₀ to Y ₄₇₉ , one screen is displayed.

FIG. 27 shows an embodiment shown in FIG. 26 of the present invention, in which one switch is used to sequentially apply a two-level voltage to one power supply line during one scanning period, and to display data in accordance with display data. FIG. 3 is a block diagram of a liquid crystal driving device for one pixel, which applies only the applied voltage to the liquid crystal. FIG. 28 is a time chart showing the operation of FIG.

Reference numeral 2900 is display data having binary values of “high” and “low”, 2901 is a latch circuit, 2902 is a clock, and 2903 is latch data.
01 is display data 2900 in synchronization with the clock 2902.
Is read and output as latch data 2903. The latch circuit 2901 outputs the latch data 2903 until the next display data is read.

Reference numeral 2904 is a voltage selector, and 2905 and 29.
Reference numeral 06 designates selector lines S0 and S1, and the voltage selector 29
04 is S0 when the latch data 2903 is "low"
Is set to "high", and when it is "high", S1 is set to "high".

2907 is timer setting data, 2908 is a scanning signal, 2909 is a timer, and 2910 is a timer 909.
Output T0, 2911 is the output T1 of the timer 2909, and the timer setting data 2907 defines the time for which the timer output T0 is "high".
And The timer 2909 uses the timer setting data 2907.
Is read, and the output T0 is set to “high” in synchronization with the scanning signal 2908 until t0 set by the timer setting data 2907. Further, the output T1 of the timer 2909 becomes "high" at the same time as the output T0 becomes "low" after t0, and becomes "low" in synchronization with the next scanning signal. This "high" period is t1. 2912 is a power supply circuit, 291
3, 2914 are power supply outputs, and the power supply circuit 2912 is 2
Level voltages V0 and V1 (V0 <V1) are generated, and V0 is output to the power supply output 2913 and V1 is output to the power supply output 2914.

2915 is a pulse selector and 2916 is a gate signal. The pulse selector 2915 gates the timer output T0 when the select line S0 is "high" and the timer output T1 when the select line S1 is "high". The signal 2916 is output.

Reference numerals 2917 and 2918 are power supply switching elements, and 2919 is a power supply line. When the timer output T0 is "high", the power supply switching element 2917 becomes conductive and the voltage V0 is supplied to the power supply line 2919 and the timer output T1.
Is high, the power supply switching element 2918
Becomes conductive and outputs the voltage V1 to the power supply line 2919.

2920 is a switching element, 2921 is a drain line for applying a voltage to the liquid crystal, and the gate signal 2
When 916 is “high”, the switching element 2920 becomes conductive and the voltage of the power supply line 2919 becomes the drain line 2921.
Output to.

Reference numeral 2922 is a scan drive circuit, 2923 is an enable signal, and 2924 and 2925 are scan lines. The enable signal 2923 is a signal which becomes “high” when scanning of one frame is started, and the scan driving circuit 2922 is used.
After reading the enable signal 2923 that has become "high", when the scanning signal 2908 becomes "high", the output Y0 is made "high" for one scanning period. After that, the scan driving circuit 2922 synchronizes with the scan signal 2908 and outputs Y0,
Y1, ..., Yn−1 (n is the number of scanning lines) are sequentially set to “high” for one scanning period. For example, output Y at some point
When 0 is "high", the next time the scanning signal 2908 becomes "high", the output Y0 becomes "low" and the output Y1 becomes "high". This operation is repeated from Y0 to Yn-1, and after Yn-1, Y0 becomes "high" in synchronization with the enable signal 2923.

2926 and 2928 are liquid crystal switching elements, 2927 and 2929 are liquid crystals, and 2930 and 2931.
Is an additional capacitance, and is a liquid crystal switching element 2926.
Becomes conductive when Y0 connected to the scanning line 2924 becomes "high", the voltage of the drain line 2921 is applied to the liquid crystal 2927 and the additional capacitor 2930, and cuts off when Y0 becomes "low". , The charges of the liquid crystal 2927 and the additional capacitor 2930 are retained. This additional capacity 2930
Is connected to the dummy scanning line 2924-a in the previous stage to stabilize the liquid crystal 2927. Similarly, when Y1 becomes “high”, the switching element 2928 becomes conductive and the voltage of the drain line 2921 is applied to the liquid crystal 2929 and the additional capacitor 2931. The additional capacitance 2931 corresponds to the scanning line 292 of the preceding stage.
4 to stabilize the liquid crystal 2929.

Next, the detailed operation will be described. Scanning signal 2
908 emits a short rectangular pulse at the beginning of one scanning period as shown in FIG. The timer 2909 and the scan drive circuit 2912 operate in synchronization with the scan signal 2908. The output T0 of the timer 2909 becomes "high" for t0 in synchronization with the rising edge of the scanning signal 2908 as shown in FIG. The other output T1 becomes "high" in synchronization with the falling edge of T0 and becomes "low" in synchronization with the rising edge of the scanning signal 2908. Due to the output of the timer 2909, the switching elements 2917 and 2918 connected to the output of the power supply circuit 2912 are alternately turned on during one scanning period, and the power supply line 2919 has V0 for t0 as shown in FIG. , V1 are applied alternately during t1.

The scan drive circuit 2922 takes in the enable signal 2923 which has become "high", and then, as shown in FIG. 28, Y0 is made "high" in synchronization with the rising edge of the scan signal 2908, and Y1 to Yn-1. Is "low". Further, when Y0 is "high", the liquid crystal switching element 2926 connected to Y0 becomes conductive. In synchronization with the next rising edge of the scan signal 2908, Y0 becomes "low" and Y1 becomes "high". This operation is sequentially repeated. When Y0 of the scan drive circuit 2912 is "high",
When the output S0 of the voltage selector 2904 that has read the latch data 2903 in the “low” state becomes “high”, the output T0 of the timer is output to the output 2916 of the pulse selector 2915.

Therefore, the drain line 2921 and the power source line 29
The switching element 2920 connecting 19 is conductive for t0, and the voltage V0 is applied to the liquid crystal 2927.
The voltage of the liquid crystal 2927 is V0 within t0 as shown in FIG.
become. During the subsequent t1, the switching element 2926 of the liquid crystal 2927 is in the conductive state, but the gate signal 291 is generated.
Since 6 is "low", the switching element 2920 is in a high impedance state, so that the charge accumulated in the liquid crystal 2927 is retained. Scan line selector 2922
When the output Y0 of the switch goes low, the switching element 292
6 is cut off, the electric charge of the liquid crystal 2927 is held,
The voltage V0 is held until Y0 becomes "high" next time.

Next, when Y1 is "high", the voltage selector 2 which has read the latch data 2903 in the "high" state
When the output S1 of 904 becomes “high”, the output T1 of the timer is output to the output 2916 of the pulse selector 2915. Therefore, the drain line 2921 and the power source line 2919
The switching element 2920 connecting to the switch is conductive for t1 and the voltage V1 is applied to the liquid crystal 2927. The voltage of the liquid crystal 2927 becomes V1 within t1 as shown in FIG. 30, and the voltage V1 is held until Y1 next becomes “high”. By preparing the latch circuit 2910, the voltage selector 2904, and the pulse selector 2915 for one line of pixels, one line of display can be performed.

FIG. 29 shows another embodiment of the present invention. Figure 2
Reference numeral 9 is the liquid crystal of the embodiment shown in FIG. 27 with a parallel capacitor added in order to prevent the voltage drop of the liquid crystal due to leakage or the like.

Reference numeral 3100 denotes a capacitor, which is a liquid crystal 292.
7 and 2929 are connected in parallel to the drain line 2921. Other operations are the same as those in the embodiment shown in FIG. When a voltage is applied to the drain line 2921, electric charges are accumulated in the capacitor 3100 so that the voltage becomes the same as that of the liquid crystal. For example, a voltage is applied to the liquid crystal 2927 to accumulate charges, and then the liquid crystal switching element 2
Even when 926 is in a conductive state and no voltage is applied to the drain line 2921, the capacitor 3100
In addition, since the electric charge having the same potential as that of the liquid crystal 2927 is accumulated, it is possible to reduce the influence of leak current or the like on the display quality. By preparing the latch circuit 2901, the voltage selector 2904, and the pulse selector 2915 for one line of pixels, one line of display can be performed.

FIG. 30 shows another embodiment of the present invention. Figure 3
Reference numeral 0 is a block diagram of a liquid crystal drive device that applies only a voltage corresponding to display data among eight levels of voltage to the liquid crystal using four embodiments shown in FIG.

3200 is 3-bit display data, 320
1 is a latch circuit, 3202 is latch data, the latch circuit 3201 latches the display data 3200 in synchronization with the rising edge of the clock 2902, and the latch data 32
Output as 02.

3203 is a voltage selector, and 3202 to 3
211 is an output of the voltage selector 3203, and the voltage selector 3203 outputs 32 according to the latch data 3202.
Make only one from 04 to 3211 "high".

3212 is a power supply circuit having 8-level output, 3213 is output of voltage V0, 3214 is output of voltage V1, 3215 is output of voltage V2, 3216 is voltage V3.
Output, 3217 is voltage V4 output, 3218 is voltage V
5, 3219 is an output of voltage V6, 3220 is an output of voltage V7, 3221 to 3228 are power supply switching elements, and 3234 to 3237 are power supply lines. The power supply circuit 3212 outputs an 8-level voltage from V0 to V7. Switching elements 3221, 3223, 322
5, 3227 become conductive only while the timer output T0 is "high", and V0 and the power supply line 323 are connected to the power supply line 3234.
5 to V2, power line 3236 to V4, power line 3237 to V
6 is applied. Switching elements 3222, 3224,
3226 and 3228 become conductive only while the timer output T1 is "high", and the power supply line 3234 is V1, the power supply line 3235 is V3, the power supply line 3236 is V5, and the power supply line 323 is.
V7 is applied to 7.

3229 is a pulse selector, 3230 is a gate signal S'0, 3231 is a gate signal S'1, 323.
2 is the gate signal S'2, 3233 is the gate signal S'3,
3238 to 3241 are switching elements, and 3242 is a drain line. The pulse selector 3229 outputs a signal in synchronization with the output T0 of the timer 2909 from the gate signal S′0 when the output S0 of the voltage selector 3203 is “high”. Only when the gate signal S′0 is “high”, the switching element 3238 becomes conductive,
The voltage V0 is applied to the drain line 3236. The pulse selector 3229 outputs the output S of the voltage selector 3203.
When 1 is "high", the gate signal S'0 to timer 2
A signal synchronized with the output T1 of 909 is output. Only when the gate signal S′0 is “high”, the switching element 3238 becomes conductive, and the voltage V1 is applied to the drain line 3236. Similarly, the voltage selector 320
When the output S2 of 3 is "high", the gate signal S'1
Outputs a signal synchronized with the output T0, and the drain line 3
A voltage V2 is applied to 236. Voltage selector 320
When the output S3 of 3 is "high", the gate signal S'1
Outputs a signal synchronized with the output T1, and the drain line 3
A voltage V3 is applied to 236. Voltage selector 320
When the output S4 of 3 is "high", the gate signal S'2
Outputs a signal synchronized with the output T0, and the drain line 3
The voltage V4 is applied to 236. Voltage selector 320
When the output S5 of 3 is "high", the gate signal S'2
Outputs a signal synchronized with the output T1, and the drain line 3
A voltage V5 is applied to 236. Voltage selector 320
When the output S6 of 3 is "high", the gate signal S'3
Outputs a signal synchronized with the output T0, and the drain line 3
A voltage V6 is applied to 236. Voltage selector 320
When the output S7 of 3 is "high", the gate signal S'3
Outputs a signal synchronized with the output T1, and the drain line 3
A voltage V7 is applied to 236.

The operation will be described in detail. If the display data 3200 is “high, low, high”, the clock 2
In synchronization with 902, the latch circuit 3201 displays the display data 32.
00 is latched and output as latch data 3202. The voltage selector 3203 uses this latch data 3201.
"High, low, high" is read, and the gate signal S'2 corresponding to this latched data is made "high" during the period synchronized with the timer output T1. Gate signal S'of pulse selector
2 becomes “high”, the switching element 3240 becomes conductive and the voltage of the power supply line 3236 changes to the drain line 32.
42 is output. At this time, the voltage V is applied to the power line 3236.
5 is applied, the voltage V5 is output to the drain line 3242, and the voltage V5 is applied to the liquid crystal in the future.

By combining a plurality of the embodiments shown in FIGS. 27, 29 and 30, it is possible to apply multi-level voltages to the liquid crystal with a small number of power supply lines and switching elements.

By installing a capacitor on the drain line in parallel with the liquid crystal, a higher quality display can be obtained.

31 and 32 show another embodiment of the present invention. FIG. 31 is a block diagram of a liquid crystal driving device in which a voltage of four levels is sequentially applied to one power supply line during one scanning period by using one switch and only a voltage corresponding to display data is applied to the liquid crystal. is there. FIG. 32 is a time chart explaining the operation of FIG.

3300 is 2-bit display data having two values of "high" and "low" per bit, and 3301 is 2
The bit latch circuit 3302 is 2-bit latch data, the display data 3300 is latched by the latch circuit 3301 in synchronization with the clock 2902, and the latch data 3302 having the same value as the display data 3300 until the next clock 2902 is input. Is output.

Reference numeral 3303 is a voltage selector. The voltage selector 3303 sets the output S0 to "high" when the 2-bit latch data is "low, low". Similarly, when the latch data is "low, high", the output S1 is "high".
When the latch data is "high, low", output S2
Is set to "high", and the output S3 is set to "high" when the latch data is "high, high".

Reference numeral 3304 is timer setting data, 3305 is a timer, and 3310 to 3313 are timer outputs. The timer 3305 outputs T0 to T3 from 3310 to 3313 in synchronization with the scanning signal 2908 in accordance with the timer setting data 3304. The timer setting data 3304
Sets the "high" period of the timer outputs T0 to T2. The timer output T0 becomes "high" in synchronization with the rising edge of the scanning signal 2908, and becomes "low" after the set time t0. The timer output T1 becomes "high" in synchronization with the falling of the timer output T0, and becomes "low" after the set time t1. The timer output T2 becomes “high” in synchronization with the falling of the timer output T1, and becomes “low” after the set time t2.
become. The timer output T3 becomes “high” in synchronization with the falling edge of the timer output T2, and the scanning signal 290 after t3.
It goes low in synchronization with the next rising edge of 8. t3 is 1
This is the time obtained by subtracting the timer set times t0, t1, and t2 from the scanning period.

3314 is a power supply circuit for generating four levels of voltage, 3315 to 3318 are power supply outputs, 3319 to 3322 are power supply switching elements, and the power supply circuit 3
314 generates four-level voltage from V0 to V3 (V0 <V1 <V2 <V3), and outputs V to the power output 3315.
0, V1 at power output 3316, V at power output 3317
2. Output V3 to the power output 3318. The power switching element 3319 is connected to the power output 3315, the power switching element 3320 is connected to the power output 3316, the power switching element 3321 is connected to the power output 3317, and the power switching element 3322 is connected to the power output 3318. Power supply switching elements 3319 to 33
22 is turned on / off by the timer outputs T0 to T3. When the timer output T0 is "high", the power supply switching element 3319 is rendered conductive, and the output V0 of the power supply circuit is applied to the power supply line 2919. Similarly, when the timer output T1 is "high", the power supply switching element 3
When 320 is conductive, the output V1 of the power supply circuit is applied to the power supply line 2919, and the timer output T2 is "high", the power supply switching element 3321 is conductive and the output V2 of the power supply circuit is the power supply line. Applied to 2919,
When the timer output T3 is "high", the power supply switching element 3322 becomes conductive, and the power supply circuit output V3 is output.
Is applied to the power supply line 2919. Timer output is “low”
At the time of, each of the power supply switching elements is cut off, and the output of the power supply circuit is not applied to the power supply line 2919.

Reference numeral 3323 denotes a pulse selector, 3324 denotes a gate signal, and the pulse selector 3323 has outputs S0 to S3 of the voltage selector 3303 and output T0 of the timer.
To T3 are input. This pulse selector 3323
Outputs a signal of T0 from the gate signal 3324 of the pulse selector 3323 when S0 is “high”. Similarly, when S1 is “high”, the signal of T1 is output from the gate signal 3324 of the pulse selector 3323, and when S2 is “high”, the signal of T2 is output by the pulse selector 332.
3 is output from the gate signal 3324, and when S3 is “high”, the signal of T3 is output from the gate signal 3324 of the pulse selector 3323.

FIG. 3 shows the operation of another embodiment of the present invention.
1 and FIG. 32. The timer 3305 uses the timer setting data 3304 and the scan signal 2908 shown in FIG.
Controls the outputs T0 to T3. As shown in FIG. 32, the output T0 of the timer 3305 is the scan signal 29
It goes high in synchronization with the rising edge of 08, and goes low after t0. Similarly, the output T1 becomes "high" in synchronization with the fall of the output T0, and becomes "low" after t1.
The output T2 becomes "high" in synchronization with the fall of the output T1 and becomes "low" after t2. Output T3 is output T2
Becomes "high" in synchronization with the falling edge of, and becomes "low" after t3. Further, when the output T0 of the timer 3305 is "high", the power supply switching element 3315 is in a conductive state, the output V0 of the power supply circuit 3310 is applied to the power supply line 2919, and when the output T0 is "low", it is cut off. In this state, V0 is no longer applied to the power supply line 2919.
Similarly, when the output T1 is “high”, the power supply switching element 3316 becomes conductive, and the output V1 of the power supply circuit 3310 is applied to the power supply line 2919. When the output T2 is "high", the power supply switching element 3317 becomes conductive, and the output V2 of the power supply circuit 3310 is applied to the power supply line 2919. When the output T3 is "high", the power supply switching element 3318 becomes conductive, and the output V3 of the power supply circuit 3310 is applied to the power supply line 2919.
Due to this operation, as shown in FIG. 32, the voltage V0 is applied to the power supply line 2919 for t0 and the voltage V1 is applied for t1 during one scanning period.
Voltage V2 is applied for t2 and voltage V3 is applied for t3.

On the other hand, the 2-bit display data is latched by the latch circuit 3301 in synchronization with the clock 2902,
It is input to the voltage selector 3303 as 2-bit latch data 3302. Latch data 3302, for example,
When the latch data 3302 is "high, low", the voltage selector 3303 sets S2 to "high". As shown in FIG. 32, the pulse selector 3303 is a voltage selector 3304.
Since S2 of is high, the output T2 of the timer 3305 is output to the gate signal 3320. Switching element 2
920 is a gate signal 332 of the pulse selector 3319
It is controlled by 0 and becomes conductive when the gate signal 3320 is “high”. Therefore, the switching element 292
0 becomes conductive only for t2, and the voltage V2 is applied to the drain line 2921 only for t2 as shown in FIG. The drain line 2921 is connected to the scan drive circuit 292.
Since the liquid crystal is connected to the liquid crystal via the liquid crystal switching element controlled by 2, the voltage V2 is applied to the liquid crystal in which the liquid crystal switching element is in the conductive state. That is, one of the four levels of voltage corresponding to the value of the display data can be applied to the liquid crystal, and a display corresponding to the display data can be obtained. As described above, one switching operation is performed by the voltage selector having n outputs, the timer having n outputs, the n-1 timer setting data, the power supply circuit having the n level outputs, and the n power supply switching elements. N in element
Gradation display can be obtained. Further, by disposing a capacitor in parallel with the liquid crystal on the drain line of the liquid crystal driving device having such n gradation, a display of higher quality can be obtained.

33 and 34 show another embodiment of the present invention. The driving device applies the voltage to the liquid crystal by using one switching element only when the voltage corresponding to the display data among the n-level voltages is applied to the power supply line.
In this embodiment, a voltage of four levels is sequentially applied to one power supply line during one scanning period by using one switch, and a voltage corresponding to display data is applied to the liquid crystal from the beginning of one scanning period. FIG. 33 is a block diagram of the liquid crystal drive device of the present embodiment. FIG. 34 is the time chart.

3500 is a timer setting data, 3501 is a timer, and the timer 3501 is a timer setting data 3
The output T0 to the output T3 are set to “high” for a set time in synchronization with the scanning signal 2908 by 500, and output from the output line 3310 to the output line 3313. The set time of the timer output T0 is t0, the set time of the output T1 is t1, and the set time of the output T2 is t2. One scanning period is t3. Timer 3
The output T0 of 501 becomes "high" in synchronization with the rising edge of the scanning signal 2908, and becomes "low" after the set time t0. Similarly, the output T1 becomes “high” in synchronization with the rising edge of the scanning signal 2908, becomes “low” after the set time t1, and the output T2 becomes “high” in synchronization with the rising edge of the scanning signal 2908. , Becomes “low” after the set time t2.
The output T3 always remains "high".

Reference numerals 3502 to 3504 are 2-input XOR elements, and reference numerals 3505 to 3507 are outputs of the XOR elements.
The XOR elements 3502 to 3504 output "high" when one of the inputs is "high", and output "low" when both have the same value. The XOR element 3502 has
The timer outputs T0 and T1 are input to the XOR element 3503.
The timer outputs T1 and T2 are input to the XOR element 3
Timer outputs T2 and T3 are input to 504.

Next, the detailed operation will be described.

The timer 3501 has timer setting data 3
The scan signal 2908 as shown in FIG. As shown in FIG. 34, timer outputs T0 to T2
Becomes "high" in synchronization with the rising edge of the scanning signal 2908, and becomes "low" after the respective set times t0, t1 and t2. The timer output T3 is always "high". Also,
The output T0 of the timer 3501 is a 4-level voltage (V0 <
The power supply switching element 3319 that connects the output V0 of the power supply circuit 3314 that generates V1 <V2 <V3) and the power supply line 2919 is made conductive only for t0. Output T0
Is also input to the XOR element 3502. XOR element 35
02, the timer outputs T0 and T1 are input, and as shown in FIG. 34, the output 3505 of the XOR element 3502 becomes “low” from the rising of the scanning signal 2908 to t0, and t
It goes "high" from 0 and goes "low" after t1. XO
While the output 3505 of the R element 3502 is “high”, the switching element 3320 connecting the output V1 of the power supply circuit 3314 and the power supply line 2919 is brought into a conductive state. Similarly,
The timer outputs T1 and T2 are input to the XOR element 3503, and the output 3 of the XOR element 3503 is output as shown in FIG.
506 becomes “low” from t1 to the rising of the scan signal 2908, becomes “high” after t1 and becomes “low” after t2. The output 3505 of the XOR element 3502 is
During the “high” period, the power supply switching element 3321 that connects the output V2 of the power supply circuit 3314 and the power supply line 2908.
To the conduction state. The timer outputs T2 and T3 are input to the XOR element 3504. As shown in FIG. 36, the output 3507 of the XOR element 3504 is “low” from the rising of the scanning signal 2908 to t2, and is “high” after t2. And becomes low after t3. While the output 3507 of the XOR element 3504 is "high", the power supply switching element 3322 that connects the output V3 of the power supply circuit 3314 and the power supply line 2908 is made conductive. As a result, as shown in FIG. 34, a voltage varying stepwise from V0 to V3 is applied to the power supply line 2908. On the other hand, the 2-bit display data is synchronized with the clock 2902 in the latch circuit 3301.
And latched as a 2-bit latch output 3302,
Input to the voltage selector 3303. Latch data 330
2, for example, "high, low", the voltage selector 330
3 makes S2 "high". As shown in FIG. 34, the pulse selector 3303 outputs the output T2 of the timer 3501 to the gate signal 3324 because S2 of the voltage selector 3304 is “high”. The switching element 2920 is controlled by the gate signal 3324 of the pulse selector 3323, and becomes conductive when the gate signal 3324 is “high”. Therefore, the switching element 2920 is in the conductive state only for t2, and the drain line 2 is turned on as shown in FIG.
Voltages V0 to V2 are applied to 921 within t2. Since the drain line 2921 is connected to the liquid crystal through the switching element controlled by the scan drive circuit 116 as in the embodiment shown in FIG. 27, the drain line 2921 is not connected to the liquid crystal in which the switching element is in the conductive state. Specifically, electric charges are accumulated up to the voltage V2. Even when the switching element 2920 is turned off after t2, the voltage V2 is applied to the drain line because the liquid crystal has accumulated charges up to the voltage V2.

For example, if "low, high", the voltage selector 3304 sets S1 to "high". Since S1 of the voltage selector 3304 is “high” in the pulse selector 3303, the output T of the timer 3501 is output to the gate signal 3324.
1 is output. The switching element 2920 becomes conductive when the gate signal 3324 is “high”. Therefore, the switching element 2920 is in a conductive state only during t1, and the voltages V0 to V1 are applied to the drain line 2921 within t1. This drain wire is shown in FIG.
Since the liquid crystal is connected to the liquid crystal through the switching element controlled by the scan drive circuit 116 as in the described embodiment, the liquid crystal in which the switching element is in the conductive state is finally charged up to the voltage V1. Accumulated.

Thus, a voltage selector having n outputs, a timer having n outputs, n-1 timer setting data, a power supply circuit having n level outputs, n power supply switching elements, and n power supply switching elements. With one XOR element, one switching element can display n gradations. Further, by disposing a capacitor in parallel with the liquid crystal on the drain line of the liquid crystal driving device having such n gradation, a display of higher quality can be obtained.

35 and 36 show another embodiment of the present invention. In the above embodiment, the n-level voltage is applied to the power supply line in a stepwise manner, and only the voltage corresponding to the display data or the voltage from the beginning of one scanning period to the voltage corresponding to the display data is applied to the liquid crystal. It is a method to do. However, the present embodiment is a system in which the voltage that changes stepwise of the power supply line is changed to a voltage that changes in a slope, and a voltage from the beginning of one scanning period to a voltage corresponding to display data is applied. FIG. 35 is a block diagram of the liquid crystal driving device, and FIG. 36 shows its time chart.

In FIG. 35, reference numeral 3700 is a sawtooth wave generation circuit, 3701 is an output of the sawtooth wave generation circuit, and 370.
2 is an amplifier circuit, and the sawtooth wave generation circuit 3702 is
A sawtooth wave is generated in synchronization with the scanning signal 2908, and is input to the amplifier circuit 3702 through the output 3701. The amplifier circuit 3702 amplifies the input sawtooth wave to a voltage level capable of driving the liquid crystal.

The operation will be described in detail. The 2-bit display data 3300 is latched by the latch circuit 3301 in synchronization with the clock 3302 and output as the latch data 3302. The latch data 3302 is the voltage selector 33.
03, the voltage selector 3303 sets one of the outputs S0 to S3 to “high” corresponding to the latch data 3302. For example, when the latch data 3302 is "high, low", the voltage selector 3303 sets S2 to "high".

A timer 3305 similar to that of the embodiment of FIG.
Reads the timer setting data 3304 and the scanning signal 2908 shown in FIG. 36, and sets the timer outputs T0 to T3 synchronized with the rising edge of the scanning signal 2908 to the specified time t0, t.
A signal which becomes "high" between 1, t2 and t3 is output.

The scanning signal 2908 is input to the sawtooth wave generation circuit 3700, and the sawtooth wave generation circuit 3700 is
Outputs a sawtooth wave synchronized with scanning signal 2908 3701
Output from. The output 3701 of the sawtooth wave generation circuit 3700 is input to the amplifier circuit 3702, and as shown in FIG. 36, the output 3701 is amplified to the liquid crystal drive voltage level (Vcom to Vmax) and output to the power supply line 2919.
Since the pulse selector 3323 corresponds to the latch data “high, low”, and S2 is “high”, the gate signal 3324 has a timer 3305 as shown in FIG.
Output T2 is output. This pulse selector 3323
Since the gate signal 3324 of is “high” during t2,
The switching element 2920 is in a conducting state for t2, and the drain line 2921 and the power supply line 2919 are connected during that period.

As a result, as shown in FIG. 36, the scan signal 2
After t2 from the rise of 908, the voltage of the power supply line 2919 is V
Since it is 2, the drain line 2921 has Vcom to V2.
Voltage is applied. This drain wire 2921 is
Since the liquid crystal is connected to the liquid crystal through the liquid crystal switching element controlled by the scanning drive circuit 116 as in the embodiment shown in FIG. 27, the liquid crystal in which the liquid crystal switching element is in the conductive state is finally connected to the liquid crystal. Charges are accumulated up to the voltage V2. Even when the switching element 2920 is turned off after t2, the voltage V2 is applied to the drain line because the liquid crystal has accumulated charges up to the voltage V2.

Although the sawtooth wave is used in this embodiment, other waveforms may be used.

FIG. 37 shows another embodiment of the present invention. The present embodiment is a liquid crystal driving device for applying a multi-level voltage to liquid crystal by using a plurality of stepwise voltage applying methods which is the embodiment shown in FIG. FIG. 37 is a block diagram of the liquid crystal drive device of this embodiment.

Reference numeral 3900 denotes k-bit display data, 390
Reference numeral 1 denotes a k-bit latch circuit, 3902 denotes latch data, and the latch circuit 3901 latches k-bit display data 3900 in synchronization with the clock 2902 and outputs it as k-bit latch data 3902. Reference numeral 3903 denotes a voltage selector, reference numeral 3904 denotes a k-th power of 2 (hereinafter, K = 2 to the k-th power) output bus, and the voltage selector 390
3 reads the latch data 3902, and outputs the output bus 39
Only one output corresponding to the latch data 3902 out of 04 is set to “high” and the other outputs are set to “low” and output.

3906 is timer 1 having M (M <K) outputs, 3905 is timer setting data for timer 1, 3
Reference numeral 907 denotes power supply circuits 1 and 390 having an output voltage of M level
9 is a timer 2, 390 having N (N = K−M) outputs
Reference numeral 8 is timer setting data for the timer 2, 3910 is a power supply circuit 2 having an N level output voltage, 3911 is an output of M buses of the timer 1, 3912 is M buses of the power supply circuit 1,
Reference numeral 3913 denotes M power supply switching elements, 3914 denotes the output N buses of the timer 2, and 3915 denotes N of the power supply circuit 2.
Book bus, 3916 N switching elements for power supply,
3920 and 3921 are power supply lines, and the timer 1 reads the timer setting data 3905 and the scanning signal 2908, and the timer output T0 is "high" in synchronization with the rising edge of the scanning signal 2908, as in the embodiment described above. And set to "low" after the set time t0. The timer output T1 becomes "high" in synchronization with the fall of the timer output T0, and becomes "low" after the set time t1. Similarly, the timer output T2
To the last output TM-1 of timer 1 is repeated. The timer 2 uses the timer setting data 3905 and the scan signal 2908.
Is read, and the timer output TM is set to “high” in synchronization with the rising edge of the scanning signal 2908, and is set to “low” after the set time tM. The timer output TM + 1 becomes “high” in synchronization with the falling of the timer output T0, and the set time tM + 1
Later goes "low". Similarly, the timer output T2 to the final output TK-1 of the timer 1 are sequentially output within one scanning period.

The power supply circuit 1 uses the M level voltages V0 to V
Up to M-1 are generated and output from the output bus 3912.
The power supply circuit 2 generates N-level voltages VM to VK−1 and outputs it from the output bus 3915.

M power supply switching elements 3913
Has one end connected to the power supply line 3920 and the other end connected to one of the output buses of the power supply circuit 1. The output bus 39 of the timer 1 is used for controlling this power supply switching element.
One of 11 is connected, and when the output of the timer 1 is "high", it is conductive, and when it is "low", it is cut off. For example, the power supply switching element 0 has a timer 1 for control.
Output T0 and the output V0 of the power supply circuit 1 are connected to each other. Similarly, the power supply switching element 1 is
The output T1 of the timer 1 and the output V1 of the power supply circuit 1 are respectively connected for control. Power supply switching element TM
The output TM-1 of the timer 1 and the output VM-1 of the power supply circuit 1 are connected to -1 for control.

N power supply switching elements 3916
Has one end connected to the power supply line 3921 and the other end connected to one of the output buses of the power supply circuit 2. The output bus 39 of the timer 2 is used for controlling this power supply switching element.
One of 14 is connected, and when the output of the timer 2 is "high", it is conductive, and when it is "low", it is cut off. For example, the power supply switching element N includes a timer 2 for control.
Output TN and the output VN of the power supply circuit 1 are connected to each other. Similarly, the power supply switching element 1 is
Output TN + 1 of timer 2 for control, output V of power supply circuit 2
N + 1 are respectively connected. The power supply switching element TK-1 includes an output TK-1 of the timer 1 for control,
The outputs VK-1 of the power supply circuit 1 are connected to each other.
By these operations, a voltage that changes in a stepwise manner of M steps is applied to the power supply line 3920, and a voltage that changes in a stepwise manner of N steps is applied to the power supply line 3921 in one scanning period.

3917 is a pulse selector, 3918 and 3
Reference numeral 919 denotes a gate signal, and the pulse selector 3917
Reads the output of the voltage selector 3903 from the output bus 3919 of the voltage selector and outputs one of the outputs of the timers 1 and 2 to the output P0 of the pulse selector corresponding to the output value.
To gate signal 3918 or output P1 to gate signal 3
It is output as 919. For example, the voltage selector 3903
When Sn (0≤n≤M-1) is "high", the output Tn of the timer 1 is output from the output P0 to the gate signal 3
Output as 918. Further, when Sn (M ≦ n ≦ K−1) of the outputs of the voltage selector 3903 is “high”, the output Tn of the timer 1 is output from the output P1 to the gate signal 39.
It outputs as 19.

3922 and 3923 are switching elements, and the switching element 3922 is a gate signal 3918.
Is high when is high, and is low when is low. When the switching element 3922 becomes conductive, the power supply line 3920 and the drain line 2921 are connected. The gate signal 3919 of the switching element 3923 is “high”.
When, it is conductive, when it is "low", it is cut off. When the switching element 3923 becomes conductive, the power supply line 3921
And the drain wire 2921 are connected.

The operation will be described with reference to FIG. The display data 3900 is latched by the latch circuit 3901 in synchronization with the clock 2902 and output as the latch data 3902. The voltage selector 3903 uses the latch data 390.
2 is read, and only the output Sn (0 ≦ n ≦ M−1) corresponding to the data in the data bus 3904 is “high”.
To The pulse selector 3917 reads the value of the data bus and the outputs of the timers 1 and 2, and outputs the output Tn of the timer 1 as the gate signal 3918 from the output P0.
When the gate signal 3918 is "high", the switching element 3902 becomes conductive. Further, when the output Tn of the timer 1 is “high”, the power supply switching element n is in a conductive state and the voltage Vn is applied to the power supply line 3920. Therefore, only the voltage Vn is applied to the drain line 2921. To be done. Next, the voltage selector 3903 reads the latch data 3902, and outputs Sn (M ≦ n ≦ K−1) corresponding to the data on the data bus 3904.
If only "High", the pulse selector 3917
Read the value of this data bus and the output of timer 1 and 2,
The output P1 outputs the output Tn of the timer 2 as the gate signal 3919. When the gate signal 3919 is "high", the switching element 3922 becomes conductive.
Further, when the output Tn of the timer 2 is “high”, the power supply switching element n becomes conductive and the power supply line 3921
Since the voltage Vn is applied to the drain line 292,
Only the voltage Vn is applied to 1.

As described above, the voltage selector having k outputs, the m (m <k) timers in total of k, the power supply circuit having the same number of output voltages as the number of outputs of each timer, and k
By using the power supply switching elements, the pulse selector having the m outputs, and the m switching elements, it is possible to obtain k gradation display with the m switching elements. Further, by installing a capacitor in parallel with the liquid crystal on the drain line of the liquid crystal driving device having such a k gradation, a display of higher quality can be obtained.

Further, FIG. 38 shows an information device using the liquid crystal display device of the present invention.

In FIG. 38, 4200 is a microprocessor unit (hereinafter abbreviated as MPU), 4201 is a main memory, 4202 is a system bus, 4203 is a display controller, 4204 is a display bus, 4205 is display memory, 4206 is display data. A bus 4207 is a liquid crystal display device. 4208 of the liquid crystal display devices 4207
Is a liquid crystal controller, 4209 is a signal drive circuit control signal, 4210 is a scan drive circuit control signal, 4211 is a signal drive circuit, 4212 is a scan drive circuit, 4213 is a liquid crystal panel, 4214 is a system control signal, and this system control signal 4213 is Are the same as the system control signals 2000 and 2100 in FIGS.

Next, the operation will be described.

The MPU 4200 reads the program stored in the main memory 4201 and draws the display data in the display memory 4205 via the system bus 4202 and the display controller 4203. The drawn display data is read by the display controller 4203. Then, the data is transferred to the liquid crystal display device 4207 via the display data bus 4206. The liquid crystal display device 4207 inputs the display data and the synchronizing signal transferred through the display data bus 4206, and the liquid crystal controller 4208 inputs the signal drive circuit control signal 42 based on the system control signal 4214.
09 and a scan drive circuit control signal 4210 are generated. The signal drive circuit 4211 uses the signal drive circuit control signal 4209.
Then, the scan drive circuit 4212 inputs the scan drive circuit control signal 4210 and applies a voltage corresponding to display data to each pixel portion of the liquid crystal panel 4213 to perform display.

The signal drive circuit described in the above embodiment is applied to the TFT.
Although described as a drive circuit of a liquid crystal display, the present signal drive circuit can be applied to a matrix type device which performs line-sequential scanning and whose display state changes according to a voltage value.

[0229]

[Effect] Even when any of the signal drive circuits of FIGS. 1, 7, 8 and 9 of the present invention is used, display data for one horizontal line is stored as an analog value. Since the circuit is not changed even if the number of colors increases,
This has the effect of preventing an increase in circuit scale.

In addition, since the signal drive circuits of any of FIG. 1, FIG. 7, FIG. 8 and FIG. 9 process display data with digital data, the current operating speed of the digital driver is 1.
High-speed processing of 5 MHz or more is possible, and in the case of configuring the liquid crystal display device shown in FIG. 10, there is an effect that high-speed data processing such as high definition can be supported.

Further, in the signal drive circuits of any of FIG. 1, FIG. 7, FIG. 8 and FIG.
The number of horizontal lines can be configured to be considerably smaller than the number of data, and the increase in the circuit scale due to the increase in the number of gradations or the number of display colors has an effect of suppressing the increase by about 1/10 or less of that of the conventional digital driver.

Further, in the digital type signal drive circuit shown in FIGS. 8 and 9, since the multi-level voltage is generated inside the integrated circuit, the circuit for generating the multi-level voltage externally becomes unnecessary.

When a liquid crystal display device is constructed using the signal drive circuit of the present invention shown in FIGS. 1, 7, 8 and 9, the area occupied by the drive circuit around the liquid crystal panel can be reduced. effective.

Furthermore, when color display is performed using the signal drive circuit of the present invention shown in FIGS. 7 and 9, since different levels of voltage can be selected for each color, color correction is possible and high quality display colors are obtained. There is an effect to be obtained.

Further, by using the DAC of the present invention shown in FIGS. 13 and 14, it is possible to obtain the display brightness in accordance with the visual characteristics from the digital display data.

Further, using the DAC of the present invention shown in FIG.
Even when a liquid crystal having no curve characteristic as shown in FIGS. 11 and 12 is used, the inclination of the approximate straight line can be easily changed, and therefore the effect of easily changing the relationship between the digital display data and the display brightness can be obtained. There is.

Further, according to FIGS. 27, 29, 30, 31, 31, 33, 35, and 37 of the present invention, it is possible to suppress an increase in power supply lines due to the multicolor of the liquid crystal device, and Since the switching element connecting the power supply line and the drain line and the output line of the voltage selector can be reduced, the circuit scale of the X drive means can be reduced. Due to these effects, multi-color / multi-gradation display can be expected even if the area occupied by the drive circuit system around the display unit is reduced.

In the data converting means shown in FIGS. 17 and 22 of the present invention, since the display data is weighted from n bits to m (> n) bits for each R, G, B display data, a color filter or the like is used. A conversion suitable for the characteristic can be performed. As a result, it is possible to supply a voltage level of (2 m-th power) level to the liquid crystal panel, and it is possible to obtain good display quality in accordance with human visual characteristics.

Furthermore, by separating the processing system for each of the R, G, and B display data shown in FIGS. 17 and 22, there is an effect that color correction suitable for the characteristics of the color filter or the like can be performed.

Further, by making the data conversion circuit shown in FIG. 20 writable at any time, or by making the structure switchable at any time shown in FIG. 21, it is possible to maintain the display quality adapted to the characteristics of the pixel.

[Brief description of drawings]

FIG. 1 is a diagram showing a signal drive circuit (D / A system) of the present invention.

FIG. 2 is a block diagram of a conventional liquid crystal display drive circuit.

3 shows an equivalent circuit of the liquid crystal panel shown in FIG.

FIG. 4 shows a driving waveform of a conventional pixel section.

5 is a diagram showing a sample hold circuit for generating the sampling clock shown in FIG.

6 is a diagram showing the timing of the signal drive circuit shown in FIG.

FIG. 7 is a diagram showing a color-correctable signal drive circuit (D / A method) of the present invention.

FIG. 8 is a diagram showing a signal drive circuit (digital system) of the present invention.

FIG. 9 is a diagram showing a signal drive circuit (digital system) capable of color correction of the present invention.

FIG. 10 is a diagram showing a liquid crystal display device using the signal drive circuit of the present invention.

FIG. 11 is a diagram showing a characteristic curve of gradation number and display luminance.

FIG. 12 is a diagram showing a characteristic curve of voltage and display luminance.

FIG. 13 is a diagram showing a DAC to which the correction circuit of the present invention is added.

FIG. 14 is a diagram showing a DAC to which an externally controllable correction circuit of the present invention is added.

15 is a diagram showing a voltage divider and a voltage multiplexer capable of color correction in the signal drive circuit shown in FIGS. 8 and 9. FIG.

16 is a diagram showing a voltage-dividing circuit and a voltage multiplexer capable of color correction in the signal drive circuit shown in FIGS. 8 and 9;

FIG. 17 is a diagram showing a signal drive circuit (D / A system) of the present invention to which a data conversion circuit is added.

FIG. 18 shows drive waveforms when VCOM of the present invention is constant.

FIG. 19 shows drive waveforms when the VCOM of the present invention is made alternating.

FIG. 20 is a block diagram of a data conversion circuit of the present invention that can be rewritten at any time.

FIG. 21 is a block diagram of a data conversion circuit that can be selected at any time according to the present invention.

FIG. 22 is a diagram showing a signal drive circuit (digital system) of the present invention to which a data conversion circuit is added.

FIG. 23 is a diagram showing a conventional signal drive circuit (HD66300).

FIG. 24 is a block diagram of a conventional liquid crystal drive circuit.

FIG. 25 shows an operation timing of the liquid crystal drive circuit shown in FIG. 24.

FIG. 26 is a diagram showing a liquid crystal display device of the present invention.

FIG. 27 is a block diagram of a two-level voltage application method of the present invention.

FIG. 28 is a time chart of a 2-level voltage application method according to the present invention.

FIG. 29 is a block diagram of a two-level voltage application method of the present invention.

FIG. 30 is a block diagram of a multi-level voltage applying method of the present invention.

FIG. 31 is a block diagram of a 4-level voltage stepwise application method according to the present invention.

FIG. 32 is a time chart of a 4-level voltage stepwise application method according to the present invention.

FIG. 33 is a block diagram of a 4-level voltage stepwise application method according to the present invention.

FIG. 34 is a time chart of a 4-level voltage stepwise application method according to the present invention.

FIG. 35 is a block diagram of a sloped voltage application method of the present invention.

FIG. 36 is a time chart of the sloped voltage application method of the present invention.

FIG. 37 is a block diagram of a multi-level voltage stepwise application method of the present invention.

FIG. 38 is a block diagram of an information device using the liquid crystal display device of the present invention.

[Explanation of symbols]

100 ... Digital display data, 101 ... Shift clock, 102 ... Shift register, 103 ... Data line, 10
4 ... Latch clock, 105 ... Latch, 106 ... Data line, 107 ... D / A converter (DAC), 108 ... Data line, 109 ... Sampling clock, 110 ... Sample hold circuit, 111 ... Hold clock, 112
... data line, 113 ... buffer, 114 ... signal line, 11
6 ... Scan drive circuit 117 ... Enable signal for validating vertical first line 118 ... Clock for sequentially selecting lines 119 ... Gate line 120 ... Color liquid crystal panel 200 ... Display data 200R ... 3 bits R
Data, 200G ... 3-bit G data, 200B ... 3
Bit B data, 201 ... Data rearrangement circuit, 20
2 ... Display data, 203 ... Block diagram of liquid crystal drive circuit composed of HD66310T, 204 ... Shift circuit, 20
5 ... Capture clock, 206 ... Latch circuit, 207 ...
Latch clock, 208 ... Data decode circuit, 209
... voltage multiplexer, 211 ... voltage generation circuit, 212
Input high level voltage, 213 Input low level voltage,
214 ... 16-level liquid crystal applied voltage, 300 ... One pixel portion, 301 ... Thin film transistor, 302 ... Liquid crystal, 30
3 ... Storage capacitor, 304 ... Counter electrode, VGH ... Gate on voltage, VGL ... Gate off voltage, VCOM ... Counter voltage,
V7-V0, -V0, -V7 ... Drain voltage, 500
... sample clock generation circuit, 501 ... enable signal, 502 ... enable signal, 100R ... R digital display data, 100G ... G digital display data, 100B
... B digital display data, 102R ... R shift register, 102G ... G shift register, 102B ... B shift register, 103R ... R data line, 103G ... G
Data line, 103B ... B data line, 105R ... R latch, 105G ... G latch, 105B ... B latch, 10
6R ... R data line, 106G ... G data line, 106
B ... B data line, 107R ... R DAC, 107G ...
G DAC, 107B ... B DAC, 108R ... R data line, 108G ... G data line, 108B ... B data line, 800 ... Decoder, 801, ... Selection signal, 802 ...
Power supply, 803 ... Power supply, 804 ... Voltage dividing circuit, 805 ... Multi-level voltage, 806 ... Voltage multiplexer, 800R ... R
Decoder, 800G ... G decoder, 800B ... B decoder, 801R ... R selection signal, 801G ... G selection signal, 801B ... B selection signal, 804R ... R voltage dividing circuit, 804G ... G voltage dividing Circuit, 804B ... B voltage dividing circuit, 805R ... R multi-level voltage, 805G ... G multi-level voltage, 805B ... B multi-level voltage, 806R ... R
Voltage multiplexer, 806G ... G voltage multiplexer, 806B ... B voltage multiplexer, 1000-
1 to 1000-8 ... Signal drive circuit, 1001-1, 1
001-2 ... Enable signal, 1100 ... Characteristic curve of gradation number and display brightness, 1200 ... Characteristic curve of voltage and display brightness, 201, 1202, 1203 ... Approximate straight line, 1300
... current generation circuit, 1301 ... power supply, 1302 ... reference power supply, 1303 ... data line, 1304 ... determination circuit, 130
5 ... Data line, 1306 ... Current selection circuit, 1307 ... Data line, 1308 ... Addition circuit, 1309 ... Switch, 1
310 ... Resistance, 1400 ... Power supply, 1401 ... Variable resistance,
1402 ... Data line, 1403 ... Current generation circuit, 140
4 ... Reference current source, 1500 ... High-order bit decoder, 15
01 ... Lower bit decoder, 1502 ... Decode signal,
1503 ... Decode signal, 1504 ... Voltage dividing circuit, 150
5 ... Voltage line, 1507 ... Voltage dividing resistor, 1508 ... Switching circuit, 1509 ... Switching circuit, 1512 ... Voltage dividing circuit, 1513 ... Voltage dividing resistor, 1514 ... Switching circuit, 1515 ... Data line, 1600 ... Decoder, 16
01 ... Decode signal, 1602 ... Voltage dividing resistor, 1603 ...
Switching circuit, 700R ... R display data, 700
G ... G display data, 700B ... B display data, 70
1 ... Data conversion circuit, V (2 m-1) to V0, -V
0-V (2 m-1) ... Drain voltage, 2000 ...
System control signal, 2001R ... R / G data selector, 2001B ... G / B data selector, 2002 ... n
Bit R data, 2003 ... n bit B data, 2
004 ... Control circuit, 2005 ... Color / monochrome control signal, 2006 ... Data conversion circuit control signal, 2007 ... Constant storage circuit control signal, 2008R ... R data conversion circuit,
2008G ... G data conversion circuit, 2008B ... B data conversion circuit, 2009 ... constant storage circuit, 2010 ... constant data bus, 100R ... m bit R data, 100G ...
m-bit G data, 100B ... m-bit B data,
2100 ... System control signal, 2101R ... R / G data selector, 2101B ... G / B data selector, 21
02R ... n bit R data, 2102B ... n bit B data, 2103 ... control circuit, 2104 ... color / monochrome control signal, 2105a ... enable signal, 210
5b ... Enable signal, 2106R ... R system data conversion circuit, 2107R ... R system data conversion circuit, 2106G ... G
System data conversion circuit, 2107G ... G system data conversion circuit,
2106B ... B system data conversion circuit, 2107B ... B system data conversion circuit, 2108R ... m bit R data, 21
08G ... m-bit G data, 2108B ... m-bit B data, 2300 ... analog display data, 2301 ...
Sample-and-hold clock 2302 ... Sample-and-hold circuit, 2303 ... Data line, 2304 ... Buffer, 2
305 ... Signal line, 2400 ... Input signal, 2401 ... Storage circuit, 2402 ... Storage circuit, 2403 ... Storage circuit, 24
04 ... storage circuit, 2405 ... storage circuit, 2406 ... storage circuit, 2407 ... latch signal, 2408 ... latch signal,
2409 ... Latch signal, 2410 ... Latch signal, 241
1 ... Signal line, 2412 ... Signal line, 2413 ... Signal line, 2
414 ... Switching circuit, 2415 ... D / A converter,
2416 ... Switching circuit, 2417 ... Signal electrode, 241
8 ... Signal electrode, 2419 ... Signal electrode, 2420 ... Selection signal, 2421 ... Selection signal, 2422 ... Driving circuit, 242
3 ... Latch signal, 2424 ... Latch signal, 2425 ... Latch signal, 2426 ... Signal electrode, 2427 ... Signal electrode,
2428 ... Signal electrode, 2800 ... Display data, 2801
... Clock, 2802 ... Signal drive circuit, 2803 ... Multi-level power supply circuit, 2804 ... Power supply output bus, 2805 ... Timer, 2806 ... Timer output bus, 2807 ... Liquid crystal panel, 2900 ... Display data, 2901 ... Latch circuit, 2
902 ... Clock, 2903 ... Latch data, 2904
... Voltage selector, 2905 ... Selector lines S0, 2906
... Selector lines S1, 2907 ... Timer setting data, 29
08 ... Scan signal, 2909 ... Timer, 2910 ... Timer output T0, 2911 ... Timer output T1, 2912 ... Power supply circuit, 2913 ... Power supply line V0, 2914 ... Power supply line V1,
2915 ... Pulse selector, 2916 ... Gate signal, 2
917, 2918 ... Switching element for power supply, 2919
... power supply line, 2920 ... switching element, 2921 ... drain line, 2922 ... scan drive circuit, 2923 ... enable signal, 2924 ... scan line, 2924-a ... dummy scan line, 2925 ... scan line, 2926, 2928 ... liquid crystal switching Element, 2927, 2929 ... liquid crystal, 293
0, 2930 ... added capacity, 3100 ... capacitor, 32
00 ... Display data, 3201 ... Latch circuit, 3202 ...
Latch data 3203 ... Voltage selector 3204 ... Selector lines S0, 3205 ... Selector lines S1, 3206 ...
Selector lines S2, 3207 ... Selector lines S3, 3208
... Selector lines S4, 3209 ... Selector lines S5, 321
0 ... Selector lines S6, 3211 ... Selector lines S7, 32
12 ... Power supply circuit, 3213 ... Power supply output V0, 3214 ...
Power output V1, 3215 ... Power output V2, 3216 ... Power output V3, 3217 ... Power output V4, 3218 ... Power output V5, 3219 ... Power output V6, 3220 ... Power output V7, 3221, 3222, 3223, 3224, 3
225, 3226, 3227, 3228 ... Power supply switching element, 3229 ... Pulse selector, 3230 ... Gate signal S'0, 3231 ... Gate signal S'1, 323
2 ... Gate signal S'2, 3233 ... Gate signal S'3,
3234, 3235, 3236, 3237 ... Power supply line, 3
238, 3239, 3240, 3241 ... Switching element, 3242 ... Drain line, 3300 ... Display data,
3301 ... Latch circuit, 3302 ... Latch data, 33
03 ... voltage selector, 3304 ... timer installation data, 3
305 ... Timer, 3306 ... Selector line S0, 3307
... Selector lines S1, 3308 ... Selector lines S2,330
9 ... Selector lines S3, 3310 ... Timer outputs T0, 33
11 ... Timer output T1, 3312 ... Timer output T2,3
313 ... Timer output T3, 3314 ... Power supply circuit, 331
5 ... Power output V0, 3316 ... Power output V1, 3317
Power supply output V2, 3318 ... Power supply output V3, 3319,
3320, 3321, 3322 ... Power supply switching element, 3323 ... Pulse selector, 3324 ... Gate signal, 3500 ... Timer setting data, 3501 ... Timer,
3502, 3503, 3504 ... XOR element, 350
5,3506,3507 ... XOR element output, 3700 ...
Sawtooth wave generation circuit, 3701 ... Sawtooth wave generation circuit output, 3702 ... Amplification circuit, 3900 ... Display data, 39
01 ... Latch circuit, 3902 ... Latch data, 3903
... Voltage selector, 3904 ... Voltage selector output bus, 3
905 ... Timer setting data, 3906 ... Timer 1, 39
07 ... power supply circuit 1, 3908 ... timer setting data, 39
09 ... Timer 2, 3910 ... Power supply circuit 2, 3911 ... Timer 1 output bus, 3912 ... Power supply circuit 1 output bus, 39
13 ... Power supply switching element, 3914 ... Timer 2 output bus, 3915 ... Power supply circuit 2 output bus, 3916 ... Power supply switching element, 3917 ... Pulse selector, 3
918, 3919 ... Gate signal, 3920, 3921 ...
Power line, 3922, 3923 ... Switching element, 42
00 ... MPU, 4201 ... Main memory, 4202 ... System bus, 4203 ... Display controller, 4204 ...
Display bus, 4205 ... Display memory, 4206 ... Display data bus, 4207 ... Liquid crystal display device, 4208 ... Liquid crystal controller, 4209 ... Signal drive circuit control signal, 421
0 ... Scan drive circuit control signal, 4211 ... Signal drive circuit, 4212 ... Scan drive circuit, 4213 ... Liquid crystal panel.

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Masaaki Kitajima 4026 Kujimachi, Hitachi City, Ibaraki Hitachi, Ltd., Hitachi Research Laboratory (72) Norio Tanaka, 292 Yoshidacho, Totsuka-ku, Yokohama, Kanagawa Hitachi, Ltd. Microelectronics Device Development Laboratory (72) Inventor ▲ Hiroyuki Mano 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Ltd. Microelectronics Device Development Laboratory (72) Inventor Toshio Futami 3300 Hayano, Mobara-shi, Chiba Prefecture Hitachi Ltd. Mobara factory

Claims (36)

[Claims] 1. A liquid crystal display device having a pixel portion arranged in a matrix, the pixel portion having a switching element and a liquid crystal, wherein light transmission is controlled by a display signal applied to the liquid crystal to display an image. In the drive circuit, means for sequentially taking in digital display data having a capacity smaller than the number of signal lines output in parallel to the pixel portion and temporarily storing the digital display data, and means for converting the digital display data having the capacity to corresponding analog display data. A liquid crystal display, wherein a plurality of sets of the analog display data whose capacities have been converted are sequentially captured, and the analog display data of the number of signals to be output in parallel are captured and then simultaneously output. Multi-gradation drive circuit of the device. 2. The digital display data is red (hereinafter, R
ed: Abbreviated as R. ), Green (hereinafter abbreviated as Green: G), and blue (hereinafter abbreviated as Blue: B) digital display data, each of the R, G, and B digital display data is weighted differently, and the analog The multi-gradation drive circuit for a liquid crystal display device according to claim 1, wherein the multi-gradation drive circuit converts the display data. 3. A matrix by combining a plurality of multi-gradation driving circuits according to claim 1, and simultaneously outputting the analog display data of the number of the display signals output in parallel in each of the multi-gradation driving circuits. The liquid crystal display device is characterized in that the display signal for one horizontal line of the pixel portion arranged in the above is used. 4. A liquid crystal display having pixel portions arranged in a matrix, each pixel portion having a switching element and a liquid crystal, wherein light transmission is controlled by display data applied to the liquid crystal to display an image. In the apparatus, means for dividing the display data for one horizontal line into N (N is an integer), sequentially taking in digital display data for 1 / N horizontal lines, and temporarily storing the digital display data for 1 / N horizontal lines; Means for converting digital display data into corresponding analog display data, and sequentially taking in each analog display data for 1 / N horizontal lines, after taking in the analog display data for one horizontal line, and simultaneously for the pixel section A multi-gradation driving circuit for a liquid crystal display device, which is provided with a means for outputting. 5. The digital display data is red (hereinafter, R
ed: Abbreviated as R. ), Green (hereinafter abbreviated as Green: G), and blue (hereinafter abbreviated as Blue: B) digital display data, each of the R, G, and B digital display data is weighted differently and the analog display is performed. The multi-gradation driving circuit for a liquid crystal display device according to claim 4, wherein the multi-gradation driving circuit converts the data. 6. A pixel unit arranged in a matrix, each pixel unit comprising a switching element and a display unit, and the display unit via the switching element for each horizontal line of the pixel unit. In an image display device that applies a display signal to a multi-gradation image display, the horizontal direction of the pixel portions arranged in a matrix is set to M.
(M is an integer), and the M-divided pixel units are provided with M multi-gradation driving circuits arranged in the horizontal direction for applying the display signal for each horizontal line to each of the M-divided pixel units. The M multi-gradation driving circuits arranged in each direction sequentially divide the display signal of the M-divided pixel portion into N (N is an integer) to obtain 1 / (M × N) horizontal lines. Means for sequentially fetching and temporarily storing digital display data corresponding to a minute, and connected to the storage means, and each time the digital display data corresponding to 1 / (M × N) horizontal lines is fetched, a corresponding analog display data is obtained. A unit for converting, and a unit connected to the converting unit for taking in the analog display data for 1 / M horizontal lines, the M multi-gradation driving circuits all have the analog display data for 1 / M horizontal lines. 1 horizontal line after capturing An image display device comprising a minute of the analog display data simultaneously applied to the display unit. 7. The digital display data is red (hereinafter, R
ed: Abbreviated as R. ), Green (hereinafter abbreviated as Green: G), and blue (hereinafter abbreviated as Blue: B) digital display data, each of the R, G, and B digital display data is weighted differently and the analog display is performed. The image display device according to claim 6, wherein the image display device converts the data. 8. Each of the M multi-grayscale driving circuits arranged in the horizontal direction, when the analog display data is taken in by 1 / M horizontal lines, the other multi-grayscale driving circuits adjacent to each other are fetched. 7. The image display device according to claim 6, wherein the image display device generates an enable signal for operating. 9. The means for temporarily storing is 1 / (M × N)
7. The image display device according to claim 6, comprising a shift register for taking in the digital display data corresponding to horizontal lines, and a latch circuit for latching parallel outputs of the shift register. 10. The conversion means comprises a digital / analog converter for converting the digital display data corresponding to 1 / (M × N) horizontal lines into the corresponding analog display data. 6. The image display device according to 6. 11. The image display device according to claim 6, wherein the means for taking in the analog display data for 1 / M horizontal lines comprises a sample hold circuit for holding the analog display data. 12. The converting means includes a decoder for decoding the digital display data corresponding to 1 / (M × N) horizontal lines, a means for generating a plurality of voltage levels, and an output of the decoder. 7. The image display device according to claim 6, further comprising selection means for selecting the plurality of voltage levels from the voltage level generation means. 13. A digital / analog conversion means for generating a voltage applied to a liquid crystal necessary for obtaining a display brightness represented by the digital display data, wherein a plurality of curves showing a relationship between the voltage applied to the liquid crystal and the display brightness are provided. Which straight line is approximated, and which straight line is used to approximate the digital display data in order to make the display brightness expressed by the digital display data correspond to the voltage applied to the liquid crystal so as to follow the trajectory of the plurality of straight lines? Determination means for determining, a current generation means having a plurality of weights for each bit of the digital display data, based on the result of the determination means of the current value having a plurality of weights for each bit of the digital display data It is characterized by comprising selection means for selecting any one and addition means for performing addition processing of the selected current values to generate a desired voltage. Multi-gradation driving circuit of 1 wherein. 14. A digital / analog converting means for generating a voltage applied to a liquid crystal necessary for obtaining a display brightness represented by the digital display data, wherein a plurality of curves showing a relationship between the voltage applied to the liquid crystal and the display brightness are provided. Which straight line is approximated, and which straight line is used to approximate the digital display data in order to make the display brightness expressed by the digital display data correspond to the voltage applied to the liquid crystal so as to follow the trajectory of the plurality of straight lines? Based on the result of the determination unit, a current generation unit having a plurality of weights for each bit of the digital display data, a voltage generation circuit that makes the voltage supplied to the current generation circuit variable, Selecting means for selecting one of a plurality of current values having a plurality of weights for each bit of the digital display data, and adding the selected current values, 2. The multi-gradation driving circuit for a liquid crystal display device according to claim 1, further comprising an adding means for generating a desired voltage. 15. The digital-to-analog converter of the conversion means according to claim 16, wherein the digital-analog converter of the conversion means generates a voltage required to obtain a display brightness represented by the digital display data. Top m of
Decoding means for decoding bits, decoding means for decoding lower (n−m) bits, and two adjacent voltage levels of the (2 m + 1) level voltage from the decoding result of the upper m bits Means, a voltage dividing means for dividing the voltage of the selected two levels, and a decoding result of the lower (nm) bits, the voltage dividing means divides the voltage (2 (nm)). 11. The multi-gradation drive circuit for a liquid crystal display device according to claim 10, comprising means for selecting any one of the (multiplied) level voltages. 16. The multi-gradation device of a liquid crystal display device according to claim 12, wherein voltage dividing means for dividing a voltage among a plurality of levels of an input voltage between adjacent voltage levels is integrated. Drive circuit. 17. A color liquid crystal display driving device for controlling display brightness by a voltage value applied to a liquid crystal panel having R, G, B pixels, wherein n (bit) R, G, B display data are respectively represented by m ( > N)
A drive circuit for a liquid crystal display device, comprising: a data conversion means for converting into bit display data; and the multi-gradation drive circuit according to claim 1. 18. A drive circuit for a liquid crystal display device according to claim 1, wherein said data conversion means is configured to store a conversion constant, and the conversion constant is read from the means for storing said conversion constant. 19. The drive circuit for a liquid crystal display device according to claim 1, wherein said data conversion means has a plurality of data conversion circuits having different conversion contents for each of R, G and B. 20. The liquid crystal display device according to claim 17, further comprising means for receiving a control signal from the outside and switching the display data bus connected to the input of the data conversion means to another display data bus. Drive circuit. 21. A pixel unit arranged in a matrix,
The pixel portion has a switching element and a liquid crystal, and in a driving method of a liquid crystal display device that controls light transmission by a display signal applied to the liquid crystal to display an image, the number of signal lines output in parallel to the pixel portion. Digital display data of a smaller capacity is sequentially captured, temporarily stored, digital display data of the capacity is converted to corresponding analog display data, and a plurality of sets of the analog display data having the converted capacity are sequentially captured, A multi-gradation driving method for a liquid crystal display device, wherein the analog display data corresponding to the number of output signals is captured and then simultaneously output. 22. The digital display data is red (hereinafter,
Red: Abbreviated as R. ), Green (hereinafter abbreviated as Green: G), and blue (hereinafter abbreviated as Blue: B) digital display data, each of the R, G, and B digital display data is weighted differently, and the analog 22. The multi-gradation driving method for a liquid crystal display device according to claim 21, wherein the display data is converted into display data. 23. Arrangement in a matrix by performing a plurality of the temporary storages and the conversion into the analog data in parallel, and simultaneously outputting the analog display data of the number of the display signals to be output in parallel. 1 of the pixel unit
A liquid crystal display method, wherein the display signal for horizontal lines is used. 24. An active matrix liquid crystal panel that constitutes each display pixel portion with a switching element and liquid crystal, and n of 2 based on input n-bit (n is an integer) liquid crystal display data.
A voltage selector that selects one of the power level voltages,
In a liquid crystal display device comprising an X driving means capable of applying a selected voltage to each display pixel portion and obtaining a gradation color having a display brightness of 2n level, within a scanning time of one line in the X direction, That is, when the switching element is in the conducting state, a means for sequentially applying different levels of voltage to the power supply lines for liquid crystal applied voltage of 2n or less, and the voltage corresponding to the display data is the power supply line for liquid crystal applied voltage. A liquid crystal drive device capable of obtaining a gradation color according to display data by accumulating in the liquid crystal by means for propagating the selected voltage to each display pixel portion when applied to the liquid crystal display device. .. 25. A liquid crystal driving method according to claim 24, wherein the application time of the voltage of each level sequentially supplied to the drain line of each pixel portion can be set arbitrarily. 26. The voltage applied to one power supply line is made stepwise, and the voltage is supplied to each pixel portion during a period in which a voltage of a level corresponding to liquid crystal display data is selected. A liquid crystal driving method characterized in that a means for not supplying the voltage is provided to each pixel portion during a period in which a voltage of a level not corresponding to display data is selected. 27. The voltage applied to one power supply line is made stepwise, and the voltage is supplied to each pixel portion until a voltage of a level corresponding to liquid crystal display data is selected, A liquid crystal driving method characterized in that a means for not supplying the voltage is provided to each pixel portion after a period of selecting a voltage of a level corresponding to liquid crystal display data has passed. 28. Means for increasing or decreasing the applied voltage of one power supply line relative to time according to claim 24, and applying a voltage to each pixel portion from the beginning of scanning to a voltage corresponding to liquid crystal display data, A liquid crystal driving method characterized in that the voltage is not applied to each pixel section when the voltage corresponding to the display data is exceeded. 29. The voltage applied to a plurality of power supply lines according to claim 24, wherein each of the voltages has a stepwise pattern of different levels, and only when the voltage is applied from a power supply line to which a voltage corresponding to display data is applied. A liquid crystal driving method, characterized in that means is provided for not supplying the voltage to each pixel portion during a period in which the voltage is applied to each pixel portion and a voltage of a level not corresponding to the liquid crystal display data is selected. 30. An active matrix liquid crystal panel comprising a first switching element and a liquid crystal forming each pixel of a matrix display pixel section, and a scanning line selecting means for selecting the pixel on one horizontal line of the display pixel section. And the voltage corresponding to the input n-bit (n is an integer) display data,
A driving device for a liquid crystal display device, comprising: an X driving unit which is applied to each of the pixels selected by the scanning line selecting unit and obtains a gradation color having a display luminance of 2 n level. A power supply line for liquid crystal applied voltage of at least 1 and less than or equal to 2 n power lines, and a voltage of 2 n power level is sequentially applied to the power supply line for liquid crystal applied voltage within the scanning time of one line in the X direction. And a means for driving the liquid crystal by propagating the voltage to each display pixel portion when the voltage corresponding to the display data is applied to the liquid crystal applied voltage power supply line, A driving device for a liquid crystal display device, which obtains a gradation corresponding to the display data. 31. The driving device of a liquid crystal display device according to claim 30, wherein the applying means can arbitrarily set an application time of the voltage applied sequentially. 32. The applying means generates the n-th power level voltage, and the n-th power level voltage output from the generating means.
Within the scanning time of one line in the X direction, a timer means for sequentially generating a timing pulse for applying to the power source line for liquid crystal application voltage for a predetermined time, and the timing pulse generates the voltage of the n-th power level of 2 31. The drive device for a liquid crystal display device according to claim 30, further comprising a gate means for applying the power supply line for the liquid crystal applied voltage. 33. The liquid crystal driving means receives the voltage selector means for generating a voltage select signal based on the display data, the output of the voltage select means, and the timing pulse which is the output of the timer means. A second switching element that applies the voltage to the drain line connected to the first switching element when the voltage corresponding to the display data is applied to the liquid crystal application voltage power supply line. 33. The drive device for a liquid crystal display device according to claim 32, comprising: 34. The driving device for a liquid crystal display device according to claim 33, wherein a capacitance is connected to the drain line. 35. The driving device of a liquid crystal display device according to claim 33, wherein the liquid crystal driving means for at least several pixels in the horizontal direction are contained in one LSI chip. 36. The applying means for sequentially applying the voltage of the n-th power level of 2 is a voltage generating means for generating a voltage of a different level, and a gate for applying a voltage of the different level to the liquid crystal applied voltage power source line. Gate means and timer means controlled by timer setting data that defines the connection time of the gate means, wherein the liquid crystal driving means comprises the liquid crystal applied voltage power supply line and the first switching means. A second switching element for connecting a drain line connected to the element, voltage selector means for outputting a select signal for determining an applied voltage from the display data, the select signal of the voltage selector means and the timer 31. The drive device for a liquid crystal display device according to claim 30, further comprising a logic circuit which receives an output of the means and generates an open / close control signal for the second switching element.