JPH07104716A - Display device - Google Patents

Abstract

PURPOSE:To decrease the number of reference voltages to be smaller than the number of gradations of display without complicating a peripheral circuit and to make multilevel image even when the packaging space of drivers on the data line side is limited by outputting a gradation signal of a voltage value of averaged reference voltage values selected corresponding to the respective digital video signal groups. CONSTITUTION:Respective decoder circuits 21, 22 select one reference voltage from a reference voltage source of the reference voltage group 23 composed of reference voltages V11-V1A supplied from a generating source and of a reference voltage group 24 composed of reference voltages V21-V2B in accordance with an inputted digital video signal by means of analog switches SW11-SW1A, SW21-SW2B, respectively. The voltage value on X point is the averaged value between two reference voltages selected from the reference voltage groups 23, 24 by means of the ON resistance of analog switches of one among the switches SW11-SW1A and one among switches SW21-SW2B modes turned on by means of the decoder circuits 21, 22, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device capable of displaying an image corresponding to a digital video signal.

[0002]

2. Description of the Related Art FIG. 6 shows a data line side driver IC of a conventional TFT active matrix type liquid crystal display device. The driver IC of FIG. 6 is for 8-gradation display, and is a 3-bit digital video signal D _0j , D _1j , D corresponding to a liquid crystal pixel.
_2j synchronizes with the clock signal CL2 and the first latch circuit 1
01 is input. The digital video signal input to the first latch circuit 101 is then input to the second latch circuit 102 in synchronization with the clock signal CL1. And
The output of the second latch circuit 102 is the voltage selector circuit 10.
Input to 3.

The voltage selector circuit 103 is composed of a decoder circuit and the like. For example, 2 ³ = 8 reference voltage groups (V ₀ according to a ³ -bit digital video signal).
~V ₇₎ from performs data output to the analog switch 104a~104h for selecting one of the reference voltages, the one analog switch reference selection of 104a~104h became ON state One of the reference voltages V _{0 to} V ₇ connected to it is selected and output to the driver output Yn. In addition,
In the example of FIG. 6, 2 ³ = having different voltage values from each other
The eight reference voltages V _{0 to} V ₇ are supplied from an unillustrated source.

[0004]

In the above structure, since the number of display gradations and the number of reference voltages are equal, it is necessary to increase the number of reference signals in order to achieve multiple gradations. However, if the number of reference voltages increases, the wiring space for supplying the reference voltage to the data line side driver IC becomes large, which hinders the miniaturization of the display panel. Therefore, when the mounting space of the data line side driver IC is limited, it is difficult to realize multiple gradations. Further, when the number of reference voltages increases, the wiring space in the data line side driver IC also becomes large, and it becomes difficult to reduce the size of the IC, which hinders cost reduction.

Therefore, there is a TFT type active matrix type liquid crystal display device which adopts a frame rate control (FRC) method for displaying a halftone by blinking a pixel for each frame or field. For example, when one frame is composed of three fields and four gradations are displayed by a 2-bit digital video signal, the digital video signals (D ₁ , D ₀ ) are supplied to the peripheral circuit as shown in (2) of FIG. 1
Then, the pixel is turned off for three consecutive fields in the darkest first gradation as shown in (1) of FIG. In the second field, the pixel is turned off, the pixel is turned on in the first field, and in the second brightest gradation, the pixel is turned off in the first field and the pixel is turned on in the second field. In the fourth gradation, the pixels are turned on for three consecutive fields. Further, since flicker is conspicuous when pixels adjacent to each other continue to blink, a plurality of pixels are grouped into one group, and the pixels in each group are blinked so as to exhibit a mosaic pattern. However, in order to perform such frame rate control, it is necessary to perform arithmetic processing on the digital video signal in advance and send it to the source driver, which causes a problem that the peripheral circuit 121 of the source driver becomes complicated.

It is an object of the present invention to provide a display device which can solve the above-mentioned problems of the prior art.

[0007]

According to the present invention, in a display device for outputting a gradation signal having a voltage value corresponding to a digital video signal to each data line of a matrix type display panel, the digital video signal is sequentially arranged from the upper bits. It is divided into m (m ≧ 2) digital video signal groups, and the reference voltage corresponding to each digital video signal group is selected and selected from each of the m reference voltage groups corresponding to each digital video signal group. It is characterized in that a gradation signal having a voltage value obtained by averaging m reference voltage values is output to the data line.

[0008]

According to the structure of the present invention, for example, when the digital video signal is n bits, and is divided into a bit and ab bit (a + b = n) from the upper bit, it corresponds to the upper a bit digital video signal. A reference voltage is selected from a first reference voltage group consisting of 2 ^a reference voltages, and ^a reference voltage corresponding to a lower b-bit digital video signal is selected as a second reference voltage group consisting of 2 ^b reference voltages. Select from. A gradation signal whose voltage value is the average value of the reference voltage selected from the first reference signal group and the reference voltage selected from the second reference voltage group is output to the data line. Therefore, the maximum value of the number of gradations is the product of the reference voltage number 2 ^a of the first reference voltage group and the reference voltage number 2 ^b of the second reference voltage group, and 2 ^{a + b} =
2 ⁿ gradations can be obtained. On the other hand, the reference signal number is 2 ^a +2 ^b , and if the digital video signal is 3 bits or more, the reference signal number can be smaller than the gradation number. As a result, it is possible to increase the number of gradations without increasing the reference voltage, as compared with the case where the number of gradations is equal to the number of reference voltages in the related art.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 shows a structure of a TFT type active matrix type liquid crystal display device capable of displaying an image corresponding to a digital video signal. The liquid crystal display panel 5 is shown in FIG.
Source driver 52 which is the driver IC on the data line side 1
And a gate driver 53 which is a scanning line side driver IC. A gradation display signal corresponding to the digital video signal is output from the source driver 52 to each data line 55 of the liquid crystal display panel 51, and the source driver 52 and the gate driver 53 according to the horizontal synchronizing signal and the vertical synchronizing signal of the video signal. An image is displayed by sending a drive signal from the non-illustrated control device.

FIG. 1 is a block diagram showing a gradation drive circuit according to an embodiment of the present invention, in which 2 ⁿ per pixel of a liquid crystal display element.
This is an example of reproducing gradation display of gradation (where n is an integer of 2 or more). In FIG. 1, n-bit digital video signal data D0 to Dn corresponding to display pixels are sequentially stored in the data register circuit 2 at the timing of the shift clock CP. When the digital video signal data for one horizontal scanning line is stored in the data register circuit 2, O
The signals are simultaneously stored in the latch circuit 3 at the timing of the E signal. Here, the data register circuit 2 and the latch circuit 3 correspond to the memory circuit of the present invention. The digital video signal data output from the latch circuit 3 is input to the D / A conversion circuit 5 after passing through the level shifter circuit 4. The D / A conversion circuit 5 inputs the r-type (2 <r <2 ⁿ ) gradation driving reference voltages (V _{0 to} V _r ) and outputs a voltage value corresponding to n-bit digital video signal data to each data. Output to the lines O _{1 to} O _k .

FIG. 2 shows a D / A conversion circuit according to an embodiment of the present invention. Level shift circuit 5 in FIG.
The n-bit digital video signal output from is divided into two groups of upper a bits and lower b bits (a + b = n),
It is inputted to the upper a-bit decoder circuit 21 and the lower b-bit decoder circuit 22, respectively. Each decoder circuit 2
Reference numerals 1 and 22 denote 2 ^a = A reference voltages (V _{11 to} V) supplied from an unillustrated generation source according to an input digital video signal.
_1A ) of a first reference voltage group 23 and ^2b = B of B reference voltages (V _{21 to} V _2B ) of a second reference voltage group 24.
Analog switches SW _{11 to} S from the two reference voltage sources
By W _1A, and SW ₂₁ to SW _2B, selects one of the reference voltages, respectively. The voltage value at the point X in FIG. 2 is SW ₁₁ in which the two reference voltages selected from the reference voltage groups 23 and 24 are turned on by the decoder circuits 21 and 22.
To SW _1A and one of SW _{21 to} SW _2B , the ON resistance of the analog switch causes the voltage value to be averaged, and this voltage value is transferred from the buffer amplifier circuit 25 to the matrix display panel. Is output to the data line 26 of.

In the above structure, the total number of reference voltages forming each reference voltage group is set to be smaller than the number of gradations. For example, when the digital video signal is divided into two groups of upper 3 bits and lower 3 bits with 6 bits, the first reference signal group (corresponding to the digital video signals (D ₁ to D ₃ ) of the upper 3 bits ( The respective reference voltages included in V _{1 to} V ₈ ) are set as shown in (1) of FIG. 3, and the second reference signal corresponding to the lower 3 bits of the digital video signal (D _{4 to} D ₆ ). By setting the respective reference voltages included in the group (V _{9 to} V ₁₆ ) as shown in (2) of FIG. 3, 64 gray scales having different voltage values as shown in (3) of FIG. A gradation signal can be obtained. As a result, as shown in (4) of FIG. 3, the transmittance of each pixel of the liquid crystal display device can be changed according to the voltage value of the gradation signal. That is, the maximum value of the number of gradations is the product of the reference voltage number 2 ^a of the first reference voltage group and the reference voltage number 2 ^b of the second reference voltage group, and 2 ^{a + b} = 2 ⁿ It is possible to set gradation (64 gradations in the illustrated example). On the other hand, the reference voltage is 2 ^a
The number is +2 ^b (16 in the illustrated example), and if the digital video signal is 3 bits or more, the number of reference voltages can be smaller than the number of gradations. That is, the number of gradations can be increased without increasing the reference voltage, as compared with the case where the number of gradations is equal to the number of reference voltages in the related art. further,
The number of divisions of the digital video signal and the number of reference voltage groups corresponding thereto can be three or more. It should be noted that the voltage value of the gradation signal output to the data line 26 in FIG. 2 has a polarity that is inverted between positive and negative in each field to prevent deterioration of the liquid crystal, and positive and negative in each horizontal period to prevent flicker. Each reference voltage may be alternating so as to be inverted.

According to the above liquid crystal display device, the number of gradation driving reference voltages can be made smaller than the number of display gradations without complicating the peripheral circuits of the source driver 2, and the source driver 2 is mounted. Even if the space is limited, multi-gradation can be performed.

FIG. 4 shows a second embodiment of the present invention. The difference from the above embodiment is that each divided signal of the digital video signal is input to two different source drivers 6 ′ and 6 ″. Further, the source driver used in this embodiment is the conventional one. As an example, a commercially available one as shown in Fig. 6 may be used, that is, in Fig. 4, n = n '+, where n is the total number of bits of the digital video signal.
n ″ and the upper n′-bit digital video signal (D ₁₁
~ D _{1n '} ) is input to the source driver 6', and the lower-order n "-bit digital video signal (D _{21 to} D _2n" ) is input to the source driver 6 ". In this case, the digital video signal (D
_{11 to} D _{1n '} and D _{21 to} D _{2n "} ) are shift clocks C commonly connected to the shift register circuits 1'and 1".
They are sequentially stored in the data register circuits 2'and 2 "at the timing of P. Next, the source driver 6 '.
R '= 2 ^n'reference voltage groups (V ₁₁ inputted from an external source to the D / A conversion circuit 5'in response to the upper n'bit digital video signal inputted to the data register circuit 2'of
~ _{V1r '} ), one reference voltage is selected and output as a gradation signal. Similarly, in the source driver 6 ″, r ″ = according to the input lower n ″ -bit digital video signal.
One reference voltage is selected and output from the 2 ^{n "} group of reference voltages (V _{21 to} V _2r" ). The source driver 6 ',
The output from 6 "is performed at the timing of the OE signal commonly connected to the latch circuits 3'and 3". Further, if the output numbers of the source drivers 6 ′ and 6 ″ are equal and the outputs of the source driver 6 ′ are O _{11 to} O _1k and the outputs of the source driver 6 ″ are O _{21 to} O _2k , the output O _1j and the output O _{1j. 2j}
(Where 1 ≦ j ≦ k) is connected to common data lines (O _{1 to} O _k ) outside the source drivers 6 ′ and 6 ″.

According to the above configuration, the reference voltage corresponding to the upper _{n'bits of the} n (= n '+ n ")-bit digital video signal from the reference voltage group (V _{11 to} V _1r' ) of the source driver _6'is provided. A reference voltage corresponding to the lower n "bits of the reference voltage group (V _{21 to} V _2r" ) of the source driver 6 "is selectively output, and a gray scale having an average value of the pair of reference voltages as a voltage value. The signal is output to each data line 25.
The total number of reference voltages of each reference voltage group is set to be smaller than the number of gradations. As a result, in this embodiment, the same operational effects as those of the above-described embodiment can be obtained. Also,
In the present embodiment, the number of bits of the digital video signal input to each of the source drivers 6'and 6 "is smaller than the number of bits of the digital video signal input to the source driver 6 of the above-described embodiments, so that each source driver As 6'and 6 '', inexpensive ones can be used. On the other hand, in the above-mentioned embodiment, since a single source driver 6 may be connected to each data line 25, the source driver 6 is more suitable than the present embodiment in which two source drivers 6 ′ and 6 ″ are connected to each data line 55. Easy to implement.

The present invention is not limited to the above embodiments. For example, in the above embodiment, the digital video signal is divided so that each divided signal has the same number of bit data, but it may be divided so as to have a different number of bit data. Further, the specific number of bits of the digital video signal and the voltage value of the reference signal are not limited to those in the above embodiments, and the number of reference voltages may be set to be smaller than the number of gradations.

[0018]

According to the present invention, a digital video signal is divided into m (m ≧ 2) digital video signal groups in order from the upper bits, and m reference voltage groups corresponding to the respective digital video signal groups are divided. From each, a reference voltage corresponding to each digital video signal group is selected, and a gradation signal having a voltage value obtained by averaging the selected m reference voltage values is output to the data line, which complicates the peripheral circuit. It is possible to reduce the number of reference voltages to less than the number of gray scales to be displayed without increasing the number of gray scales to be displayed, and it is possible to increase the number of gray scales even when the mounting space of the data line driver IC is limited.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit block of a source driver of a TFT type active matrix type liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a D / A conversion circuit of a source driver of a TFT active matrix type liquid crystal display device according to a first embodiment of the present invention.

FIG. 3 is a diagram showing specific numerical values of a digital video signal, a reference voltage, and a gradation signal of the TFT active matrix type liquid crystal display device of the embodiment of the invention.

FIG. 4 is a diagram showing a configuration of a source driver of a TFT type active matrix type liquid crystal display device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a TFT active matrix liquid crystal display device according to an embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a source driver of a conventional TFT active matrix liquid crystal display device.

7A and 7B are views for explaining an operation and FIG. 2 for explaining a conventional TFT active matrix liquid crystal display device.

[Explanation of symbols]

 51 display panel 55 data line

Claims (1)

[Claims] 1. In a display device for outputting a gradation signal having a voltage value corresponding to a digital video signal to each data line of a matrix type display panel, the digital video signal is m (m ≧ 2) in order from an upper bit. The reference voltage corresponding to each digital video signal group is selected from each of the m reference voltage groups corresponding to each digital video signal group, and the selected m reference voltage values are calculated. A display device characterized in that a gradation signal having an averaged voltage value is output to a data line.