KR100209644B1 - Driving circuit for liquid crystal device - Google Patents

Abstract

The present invention relates to a liquid crystal display device driving circuit capable of switching between line, column, and dot inversion in one data driver. Specifically, the present invention relates to any one of a horizontal synchronous signal and a vertical synchronous signal. A multi-gradation voltage generating means for generating a voltage group of the first group and a voltage group of the second group whose polarities are mutually changed in accordance with the synchronized control signal, and an odd-numbered source to selectively apply the gray-level voltage to the source line according to the digital data A first decoder connected to a line and a second decoder connected to an even source line, and between at least one of the first or second decoders and voltage sources of the first group and the second group; And a gray voltage output unit configured to select one of the voltage sources of the second group of voltage sources and input the same to the decoder.

Description

LCD driving circuit

1 is a detailed block diagram of a multilevel voltage generation circuit in a conventional LCD driving circuit.

2 is a block diagram of a conventional LCD driving circuit using the multilevel voltage generation circuit of FIG.

3 is a detailed block diagram of a multi-gradation voltage generation circuit in the LCD driving circuit according to the present invention.

4 is a detailed circuit diagram of the switching controller of FIG.

5 is an operation timing diagram of each part of FIG. 4;

6 is an LCD driving circuit diagram according to the present invention using the multi-gradation voltage generation circuit of FIG.

7 is a detailed block diagram of FIG.

8 is a detailed block diagram of the decoder of FIGS. 6 and 7;

* Explanation of symbols for main parts of the drawings

31: switch control unit 32: inverter

33: first selection unit 35: second selection unit

37: first multi-gradation voltage generator 39: second multi-gradation voltage generator

40: reference voltage generator 31-1, 31-2: end gate

31-3: Oa gate 51: shift register

53: memory 55: gradation voltage output unit

57: decoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to driving a liquid crystal display (LCD), and in particular, a liquid crystal display device that facilitates switching of a line, a column, and a dot inversion in one data driver. It relates to a driving circuit.

In order to prevent deterioration of liquid crystals, LCDs are driven by alternating current, so when one pixel is used as a reference, the positive and negative signals are alternately displayed depending on the field. This is called data inversion. Line inversion, column inversion, and dot inversion.

At this time, the line inversion is alternately applied to the data signal according to the gate line to drive the polarity of the voltage applied to the pixels of the odd-numbered gate lines and the pixels of the even-numbered gate lines alternately. In this way, flickers generated in two adjacent pixels in the vertical direction cancel each other and are reduced.

In addition, the column inversion is alternately applied to the data signal to the pixels of the odd-numbered data line and the pixels of the even-numbered data line according to the data line, so that the polarities of the voltages are reversed. In this way, the plugs generated in the two adjacent pixels in the horizontal direction cancel each other and are reduced.

In addition, the dot inversion is a driving method combining the line inversion and the column inversion, and the polarities of adjacent pixels in the horizontal and vertical directions are reversed, and the plugs generated in the pixels adjacent in the horizontal and vertical directions cancel each other and are reduced.

1 is a conventional LCD driving circuit diagram, which is disclosed in Japanese Patent Laid-Open No. 4-20991.

Referring to FIG. 1, the positive and negative voltages V + and V- are input to the selectors 611 and 612, respectively, and are selected by the frame switching signal 6 in synchronization with the vertical synchronization signal Vsync (one frame period). The outputs of the sections 611 and 612 are simultaneously changed to (+) and (-). Accordingly, the polarities of the signals input to the m-level voltage generation circuits 621 and 622 alternate with (+) and (-) in synchronization with the vertical synchronization signal Vsync.

The m-level voltage generation circuits 621 and 622 output m inputs to the analog switches 91 and 92 of FIG.

At this time, the decoders 81 and 82 select corresponding gray voltages from the m gray voltage input terminals 3 and output them to the source driving circuits 111 and 112 by the digital image data 71 and 72, respectively.

Since the source driver circuits 111 and 112 are connected to odd and even lines of the source line of the panel, respectively, column inversion driving is performed in which polarities of the left and right source lines are changed.

In addition, since the input voltage polarity input to the source driving circuits 111 and 112 is changed every one vertical synchronization signal period, the polarity of the same source line is also changed in units of frames.

However, the conventional LCD driving circuit described above requires only a column inversion driving, so a new circuit is required for line inversion or dot inversion, and since a source driving circuit is formed above and below the channel, a double bank is required. As the cost increases, there is a problem that the size of the entire set increases. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to easily switch between lines, columns, and dot inversions through one data driver during digital driving, and to easily invert the polarity of the data voltage. In providing the furnace.

Features of the LCD driving circuit according to the present invention for achieving the above object, the first group of voltage source and the second group of the polarity is mutually changed in accordance with the control signal synchronized to any one of the horizontal synchronization signal and the vertical synchronization signal A multi-gradation voltage generating means for generating a voltage source, a first decoder connected to an odd-numbered source line and a second decoder connected to an even-numbered source line so as to selectively apply a gray-scale voltage to a source line according to digital data; A gray level voltage is selected between a voltage source of the first group and a voltage source of the second group and input to the decoder between at least one of the first and second decoders and the voltage sources of the first and second groups. It has an output unit.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a multi-gradation voltage generation in the LCD driving circuit according to the present invention.

Referring to FIG. 3, a signal HS inverted in a 1H (1H: horizontal scan period) period, a signal inverted in a 1V (1V: vertical scan period) period, a VS, an HS select signal (HSS), and a VS select signal ( The switching control unit 31 for ORing the VSS and outputting the control signal SCS, the inverter 32 for inverting the control signal SCS of the switching control unit 31, and the control signal of the switching control unit 31. A first selector 33 for selectively outputting a V + or V- voltage, a second selector 35 for selectively outputting a V + or V- voltage according to a control signal of the inverter 32, and a reference voltage Vr. The gray level of m (m is an integer of 2 or more) by comparing the output of the generated reference voltage generator 40 and the first selector 33 with the reference voltage Vr generated by the reference voltage generator 40. M-level gradation by comparing the output of the first multi-gradation voltage generator 37 and the first selector 33 to generate a voltage with the reference voltage Vr generated by the reference voltage generator 40 The second multi-gradation voltage generator 39 generates a voltage. At this time, the outputs of the first selector 33 and the second selector 35 switch V + and V−, and the polarities of the first and second multi-gradation voltage generators 37 and 39 are HSS and VSS. The period of inversion is determined by.

The first multi-gradation voltage generator 37 compares the output of the first selector 33 with the respective reference voltages, and outputs m multi-gradation voltages V0 to Vm-1. M, which is composed of a comparator, and the second multi-gradation voltage generator 39 also outputs the multi-gradation voltages V0 to Vm-1 having m levels by comparing the output of the second selector 35 with the respective reference voltages. It consists of two comparators.

In this case, the reference voltage input to each comparator is a voltage obtained by dividing the reference voltage Vr generated by the reference voltage generator 40 through a resistor connected to each comparator.

The polarities of the first multi-gradation voltage generator 37 and the second multi-gradation voltage generator 39 are always opposite to each other, and are changed by the first and second selection units 33 and 35.

4 is a detailed circuit diagram of the switching controller 31, which includes an AND gate 31-1 for logically combining an HS signal and an HSS signal, an AND gate 31-2 for logically combining a VS signal and a VSS signal, and The OR gates 31-3 are configured to logically combine the outputs of the AND gates 31-1 and 31-2 to output the control signal SCS.

FIG. 6 is a data driver of the LCD driving circuit according to the present invention configured by using the positive m-level gradation voltages and the negative m-level gradation voltages generated in FIG. 3 as input voltage groups GL _A and GL _B. As a block diagram, the m-level gradation voltage of the first multi-gradation voltage generator 37 in FIG. 3 is input to GL _A , and the m-level gradation voltage of the second multi-gradation voltage generator 39 is input to GL _B.

At this time, if the input digital data is n bits, 2 ^N = m is satisfied.

Since the outputs of the first and second multi-gradation voltage generators 37 and 39 are m-level multi-gradation voltages, the number of input lines to which the input voltage groups GL _A and GL _B are input is 2 m.

That is, FIG. 6 shows a shift register 51 for sampling input digital image data, a memory 53 for storing the sampled data and outputting the output data by an output enable signal OE, and the gradation voltage input line GL _A. The odd-numbered input line of GL _A among GL _B is directly, the even-numbered input line of GL _A and GL _B is a gray voltage output unit 55 for outputting a gray voltage through switching, and 1 output from the memory 53. The decoder 57 inverts the sampling data for the line in accordance with the gray voltage output from the gray voltage output unit 55.

Here, when the gray voltage is input to the decoder 57 from the gray voltage input lines GL _A and GL _B , the odd-numbered input lines IL (2i + 1) (i = 0, 1, 2, ...) are decoded from the GL _A decoder ( 57, but the even-numbered input line IL (2i) (i = 0, 1, 2, ...) is connected between the gray scale voltage input lines GL _A , GL _B and the decoder via an analog switch.

At the same time, analog switches located on even-numbered input lines IL 2i are controlled by signals CS0 and CD1 that select inputs from GL _A and inputs from GL _B , respectively.

FIG. 7 is a detailed block diagram of FIG. 6, wherein the first decoder 71 decodes the gray voltage output through the odd-numbered input line IL (2i + 1) of GL _A among the gray voltage input lines GL _A and GL _B. ), _A plurality of (e.g., 2m) analog switches 72 which are switched by CS0, CS1 signals to selectively output the grayscale voltages outputted through the even-numbered input lines IL2i of GL _A and GL _B , and the And a second decoding 73 for decoding the gray voltage output through the plurality of analog switches 72.

FIG. 8 is a schematic block diagram of the decoding unit of FIGS. 6 and 7 to shift a level of a digital value output from the multiplexer 81 and a multiplexer 81 for selectively outputting n-bit input digital data. M analog switches A0 to Am-1 which switch according to the level shift 83 and the gray voltages V0 to Vm-1 input to the decoder to selectively output data output from the level shift 83. It is composed.

Here, m output terminals of the level shift 83 are connected to input terminals of the m analog switches to which m gray voltages are respectively input as control signals.

The present invention configured as described above will be described first from the multi-gradation voltage generation process.

That is, as shown in FIG. 5A, a signal HS inverting at a period of 1H (1H: horizontal scanning period) and a signal HSS for selecting HS are input to the AND gate 31-1 of the switching controller 31. And a logic combination is inputted to the AND gate 31-2 by inputting a signal VS for inverting in a period of 1V (1V: vertical scanning period) and a signal VSS for selecting VS as shown in FIG. 5 (b). do.

Here, the two selection signals HSS and VSS are signals designed by the system designer, and the two selection signals cannot be high or low at the same time and have different levels.

The outputs of the AND gates 31-1 and 31-2 generate a control signal SCS by a logic combination at the OR gate 31-3, and are output to the first selector 33. 32 is output to the second selector 35.

In this case, V + and V− voltages are input to the first and second selectors 33 and 35, and the first selector 33 supplies V + voltage when the control signal SCS is high and V when low. The voltage is selected and output to the first multi-gradation voltage generator 37, and the second selector 35 supplies V + voltage when the control signal inverted by the inverter 32 is high and V− when low. The voltage is selected and output to the second multi-gradation voltage generator 39. Therefore, when the first selector 33 outputs the V + voltage, the second selector 35 outputs the V− voltage, and when the first selector 33 outputs the V− voltage, the second selector ( 35) outputs a V + voltage. That is, the outputs of the first and second selectors 33 and 35 are always opposite in polarity.

In this way, the control signal SCS changes in accordance with the timing of the VS selected by the HS or VSS signal selected by the HSS signal, whereby the outputs of the first and second selectors 33 and 35 are V + and V−. Switch to.

In addition, the first multi-gradation voltage generator 37 compares the voltage output from the first selector 33 with the reference voltage provided from the reference voltage generator 40 so that m of (+) or (-) is increased. A level gray scale voltage is output, and the second multi-gradation voltage generator 39 compares the voltage output from the second selector 35 with the reference voltage provided from the reference voltage generator 40 to form a positive or negative value. The negative m-level gradation voltage is output.

At this time, the polarity of the m-level gradation voltages output from the first and second multi-gradation voltage generators 37 and 39 depends on the output voltage polarities of the first and second selector units 33 and 35.

That is, the period in which the polarities of the first and second multi-gradation voltage generators 37 and 39 are reversed is determined by the selection signal HSS or VSS input to the switching controller 31.

In other words, the polarities of the m-level multi-gradation voltages output from the first and second multi-gradation voltage generators 37 and 39 are inverted every 1H period or 1V period by the HSS signal and the VSS signal.

Therefore, the selection signals HSS and VSS cannot be high or low at the same time and have different levels.

In this case, the V + and V− voltages input to the first and second selectors 33 and 35 correspond to the highest gray level voltages, for example, the darkest voltages in the case of normally white.

On the other hand, the positive m-level gradation voltages and the negative m-level gradation voltages output from the first and second multi-gradation voltage generators 37 and 39 are input voltage groups GL _A and GL _B , If the output of the first multi-gradation voltage generator 37 is input to GL _A and the output of the second multi-gradation voltage generator 39 is input to GL _B , the number of gray voltage input lines is required to be 2 m in total. .

And if the input digital data is n bits, 2 ⁿ = m is satisfied.

First, when digital image data is input to the shift register 51, the shift register 51 samples the digital image data in synchronization with the clock clk and stores it in the memory 53.

The data stored in the memory 53 is sampled for one line by the output enable signal OE, and then, the data of the next line is transferred to the decoder 57 while the data of the next line is sampled in the shift register 51. Is output.

The gray voltage is input to the decoder 57 from the gray voltage input lines GL _A and GL _B.

At this time, the odd-numbered input line IL (2i + 1) (i = 0,1,2, ...) of the source line of the panel is directly connected from the GL _A to the decoder 57, but the even-numbered input line IL (2i) (i = 0, 1, 2, ... are connected between the gray voltage input lines GL _A , GL _B and the decoder 57 via an analog switch of the gray voltage output section 55.

At the same time, the analog switches of the gradation voltage output section 55 located on the even-numbered input line IL 2i are controlled by signals CS0 and CS1 that select inputs from GL _A and inputs from GL _B , respectively.

That is, when the control signals CS0 = 1 and CS1 = 0 of the gray voltage output unit 55, the odd-numbered input lines IL (2i + 1) output the gray voltage provided from the gray voltage input line GL _A to the decoder 57. The even-numbered input lines IL2i output the grayscale voltage provided from GL _B to the decoder 57.

If CS0 = 0 and CS1 = 1, the odd-numbered and even-numbered input lines IL (2i + 1) and IL (2i) output the grayscale voltage provided from GL _A to the decoder 57.

Here, each of the displayed ILs is m lines each, and each IL is processed at each decoder 71, 73, ... as shown in FIG.

That is, since a decoder is required for every line input to the decoder 57, the decoder 57 requires as many decoders as the input lines IL (2i + 1) and IL (2i).

As shown in FIG. 8, when the n-bit digital image data is multiplexed to the m level through the multiplexer 81 and input to the level shift 83, the level shift 83 is a digital value and the analog switches A0 to A. Adjust the difference between on and off values of Am-1).

At this time, if the selection signals HSS and VSS inputted to the switching controller 31 and the selection signals CS0 and CS1 of the gray voltage output unit 55 are properly adjusted, they can be switched to different inversion driving methods as shown in Table 1 below. Can be.

i) column inversion

When VSS = 1, HSS = 0, CS0 = 0, CS1 = 1, the polarity of the gradation voltage input to GL and GL is inverted every 1V, and the voltage input line IL (2i + 1) from GL and GL is GL In turn, IL 2i is connected to GL so that voltages of different polarities are transmitted. Therefore, since the polarity between the source lines (or data lines) adjacent to each other during 1V is reversed, column inversion is achieved.

ii) line inversion

When VSS = 0, HSS = 1, CS0 = 1, CS1 = 0, the polarities of the gray voltages inputted to GL and GL are inverted every 1H, and all voltage input lines IL (2i + 1) and IL (2i) are inverted. Since this GL is connected, the polarity of the data of one line is the same. Therefore, the polarity of the data between the line and the line is reversed by polarity inversion every 1H, but the line inversion is achieved because the polarity of the data of one line is the same.

iii) Dot Inversion

When VSS = 0, HSS = 1, CS0 = 0, CS1 = 1, the polarity of the gradation voltage input to GL and GL is inverted every 1H and the voltage input line IL (2i + 1) from GL and GL is connected to GL. , IL 2i is connected to GL so that voltages of different polarities are transmitted. Therefore, the polarity of the data adjacent to each other on the one line is reversed, and the polarity is reversed every 1H, so dot inversion is achieved.

According to the LCD driving circuit according to the present invention as described above, the voltage source of any one group of the first group voltage source and the second group voltage source for outputting the m-level multi-gradation voltage with different polarity is odd of the source line of the panel By connecting directly to the line (even line) decoder and selectively outputting one of the first and second groups of voltage sources to the even line (odd line) decoder, all column, line, and dot inversion operations are performed through one data driver. It becomes possible.

In addition, the selection signal HSS for inverting the signal in 1H period and the selection signal VSS for inverting the signal in 1V period and the signals CS0 and CS1 for selecting the input voltage lines GL and GL are changed to change the column, line, and dot. The switching between inversions is easy, and the polarity inversion of the data voltage is easier.

Claims (7)

Multi-gradation voltage generating means for generating a voltage group of the first group and a voltage group of the second group whose polarities change mutually according to a control signal synchronized with either the horizontal synchronization signal or the vertical synchronization signal, and the gray level at the source line according to the digital data. A first decoder connected to the odd-numbered source lines and a second decoder connected to the even-numbered source lines so as to selectively apply a voltage, and at least one of the first or second decoders and voltage sources of the first group and the second group And a gradation voltage output section for selecting a voltage source of one group from among the voltage source of the first group and the voltage source of the second group and inputting it to the decoder. 2. The multi-gradation voltage generating means according to claim 1, wherein the multi-gradation voltage generating means includes: a signal HS inverted at a period of 1H (1H: horizontal scanning period), a signal VS inverted at a period of 1V (1V: vertical scanning period), and an HS selection signal ( A switching controller for logically combining the HSS and the VS selection signal VSS to output a control signal, a selection unit for selectively outputting a V + or V− voltage using a control signal inverted from the control signal of the switching controller; The output of the selector is compared with a preset reference voltage to generate a m level gray voltage of (+) and a m level gray voltage of (−) and a m level gray voltage of (+) and (− And a multi-gradation voltage generator for setting the m-level gradation voltages of < RTI ID = 0.0 >) < / RTI > as the voltage source of the first group and the voltage source of the second group. 2. The liquid crystal display element driving circuit according to claim 1, wherein the voltage source of the first group and the voltage group of the second group of the multi-gradation voltage generating means supply voltages having different polarities with respect to a preset reference voltage. The liquid crystal display device driving circuit according to claim 1, wherein the control signal is synchronized with a horizontal synchronous signal, and the first decoder and the second decoder receive a selection of the same group of voltage sources. 2. The liquid crystal display device driving circuit according to claim 1, wherein the control signal is synchronized with a vertical synchronization signal, and the first decoder and the second decoder receive a selection of different voltage sources. The liquid crystal display device driving circuit according to claim 1, wherein the control signal is synchronized with a horizontal synchronous signal, and the first decoder and the second decoder receive a selection of different voltage sources. 3. The liquid crystal display device driving circuit according to claim 2, wherein the + voltage and the-voltage selected and output by the selector are the highest gray voltages.