KR100322822B1 - Liquid crystal panel and liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device having a liquid crystal panel of an active matrix driving method, and more particularly, to a structure and a driving method thereof, wherein distortion occurs in a voltage of a common electrode and the applied voltage of the liquid crystal corresponds to display data. In order to solve the problem of deterioration in image quality due to being different from the original applied voltage, M rows and N columns formed on the substrate as liquid crystal panels having two oppositely arranged substrates and liquid crystals filled between the two substrates. M x N pixel portions, a plurality of drain lines, a plurality of gate lines, and two counter electrode lines corresponding to the pixels, each pixel portion being connected to a gate electrode connected to any one gate line, or any one drain line. A thin film transistor having a drain electrode and a source electrode, paired with a pixel electrode and a pixel electrode connected to the source electrode of the thin film transistor For example, a counter electrode for applying an electric field to the liquid crystal and changing the transmittance of the liquid crystal with respect to the corresponding pixel is provided, and the counter electrode is divided into two groups and connected to two counter electrode lines for each group.

By doing so, the frequency of the voltage applied to the common electrode can be reduced without increasing flicker, making it possible to reduce the power consumption of the liquid crystal display device, and to eliminate the concentration of current in the common electrode and to deteriorate the display quality. The effect that can be reduced is obtained.

Description

LCD panel and LCD

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having a liquid crystal panel of an active matrix driving method, and more particularly, to a configuration and a driving method thereof.

In the liquid crystal panel of the liquid crystal display device, there is an active matrix driving liquid crystal panel (TFT liquid crystal panel) in which a pixel portion formed by TFT (Thin Film Transister), a pixel electrode or the like is arranged on a transparent substrate in which liquid crystal is enclosed. Japanese Laid-Open Patent Publication No. 63-237095 discloses a liquid crystal display device which performs color display by applying a gray scale voltage corresponding to display data to a TFT liquid crystal panel.

A conventional liquid crystal display device using a TFT liquid crystal panel will be described below. 15 shows an equivalent circuit diagram of the TFT liquid crystal panel. In Fig. 15, the TFT liquid crystal panel 201 includes a plurality of gate lines 202 arranged in the horizontal direction, several drain lines 203 arranged in the vertical direction, and one drain each arranged in a matrix and corresponding to the arrangement position. A common electrode (Com) 209 and a common electrode (Strg) 210 are provided in common in the pixel portion 204 connected to the line 203, the gate line 202, and all the pixel portions 204.

Each pixel portion 204 is constituted by a thin film transistor (TFT) 205, a pixel electrode 206, a liquid crystal 208, and an additional capacitor 207. Here, the liquid crystal 208 is disposed between the pixel electrode 206 and the common electrode (Com) 209, and the additional capacitor 207 is disposed between the pixel electrode 206 and the common electrode (Strg) 210. It is. Each pixel portion 204 in the same row is driven by the voltage of the same one gate line 202, and each pixel portion 204 in the same column is driven by the voltage of the same one drain line 203. It is.

16 shows an overall configuration diagram of the liquid crystal display device. In Fig. 16, the liquid crystal display device includes the above-described liquid crystal panel 201 in which the pixel portions are arranged in m rows and n columns, a liquid crystal controller 302 for outputting display data and various synchronization signals, and data voltages corresponding to the display data. The drain driver 306 applied to the 203, the gate driver 307 for applying the scan voltage to the gate line 202, and the AC voltage generation circuit 309 for alternating the voltage applied to each pixel portion 204. , (310), (313) and the division resistor (311).

The liquid crystal controller 302 sequentially latches display data in accordance with the data synchronization signal 402 by the circuit shown in FIG. 17 and transmits the display data to the drain driver 306. In addition, the circuit shown in Fig. 18 generates an AC signal 304 for specifying the polarity of the reference voltage in the vertical synchronizing signal 501 and the horizontal synchronizing signal 502, so as to generate the AC voltage generating circuits 309 and 310. ), (313). The alternating signal 304 is changed to invert the polarity of the voltage applied to each pixel portion 204 at each period of the horizontal synchronization signal.

In the gate driver 307, the synchronizing signal 601 for validating the selection of the first line in the configuration shown in Fig. 19 is shifted according to the synchronizing signal 602 of the same frequency as the horizontal synchronizing signal. Shifting inside, the level shifter 605 and the voltage selection circuit 607 move the liquid crystal drive gate suppressors G (1), G (2), G (3),... According to the logic level of the output 604. Is generated and applied to the gate line 202. As a result, the gate line 202 has G (1), G (2), G (3),... The selection voltage for turning on the TFT 205 is applied in the following order.

In the drain driver 306, in the configuration shown in Fig. 20, the latch circuit 707 fetches display data sequentially and stores one line for each line according to the sampling clock 706 generated by the shift register 705. The stored display data for one line is fetched in unison to the latch circuit 709 by the synchronization signal 704 of the same frequency as the horizontal synchronization signal, and the drain voltage according to the AC voltage 312 by the gray voltage generator 711. It is converted to Vd and applied to the drain line 203.

In addition, when the polarity of the voltage applied to the liquid crystal 208 of each pixel portion 204 of the liquid crystal panel 201 is the same in one frame period, flicker (also referred to as flicker) occurs in the pixel. In order to reduce the flicker, the liquid crystal display device inverts the polarity of the voltage applied to each pixel portion 204 by the AC voltage generating circuits 309, 310, 313, and the like every one line period.

Next, the operation of the above-described liquid crystal display device will be described with reference to FIG. In parallel with the gate driver 307 setting the voltage VG 2 of the gate line 202 of the second horizontal line (the second row) as the selection voltage Vgon, the drain driver 306 displays the display data and the alteration signal of the second row. The gradation voltage Vd according to this is applied to each drain line 203. As a result, in each pixel portion 204 of the second row, the TFT 205 is turned on, and the gray scale voltage Vd is applied to the pixel electrode 206, and the common electrodes Com and Strg 209 and 210 are also applied. The reference voltage according to the AC signal is applied. The potential difference between these gradation voltages and the reference voltage controls the transmittance of the liquid crystal 208 and is applied to the liquid crystal 208 and the additional capacitance 207 even after the TFT 205 is turned off because the voltage VG 2 becomes the unselected voltage Vgoff. Is maintained by.

When the gate driver 307 sets the voltage VG 2 to the non-selection voltage Vgoff and the voltage VG 3 of the third gate line 202 is the selection voltage Vgon, the drain driver 306 displays the third row of display data. And a gray voltage Vd according to the polarity signal. As a result, the same driving as described above is performed for each pixel portion 204 in the third row.

In the above operation, when the level of the reference voltage applied to the common electrodes (Com, Strg) 209 and 210 is the positive polarity level VcomP, the pixel electrode 206 of the pixel portion 204 of the drive target row is negative. Since the gray scale voltage Vd of polarity is applied, the potential difference in the liquid crystal 208 and the additional capacitance 207 becomes negative when the reference voltage is referenced. On the contrary, when the common electrodes Com and Strg 209 and 210 are at VcomN of the negative polarity level, the potential difference between the liquid crystal 208 and the additional capacitance 207 becomes positive.

As described above, in the conventional liquid crystal display device, the additional capacitances 207 of all the pixel portions 204 are commonly connected to the common electrode Strg 210, and each pixel portion has a larger capacitance than the liquid crystal 208. The additional capacitance 207 of 204 maintains the potential difference of the same polarity in each row. For this reason, when a voltage having a different polarity is applied to the additional capacitor 207 when the pixel unit 204 is driven, a current is concentrated between the additional capacitor 207 of the pixel unit 204 and the common electrode Strg 210 which are simultaneously driven. Flows and distortion occurs in the voltage of the common electrode due to the resistance of the wiring and the additional capacitance of the common electrode. Due to this distortion, in the conventional liquid crystal display device, the applied voltage of the liquid crystal 208 is different from the original applied voltage corresponding to the display data, causing a problem of deterioration in image quality.

In the conventional liquid crystal display device, in order to prevent the generation of flicker, the reference voltage applied to the common electrode is alternated, and its polarity is inverted for each drive of one row. For this reason, it is necessary to change the voltage applied to the common electrode at a high frequency of about 30 Hz to 60 Hz, which also increases the power consumption.

An object of the present invention is to reduce the frequency of the voltage applied to the common electrode without increasing flicker. In addition, deterioration of image quality caused by concentration of current in the common electrode is reduced.

1 is an equivalent circuit diagram of a liquid crystal panel of a first embodiment of the present invention;

2 is a configuration diagram of the liquid crystal display device of the first embodiment;

3 is a block diagram of a data processing unit of a liquid crystal controller;

4 is a block diagram of an AC signal generation unit of a liquid crystal controller;

5 is a timing diagram showing a process of a data processing unit;

6 is a block diagram of a gate driver;

7 is a block diagram of a drain driver,

8 is a waveform diagram showing the operation of the liquid crystal display device of the first embodiment;

9 is an equivalent circuit diagram of a liquid crystal panel of a second embodiment of the present invention;

10 is a configuration diagram of a liquid crystal display device of a second embodiment;

11 is a waveform diagram showing the operation of the liquid crystal display device of the second embodiment;

12 is an equivalent circuit diagram of a liquid crystal panel of a third embodiment of the present invention;

13 is a configuration diagram of a liquid crystal display device of a third embodiment;

14 is a waveform diagram showing the operation of the liquid crystal display device of the third embodiment;

15 is an equivalent circuit diagram of a conventional liquid crystal panel;

16 is a configuration diagram of a conventional liquid crystal display device;

17 is a block diagram of a data processing unit of a conventional liquid crystal controller;

18 is a block diagram of an AC signal generation unit of a conventional liquid crystal controller;

19 is a block diagram of a conventional gate driver;

20 is a block diagram of a conventional drain driver,

21 is a waveform diagram showing an operation of a conventional liquid crystal display device.

In order to achieve the above object, the present invention provides a liquid crystal panel having two substrates disposed opposite to each other and a liquid crystal filled between the two substrates, the M × N pixels corresponding to the pixels of M rows and N columns formed on the substrate. And a drain electrode, a plurality of drain lines, a plurality of gate lines, and two counter electrode lines, wherein each pixel portion includes a gate electrode connected to any one of the gate lines, a drain electrode connected to any one of the drain lines, and a source electrode. A thin film transistor having a thin film transistor, a pixel electrode connected to a source electrode of the thin film transistor, and a counter electrode paired with the pixel electrode to apply an electric field to the liquid crystal and to change the transmittance of the liquid crystal with respect to a corresponding pixel. An electrode is divided into two groups, and each group is connected to the two opposite electrode lines, respectively, to provide a liquid crystal panel.

In such a liquid crystal panel, reference voltages having different polarities may be applied to two groups of counter electrodes through two counter electrode lines. When a reference voltage having a different polarity is applied, the liquid crystal for each pixel of the liquid crystal panel is divided into a positive reference voltage and a negative reference voltage. Therefore, even when the polarity of the reference voltage is not changed. The same effect as in the conventional example of changing the polarity of the voltage occurs. That is, according to the present invention, even when the polarity of the reference voltage is changed at a frequency lower than that of the prior art, flicker can be sufficiently suppressed.

In the liquid crystal panel according to the present invention, the counter electrode is paired with the pixel electrode to form a capacitor to hold the electric field, and the same counter electrode line among the thin film transistors connected to each of the one gate line is provided. The liquid crystal panel is characterized in that the number of the connected counter electrodes and the thin film transistors connected to the pair of pixel electrodes is approximately N / 2.

In such a liquid crystal panel, for example, when N thin film transistors are driven at the same time, the current flowing from the liquid crystal and the condenser is distributed approximately equally to the two opposing electrode lines, so that the current does not concentrate on one opposing electrode line. The deterioration of the image quality due to the current of is reduced compared with the prior art.

EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described using drawing.

1 is an equivalent circuit diagram of a liquid crystal panel according to a first embodiment of the present invention. Here, an example in which four pixel units are arranged in the horizontal and vertical directions will be described.

The liquid crystal panel 101 shown in FIG. 1 includes five gate lines 102 arranged in the horizontal direction, four drain lines 103 arranged in the vertical direction, four rows and four columns, and one drain line 103 in each. ) And a common electrode (Strg0) 109 and even rows (2, 4 rows) commonly provided in the pixel portion 104 connected to the gate line 102, and the pixel portion 104 in the odd rows (1, 3 rows). Has a common electrode Strg1 (110) provided in common in the pixel portion 104 of FIG. When the pixel portion 104 is arranged in m rows and n columns, (m + 1) gate lines 102 may be disposed, and n drain lines 103 may be disposed.

Each pixel portion 104 is composed of a thin film transistor (TFT) 105, a pixel electrode 106, a liquid crystal 107, 111, an additional capacitance 108, and an opposite electrode 112. In each of the three adjacent pixel units 104 in each row, R (red), G (green), and B (blue) color filters (not shown) are provided. The liquid crystal 111 is an auxiliary liquid crystal of the liquid crystal 107.

As shown in the drawing, the liquid crystals 107, 111 and the additional capacitor 108 are disposed between the pixel electrode 106 and the counter electrode 112.

The counter electrode 112 in the odd row is connected to the common electrode Strg0 109, and the counter electrode 112 in the even row is connected to the common electrode Strg1 110.

In the first row, the pixel portions 104 in the odd rows (first and third columns) are driven by the electrode G1 of the gate line 102. The pixel portion 104 in the even row (2, 4) in the first row and the odd row in the second row is driven by the electrode G2. The pixel portion 104 in the even column in the second row and the odd column in the third row is driven by the electrode G3. In the fourth row, which is the last row, the pixel section 104 in the even column is driven by the electrode G5.

Each pixel portion 104 in the same column is driven by the voltage of the same one drain line 103.

In the case where the pixel portion 104 is arranged in m rows and n columns, the pixel portion 104 in the even column in the (a-1) row and the pixel portion 104 in the odd column in the a row are driven by the voltage G (a). Where 1 <a <m. The pixel portion 104 in the b-th column is driven by the voltage D (b).

2 is a configuration diagram of a liquid crystal display device according to a first embodiment of the present invention.

The liquid crystal display of FIG. 2 includes the above-described liquid crystal panel 101 in which the pixel portion 104 is arranged in m rows and n columns, a liquid crystal controller 902 for generating and outputting display data and various synchronization signals, and data voltages corresponding to the display data. Is applied to the drain electrode 907 for applying the drain line 103 to the drain line 103, the gate driver 908 for applying the scan voltage to the gate line 102, and the counter electrode 112 of each pixel portion 104 via the common electrode. AC voltage generating circuits 910 and 911 for applying a voltage, and splitting resistors 912 and 913 for applying a gray scale voltage to the pixel electrodes of the pixel units 104.

3 is a configuration diagram of a circuit portion for generating display data in the liquid crystal controller 902, and FIG. 4 is a configuration diagram of a circuit portion for generating the AC signals 904 and 905 in the liquid crystal controller 902. .

As shown in Fig. 3, the circuit portion for generating display data has a data delay circuit 1003 and a selection circuit 1005. The data delay circuit 1003 is supplied with display data 1001 included in a bus signal 901 supplied from a system (not shown) and a synchronization signal 1002 indicating the transmission timing of the display data. The supplied display data 1001 is delayed by a predetermined period of the synchronization signal 1002 in the data delay circuit 1003 and output as the display data 1004. The selection circuit 1005 generates new display data 1006 from the display data 1001 and the delayed display data 1004 by the method shown in the timing diagram of FIG. 5 and outputs the new display data 1006 to the drain driver 907. For example, the first display data (R1-0, G1-0, B1-0), (R1-1, G1-1, B1-1),... , Second display data (R2-0, G2-0, B2-0), (R2-1, G2-1, B2-1),... The display data inputted in the order of (R2-0, G1-0, B2-0), (R1-1, G2-1, B1-1),... Rearrange in order. In parallel with this, a synchronization signal for enabling display of the display data 1006 is outputted to the drain driver 907 and the gate driver 908.

As shown in Fig. 4, the circuit section for generating the AC signal is composed of FF (flip-flop) circuits 1103, 1105, 1111, 1112, exclusive logical sum circuit 1107, and inverting circuit. 1109). The vertical synchronizing signal 1101 included in the bus signal 901 is divided into two by the FF circuit 1103, becomes a signal 1104, and is supplied to the FF circuit 1111. The FF circuit 1111 fetches the supplied signal 1104 by a signal 1110 obtained by inverting the horizontal synchronization signal 1102 of the bus signal 901, and converts the AC voltage generation circuit (905) into an AC signal 905. 910 and 911. The AC signal 905 becomes a signal whose polarity is inverted every one frame period. On the other hand, the horizontal synchronization signal 1102 included in the bus signal 901 is divided by two by the FF circuit 1105, and then an exclusive logical sum with the signal 1104 is calculated by the calculation circuit 1107. The operation result is fetched by the signal 1110 in the FF circuit 1112, and is output to the drain driver 907 as the alternating signal 904. This alteration signal 904 becomes a signal whose polarity is inverted every one line period.

6 is a block diagram of the gate driver 908.

In FIG. 6, the gate driver 908 includes a shift register 1303 of a +1 stage, a level shifter 1305, and a voltage selection circuit 1307. The synchronization signal 906 supplied from the liquid crystal controller 902 to the gate driver 908 includes a synchronization signal 1301 for validating the selection of the first line and a synchronization signal 1302 for instructing replacement of the selected line. . The shift register 1303, when the synchronization signal 1301 is input, makes the leading signal of the output signal 1304 high and sequentially shifts the output signal 1304 that is made high in accordance with the synchronization signal 1302. The level shifter 1305 and the voltage selection circuit 1307 apply a selection voltage for turning on the TFT 105 to the gate line 102 corresponding to the high output signal 1304, and apply the voltage to the other gate line 102. A non-selection voltage is applied to turn off the TFT 105. As a result, in the gate line 102, the voltages G (1), G (2),... , G (m + 1) becomes the selection voltage sequentially and repeats this.

7 is a block diagram of the drain driver 907.

In Fig. 7, the drain driver 907 includes a shift register 1405 for generating display data fetch timing, a line latch circuit 1407, 1409 for fetching and holding display data for one line, and display data. A positive gradation voltage generation circuit 1411 for generating a positive gradation voltage, a negative gradation voltage generation circuit 1413 for generating a negative gradation voltage according to display data, and one of the positive gradation voltage and the negative gradation voltage Has a voltage selection circuit 1415 for selecting and outputting.

In the shift register 1405, the display data 1401 included in the bus signal 901 is latched in accordance with the synchronization signals 1402 and 1403 included in the bus signal 903 supplied from the liquid crystal controller 902. A timing signal 1406 is generated to be fetched one horizontal line sequentially at 1407 and output to the latch circuit 1407. The display data for one horizontal line fetched and held by the latch circuit 1407 is fetched simultaneously by the synchronization signal 1404 of the bus signal 901 to the latch circuit 1409 and is positively passed through the data bus 1410. The gray level voltage generating circuit 1411 and the negative gray level voltage generating circuit 1413 are supplied. Each of the gradation voltage generating circuits 1411 and 1413 generates a positive drain voltage Vd + 1412 and a negative drain voltage Vd- 1414 according to the supplied display data for one horizontal line, respectively. (1415). The voltage selection circuit 1415 selects one of the supplied drain voltage Vd + 1412 and the drain voltage Vd−1414 according to the alternating signal 904 supplied from the liquid crystal controller 902 to the drain line 103. Is authorized. At this time, the polarity of the drain voltage Vd applied to the odd-numbered drain line 103 and the even-numbered drain line 103 is different. In addition, a positive drain voltage and a negative drain voltage are alternately applied to each drain line 103 every one line period.

Next, the operation of the liquid crystal display device of this embodiment will be described using FIG.

The liquid crystal controller 902 is provided with display data (R2-0, G1-0, B2-0), (R1-1, G2-1, B1-1)... Is output to the drain driver 907. When the voltage G (2) of the gate line 102 becomes the selection voltage Vgon by the gate driver 908, the TFT 105 of each pixel portion 104 in the even column of the first row and the odd column of the second row is turned on. It is in a state. In parallel with this, in the drain driver 907, display data of each pixel in the even row of the first row and the odd row of the second row (R2-0, G1-0, B2-0, R1-1, G2-1, The gray scale voltage corresponding to B2-1... And the alternating signal 904 is output to the drain line 103. This gray voltage is applied to the pixel electrode 106 of each pixel portion 104 in the on state. The AC reference voltage is applied to the counter electrode via the common electrodes Strg0 and Strg1 109 or 110. The transmittance of the liquid crystal 107 is controlled by the potential difference between the voltages applied to the liquid crystal 107 and the additional capacitance 108 to perform gray scale display. This potential difference is maintained by the liquid crystal 107 and the additional capacitance 108 even after the voltage G 2 of the gate line 102 becomes the non-selection voltage Vgoff.

After one line period, when the voltage G2 becomes the non-selection voltage Vgoff and the voltage G3 becomes the selection voltage Vgon, the TFTs of each pixel portion 104 in the even column of the second row and the odd column of the third row 105 is turned on and in parallel with this, the display data of each pixel in the even column of the second row and the odd column of the third row and the gradation voltage corresponding to the AC signal 904 are output. In this way, the same operation is repeated every one line period, and all the pixel portions 104 are driven in one frame period.

For example, in the period in which the voltage G 2 becomes the selection voltage Vgon, the reference voltage Vstrg0 of the common electrode Strg0 109 is negative in the pixel portion 104 of the first to the even columns as shown in FIG. The potential difference of positive polarity arises as it becomes polarity VstrgN. At this time, in the pixel portion 104 of the second row, the negative potential difference occurs because the reference voltage Vstrg1 of the common electrodes Strg1 and 110 becomes the positive voltage VstrgP. That is, the potential difference generated in each pixel portion 104 is inverted in polarity alternately for each row.

As described above, in the liquid crystal display of the present embodiment, the current generated by the change of the reference voltage in the n pixel units 104 that are simultaneously driven is divided into two parts of the common electrodes Strg0 and Strg1 109 and 110. Inflow. Since current does not flow intensively into one common electrode, deterioration in image quality due to variation in the applied voltage of the common electrode is reduced as compared with the conventional example.

In the liquid crystal display according to the present embodiment, even when the polarities of the voltages applied to the common electrodes Strg0 and Strg1 109 and 110 are fixed in one frame period, the liquid crystals of the pixels of the liquid crystal panel have a positive polarity. Since the voltage and the negative voltage are applied evenly, the effect of preventing flicker is obtained. For this reason, the frequency of the reference voltage applied to the common electrodes Strg0 and Strg1 109 and 110 can be reduced while maintaining the effect of preventing flicker, thereby reducing power consumption.

Next, a second embodiment of the present invention will be described with reference to Figs.

9 is an equivalent circuit diagram of a liquid crystal panel according to a second embodiment of the present invention.

The liquid crystal panel 1601 shown in FIG. 9 includes four gate lines 1602, four drain lines 1603, pixel portions 1604 arranged in four rows and four columns, a common electrode Strg0 1609, and a common electrode. (Strg1) 1610. Like the liquid crystal panel 101 of FIG. 1, each pixel portion 1604 is formed by a TFT 1605, liquid crystals 1607, 1611, an additional capacitor 1608, a pixel electrode 1606, and an opposite electrode 1612. It is composed.

In this liquid crystal panel 1601, each pixel portion 1604 is connected to a gate line 1602 corresponding to the arranged row and a drain line 1603 corresponding to the arranged column. That is, the pixel portion 1604 in the a to b columns is driven by the voltages G (a) and D (b).

In the odd-numbered pixel portion 1604, the odd-numbered counter electrodes 1612 are commonly connected to the common electrodes Strg1 and 1610, and the even-numbered counter electrodes 1612 are common electrodes Strg0 (1609). ) Are commonly connected. In the even-numbered pixel portion 1604, the odd-numbered counter electrodes 1612 are connected to the common electrodes Strg0 1609 and the even-numbered counter electrodes 1612 are connected to the common electrodes Strg1 and 1610, respectively. . That is, the wiring between the counter electrodes 1612 is arranged in the oblique direction in the region constituting the pixel portion 1604 to connect the pixel portions 1604 in the oblique direction.

10 is a configuration diagram of a liquid crystal display device according to the present embodiment.

In the liquid crystal display of FIG. 10, the liquid crystal panel 1601, the liquid crystal controller 1701, the drain driver 907, the gate driver 908, the AC voltage generation circuit 910, (the pixel portion of which is arranged in m rows n columns) 911 and splitting resistors 912 and 913. In the liquid crystal panel 1601, since the pixel portion 1604 is driven for each row, the liquid crystal controller 1701 transfers display data to the drain driver 907 by the conventional circuit of FIG. The conventional circuit of FIG. 19 can also be used for the gate driver 908. The alternating operation is the same as that of the liquid crystal display of FIG. 2, and the AC voltage generating circuits 910, 911, the division resistors 912, and 913 of FIG. 2 are used, and the drain driver 907 is shown in FIG. 7. Use the same circuit. In addition, the same circuit as that in Fig. 4 is used for generating the alternating signal in the liquid crystal controller 1701.

Next, the operation of the liquid crystal display device of this embodiment will be described using FIG.

In parallel with the gate driver 908 setting the voltage G2 of the gate line 1602 as the selection voltage Vgon, the drain driver 907 displays the second row of display data R2-0, G2-0, and B2-. 0, R2-1, G2-1, B2-1, ... and the drain voltages Vd + and Vd- selected in accordance with the AC signal 904 are output to the drain line 1603. As a result, the drain voltage Vd + or Vd- and the reference voltage are applied to each pixel portion 1604 of the second row. The transmittance of the liquid crystal 1607 is controlled by the potential difference between the voltage applied to the liquid crystal 1607 and the additional capacitance 1608, and gray scale display is executed. This potential difference is maintained by the liquid crystal 1607 and the additional capacitance 1608 even after the voltage G2 of the gate line 1602 becomes the non-selection voltage Vgoff.

After one line period, when the voltage G2 becomes the non-selection voltage Vgoff and the voltage G3 becomes the selection voltage Vgon, the TFT 1605 of each pixel portion 1604 of the third row is turned on. In parallel, the drain line 1603 outputs the display data of the third row and the gradation voltage corresponding to the AC signal 904. In this way, the same operation is repeated every one line period, and all the pixel portions 1604 are driven in one frame period.

For example, in the period in which the voltage G2 becomes the selection voltage Vgon, the reference voltage of the common electrode Strg0 1609 is shown in the pixel portion 1604 of the second row to the odd column as shown in FIG. The potential difference of positive polarity arises because Vstrg0 becomes negative VstrgN. At this time, in the pixel portion 1604 of the even row in the second row, the negative potential difference occurs because the reference voltage Vstrg1 of the common electrodes Strg1 and 1610 becomes the positive voltage VstrgP. That is, the polarity of the potential difference generated in the pixel portion 1604 of each row is inverted for each column. In addition, the current flowing into each of the common electrodes Strg0 and Strg1 1609 and 1610 flows in individual wirings for each pixel current in the region constituting the pixel portion 1604, and causes the pixel portion 1604 to flow through. The current is n / 2 pixels in the wiring area other than the configured area. In the wiring regions other than the region constituting the pixel portion 1604, the resistance can be reduced in the region constituting the pixel 1604, while the wiring can be thickened to achieve low resistance. For this reason, only one pixel of current flowing through each wiring in the region constituting the pixel portion 1604 greatly contributes to the low distortion of the liquid crystal applied voltage.

As described above, in the liquid crystal display of the present embodiment, the current generated by the change in voltage in the n pixel portions 1604 of each row simultaneously driven is one of the common electrodes Strg0, Strg1 1609, 1610. In this case, the deterioration of the image quality due to the variation of the voltage of the common electrode can be reduced as compared with the conventional example. Further, even when the polarities of the reference voltages applied to the common electrodes Strg0 and Strg1 1609 and 1610 are fixed in one frame period, the positive voltage and the negative voltage are applied to the liquid crystal for each pixel of the liquid crystal panel. Since evenly applied, even when the frequency of the reference voltage is reduced, the effect of preventing flicker is obtained and power consumption can be reduced as compared with the conventional example.

Next, a third embodiment of the present invention will be described with reference to Figs.

12 is an equivalent circuit diagram of a liquid crystal panel according to a third embodiment of the present invention. In the liquid crystal panel 1901 of FIG. 12, only the connection state of each pixel portion and the common electrode is different from that of the liquid crystal panel 1601 of FIG. 9. That is, in the liquid crystal panel 1901 of the present embodiment, the wirings between the counter electrodes 1912 are arranged in the vertical direction in the area constituting the pixel portion 1904 and connect every other pixel portion 1904 in the vertical direction. do. As a result, the pixel portion 1904 of the odd-numbered row and the pixel portion 1904 of the even-numbered row are connected to the common electrode Strg0 (1909), and all other pixel portions 1904 are connected to the common electrode ( Strg1) 1910.

13 is a configuration diagram of a liquid crystal display device according to a third embodiment of the present invention. The liquid crystal display of FIG. 13 has the same configuration as the liquid crystal display of FIG. 10 except that the above-described liquid crystal panel 1901 is used as the liquid crystal panel.

The operation of the liquid crystal display device of the present embodiment will be described with reference to FIG.

In the liquid crystal display according to the present embodiment, as in the second embodiment, the voltage G 2 of the gate line 1902 becomes the selection voltage Vgon, and the drain line 1903 alternates with the display data of the second row of pixels. The selected drain voltages Vd + and Vd- are output in accordance with the speech signal 904. As a result, the drain voltage Vd + or Vd- and the reference voltage are applied to each pixel portion 1904 of the second row. After one line period, when the voltage G2 becomes the non-selection voltage Vgoff and the voltage G3 becomes the selection voltage Vgon, the TFT 1905 of each pixel portion 1904 of the third row is turned on and in parallel with this. Thus, the display data of each pixel of the third row and the gradation voltage corresponding to the AC signal 904 are output to the drain line 1903. In this way, the same operation is repeated every one line period, and all the pixel portions 1904 are driven in one frame period.

For example, in the period in which the voltage G2 becomes the selection voltage Vgon, in the pixel portion 1904 in the second row and in the odd column, as shown in FIG. 14, a potential difference of positive polarity occurs and the even row in the second row. A negative potential difference occurs in the pixel portion 1904. That is, the potential difference generated in the pixel portion 1904 of each row is reversed in polarity for each column. In addition, the current flowing into each of the common electrodes Strg0 and Strg1 1909 and 1910 flows in individual wirings for each pixel of current in the region constituting the pixel portion 1904, thereby flowing the pixel portion 1904. The current is n / 2 pixels in the wiring area other than the configured area. For this reason, the liquid crystal applied voltage can be stabilized similarly to the second embodiment.

As described above, even in the liquid crystal display device of the present embodiment, the deterioration of the image quality due to the variation of the voltage of the common electrode can be reduced as compared with the conventional example. Moreover, since the flicker prevention effect is acquired even when the frequency of a reference voltage is reduced, power consumption can be reduced compared with the conventional example.

As described above, according to the present invention, the frequency of the voltage applied to the common electrode can be reduced without increasing the flicker, thereby making it possible to reduce the power consumption of the liquid crystal display device. In addition, the concentration of the current in the common electrode can be eliminated and the deterioration of the display quality can be reduced.

Claims (21)

A liquid crystal panel of an active matrix having two substrates arranged opposite to each other and a liquid crystal filled between the two substrates, An M x N pixel portion, a plurality of drain lines, a plurality of gate lines and two counter electrode lines corresponding to the pixels of the M rows and N columns formed on the substrate, Each pixel portion A thin film transistor having a gate electrode connected to any one of the gate lines, a drain electrode connected to any one of the drain lines, and a source electrode; A pixel electrode connected to the source electrode of the thin film transistor; A counter electrode paired with the pixel electrode to apply an electric field to the liquid crystal and to change the transmittance of the liquid crystal with respect to the corresponding pixel; The counter electrodes are divided into two groups and connected to the two counter electrode lines for each group; The counter electrode is paired with the pixel electrode to form a capacitor for maintaining the electric field; The number of thin film transistors connected to the pixel electrode paired with the counter electrode connected to the same counter electrode line among the thin film transistors connected to each one gate line is approximately one-third of the number of thin film transistors connected to each one gate line. 2, Each one drain line is connected to a drain electrode of a thin film transistor corresponding to each one column, Each one gate line is connected to each one row of thin film transistors, One counter electrode line is commonly connected to the counter electrode corresponding to the thin film transistor of the odd or even column in the odd row and the even or odd column in the odd row, and the other opposite electrode line is superior in the odd row. A liquid crystal panel, wherein the liquid crystal panel is connected in common to the counter electrode corresponding to the thin film transistors in the odd or even columns in the first or odd columns and even rows. The method of claim 1, The two opposing electrode lines are made of a plurality of wirings arranged in parallel in the vertical direction or the inclined direction on the substrate, And the number of the thin film transistors corresponding to the opposite electrodes connected to the same wiring among the thin film transistors connected to each one gate line is one. A liquid crystal panel of an active matrix having two substrates arranged opposite to each other and a liquid crystal filled between the two substrates, wherein the liquid crystal panel is arranged in pixels arranged in a matrix of M rows and N columns of odd and even rows and odd and even columns. Correspondingly including M x N pixel portions, a plurality of drain lines, a plurality of gate lines and two opposing electrode lines arranged in an M row N column matrix on the substrate, wherein each pixel portion includes the drain for supplying a gray scale voltage. A switching element having a drain electrode coupled to one of the lines, a gate electrode coupled to one of the gate lines for applying a selection voltage or a non-selection voltage, and a source electrode for applying the gray scale voltage to the liquid crystal of each pixel portion. And a thin film transistor, wherein the first shape pixel portion of the odd rows is provided on the gate lines of the odd rows, the drain lines of the odd rows, and the first counter electrode. Is driven and the second shape pixel portion of the even row is driven by the gate line of the even row, the drain line of the even column and the first counter electrode, and the third shape pixel part of the even row is the gate of the even row. A line, a drain line of the radix row, and a second counter electrode, and a fourth form pixel portion of the even row of even columns is driven by the gate line of the odd row, the drain line of the even row, and the second counter electrode; A first opposing electrode connected to a first opposing electrode line of the two opposing electrode lines, the second opposing electrode connected to a second opposing electrode line of the two opposing electrode lines, and each pixel portion being a pixel connected to the source electrode First and second units arranged in pairs with an electrode and the associated pixel electrode to change the transmittance of the liquid crystal to a corresponding pixel portion by applying an electric field to the liquid crystal; The liquid crystal panel further including one of the electrodes; A liquid crystal controller that receives display data and a synchronization signal and generates liquid crystal display data and a liquid crystal synchronization signal for enabling display of an image corresponding to the display data on the liquid crystal panel according to the received display data and the synchronization signal; Scanning voltage generating means for applying a selected voltage or a non-selected voltage to the gate line in accordance with the liquid crystal synchronization signal; Reference voltage generating means for respectively applying reference voltages of predetermined levels having different polarities to the two opposing electrode lines in accordance with the liquid crystal synchronization signal, and inverting the polarities of the two reference voltages at predetermined cycles; And a gradation voltage generating means for generating a gradation voltage corresponding to the liquid crystal display data and the reference voltage and applying the gradation voltage to the drain line. A liquid crystal panel of an active matrix having two substrates arranged opposite to each other and a liquid crystal filled between the two substrates, wherein the liquid crystal panel is arranged in pixels arranged in an M-row N-column matrix of odd and even rows and odd and even columns. Correspondingly including M x N pixel portions, a plurality of drain lines, a plurality of gate lines and two opposing electrode lines arranged in an M row N column matrix on the substrate, wherein each pixel portion includes the drain for supplying a gray scale voltage. A switching element having a drain electrode coupled to one of the lines, a gate electrode coupled to one of the gate lines for applying a selection voltage or a non-selection voltage, and a source electrode for applying the gray scale voltage to the liquid crystal of each pixel portion. And a thin film transistor, wherein the first shape pixel portion of the odd rows is provided on the gate lines of the odd rows, the drain lines of the odd rows, and the first counter electrode. Is driven and the second shape pixel portion of the even row is driven by the gate line of the even row, the drain line of the even column and the first counter electrode, and the third shape pixel part of the even row is the gate of the even row. A line, a drain line of the odd columns, and a second counter electrode, and a fourth type pixel portion of even rows of even rows is driven by a gate line of the odd rows, a drain line of the even rows, and the second counter electrode; A first opposing electrode connected to a first opposing electrode line of the two opposing electrode lines, the second opposing electrode connected to a second opposing electrode line of the two opposing electrode lines, and each pixel portion being a pixel connected to the source electrode First and second units arranged in pairs with an electrode and the associated pixel electrode to change the transmittance of the liquid crystal to a corresponding pixel portion by applying an electric field to the liquid crystal; A counter electrode connected to the same counter electrode line among thin film transistors connected to each of the one gate line; A liquid crystal panel in which the number of the thin film transistors connected to a pixel electrode paired with an electrode is approximately N / 2; A liquid crystal controller for receiving display data and a synchronization signal and generating liquid crystal display data and a liquid crystal synchronization signal for enabling display of an image corresponding to the display data on the liquid crystal panel according to the received display data and the synchronization signal; Scanning voltage generating means for applying a selected voltage or a non-selected voltage to the gate line in accordance with the liquid crystal synchronization signal; Reference voltage generating means for applying a reference voltage to the two opposing electrode lines in accordance with the liquid crystal synchronization signal; And a gradation voltage generating means for generating a gradation voltage corresponding to the liquid crystal display data and the reference voltage and applying the gradation voltage to the drain line. The method of claim 3, The reference voltage generating means inverts the polarity of the reference voltage every display period of one frame of the liquid crystal display data; And the gradation voltage generating means generates the gradation voltage according to a reference voltage having a different polarity for each display period of one line of the liquid crystal display data. The method of claim 3, And the liquid crystal controller generates the liquid crystal display data by rearranging the received display data in accordance with the connection state of the thin film transistor, gate line and drain line in the liquid crystal panel. The method of claim 4, wherein And the liquid crystal controller generates the liquid crystal display data by rearranging the received display data in accordance with the connection state of the thin film transistor, gate line and drain line in the liquid crystal panel. A liquid crystal panel of an active matrix having two substrates arranged opposite to each other and a liquid crystal filled between the two substrates, The liquid crystal panel M x N pixel portions arranged in an M row N column matrix on the substrate so as to correspond to pixels arranged in an odd and even row and an M and N column matrix of odd and even columns; Several drain lines; Several gate lines; Including two opposing electrode wires, Each pixel portion may include a drain electrode coupled to one of the drain lines for supplying a gray scale voltage, a gate electrode coupled to one of the gate lines for applying a selection voltage or a non-selection voltage, and the gray voltage to each of the pixel portions. A thin film transistor, which is a switching element having a source electrode applied to the liquid crystal, A pixel portion of a first row of odd rows is driven by a gate line of the odd rows, a drain line of the odd rows, and a first counter electrode; The second shape pixel portion of the odd row even column is driven by the gate line of the even row, the drain line of the even row, and the first counter electrode; The third shape pixel portion of the even row column is driven by the gate line of the even row, the drain line of the odd row, and the second counter electrode; The fourth shape pixel portion of the even row even column is driven by the gate line of the odd row, the drain line of the even column and the second counter electrode; And the first counter electrode is connected to a first counter electrode line of the two counter electrode lines, and the second counter electrode is connected to a second counter electrode line of the two counter electrode lines. The method of claim 8, The voltage level of the first counter electrode and the second counter electrode in an arbitrary cycle period is different from each other, A gray level voltage corresponding to a first group of the first shape pixel portion of the even row even column and a second group of the fourth shape pixel portion of the odd row odd number column is simultaneously supplied to the drain line, When the gray level voltage applied to the second group of the fourth form pixel portion of the odd row is the gray level voltage level of the electrostatic potential with respect to the voltage level of the first counter electrode, the first form pixel portion of the first form pixel portion of the even row The gradation voltage applied to the group becomes the gradation voltage level of the negative potential with respect to the voltage level of the second counter electrode, When the gray level voltage applied to the second group of the fourth form pixel portion of the odd row is a gray level voltage level of negative potential with respect to the voltage level of the first counter electrode, the first form pixel portion of the first form pixel portion of the even row even column The gradation voltage applied to the group becomes the gradation voltage level of the electrostatic potential with respect to the voltage level of the second counter electrode, A gradation voltage corresponding to a third group of the second form pixel portion of the even row, and the fourth group of the third form pixel portion of the even line, is supplied to the drain line at the same time, When the gradation voltage applied to the fourth group of the third form pixel portion of the even row sequence is the gradation voltage level of the potential potential relative to the voltage level of the second counter electrode, The gradation voltage applied to the group becomes the gradation voltage level of the negative potential with respect to the voltage level of the first counter electrode, The third group of the second pixel portion of the even row when the gray level voltage applied to the fourth group of the pixel portion of the third row of even row is the level of negative potential with respect to the voltage level of the second counter electrode; The gradation voltage applied to the liquid crystal panel is characterized in that the gradation voltage level of the potential potential with respect to the voltage level of the first counter electrode. The method of claim 8, The voltage level of the first counter electrode and the second counter electrode in an arbitrary cycle period is different from each other, Wherein the voltage levels are switched after each data processing for one screen is finished. The method of claim 8, Each pixel portion A pixel electrode connected to the source electrode and A liquid crystal further comprising one of first and second counter electrodes arranged in pairs with the associated pixel electrode and for applying an electric field to the liquid crystal to change the transmittance of the liquid crystal to a corresponding pixel portion; panel. The method of claim 8, The first and second counter electrodes are divided into two groups, The two groups of the first and second counter electrodes are separately connected to the two counter electrode lines, respectively. And the light current flowing in each group of the first and second counter electrodes is reduced to a value corresponding to approximately 1/2 of the number of pixel portions in each row. The method of claim 11, The counter electrodes are paired with the pixel electrodes to form a capacitor for maintaining the electric field; And the number of the thin film transistors connected to the pixel electrode paired with the counter electrode connected to the same counter electrode line among the thin film transistors connected to each one gate line is approximately N / 2. The method of claim 11, Each one drain line is connected to a drain electrode of the thin film transistor on one column; One of the two opposite electrode lines is connected to the counter electrode corresponding to the thin film transistor in the odd row, and the other of the opposite electrode lines is connected to the counter electrode corresponding to the thin film transistor in the even row. Wherein each one gate line is connected to a thin film transistor in an even row or an odd column in an arbitrary row, or is connected to a thin film transistor in an odd or even column in an adjacent row together with the thin film transistor. LCD panel. The method of claim 13, Each one drain line is connected to a drain electrode of the thin film transistor on one column; One of the electrode lines is connected to a counter electrode corresponding to the thin film transistor in the odd row, and the other electrode line is connected to a counter electrode corresponding to the thin film transistor in the even row; Each one of the gate lines is connected to the thin film transistor in the even-numbered column or the odd-numbered column in an arbitrary row, or connected to the thin film transistor in the odd-numbered or even-numbered column in a row adjacent to the thin film transistor. A liquid crystal panel characterized by the above. The method of claim 11, Each one drain line is connected to a drain electrode of the thin film transistor on one column; The gate lines are connected to the thin film transistors on one row; One electrode line of the counter electrode lines is connected as a column line to the thin film transistor of the odd or odd column in the odd row and the counter electrode corresponding to the thin film transistor of the even or odd column in the even row. The electrode line of the side is connected as a column line to the thin film transistor of the even row or the odd column in the even row and the counter electrode corresponding to the thin film transistor of the even column or the odd row in the odd row. . The method of claim 13, Each one drain line is connected to a drain electrode of the thin film transistor on one column; The gate lines are connected to the thin film transistors on one row; One electrode line of the counter electrode lines is connected as a column line to the thin film transistor of the odd or odd column in the odd row and the counter electrode corresponding to the thin film transistor of the even or odd column in the even row. The electrode line of the side is connected as a column line to the thin film transistor of the even row or the odd column in the even row and the counter electrode corresponding to the thin film transistor of the even column or the odd row in the odd row. . The method of claim 14, The two opposing electrode lines include a plurality of wiring patterns made in a vertical direction or an inclined direction on the substrate. And the number of the thin film transistors corresponding to the opposite electrodes connected to the same wiring among the thin film transistors connected to the respective gate lines is one. The method of claim 15, The two opposing electrode lines include a plurality of wiring patterns made in a vertical direction or an inclined direction on the substrate. And the number of the thin film transistors corresponding to the opposite electrodes connected to the same wiring among the thin film transistors connected to the respective gate lines is one. The method of claim 16, The two opposing electrode lines include a plurality of wiring patterns made in a vertical direction or an inclined direction on the substrate. And the number of the thin film transistors corresponding to the opposite electrodes connected to the same wiring among the thin film transistors connected to the respective gate lines is one. The method of claim 13, The two opposing electrode lines include a plurality of wiring patterns made in a vertical direction or an inclined direction on the substrate. And the number of the thin film transistors corresponding to the opposite electrodes connected to the same wiring among the thin film transistors connected to the respective gate lines is one.

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