KR100477598B1 - Apparatus and Method for Driving Liquid Crystal Display of 2 Dot Inversion Type - Google Patents

Abstract

The present invention relates to a liquid crystal display driving method and apparatus capable of minimizing a horizontal line phenomenon generated in a two-dot inversion driving method.

The liquid crystal display driving method and apparatus selectively supplies scanning pulses having a pulse width of one horizontal period to the gate lines so that gate lines of the liquid crystal display are not continuously scanned, and supplies video data synchronized with the scanning pulses. It supplies the data lines of the liquid crystal display in a 2-dot inversion method. The scan pulse is supplied to all the gate lines of the liquid crystal display for one frame period.

By scanning the gate lines in this selective scanning method, vertically adjacent liquid crystal cells are not driven continuously, thereby minimizing the voltage difference (ΔVpp) caused by the parasitic capacitor influence with the vertically adjacent liquid crystal cells to minimize the luminance difference between the lines. It becomes possible.

Description

Apparatus and Method for Driving Liquid Crystal Display of 2 Dot Inversion Type}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display driving method and apparatus capable of minimizing a horizontal line phenomenon generated in a two-dot inversion driving method.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel. In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor, which is a switching element. The gate terminal of the thin film transistor is connected to one of the gate lines for causing the data voltage signal to be applied to the pixel electrodes for one line. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the data voltage signal supplied for each liquid crystal cell.

In fact, the liquid crystal display device includes a liquid crystal panel 2 in which liquid crystal cells are arranged in a matrix form as shown in FIG. 1, and a gate driver 4 for driving gate lines GL1 to GLn of the liquid crystal panel 2. ), A data driver 6 for driving the data lines DL1 to DLm of the liquid crystal panel 2, a gamma voltage generator 8 for supplying a gamma voltage to the data driver 6, and a gate. A control unit 10 for controlling the driver 4 and the data driver 6 is provided.

In FIG. 1, the liquid crystal panel 2 is a thin film transistor TFT formed at intersections of liquid crystal cells arranged in a matrix form and n gate lines GL1 to GLn and m data lines DL1 to DLm. ). The thin film transistor TFT supplies a video signal from the data lines DL1 to DLm to the liquid crystal cell in response to the gate signal from the gate lines GL1 to GLn. The liquid crystal cell may be equivalently represented by a liquid crystal capacitor Clc including a common electrode facing the liquid crystal and a pixel electrode connected to the thin film transistor. In the liquid crystal cell, a storage capacitor Cst is formed to maintain the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged. The storage capacitor Cst is formed between the previous gate electrode and the pixel electrode. In addition, a plurality of parasitic capacitors are formed in the thin film transistor TFT and the liquid crystal cell, such as a parasitic capacitor Cpp between the pixel electrode and the next storage capacitor Cst. These parasitic capacitors cause the data voltage charged in the liquid crystal capacitor Clc to vary by a predetermined amount. The gate driver 4 sequentially supplies scanning pulses to the gate lines GL1 to GLn to drive the thin film transistors TFT connected to the corresponding gate line.

To this end, the gate driver 4 includes a plurality of gate integrated circuits (hereinafter referred to as ICs) for sequentially driving the gate lines GL1 to GLn separately as shown in FIG. 2. ) Assuming that the gate driver 4 illustrated in FIG. 2 includes four gate driver ICs 12, signal waveforms input and output to the gate driver ICs 12 are the same as those of FIG. 3. Each of the gate driving ICs 12 includes a shift register that sequentially generates the scanning pulse SP in response to the gate start pulse GSP and the gate shift clock GSC supplied from the controller 10, and a voltage of the scan pulse. It is composed of a level shifter for shifting the to a level suitable for thin film transistor (TFT) driving. The gate driving clock signals GSC having one horizontal period 1H are commonly supplied to the gate driving ICs 12 as shown in FIG. 3. First, when the gate start pulse GSP is supplied from the controller 10, the first gate driving IC 12 performs a shift operation in response to the gate shift clock GSC to the gate lines GL1 to GLn / 4. The scanning pulse SP having one horizontal period 1H is sequentially supplied. Subsequently, the first gate driving IC 12 outputs the scan pulse SP to the last gate line GLn / 4, and simultaneously supplies a carry signal CR1 to the gate driving IC 12. Accordingly, when the carry signals CR1 to CR4 are supplied from the previous gate driving IC 12, the next gate driving ICs 12 perform the shift operation in response to the gate shift clock GSC, thereby providing the gate lines GLn. / 4 + 1 to GLn) to sequentially supply the scanning pulse (SP). Here, when the gate driver 4 includes four gate driver ICs 12, the carry signals CR1 to CR3 output from the gate start pulse GSP and the gate driver ICs 12 are 1/4. It can be seen that it occurs every vertical period (V / 4).

The data driver 6 converts the video data signal into an analog signal and outputs a video signal corresponding to one horizontal line every one horizontal period 1H during which the scanning pulse SP is supplied to the gate line GL. DLn). At this time, the gamma voltage generator 8 supplies the data driver 6 with a preset DC gamma voltage to have a different voltage level according to the voltage level of the video data signal. Accordingly, the data driver 6 adds the gamma voltage from the gamma voltage generator 8 to the video signal to supply the data lines DL1 to DLn so that the gamma characteristic of the liquid crystal display device is corrected. The controller 10 controls the driving timing of the gate driver 4 and the data driver 6 in response to clock signals and horizontal and vertical synchronization signals input through the input line 11. In other words, the controller 10 generates a gate shift clock GSC, a gate start pulse GSP, and the like in response to the clock signal and the horizontal and vertical synchronizing signals, and supplies them to the gate driver 4. In addition, the controller 10 generates a data clock signal, a data control signal, and the like in response to the input clock signal and the horizontal and vertical synchronization signals Hsync and Vsync, and supplies the same to the data driver signal. The red (R), green (G), and blue (B) video data input through the input line 11 are supplied to the data driver 6.

In such a liquid crystal display device, an inversion driving method such as a frame inversion system, a line column inversion system, and a dot inversion system is used to drive liquid crystal cells on a liquid crystal panel. This is used. The liquid crystal panel driving method of the frame inversion method inverts the polarity of the data signal supplied to the liquid crystal cells on the liquid crystal panel every time the frame is changed. In the liquid crystal panel driving method of the line inversion method, the polarities of the data signals supplied to the liquid crystal cells are reversed according to a line (column) on the liquid crystal panel. The dot inversion scheme allows each of the liquid crystal cells on the liquid crystal panel to be supplied with a data signal having a polarity opposite to that of the data signals supplied to adjacent liquid crystal cells in the vertical and horizontal directions. The polarities of the data signals supplied to the fields are reversed. Of these inversion driving methods, the dot inversion method provides an image having excellent image quality compared to the frame and line inversion methods. The inversion driving is performed in response to the data driver 4 in response to the polarity inversion signal supplied from the controller 10 to the data driver 4.

Such liquid crystal displays are generally driven by a frame frequency of 60 Hz. However, in a system requiring low power consumption such as a notebook computer, it is required to lower the frame frequency to 50 to 30 Hz. As the frame frequency is lowered, the flicker phenomenon occurs in the dot inversion method that provides excellent image quality among the inversion methods. Thus, the method of driving the liquid crystal panel of the two-dot inversion method as shown in FIGS. 4A and 4B is proposed. It became.

4A and 4B illustrate the polarity of the data signal supplied to the liquid crystal cells of the liquid crystal panel by the odd frame and the even frame by the 2-dot inversion liquid crystal panel driving method. In the odd and even frames shown in Figs. 4A and 4B, the two-dot inversion scheme changes the polarity of the data signal in the horizontal direction, as in the conventional dot inversion scheme, in the liquid crystal cell, that is, in the unit of dots. It can be seen that the drive is changed in units of 2 dots in the direction. While the two-dot inversion method has the advantage that the flicker phenomenon is reduced compared to the dot inversion method in a commercial screen driven at a frame frequency of 50 Hz, the horizontal line is generated every two scanning lines depending on the luminance difference between the scanning lines. Have.

5A and 5B illustrate horizontal lines in the odd frame and the even frame, which are caused by the two-dot inversion liquid crystal panel driving method. 5A and 5B, when the polarity of the liquid crystal cell is changed every two scan lines in the vertical direction, a horizontal phenomenon occurs due to the luminance difference between the odd scan lines G1 and the even scan lines G2. This is because, in the case of the 2-dot inversion method, the coupling effect of the pixel voltage due to the parasitic capacitor Cpp formed between the pixel electrode and the storage electrode of the liquid crystal cell adjacent in the vertical direction occurs in the liquid crystal cells. .

In detail, in the case of the dot inversion method, as shown in FIG. 6, the coupling effect of the pixel voltage due to the parasitic capacitor Cpp, that is, the variation ΔVpp of the pixel voltage occurs in all liquid crystal cells. 6 shows data voltages Vd [n] and Vd [n + charged in the nth liquid crystal cell and the n + 1th liquid crystal cell of the next line in response to the gate signals Vg [n] and Vg [n + 1]. 1]) shows the change characteristics.

In FIG. 6, ΔVp is the data voltage Vd charged to the liquid crystal cell during the supply period of the scan pulse, that is, the gate high voltage Vgh, in the current frame M, and the data voltage Vd of the next frame M + 1 It is generated by the coupling effect of parasitic capacitors Cgs and Cgd formed inside the thin film transistor with a feed through voltage which is changed until supplied. [Delta] Vpp is added to the feed throw voltage [Delta] Vp and is generated by the coupling effect of the parasitic capacitor Cpp formed between the pixel electrode and the next storage electrode. Referring to FIG. 6, the data voltage Vd [n] of positive polarity (+) is charged in the nth liquid crystal cell in the current frame M, and the data voltage of negative polarity (+) is provided in the n + 1th liquid crystal cell. (Vd [n + 1]) is charged, and the data voltages Vd [n] and Vd [n + 1] polarities are reversed in the next frame M + 1. In other words, in all liquid crystal cells, a potential change occurs in the liquid crystal cell of the next scan line in a direction opposite to the polarity of the data voltage currently charged by dot inversion driving. Accordingly, in all liquid crystal cells, the same voltage change value ΔVpp is generated in the opposite direction to the polarity of the charged data voltage due to the influence of the parasitic capacitor Cpp. As a result, the luminance difference between the scan lines does not occur in the dot inversion driving.

On the other hand, in the case of the 2-dot inversion driving method, as shown in FIG. 7, the variation ΔVpp of the pixel voltage due to the parasitic capacitor Cpp is different for each scan line. 7 shows the [m, n] th and [m + 1, n] th liquid crystal cells and the [m, n + 1] th of the next line in response to the scanning pulses GL [n] and GL [n + 1]. And data voltages Vd [m, n], Vd [m + 1, n], Vd [m, n + 1], and Vd [m + 1, which are charged in the [m + 1, n + 1] th liquid crystal cell. n + 1]).

Referring to FIG. 7, the data voltages Vd [m, n] and Vd [m + of the positive polarity (+) in the [m, n] -th and [m, n + 1] -th liquid crystal cells in the current frame M 1, n]) are charged, and the negative data voltages Vd [m, n + 1], Vd are stored in the [m, n + 1] th and [m + 1, n + 1] th liquid crystal cells. [m + 1, n + 1] is charged, and in the next frame M + 1, the data voltages Vd [m, n], Vd [m + 1, n], and Vd [m, n + 1] , Vd [m + 1, n + 1]) is reversed. In other words, in the liquid crystal cells [m, n] and [m, n + 1] included in the odd scan line G1, the adjacent liquid crystal cells [m, n + 1] and [ m + 1, n + 1]) are applied with the same polarity data voltage. Accordingly, in the liquid crystal cells [m, n] and [m, n + 1], the voltage variation value ΔVpp1 is generated in the same direction as the polarity of the data voltage currently charged by the parasitic capacitor Cpp. However, in the liquid crystal cells [m, n + 1], [m + 1, n + 1] included in the even-numbered scan line G2, a data voltage of opposite polarity is applied to the liquid crystal cells adjacent in the vertical direction. do. Accordingly, in the liquid crystal cells [m, n + 1], [m + 1, n + 1], the voltage fluctuation value ΔVpp2 is opposite to the polarity of the data voltage currently charged by the parasitic capacitor Cpp. Occurs. As described above, as the voltage fluctuation values ΔVpp1 and ΔVpp2 of the parasitic capacitor Cpp are different in the radix scan line G1 and the even scan line G2, the radix scan line G1 and the even scan line are different. The luminance difference occurs between (G2). In detail, in the normal white mode, the odd-numbered scan lines G1, in which the data voltage charged by the voltage change value ΔVpp1 increases with respect to the common voltage Vcom due to the same polarity voltage as the next scan line, appear dark, and then The even-numbered scan lines G2 in which the data voltage charged by the voltage change value ΔVpp1 decreases with respect to the common voltage Vcom due to the charging of the polarity voltage opposite to the scan line become bright.

As described above, in the two-dot driving method, the luminance difference is generated between the scanning lines due to the difference in the parasitic capacitor (Cpp) coupling effect, so that a horizontal line phenomenon occurs and display quality is deteriorated.

Accordingly, an object of the present invention is to provide a method and apparatus for driving a 2-dot inversion liquid crystal display which can minimize the difference in luminance between scan lines by coupling by selectively scanning gate lines.

In order to achieve the above object, the two-dot inversion type liquid crystal display driving method according to the present invention selects a scanning pulse having a pulse width of one horizontal period to the gate lines so that the gate lines of the liquid crystal display are not continuously scanned. Supplying; Supplying video data synchronized with the scan pulse to data lines of the liquid crystal display in a 2-dot inversion manner. The scan pulse is supplied to all the gate lines of the liquid crystal display for one frame period.

The 2-dot inversion type liquid crystal display driving apparatus according to the present invention selectively supplies a scanning pulse having a pulse width of one horizontal period to the gate lines so that the gate lines of the liquid crystal display are not continuously scanned. And a data driver circuit for supplying video data synchronized with the scan pulse to data lines of the liquid crystal display in a 2-dot inversion manner, and controlling driving timings of the gate driver circuit and the data driver circuit. And a control circuit for rearranging the video signal and supplying the video signal to the data driving circuit in a driving order of gate lines.

Other objects and advantages of the present invention in addition to the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 8 to 14.

In the liquid crystal display driving method of the present invention, the scanning pulses are selectively supplied to the gate lines GL1 to GLn so that the scanning pulses are not continuously supplied to the adjacent scanning lines. In other words, in the present invention, the gate lines GL1 to GLn are driven in a selective scanning manner so that scanning pulses that are continuous in time are supplied to the gate lines GL1 to GLn at predetermined line intervals. By the selective scanning method, the difference of the voltage fluctuation value (ΔVpp) due to the coupling effect of the parasitic capacitor can be minimized in the 2-dot inversion method. Referring to FIG. 7, it can be seen that the voltage variation value ΔVpp due to the coupling effect of the parasitic capacitor is generated in the period in which the scanning pulse is continuously supplied to the adjacent liquid crystal cells in the vertical direction. Accordingly, in the present invention, the driving pulses are not continuously supplied to the vertically adjacent liquid crystal cells by driving the gate lines GL1 to GLn in a selective scanning method, so that the voltage fluctuation value ΔVpp due to the parasitic capacitor effect with the adjacent liquid crystal cells. ) Can be minimized.

FIG. 8 illustrates a scanning pulse waveform applied to a method of driving a 2-dot inversion liquid crystal display according to an exemplary embodiment of the present invention. In FIG. 8, the n gate lines GL1 to GLn are driven by dividing the plurality of gate lines GL1 to GLn into four blocks, for example, the gate lines having a line interval of n / 4 having a continuous scan pulse SP. GL1 to GLn). In detail, the first gate line GL1 of the first block, the first gate line GLn / 4 + 1 of the second block, the first gate line GL2n / 4 + 1 of the third block, and the first gate of the fourth block Scan pulses are supplied in line (GL3n / 4 + 1) order. Next, the remaining gate lines GL2 to GLn / 4, GLn / 4 + 2 to GL2n / 4, GL2n / 4 + 2 to GL3n / 4, and GL3n / 4 + 2 to GLn of the first to fourth blocks. As described above, the driving is performed sequentially with n / 4 line intervals. In this way, as the gate lines GL1 to GLn are sequentially driven at intervals of n / 4 lines, the voltage variation value ΔVpp due to the parasitic capacitor effect with the adjacent liquid crystal cells can be minimized.

To this end, the gate driver for driving the gate lines GL1 to GLn has a configuration as shown in FIG. 9. The gate driver shown in FIG. 9 is composed of a plurality of gate driving ICs 20, that is, first to fourth gate driving ICs 20 for separately driving the gate lines GL1 to GLn. Input driving waveforms are as shown in FIG. 10. Each of the gate driving ICs 20 is a scan pulse SP as shown in FIG. 8 in response to a gate shift clock GSC, a gate start pulse GSP, and carry signals CR1 to CR3 supplied from a controller (not shown). ), And a level shifter for shifting the voltage of the scanning pulse SP to a level suitable for driving the thin film transistor TFT. Each of the first to fourth gate driving ICs 20 is separately supplied with the gate start pulse GSP and the carry signals CR1 to CR3 from a controller (not shown) as shown in FIG. 10. The gate start pulse GSP and the carry signals CR1 to CR3 have a pulse width of one horizontal period 1H and are supplied with a phase difference so as to be continuous in time sequence without overlapping each other. By the gate start pulses GSP and the carry signals CR1 to CR3, the first to fourth gate driving ICs 20 individually start a shift operation and scan pulses SP every four horizontal periods 4H. Will occur. To this end, the gate shift clock signal GSC commonly supplied to the gate driving ICs 20 has one horizontal period 1H while the conventional gate shift clock signal GSCpr has one horizontal period 1H. It has 4 horizontal periods (4H). When the gate start pulse GSP is supplied, the first gate driving IC 20 performs a shift operation in response to the gate shift clock GSC to sequentially perform four horizontal periods 1H in the gate lines GL1 to GLn / 4. Supplying a scanning pulse (SP) having a. In the same manner, each of the second to fourth gate driving ICs 20 shifts in response to the gate shift clock GSC when the carry signals CR1 to CR3 supplied with a phase difference of one horizontal period 1H are supplied. By performing the operation, the scan pulse SP is sequentially performed every four horizontal periods 1H in the gate lines GLn / 4 + 1 to GL2n / 4, GL2n / 4 + 1 to GL3n / 4, and GL3n / 4 + 1 to GLn. Will be supplied.

On the other hand, the first to fourth gate driving ICs 20 change their driving order by changing the timing of supplying the start pulse gate start pulse GSP and the carry signals CR1 to CR3 as shown in FIG. You can also drive. Referring to FIG. 11, the supply points of the carry signals CR2 and CR3 are supplied to the second and third gate driver ICs 20 interchangeably. In this case, the scan pulses SP supplied to the gate lines GL1 to GLn are driven in a different order than the form having a regular interval of n / 4 lines as shown in FIG. 8. Accordingly, the scan pulses SP generated in the first to fourth gate driver ICs 20 do not have a continuous form in time with respect to n / 4 line intervals as shown in FIG. 8. It has a predetermined line interval and has a continuous form. As a result, since the vertically adjacent liquid crystal cells are not driven continuously, the voltage fluctuation value? Vpp due to the parasitic capacitor influence with the liquid crystal cells adjacent in the vertical direction can be minimized.

12 is a block diagram illustrating a gate driver according to another embodiment of the present invention. The gate driver shown in FIG. 12 is composed of a plurality of, for example, first to fourth gate driver ICs 24 for separately driving the gate lines GL1 to GLn. Scan pulses SP output from the controllers are shown in FIG. 13. Each of the gate driving ICs 24 is shown in FIG. 8 in response to a gate shift clock GSC, a gate start pulse GSP, and even / odd control signals Even / Odd supplied from a controller (not shown). A shift register for generating the same scan pulses SP, and a level shifter for shifting the voltage of the scan pulses SP to a level suitable for driving the thin film transistor TFT. Each of the first to fourth gate driving ICs 24 is provided with a gate shift clock GSC and a gate start pulse GSP having the same period as in the prior art as shown in FIG. 3. In addition, the second to fourth gate driver ICs 24 perform a shift operation in response to the carry signals CR1 to CR3 output from the previous gate driver IC 24. In particular, the first to fourth gate driving ICs 24 may have the odd-numbered gate lines GL1, GL3, GL5 ... as shown in FIG. 13 in response to the odd / high control signal Even / Odd. The even-numbered gate lines GL2, GL4, GL6 ... are selectively driven. In other words, the first to fourth gate driver ICs 24 are sequentially driven by the gate start clock GSC and the previous carry signals CR1 to CR3, whereas in each gate driver IC 24, the odd number is used. The odd-numbered gate lines GL1, GL3, GL5 ... and the even-numbered gate lines GL2, GL4, GL6 ... are selectively driven by the / excellent control signal Even / Odd. For example, the gate lines GL1 to GLn are sequentially driven at intervals of one line in the order of GL1, GL3, GL2, GL4, GL6, GL5, ... as shown in FIG. Accordingly, since the vertically adjacent liquid crystal cells are not continuously driven, the voltage variation value ΔVpp due to the parasitic capacitor influence with the vertically adjacent liquid crystal cells can be minimized.

On the other hand, when the carry signals CR1 to CR2 are individually supplied from the controller (not shown) together with the odd / odd control signals Even / Odd to the respective gate driving ICs 24 in a different order from the above. The gate lines GL1 to GLn can be driven. For example, the odd gate lines GL1, GL3, GL5 ... are sequentially driven in the first gate driver IC, and then the even gate lines GLn / 4 + 2, GLn in the second gate driver IC. / 4 + 4, GLn / 4 + 6 ...) in sequence. Subsequently, the third to fourth gate driver ICs separately drive the odd-numbered gate lines and the even-numbered gate lines in the same manner as described above. Then, the first to fourth gate driving ICs sequentially drive the remaining gate lines not driven above. In addition to these methods, depending on the logic configuration in the gate driver IC, gate lines may be selectively driven so that adjacent lines are not driven continuously in time.

As such, when changing the driving method of the gate driver to selectively scan the gate lines GL1 to GLn, video data supplied to the data driver must also be rearranged and supplied. The rearrangement of such video data is performed in the graphics card 32 or the controller 34 which supplies the video data in the driving device of the liquid crystal display as shown in FIG.

In the liquid crystal display driving device shown in FIG. 14, the graphics card 32 is installed in the system unit. The graphics card 2 converts the input video data into the resolution of the liquid crystal panel 42 to the controller 34. Supply. In addition, the graphic card 32 generates control signals such as a main clock signal, a vertical synchronization signal, and a horizontal synchronization signal suitable for the resolution of the liquid crystal panel 3 and supplies them to the controller 34. The graphic card 32 further includes a memory and rearranges the video data to supply the control unit 34 in accordance with the selective driving order of the gate lines GL1 to GLn described above.

The controller 34 relays the video data from the graphics card 32 to the data driver 38. In addition, the control unit 34 generates control signals such as timing signals and polarity inversion signals for controlling data and driving timing of the gate drivers 38 and 40 in response to the control signal from the graphics card 32. . In other words, the control section 34 is a gate shift clock (GSC), gate start pulse (GSP), carry signal (CR), odd / / suitable for selectively driving the gate lines (GL1 to GLn) as described above The even control signal Even / Odd is generated and supplied to the gate driver 40. In addition, the controller 34 supplies a dot clock signal, a 2-dot polarity inversion signal, and the like to the data driver 38 together with the video data. In addition, the controller 34 may perform a video data rearranging function suitable for selective driving of the gate lines GL1 to GLn in the graphic card 32. The gate driver 40 selectively drives the gate lines GL1 to GLn in response to a control signal of the controller 34. The data driver 38 converts the video data signal from the controller 34 into an analog signal based on the gamma voltage from the gamma voltage generator 68 and then selectively scans the pulses SP to the gate lines GL1 to GLn. ) Is supplied to the data lines DL1 to DLm for each horizontal period 1H to which is supplied. Accordingly, since the liquid crystal cells of the liquid crystal panel 42 are driven by the selective scanning method along with the 2-dot inversion method, parasitic capacitors with the liquid crystal cells adjacent to each other in the vertical direction are not affected by the vertically adjacent liquid crystal cells. It is possible to minimize the voltage fluctuation value ΔVpp.

As described above, in the method and apparatus for driving a 2-dot inversion liquid crystal display according to the present invention, unlike the conventional sequential scanning method, by scanning the gate lines in a selective scanning method, vertically adjacent liquid crystal cells are not continuously driven. Therefore, it is possible to minimize the voltage fluctuation value ΔVpp due to the parasitic capacitor effect with the liquid crystal cell adjacent in the vertical direction. As a result, in the liquid crystal panel driven by the method and device for driving the 2-dot inversion liquid crystal display according to the present invention, the luminance difference between the lines can be minimized to improve the image quality.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a block diagram showing the configuration of a conventional liquid crystal display device.

FIG. 2 is a block diagram showing the configuration of the gate driver shown in FIG.

3 is a driving waveform diagram input and output to the gate driving ICs shown in FIG.

4A and 4B are diagrams showing polar patterns of data signals supplied to liquid crystal cells of a liquid crystal panel by a 2-dot inversion driving method.

5A and 5B are diagrams showing a horizontal line phenomenon by a 2-dot inversion driving method.

6 is a characteristic diagram of change of data signals charged in liquid crystal cells by a dot inversion driving method.

7 is a characteristic diagram of change of data signals charged in liquid crystal cells by a 2-dot inversion driving method.

8 is a gate signal waveform diagram illustrating a method of driving a liquid crystal display of a two-dot inversion driving method according to an exemplary embodiment of the present invention.

FIG. 9 is a block diagram showing the configuration of a gate driver for outputting the gate signal waveform shown in FIG. 8; FIG.

FIG. 10 is a driving waveform diagram input to gate driving ICs shown in FIG. 9; FIG.

FIG. 11 is another driving waveform diagram input to gate driving ICs shown in FIG. 9; FIG.

12 is a block diagram showing the configuration of a gate driver according to another embodiment of the present invention.

FIG. 13 is a waveform diagram of a gate signal output from the gate driver shown in FIG. 12. FIG.

14 is a block diagram showing the configuration of a liquid crystal display driving apparatus of a two-dot inversion driving method according to an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

2, 42: liquid crystal panel 4, 40: gate driver

6, 38: data driver 8, 36: gamma voltage generator

10, 34: control unit 32: graphics card

12, 20, 24: gate drive integrated circuit (IC)

Claims (9)

In a driving method of a liquid crystal display driven by a 2-dot inversion driving method, Selectively supplying a scanning pulse having a pulse width of one horizontal period to the gate lines such that the gate lines of the liquid crystal display are not continuously scanned; Supplying video data synchronized with the scan pulse to data lines of the liquid crystal display in a 2-dot inversion manner, And the scanning pulse is supplied to all the gate lines of the liquid crystal display for one frame period. The method of claim 1, And sequentially supplying the scanning pulses to gate lines having a predetermined line interval. The method of claim 2, And dividing the gate lines into k blocks, and sequentially supplying the scanning pulses to gate lines having a line interval of “total gate lines / k”. 2. The method of claim 1, And dividing the gate lines into odd and even numbers to supply the scanning pulses. In the driving apparatus of the liquid crystal display driven by the 2-dot inversion driving method, A gate driving circuit for selectively supplying a scanning pulse having a pulse width of one horizontal period to the gate lines such that the gate lines of the liquid crystal display are not continuously scanned; A data driving circuit for supplying video data synchronized with the scan pulse to data lines of the liquid crystal display in a 2-dot inversion manner; A control circuit for controlling the driving timing of the gate driving circuit and the data driving circuit and realigning the video signal according to the driving order of the gate lines and supplying the video signal to the data driving circuit; And the scanning pulse is supplied to all the gate lines of the liquid crystal display for one frame period. The method of claim 5, wherein And the gate driving circuit sequentially supplies the scanning pulses to gate lines having a predetermined line interval. The method of claim 6, The gate driving circuit includes k gate driving integrated circuits for driving the gate lines into k blocks. And the k gate driver integrated circuits sequentially supply the scanning pulses to gate lines having a line spacing of “total gate lines / k”. The method of claim 7, wherein The k gate driver integrated circuits may perform the shift operation in response to a gate start signal and a gate signal supplied in common with the gate start signal and the carry signal respectively supplied from the control circuit to supply the scan pulse. Dot inversion type liquid crystal display driving device. The method of claim 5, wherein The gate driving circuit selectively supplies the scanning pulses to the odd-numbered gate lines and the even-numbered gate lines in response to the odd / excellent control signal from the control circuit. Drive system.