KR101220206B1 - Driving device of LCD and Driving method the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device. In particular, in a liquid crystal display device driven in a line-in version, a driving device of a liquid crystal display device operating in a dot-in version by arranging pixels of a liquid crystal panel in a zigzag form around a gate line, and a device thereof It relates to a driving method.

The driving device of such a liquid crystal display device has an output line selecting means at an output terminal of a data driver, by varying the output timing of the image signal output through the odd data line and the even data line. Output

Also, by precharging the pixel electrodes with different configurations of the output line selection means, the charging time of the video signal is further secured.

Description

Driving device for LCD and driving method thereof {Driving device of LCD and Driving method the same}

1 is a block diagram schematically illustrating a configuration of a driving apparatus in a general active liquid crystal display.

2A is a block diagram illustrating a line inversion driving type liquid crystal display device.

2B is a block diagram illustrating a column inversion driving type liquid crystal display device.

3 is a block diagram illustrating a dot inversion driving type liquid crystal display device.

4A is a block diagram schematically illustrating a configuration of a driving apparatus in the liquid crystal display according to the first embodiment of the present invention.

FIG. 4B is a block diagram schematically illustrating a configuration of a timing controller in the liquid crystal display of FIG. 4A.

4C is a waveform diagram illustrating part of signals of a driving device in the liquid crystal display of FIG. 4A.

5A is a block diagram schematically illustrating a configuration of a driving device in the liquid crystal display according to the second embodiment of the present invention.

FIG. 5B is a block diagram schematically illustrating a configuration of a timing controller in the liquid crystal display of FIG. 5A.

5C is a waveform diagram illustrating a part of signals of a driving device in the liquid crystal display of FIG. 5A.

<Explanation of symbols for the main parts of the drawings>

10: liquid crystal panel 20: gate driver

40: data driver 50: output line selection means

60: timing controller 80: common voltage section

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus for a liquid crystal display device and a driving method thereof. More particularly, a liquid crystal panel is driven by a dot inversion driving method using a driving device for driving with a line inversion driving method. A driving device of a liquid crystal display device and a driving method thereof for precharging a pixel electrode at the time of charging a pixel to ensure a stable charging period.

In the field of liquid crystal displays, active matrix liquid crystal displays are mainstream. In this active liquid crystal display, one thin film transistor (TFT) defines one pixel. This TFT controls the voltage level of the pixel as a switching element to change the light transmittance of the pixel to display an image.

Hereinafter, a general active matrix liquid crystal display device will be described with reference to FIG.

FIG. 1 is a block diagram schematically showing a configuration of an active liquid crystal display device. The liquid crystal panel 1 for displaying an image, driving drivers 2 and 4 for driving the image, and the driving drivers 2 and 4 are shown in FIG. And a common voltage section 8 for supplying a common voltage to the liquid crystal panel 1.

The liquid crystal panel 1 includes a liquid crystal cell Clc and a TFT as a switching element at a point where the plurality of gate lines GL1 to GLn and the data lines DL1 to DLm intersect and are arranged in a matrix form, Each of these intersection points is defined as a pixel. In addition, a pixel electrode (not shown) and a common electrode (not shown) for forming an electric field in the liquid crystal cell CLc are provided. The TFT electrically connects the pixel electrode and the data line in response to a gate driving signal input from the gate lines GL1 to GLn.

The driving circuits 2 and 4 are constituted by a gate driver 2 for driving the gate lines GL1 to GLn and a data driver 4 for driving the data lines DL1 to DLm. Here, the gate driver 2 sequentially supplies the gate driving signals Vg to the gate lines GL1 to GLn for one frame so that the liquid crystal cells Clc on the liquid crystal panel 1 are sequentially lined up by one horizontal line. Each time the gate driver signal is supplied, the data driver 4 supplies an image signal to each of the data lines DL1 to DLm to charge the pixel electrode.

The timing controller 6 includes a control signal unit (not shown) for generating a control signal for controlling the gate driver 2 and the data driver 4, a driving method of the liquid crystal panel 1, And a data processing unit (not shown) for generating a video signal in accordance with the structure, and supplies a control signal and a video signal suitable for the data signal inputted from the outside to the driving circuit.

The common voltage section 8 generates a common voltage Vcom, which is a counter voltage with respect to the video signal of the pixel electrode, and supplies the common voltage Vcom to the common electrode on the liquid crystal panel 1.

The liquid crystal display is divided into a line inversion driving method and a column inversion driving method according to the phase of an image signal.

As shown in FIG. 2A, the line inversion driving method is a method of applying a phase of an image signal applied to a signal line in one frame unit so as to be inverted for each line, and the column inversion driving method is shown in FIG. 2B. The video signal is applied so that the phase of the video signal applied to the signal line in one frame unit is inverted for each column.

The liquid crystal display of the line inversion driving method is driven at a low voltage and applies an alternating voltage to the common electrode at intervals of one line of data transmission period (1 horizontal period, 1H), and the polarity of the voltage on a line-by-line basis. Let it be reversed.

As such, the reason for inverting the phase of the image signal in line or column units is that if the voltage difference of the same polarity persists between the pixel electrode and the common electrode, the liquid crystal between the pixel electrode and the common electrode is deteriorated and the image flickers. This is because of the darkening problem.

However, the line inversion driving method has a problem in that there is a crosstalk between the pixels in the horizontal direction, so that flickers such as stripes are generated between the horizontal lines, and the column inversion driving method uses the vertical pixels. There is a problem that flicker occurs between vertical lines due to crosstalk between them.

Accordingly, a dot inversion driving scheme has been proposed to solve this problem. As shown in Fig. 3, the dot inversion driving method causes each pixel to be supplied with an image signal having a polarity opposite to that of all adjacent pixels in the horizontal and vertical directions, and the polarity of the image signal is reversed for each frame. That is, when the video signal of the odd frame is displayed, the video signal is displayed on the pixels such that the positive and negative polarities alternate with each other as the pixel moves from the upper left pixel to the right and lower sides in one frame. When the video signal of the even-numbered frame is displayed, the video signal is alternately displayed so that the negative polarity (-) and the positive polarity (+) appear alternately from the upper left pixel to the lower right in one frame. Supplied to the pixel.

In the above-described dot inversion driving method, flicker generated between the vertical and horizontal directions cancels each other, thereby providing an image having excellent image quality compared to other inversion methods.

However, in the dot inversion driving method, since the polarity of the video signal supplied to the pixel in the data driver must be reversed in the horizontal and vertical directions, the amount of variation of the video signal charged to the pixel electrode is larger than that of other inversion driving methods. This has the disadvantage of getting bigger.

An object of the present invention is to provide a demux at an output terminal of a data driver in a driving device of a liquid crystal display device driven by a line inversion method, thereby driving the liquid crystal panel in a dot inversion method, It is to save big power consumption.

It is still another object of the present invention to provide a driving apparatus for a liquid crystal display device and a driving method thereof, which shorten the charging period of a pixel electrode and stably implement an image.

In order to achieve the above object, in the driving apparatus of the liquid crystal display according to the exemplary embodiment of the present invention, the even-numbered pixel is connected to the upper side of the gate line at a point where a plurality of gate lines and data lines intersect, and the lower side is connected to the lower side. A liquid crystal panel having a plurality of thin film transistors connected to the odd pixel and connected in a zigzag form; A timing controller configured to generate a control signal and a good / excellent data signal to a gate driver and a source driver in response to a drive signal and a data signal input from an external system; A gate driver and a data driver for outputting a gate driving signal corresponding to the control signal and a good / good data signal to the gate line and the data line; A common voltage unit supplying a common voltage to the pixel; And an output line selecting means provided at an output end of the data driver and selecting an odd data line or an even data line of the data lines in response to an output line selection signal of the control signal.

The timing controller includes: a control signal generator for controlling the gate driver and the data driver in response to the driving signal, and a control signal generator for generating an output line selection signal; A data alignment unit which receives the data signal and aligns the even-numbered data signal and the odd-numbered data signal; And a data signal processing unit including temporary storage means for storing the even-th data signal.

The output line selection signal is characterized by having a high level waveform for a half horizontal line period (1 / 2H).

The output line selecting means is characterized by being a 1 × K demultiplexer.

The 1 × K demultiplexer is a 1 × 2 demultiplexer having one input terminal and two output terminals.

The timing controller includes: a control signal generator for controlling the gate driver and the data driver and a first and second output line selection signals in response to the driving signal; A data alignment unit which receives the data signal and aligns the even-numbered data signal and the odd-numbered data signal; A data signal processing unit including temporary storage means for storing the even-th data signal; And a gradation reference unit for supplying an intermediate gradation value of the gradation implemented by the pixel to the data alignment unit.

The intermediate gradation value is characterized in that the 31 gradation value.

The output line selecting means may include a radix transistor that is turned on / off in response to the first output line selection signal and electrically connects the output terminal of the data driver and the odd data line; And an even transistor which is turned on / off corresponding to the second output line selection signal and electrically connects the output terminal of the data driver and the even-numbered data line.

The first and second output line selection signals have a waveform of a high level period of 2/3 horizontal line period (2 / 3H).

Driving method using a driving device of the liquid crystal display device implemented according to the above description,

Generating a control signal corresponding to a drive signal and a data signal input from an external system, an odd / high image signal, and an output line selection signal; Generating a gate driving signal corresponding to the control signal; And corresponding to the output line selection signal, outputting the odd / excellent image signal through the odd / excellent data line.

In the generating of a control signal corresponding to a drive signal and a data signal input from an external system, an excellent / first image signal, and an output line selection signal, the data signal is input to a data alignment unit of the timing controller. Sorting the odd and even data signals; Inputting the even-numbered data signal to the data driver; Storing the odd-numbered data signal in a temporary storage means of the timing controller; And an odd-numbered data signal stored in the temporary storage means is input to the data driver.

In response to the output line selection signal, the outputting of the odd / excellent image signal through the odd / excellent data line may include outputting the odd number when the output line selection signal is input to the output line selection means at a low level. Outputting the first image signal through an odd data line; And when the output line selection signal is input at a high level, the even-numbered image signal is output through the even-numbered data line.

Another type of driving method using a driving device of a liquid crystal display device implemented according to the above description includes a control signal corresponding to a driving signal and a data signal input from an external system, an odd / high image signal, and an intermediate tone value. Generating first and second output line selection signals; Generating a gate driving signal corresponding to the control signal; And corresponding to the first and second output line selection signals, outputting the mid-tone value and the good / excellent image signal through the good / excellent data line.

The control signal corresponding to the drive signal and the data signal input from the external system, the good / high image signal, the mid-gradation value, and the first and second output line selection signals are generated in the mid-gradation unit of the timing controller. Inputting a halftone value from the data alignment unit of the timing controller; Inputting the data signal to the data alignment unit and sorting the odd and even data signals; Inputting the halftone value to the data driver; Inputting the even-numbered data signal to the data driver; Storing the odd-numbered data signal in a temporary storage means of the timing controller; And an odd-numbered data signal stored in the temporary storage means is input to the data driver.

In response to the first and second output line selection signals, outputting the first and second video signals through the first and second data lines may include: outputting the first and second output line selection signals to the output line selection means; Outputting the halftone value when a second output line selection signal is input at a high level; When the first output line selection signal is input at a high level and the second output line selection signal is input at a low level, the odd-numbered image signal is output through the odd-numbered data line, and the even-numbered data line is Entering a floating state; When the first output line selection signal is input at a low level and the second output line selection signal is input at a high level, the odd-numbered data line is in a floating state and the even-numbered image through the even-numbered data line. And outputting a signal.

Hereinafter, a driving apparatus and a driving method thereof of a liquid crystal display according to a first embodiment of the present invention will be described with reference to the accompanying drawings.

4A is a block diagram schematically illustrating a configuration of a liquid crystal display according to an exemplary embodiment of the present invention. The liquid crystal panel 10 displaying an image, driving drivers 20 and 40 for driving the image, and the driving driver ( And a common voltage unit 80 for supplying a common voltage Vcom to the liquid crystal panel 10.

In the liquid crystal panel 10, a plurality of gate lines GL1 to GLn and data lines DL1 to DLm cross each other and are arranged in a matrix form, and a liquid crystal cell Clc and a TFT, which is a switching element, are provided at the crossing points. , Each of these intersections is defined in pixels. Further, a pixel electrode (not shown) and a common electrode (not shown) for forming an electric field in the liquid crystal cell Clc are provided. The TFT electrically connects the pixel electrode and the data lines DL1 to DLm in response to a gate driving signal input from the gate lines GL1 to GLn.

In this case, the TFTs are connected in a zigzag form around the gate lines GL1 to GLn. The uppermost gate line GL1 is electrically connected to the odd-numbered pixels of the lower horizontal line, and the lowermost gate line GLn is electrically connected to the even-numbered pixels of the upper horizontal line. Also, except for the uppermost and lowermost gate lines GL1 and GLn, the remaining gate lines GL2 to GL (n−1) are the even-numbered pixels of the upper horizontal line and the lower side around the corresponding gate line. It is electrically connected to the odd-numbered pixels of the horizontal line. In other words, the liquid crystal panel 10 of a general liquid crystal display device has a structure of controlling pixels arranged in one horizontal line with one gate line, but the liquid crystal panel of the liquid crystal display device according to an embodiment of the present invention has one gate. It is a structure for controlling pixels arranged in two horizontal lines with a line.

The driving circuits 20 and 40 include a gate driver 20 for driving the gate lines GL1 to GLn and a data driver 40 for driving the data lines DL1 to DLm.

Here, the gate driver 20 sequentially supplies the gate driving signals Vg to the gate lines GL1 to GLn for one frame, and thus to the gates GL1 to GLn to which the gate driving signals Vg are supplied. The turn-on / off operation of a pixel electrically connected is controlled, and the data driver 40 applies the image signal Vd to the corresponding data lines DL1 to DLm whenever the gate driving signal Vg is supplied. And charges the pixel electrode electrically connected to the pixel turned on by the gate driver 20.

In addition, an output line selecting means 50 is provided at an output end of the data driver 40 to divide the data lines DL1 to DLm into odd and even numbers, and selectively output an image signal for one horizontal period. It is supposed to.

The common voltage unit 80 generates a common voltage Vcom, which is a voltage opposite to the image signal of the pixel electrode, and supplies the common voltage Vcom to the common electrode on the liquid crystal panel 10.

FIG. 4B is a block diagram schematically showing the configuration of the timing controller 60 in the liquid crystal display according to the embodiment of the present invention shown in FIG. 4A. The timing controller 60 has a gate as shown in FIG. 4B. A control signal unit 61 for generating a control signal for controlling the driver 20 and the data driver 40, and a data processor 62 for generating an image signal according to the driving method and structure of the liquid crystal panel. And a control signal and a video signal corresponding to the drive signal and data signal input from the external system 9 are supplied to the drive circuit.

In addition, the data processing unit 62 includes a data alignment unit 64 for aligning the input data signal according to a setting, and temporary storage means 65 for storing a part of the data signal.

Hereinafter, a driving apparatus and a driving method thereof of a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 4A to 4C.

First, as shown in FIG. 4B, the timing controller 60 receives a signal required for driving the device from the external system 9, and correspondingly, the gate driver 20 and the data driver through the control signal unit 61. Control signals for driving 40 are generated, and the image signal Vd is supplied to the data driver through the data processor 62.

The control signals include a gate output enable signal GOE and a data output enable signal SOE, and further include an output line selection signal VDS.

 When the timing controller 60 describes an operation for one frame of the data processor 62, the data processor 62 includes temporary storage means 65, and the image signal Vd is the odd number (Odd). And Even (Even) is separated first, first even video signal (Even-Vd) is stored in the temporary storage means 65, and the odd video signal (Odd-Vd) is supplied to the data driver 40 . Next, the even-numbered video signal Even-Vd and the next odd-numbered video signal Odd-Vd stored in the temporary storage means 65 are supplied to the data driver 40, and the next even-numbered video signal Even- Vd) is stored in the temporary storage means (65). This operation is repeatedly performed, and when the pixels of the lowermost horizontal line are driven, the even-numbered image signal Even-Vd stored in the temporary storage means 65 is supplied to the data driver 40.

In this form, the video signal Vd is divided into an odd-numbered video signal Odd-Vd and an even-numbered video signal Even-Vd, and are respectively supplied to the data driver 40.

The gate driver 20 receives a control signal from the timing controller 60 and generates a gate driving signal Vg in response to the control signal, which is generated through the corresponding gate line every one horizontal period 1H. Feed sequentially.

The data driver 40 receives an image signal from the timing controller 60, converts the image signal into a form that can be output through a data line, and inverts the polarity every one horizontal period in a line-inversion manner, and then through the data line. Supply to the liquid crystal panel.

)과 우수번째 데이터라인(

)을 통해 교번으로 출력되게 된다.Here, as shown in FIG. 4A, an output line selecting means 50 is provided at an output end of the data driver 40. Preferably, the output line selecting means 50 includes a plurality of 1 × K D. Implemented by Demultiplexer (DEMUX). As shown in FIG. 4A, an example in which an output line selecting means 50 includes a 1 × 2 demux having a K value of 2 is used as an image signal Vd converted through a data driver 40. Corresponds to the output line selection signal VDS among the control signals of the timing controller 60,

) And the first data line (

) Will be displayed alternately.

)으로 영상신호를 출력하며, 하이(High)상태의 출력라인선택신호(VDS)가 디먹스(DEMUX)에 공급될 경우, 우수번째 데이터라인(

)으로 영상 신호를 출력한다. More specifically, the output line selection signal VDS is a signal having a waveform having a half cycle of one horizontal period 1H, as shown in FIG. 4C, and the output line selection signal VDS in a low state. Is supplied to the DEMUX, the DEMUX is a radix data line (

Outputs an image signal, and when the high output line selection signal VDS is supplied to the demux,

) Outputs a video signal.

)을 통해 우수번째(Even) 화소의 TFT와 전기적으로 연결되어 있는 화소전극은 1/2수평라인(1/2H)동안 차징되게 된다. 이후, 상기 출력라인선택신호가 하이(High)상태가 되면, 상기 기수번째 데이터라인(

)을 통해 기수번째(Odd) 화소의 TFT와 전기적으로 연결되어 있는 화소전극은 1/2 수평라인(1/2H)동안 차징되게 된다.Accordingly, the gate driver 20 sequentially outputs the gate driving signal Vg during one horizontal period 1H, and the odd number Odd disposed above the nth gate line Gn corresponding thereto. The TFT of the pixel and the TFT of the even pixel disposed below the n-th gate line Gn are turned on. At the same time, the demux DEMUX provided at the output terminal of the data driver receives the output line selection signal VDS in the low state, and the even-numbered data line (

The pixel electrode electrically connected to the TFT of the even pixel is charged during the 1/2 horizontal line (1 / 2H). Subsequently, when the output line selection signal becomes high, the odd data line (

The pixel electrode electrically connected to the TFT of the odd-numbered pixel is charged during the 1/2 horizontal line (1 / 2H).

In addition, the common voltage unit 80 generates a common voltage Vcom and supplies it to the common electrode disposed to face the pixel electrode of the liquid crystal panel 10. Here, in the liquid crystal display of the line-inversion driving method, the common voltage Vcom is AC driven, so that the common voltage Vcom is changed in polarity every one horizontal period 1H.

Accordingly, the light transmittance of the liquid crystal cell Clc is changed by the voltage difference between the pixel electrode and the common electrode included in the pixel of the liquid crystal panel 10, so that an image corresponding thereto is displayed.

As described above, in the driving apparatus of the liquid crystal display according to the first embodiment of the present invention, the output of the data driver is reduced by 1/2.

In addition, in order to further reduce the output of the data driver, when using a demux having a K value of 3 or more as the 1 × K demux, a data line connected to an output terminal of the demux (DEMUX) Corresponding to DL1 to DLm, it may be processed into three or more Groups.

Hereinafter, a second embodiment in which the charging operation of the pixel electrode is more stably performed in the liquid crystal display of the first embodiment.

In the second embodiment, the configuration of the liquid crystal panel 110, the pixels disposed therein, the gate driver 120 and the data driver 140 driving the same, and the common voltage unit 180 are identical to those of the first embodiment. In addition, the output line selecting means 150 and a signal line for controlling the same as shown in Figure 5a is further provided.

In addition, as shown in FIG. 5B of the timing controller 160, the data alignment unit 164 receives an image signal Vd corresponding to an intermediate value of the maximum gray scale implemented by the liquid crystal panel 110 in the data processing unit 161. A gray reference part 166 is further provided.

More specifically, the operation of one frame of the data processing unit of the timing controller will be described. The data processing unit 162 includes a data alignment unit 164, a temporary storage unit 165, and a gradation reference unit 166. The data signal inputted from the external system 9 is divided into odd number (Odd) and even number (Even), and first, the even number video signal (Even-Vd) is stored in the temporary storage means 165. The odd-numbered video signal Odd-Vd is supplied to the data driver 140. Next, the even-numbered video signal Even-Vd and the next odd-numbered video signal Odd-Vd stored in the temporary storage means 165 are supplied to the data driver, and the next even-numbered video signal Even-Vd is supplied. The temporary storage means 165 is stored. This operation is repeatedly performed, and when the pixels of the lowermost horizontal line are driven, the even-numbered image signal Even-Vd stored in the temporary storage means 165 is supplied to the data driver 140.

In this form, the video signal is divided into an odd-numbered video signal (Odd-Vd) and an even-numbered video signal (Even-Vd) and supplied to the data driver 140, respectively.

Hereinafter, a driving apparatus and a driving method thereof of a liquid crystal display according to a second exemplary embodiment of the present invention will be described with reference to FIGS. 5A to 5C.

The timing controller 160 receives a signal required for driving the device from the external system 9, and correspondingly controls signals for driving the gate driver 120 and the data driver 140 through the control signal unit 161. The image signal Vd is supplied to the data driver 140 through the data processor 162.

The control signals include a gate output enable signal GOE and a data output enable signal SOE, and further include first and second output line selection signals VDS1 and VDS2.

More specifically, the first and second output line selection signals VDS1 and VDS2 generate waveforms of a high level period of 2 / 3H and a low level period of 1 / 3H during one horizontal period 1H. It is a signal.

The gate driver 120 receives a control signal from the timing controller 160 and generates a gate driving signal Vg in response to the control signal, and the gate driver GL1 to GLn corresponding to each horizontal period 1H. It is sequentially supplied to the liquid crystal panel 110 through).

The data driver 140 receives the image signal Vd from the timing controller 160, converts the image signal into a form that can be output through the data lines DL1 to DLm on a horizontal line, and horizontally in a horizontal version. The polarity is inverted at each period and supplied to the liquid crystal panel 110 through the data lines DL1 to DLm.

)과 연결되고 우수트랜지스터(TR-e)의 드레인단은 우수번째 데이터라인(

)과 연결된다.Here, an output line selecting means 150 is provided at an output end of the data driver 140. Preferably, the output line selecting means 150 includes a plurality of odd-numbered transistors TR-o and even-numbered transistors TR. -e). As shown in FIG. 5A, the source terminals of the odd-numbered transistors TR-o and the even-numbered transistors TR-e are electrically connected to the output terminals of the data driver 140 and the drains of the odd-numbered transistors TR-o. Where the radix data line (

) And the drain terminal of the even transistor (TR-e) is the even data line (

).

)과 우수번째 데이터라인(

)을 통해 교번으로 출력되게 된다.Accordingly, the image signal converted by the data driver 140 corresponds to the first and second output line selection signals VDS1 and VDS2 among the control signals of the timing controller.

) And the first data line (

) Will be displayed alternately.

Referring to the operation, the gate driver 120 sequentially outputs the gate driving signal Vg for one horizontal period 1H, and the odd number is disposed above the n-th gate line Gn. The TFT of the (Odd) pixel and the TFT of the even pixel (Even) arranged under the n-th gate line Gn are turned on.

) 및 우수번째 데이터라인(

)을 통해 기수번째(Odd) 화소 및 우수번째(Even) 화소의 TFT와 전기적으로 연결되어 있는 화소전극은 1/3수평라인기간(1/3H)동안 프리차징(Precharging)되게 된다. The output line selecting unit 150 is turned on by receiving the first and second output line selection signals VDS1 and VDS2 having high levels, thereby turning the odd data line (

) And the first best data line (

The pixel electrode electrically connected to the TFTs of the odd and even pixels is precharged for one-third horizontal line period (1 / 3H).

Here, the image signal Vd precharged to the pixel electrode is an intermediate value of the gray level supplied from the timing controller 160. For example, when the pixels are implemented with 6 bits per RGB, one pixel is 64 in total. Since the gradation is displayed, the intermediate gradation value is 31 gradations.

Next, when the first output line selection signal VDS1 maintains a high level and the second output line selection signal reaches a low level, the odd-numbered transistor TR-o is turned on. In this state, the odd (odd) pixel electrode is charged with the odd-numbered image signal (Odd-Vd) input for 1 / 3H.

)은 플로팅(Floating)상태가 되어 차징된 전압을 유지한다.At this time, the even transistor (TR-e) is turned off, the even data line (

) Becomes a floating state to maintain the charged voltage.

Subsequently, when the first output line selection signal VDS1 becomes a low level and the second output line selection signal VDS2 becomes a high level, the even transistor TR-e is turned on. In this state, the even pixel electrode is charged with an even image signal input for 1 / 3H.

)은 플로팅(Floating)상태가 되어 차징된 전압을 유지한다.At this time, the odd transistor TR-o is turned off and the odd data line (

) Becomes a floating state to maintain the charged voltage.

The odd-numbered (Edd) and even-even (Even) pixel electrodes have a charging period of 2 / 3H, respectively, and thus a 1.33 times charging period is secured.

In addition, the common voltage unit 180 generates a common voltage Vcom and supplies it to the common electrode disposed to face the pixel electrode of the liquid crystal panel 110. Here, in the liquid crystal display of the line-inversion driving method, the common voltage Vcom is AC driven, so that the common voltage Vcom is changed in polarity every one horizontal period 1H.

Accordingly, the light transmittance of the liquid crystal cell is changed by the voltage difference between the pixel electrode and the common electrode included in the pixel of the liquid crystal panel 110, so that an image corresponding thereto is displayed.

In addition, in order to further reduce the output of the data driver 140, when the output line selecting means 150 is implemented in the form of being connected to three or more transistors per output of one data driver 140, the image signal (Vd) is It can be processed into three or more groups.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It can be understood that

Therefore, the driving apparatus and the driving method thereof of the liquid crystal display according to the embodiments of the present invention include an output line selecting means, so that one data driver output terminal alternately outputs an image signal at least two or more data lines. The output of the data driver can be reduced.

Further, according to the configuration of the output line selecting means, the charging of the pixel electrode can be further secured by precharging the pixel electrode, so that the pixel electrode can be charged stably.

Claims (15)

A liquid crystal panel having a plurality of thin film transistors connected in a zigzag form by connecting even-numbered pixels to an upper side and a radix-numbered pixel to a lower side at a point where a plurality of gate lines and data lines cross each other. and; A timing controller configured to generate a control signal and a good / excellent data signal to a gate driver and a source driver in response to a drive signal and a data signal input from an external system; A gate driver and a data driver for outputting a gate driving signal corresponding to the control signal and a good / good data signal to the gate line and the data line; A common voltage unit supplying a common voltage to the pixel; Output line selecting means provided at an output end of the data driver and selecting an odd data line or an even data line of the data lines in response to an output line selection signal of the control signal; / RTI &gt; And the output line selecting means is a 1 × K demultiplexer. The method according to claim 1, The timing controller includes: a control signal generator for controlling the gate driver and the data driver in response to the driving signal, and a control signal generator for generating an output line selection signal; A data alignment unit which receives the data signal and aligns the even-numbered data signal and the odd-numbered data signal; And a data signal processor having a temporary storage means for storing the even-th data signal. 3. The method of claim 2, And the output line selection signal has a high level waveform during a 1/2 horizontal line period (1 / 2H). delete The method of claim 1, The 1 × K demultiplexer is a 1 × 2 demultiplexer having one input terminal and two output terminals, wherein the 1 × K demultiplexer is a 1 × 2 demultiplexer. The method according to claim 1, The timing controller includes: a control signal generator for controlling the gate driver and the data driver and a first and second output line selection signals in response to the driving signal; A data alignment unit which receives the data signal and aligns the even-numbered data signal and the odd-numbered data signal; A data signal processing unit including temporary storage means for storing the even-th data signal; A gradation reference unit for supplying an intermediate gradation value of the gradation implemented by the pixel to the data alignment unit; Driving device of the liquid crystal display device comprising a. The method according to claim 6, And the intermediate gradation value is 31 gradation value. The method according to claim 6, The output line selecting means may include a radix transistor that is turned on / off in response to the first output line selection signal and electrically connects the output terminal of the data driver and the odd data line; And an even transistor which is turned on / off in response to the second output line selection signal and electrically connects the output terminal of the data driver and the even-numbered data line. The method according to claim 6, And the first and second output line selection signals have a waveform in a high level period of 2/3 horizontal line periods (2 / 3H). A driving method using a driving device of a liquid crystal display device implemented according to claim 1 or 2, Generating a control signal corresponding to a drive signal and a data signal input from an external system, an odd / high image signal, and an output line selection signal; Generating a gate driving signal corresponding to the control signal; In response to the output line selection signal, outputting the odd / excellent image signal through the odd / excellent data line; Driving device driving method of the liquid crystal display device comprising a. The method of claim 10, A control signal corresponding to a drive signal and a data signal input from an external system, an excellent / first image signal, and an output line selection signal may be generated. Inputting the data signal to a data alignment unit of the timing controller and sorting the odd and even data signals; Inputting the even-numbered data signal to the data driver; Storing the odd-numbered data signal in a temporary storage means of the timing controller; Inputting an odd data signal stored in the temporary storage means into the data driver; Driving device driving method of the liquid crystal display device comprising a. The method of claim 10, In response to the output line selection signal, the step of outputting the good / excellent video signal through the good / even data line, To the output line selection means, Outputting the odd-numbered video signal through an odd-numbered data line when the output line selection signal is input at a low level;  In response to the output line selection signal being input at a high level, outputting the even-numbered video signal through the even-numbered data line; Driving device driving method of the liquid crystal display device comprising a. A driving method using a driving apparatus of a liquid crystal display device implemented according to any one of claims 1, 6 and 8, Generating a control signal corresponding to a drive signal and a data signal input from an external system, an odd / high image signal, a half-tone value, and a first and second output line selection signal; Generating a gate driving signal corresponding to the control signal; In response to the first and second output line selection signals, outputting the halftone value and the good / excellent image signal through the good / excellent data line; Driving device driving method of the liquid crystal display device comprising a. 14. The method of claim 13, A control signal corresponding to a drive signal and a data signal input from an external system, an excellent / first image signal, a half gray level value, and a first and second output line selection signals may be generated. Inputting an intermediate gray level value from the intermediate gray level unit of the timing controller to a data alignment unit of the timing controller; Inputting the data signal to the data alignment unit and sorting the odd and even data signals; Inputting the halftone value to the data driver; Inputting the even-numbered data signal to the data driver; Storing the odd-numbered data signal in a temporary storage means of the timing controller; Inputting an odd data signal stored in the temporary storage means into the data driver; Driving device driving method of the liquid crystal display device comprising a. 14. The method of claim 13, In response to the first and second output line selection signals, the step of outputting the first and second video signals through the first and second data lines may include: To the output line selection means, Outputting the halftone value when the first output line selection signal and the second output line selection signal are input at a high level; When the first output line selection signal is input at a high level and the second output line selection signal is input at a low level, the odd-numbered image signal is output through the odd-numbered data line, and the even-numbered data line is Entering a floating state; When the first output line selection signal is input at a low level and the second output line selection signal is input at a high level, the odd-numbered data line is in a floating state and the even-numbered image through the even-numbered data line. Outputting a signal; Driving device driving method of the liquid crystal display device comprising a.

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