KR20030038332A - Data driving apparatus and method for liquid crystal display - Google Patents

Abstract

PURPOSE: A data driving device of an LCD and a method thereof are provided to reduce the number of data drives and fabrication costs and prevent a flickering phenomenon by performing a time-sharing driving process for data lines. CONSTITUTION: A shift register array(42) is used for supplying a sampling signal. The first and the second latch arrays(46,50) are used for latching pixel data according to the sampling signal. The first MUX array(54) is used for outputting the pixel data of the second latch array(50) according to a time-sharing method. The second MUX array(58) is used for controlling a processing path of the pixel data. A DAC array(62) is used for converting the pixel data to pixel voltage signals. A buffer array(68) is used for buffering the pixel voltage signals. The third MUX array(80) is used for controlling a progressing path of the output of the buffer array(68). A DEMUX array(84) is used for outputting the pixel voltage signals according to the time-sharing method.

Description

DATA DRIVING APPARATUS AND METHOD FOR LIQUID CRYSTAL DISPLAY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a data driving device and a method of a liquid crystal display device capable of reducing the number of data drive integrated circuits by time division driving of data lines.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a data driving device and a method of a liquid crystal display device capable of time-divisionally driving data lines, thereby improving data display quality while reducing data drive integrated circuits.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in an active matrix, and a driving circuit for driving the liquid crystal panel.

In fact, the liquid crystal display device includes data drive integrated circuits (ICs) 4 connected to the liquid crystal panel 2 through the data TCP (Tape Carrier Pakage) 6 and a gate TCP 10 as shown in FIG. 1. Gate drive ICs 8 connected to the liquid crystal panel 2 through the < RTI ID = 0.0 >

The liquid crystal panel 2 includes a thin film transistor formed at each intersection of the gate lines and the data lines, and a liquid crystal cell connected to the thin film transistor. The gate electrode of the thin film transistor is connected to one of the gate lines in the horizontal line unit, and the source electrode is connected to any one of the data lines in the vertical line unit. The thin film transistor supplies the pixel voltage signal from the data line to the liquid crystal cell in response to the scan signal from the gate line. The liquid crystal cell includes a pixel electrode connected to the drain electrode of the thin film transistor, and a common electrode facing the pixel electrode and the liquid crystal therebetween. The liquid crystal cell controls the light transmittance by driving the liquid crystal in response to the pixel voltage signal supplied to the pixel electrode.

Each of the gate drive ICs 8 is mounted on each of the gate TCP 10. The gate drive IC 8 mounted on the gate TCP 10 is electrically connected to the gate pads of the liquid crystal panel 2 through the gate TCP 10. The gate drive ICs 8 sequentially drive the gate lines of the liquid crystal panel 2 in units of one horizontal period (1H).

Each of the data drive ICs 4 is mounted on each of the data TCP 6. The data drive IC 4 mounted on the data TCP 6 is electrically connected to the data pads of the liquid crystal panel 2 via the data TCP 6. The data drive ICs 4 convert the digital pixel data into analog pixel voltage signals and supply the digital pixel data to the data lines of the liquid crystal panel 2 in units of one horizontal period (1H).

To this end, each of the data drive ICs 4 includes a shift register array 12 for supplying a sequential sampling signal as shown in FIG. 2, and first and second latching and outputting pixel data in response to the sampling signal. A second latch array 16, 18, a first multiplexer 15 disposed between the first and second latch arrays 16, 18, and a second latch array 18. A digital-to-analog conversion (hereinafter referred to as DAC) array 20 for converting pixel data from the data into a pixel voltage signal, a buffer array 26 for buffering and outputting the pixel voltage signal from the DAC array 20; A second MUX array 30 is provided to select a progress path of the buffer array 26 output. The data drive IC 4 further includes a data register 34 for relaying pixel data R, G, and B supplied from a timing controller (not shown), positive polarity required by the DAC array 20, and the like. A gamma voltage unit 36 for supplying negative gamma voltages is further provided.

Each of the data drive ICs 4 having such a configuration has a data output of n channels (for example, 384 or 480 channels) for driving n data lines. Of these n-channels of the data drive IC 4, FIG. 2 shows only the six-channel D1 to D6 portions.

The data register 34 relays pixel data from the timing controller to supply the first latch array 16. In particular, the timing controller divides the pixel data into even pixel data RGBeven and odd pixel data RGBodd to supply the data register 34 through each transmission line to reduce the transmission frequency. The data register 34 outputs the input even pixel data RGBeven and the odd pixel data RGBodd to the first latch array 16 through respective transmission lines. The even pixel data RGBeven and the odd pixel data RGBodd each include red (R), green (G), and blue (B) pixel data.

The gamma voltage unit 36 subdivides and outputs a plurality of gamma reference voltages inputted from a gamma reference voltage generator (not shown) for each gray.

The shift register array 12 generates sequential sampling signals and supplies them to the first latch array 16, and includes n / 6 shift registers 14 for this purpose. The shift register 14 of the first stage shown in FIG. 2 shifts the source start pulse SSP input from the timing controller according to the source sampling clock signal SSC and outputs it as a sampling signal. 14) as a carry signal CAR. As shown in FIGS. 3A and 3B, the source start pulse SSP is supplied in units of one horizontal period 1H, shifted for each source sampling clock signal SSC, and output as a sampling signal.

The first latch array 16 samples and latches pixel data RGBeven and RGBodd from the data register 34 by a predetermined unit in response to a sampling signal from the shift register array 12. The first latch array 16 is composed of n first latches 13 to latch n pixel data R, G, and B, and each of the first latches 13 includes pixel data R. FIG. , G, B) has a size corresponding to the number of bits (3 bits or 6 bits). The first latch array 16 samples and latches even-numbered pixel data RGBeven and odd-numbered pixel data RGBodd, that is, six pixel data for each sampling signal, and outputs the same.

The first MUX array 15 determines the progress path of the pixel data R, G, and B supplied from the first latch array 16 in response to the polarity control signal POL from the timing control. To this end, the first MUX array 15 includes n−1 first MUXs 17. Each of the first MUXs 17 inputs two adjacent first latch 13 outputs and selectively outputs the outputs according to the polarity control signal POL. Here, the outputs of each of the first latches 13 except for the first and last first latches 13 are shared and input to two adjacent first MUXs 17. The outputs of the first and last first latches 13 are shared and input to the second latch array 18 and the first MUX 17. In the first MUX array 15 having such a configuration, the pixel data R, G, and B from each of the first latches 13 proceed to the second latch unit 18 in accordance with the polarity control signal POL. In order to control it, or to shift to the right by one space, the control proceeds to the second latch unit 18. As shown in Figs. 3A and 3B, the polarity control signal POL is inverted in polarity every one horizontal period 1H. As a result, the first MUX array 15 has a DAC via the second latch array 18 in which each of the pixel data R, G, and B from the first latch array 16 responds to the polarity control signal POL. The polarities of the pixel data R, G, and B are controlled by being output to the P (Positive) DAC 22 or the N (Negative) DAC 24 of the array 20.

The second latch array 18 receives the pixel data R, G, and B inputted from the first latch array 16 via the first MUX array 15 from the timing controller to the source output enable signal SOE. In response to this, the latch is output at the same time. In particular, the second latch array 18 includes n + 1 second latches 19 in consideration of the case where the pixel data R, G, and B from the first latch array 16 are write-shifted and input. do. The source output enable signal SOE is generated in units of one horizontal period 1H as shown in FIGS. 3A and 3B. The second latch array 18 simultaneously latches pixel data R, G, and B input at the rising edge of the source output enable signal SOE and outputs the same at the falling edge.

The DAC array 20 uses the pixel data R, G, and B from the second latch array 18 to convert the pixels using the positive and negative gamma voltages GH and GL from the gamma voltage unit 36. The voltage signal is converted and output. To this end, the DAC array 20 includes n + 1 PDACs 22 and NDACs 24, and the PDACs 22 and NDACs 24 are alternately arranged side by side for dot inversion driving. The PDAC 22 converts the pixel data R, G, and B from the second latch array 18 into the positive pixel voltage signal using the positive gamma voltages GH. The NDAC 24 converts the pixel data R, G, and B from the second latch array 18 into a negative pixel voltage signal using the negative gamma voltages GL.

Each of the n + 1 buffers 28 included in the buffer array 26 signals-buffers and outputs a pixel voltage signal output from each of the PDAC 22 and the NDAC 24 of the DAC array 20.

The second MUX array 30 determines the progress path of the pixel voltage signal supplied from the buffer array 26 in response to the polarity control signal POL from the timing control. To this end, the second MUX array 30 has n second MUXs 32. Each of the second MUXs 32 selects one output of two adjacent buffers 28 in response to the polarity control signal POL and outputs the output to the corresponding data line D. FIG. Here, the output terminals of the remaining buffers 28 except for the first last buffer 28 are shared and input to two adjacent second MUXs 32. In the second MUX array 30 having the above configuration, in response to the polarity control signal POL, the pixel voltage signals from each of the buffers 28 except for the last buffer 28 remain unchanged with the data lines D1 to D6. One-to-one correspondence is output. In addition, in response to the polarity control signal POL, the second MUX array 30 shifts the pixel voltage signal from each of the remaining buffers 28 except for the first buffer 28 by one space to the left, thereby shifting the data lines D1 to 1. D6) and one-to-one correspondence to output. As shown in FIGS. 3A and 3B, the polarity control signal POL is inverted in polarity every one horizontal period 1H, as is supplied to the first MUX array 15. As described above, the second MUX array 30 determines the polarity of the pixel voltage signals supplied to the data lines D1 to D6 in response to the polarity control signal POL together with the first MUX array 15. As a result, the pixel voltage signal supplied to each of the data lines D1 to D6 through the second MUX array 30 has a polarity opposite to that of the adjacent pixel voltage signals. In other words, as illustrated in FIGS. 3A and 3B, the pixel voltage signal output to odd data lines Dodd such as DL1, DL3, DL5, and the like and the even data lines Deeven of DL2, DL4, DL6, etc. are output. The pixel voltage signals to be provided have polarities opposite to each other. The polarities of the odd data lines Dodd and the even data lines Deven are inverted every one horizontal period 1H in which the gate lines GL1, GL2, GL3, ... are sequentially driven, and the frame It will be reversed in units.

As such, each of the conventional data drive ICs 4 must include n + 1 DACs and buffers to drive n data lines. As a result, the conventional data drive ICs 4 have disadvantages of complicated construction and relatively high manufacturing cost.

Accordingly, it is an object of the present invention to provide a data driving apparatus and method for a liquid crystal display device capable of time-divisionally driving data lines to reduce the number of data drive ICs.

Another object of the present invention is to provide a data driving apparatus and method of a liquid crystal display device capable of compensating for a difference in pixel voltage charge due to a difference in pixel voltage charge time when time-division driving data lines.

1 is a view schematically showing a configuration of a conventional liquid crystal display device.

FIG. 2 is a block diagram showing the detailed configuration of the data drive IC shown in FIG.

3A and 3B are odd frame and even frame drive waveform diagrams of the data drive IC shown in FIG.

4 is a block diagram showing the configuration of a data drive IC according to an embodiment of the present invention.

5A and 5B are odd frame and even frame drive waveform diagrams of the data drive IC shown in FIG.

Fig. 6 is a data flow diagram in the data drive IC shown in Fig. 4 when the polarity control signal is low.

Fig. 7 is a data flow chart in the data drive IC shown in Fig. 4 when the polarity control signal is high.

8 is a block diagram showing the configuration of a data drive IC according to another embodiment of the present invention.

9A and 9B are driving waveform diagrams of the data register section shown in Fig. 8;

10A and 10B are odd frame and even frame drive waveform diagrams of the data drive IC shown in FIG. 8;

Fig. 11 is a data flow chart in the data drive IC shown in Fig. 8 when the polarity control signal is low.

Fig. 12 is a data flow chart in the data drive IC shown in Fig. 8 when the polarity control signal is high.

FIG. 13 is a diagram schematically showing a configuration of a liquid crystal display device to which the data drive ICs shown in FIGS. 4 and 8 are applied.

14A and 14B are signal waveform diagrams for driving by changing the charging order in units of frames when time division of data lines driven in a dot inversion scheme;

15A and 15B are signal waveform diagrams for driving by changing the charging order in line units and frame units when time division of data lines driven in a dot inversion scheme;

16A and 16B are signal waveform diagrams for driving by changing the charging order in line units and frame units when time division of data lines driven in a column inversion scheme;

<Description of main parts of drawing>

2, 72: liquid crystal panel 4, 74: data drive IC

6, 76: data TCP 8, 78: gate drive IC

10, 80: gate TCP 12, 42, 102: sheet register array

13, 48, 108: first latch 14, 44, 104: shifter register

15, 54, 114: first MUX array

17, 56, and 116: first mux

16, 46, 106: first latch array 18, 50, 110: second latch array

19, 52, 112: second latch 20, 62, 122: DAC array

22, 64, 124: PDAC 24, 66, 126: NDAC

26, 68, 128: buffer array 28, 70, 130: buffer

30, 58, 140: second MUX array

32, 60, 142: second mux

34, 88, 148: data register section 36, 90, 150: gamma voltage section

80: third MUX array 82: third MUX

84, 146: DEMUX array 86, 144: DEMUX

In order to achieve the above object, the data driving device of the liquid crystal display according to the present invention comprises: a first multiplexer array for time-divisionally supplying input pixel data; A digital-analog conversion array for converting time division pixel data into a pixel voltage signal; And a demultiplexer array for time-dividing the data lines to supply the pixel voltage signal.

A shift register array for sequentially generating sampling signals; A latch array for sequentially latching pixel data in predetermined units in response to a sampling signal and simultaneously outputting the pixel data to the first multiplexer array; And a buffer array for buffering the pixel voltage signal and supplying the pixel voltage signal to the demultiplexer array.

Here, the first multiplexer array includes at least n (n is an integer) multiplexer to supply a plurality of input pixel data by time-division by at least n, and the digital-analog conversion array converts the time-divided pixel data by n into a pixel voltage signal. The demultiplexer array includes at least n demultiplexers to time-division a plurality of data lines at least n times to supply pixel voltage signals.

The digital-analog conversion array includes at least n + 1 positive and negative digital-to-analog converters for converting at least n time-division pixel data into a pixel voltage signal, and includes a positive digital to analog converter and a negative digital. The analog converters are arranged alternately.

In addition, the data driving apparatus of the present invention determines the progress path of the pixel data time-divided by at least n pieces in response to the input polarity control signal so that at least n positive polarities of at least n + 1 positive and negative digital-to-analog converters and A second multiplexer array for input to the negative digital-analog converter; And a third multiplexer array configured to determine a progress path of at least n pixel voltage signals in response to the polarity control signal and to input the demultiplexer array.

Here, the second multiplexer array has at least n-1 second multiplexers for selecting any one of the outputs of at least two first multiplexers, and the third multiplexer array has any of the outputs of at least two digital-to-analog converters. Having at least n third multiplexers to select one, the output of each of the first multiplexers is shared as an input of at least two second multiplexers, the output of each of the digital to analog converters being of at least two third multiplexers It is characterized by being shared as an input.

The odd-numbered multiplexer of the at least n first multiplexers time-divisions even-numbered pixel data in response to the input first selection control signal, and the even-numbered multiplexer outputs the even-numbered pixel data in response to the input second selection control signal. It is characterized by.

The odd-numbered demultiplexer of the at least n demultiplexers time-divisionally drives odd-numbered data lines in response to a first selection control signal, and an even-numbered demultiplexer performs time-division driving of even-numbered data lines in response to the second selection control signal. .

The first and second selection control signals have logic states that are opposite to each other, and the logic states are inverted at least every 1/2 horizontal period.

The polarity control signal is characterized in that the logic state is reversed every at least one horizontal period.

The first multiplexer array and the demultiplexer array may alternately supply the time-divided pixel data and the pixel voltage signal in order of alteration in response to the first and second selection control signals.

The first multiplexer array and the demultiplexer array change the supply order of time-divided pixel data and pixel voltage signals in response to at least frame units in response to the first and second selection control signals.

The first multiplexer array and the demultiplexer array change the supply order of time-division pixel data and pixel voltage signals in response to at least one line unit in response to the first and second selection control signals.

The first multiplexer array and the demultiplexer array change the supply order of time-division pixel data and pixel voltage signals in response to at least one line and frame unit in response to the first and second selection control signals.

On the other hand, the data driving device of the present invention comprises: a data register unit for rearranging input pixel data and outputting the first multiplexer array; And a second multiplexer array configured to determine a propagation path of at least n pixel voltage signals output from the digital-analog conversion array in response to the polarity control signal and to input the demultiplexer array.

Here, the data register unit may rearrange the input pixel data by exchanging 4k-3 (k is a positive integer) th pixel data and 4k-2 th pixel data among them.

The data register unit outputs the rearranged pixel data to the first multiplexer array in the first horizontal period, and outputs the rearranged pixel data to the first multiplexer array by delaying the rearranged pixel data by two channels in the first horizontal period. Characterized in that the horizontal period is alternated.

The second multiplexer array has at least n second multiplexers for selecting any one of at least two outputs of the positive and negative digital-to-analog converters, and outputs of each of the positive and negative digital-to-analog converters. Is shared as input of the at least two second multiplexers.

The odd-numbered multiplexer of the at least n first multiplexers may time-divided the odd-numbered pixel data and the even-numbered multiplexer outputs the even-numbered pixel data in response to the input selection control signal.

The odd-numbered demultiplexer of the at least n demultiplexers may drive the odd-numbered data lines and the even-numbered demultiplexer time-divisionally divide the even-numbered data lines in response to the selection control signal.

The selection control signal is characterized in that its logic state is inverted at least every 1/2 horizontal period.

The polarity control signal is characterized in that the logic state is reversed every one horizontal period.

The first multiplexer array and the demultiplexer array may alternately supply a supply sequence of the time-division pixel data and the pixel voltage signal in response to the selection control signal for each specific unit.

The first multiplexer array and the demultiplexer array change the supply order of the time-division pixel data and the pixel voltage signal in at least a frame unit in response to the selection control signal.

The first multiplexer array and the demultiplexer array change the supply order of the time-divided pixel data and the pixel voltage signal in at least one line unit in response to the selection control signal.

The first multiplexer array and the demultiplexer array change the supply order of the time-division pixel data and the pixel voltage signal in at least one line unit and frame unit in response to the selection control signal.

The digital-analog conversion array converts adjacent pixel data into pixel voltage signals having opposite polarities in response to an input polarity control signal.

A data driving method of a liquid crystal display according to the present invention comprises the steps of: time-splitting input pixel data; Converting the pixel data into a pixel voltage signal; Time-division driving data lines to supply the pixel voltage signal.

And sequentially generating sampling signals; Sequentially latching and simultaneously supplying the pixel data in predetermined units in response to the sampling signal before the time division of the pixel data; And buffering the pixel voltage signal prior to time division of the data lines.

The converting of the pixel voltage signal may include converting each of the pixel data into a pixel voltage signal having a different polarity from adjacent pixel data.

Determining an input path for inputting time-division-divided pixel data alternately arranged in response to an input polarity control signal to the positive and negative digital-to-analog converters arranged in response to an input polarity control signal; And converting the pixel voltage signal to an output path of the pixel voltage signal in response to the polarity control signal after converting the signal to a signal.

The polarity control signal is characterized in that the logic state is reversed every at least one horizontal period.

The time-division of the pixel data may include dividing the pixel data into odd-numbered multiplexers in response to an input first selection control signal and an even-numbered multiplexer in response to an input second selection control signal. And time division of even-numbered pixel data.

The time-division driving of the data lines may include an odd-numbered demultiplexer of odd-numbered data lines in response to the first selection control signal and an even-numbered demultiplexer in response to the second selection control signal. Time-division driving of the data lines.

The first and second selection control signals have logic states that are opposite to each other, and the logic states are inverted at least every 1/2 horizontal period.

Altering the supply order of the time-divided pixel data alternately for each specific unit in time-dividing the pixel data, and alternatingly changing the supply order of the pixel voltage signals for each specific unit in the time-division driving of the data lines. It is characterized by.

The order of supplying the time-division pixel data and the pixel voltage signal is alternately changed at least in units of frames in response to the first and second selection control signals.

The order of supplying the time-division pixel data and the pixel voltage signal is changed in at least one line unit in response to the first and first selection control signals.

The order of supplying the time-division pixel data and the pixel voltage signal is changed in at least one line unit and frame unit in response to the first and first selection control signals.

On the other hand, the data driving method of the present invention comprises the steps of rearranging the input pixel data before the time division of the pixel data; And converting the pixel voltage signal to an output path of the pixel voltage signal in response to an input polarity control signal after the conversion to the pixel voltage signal.

The reordering of the data may be performed by rearranging the input pixel data by exchanging 4k-3 (k is a positive integer) pixel data and 4k-2 pixel data among them.

The rearranged pixel data are output in a first horizontal period, and the rearranged pixel data are delayed and output by two channels in a second horizontal period, and the first and second horizontal periods are alternated.

The time-dividing of the pixel data may include the step of dividing the pixel data into odd-numbered pixel data and an even-numbered multiplexer among the at least n multiplexers in response to an input selection control signal. It is done.

The time-division driving of the data lines may be performed by time-dividing the odd-numbered data lines by the odd-numbered demultiplexer and the even-numbered de-multiplexer by time-dividing the even-numbered data lines in response to the selection control signal.

The selection control signal is characterized in that its logic state is inverted at least every 1/2 horizontal period.

In the step of time-dividing the pixel data, the supply order of the time-divided pixel data is alternately changed for each specific unit in response to the selection control signal, and the supply order of the pixel voltage signals is selected in the time-division driving of the data lines. In response to the control signal it is characterized in that the alternating for each specific unit alternately.

The order of supplying the time-division pixel data and the pixel voltage signal is alternately changed at least in frame units in response to the selection control signal.

The order of supplying the time-division pixel data and the pixel voltage signal is changed in at least one line unit in response to the selection control signal.

The order of supplying the time-division pixel data and the pixel voltage signal is changed in at least one line unit and frame unit in response to the selection control signal.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 4 to 16B.

4 is a block diagram showing the configuration of a data drive IC of a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 5A and 5B are driving waveforms of odd and even frames by the data drive IC shown in FIG. 4. It is also.

The data drive IC shown in FIG. 4 includes a shift register array 42 for supplying a sequential sampling signal, and first and second latch arrays for latching and outputting pixel data R, G, and B in response to the sampling signal. (46, 50), the first MUX array 54 for time-divisionally outputting the pixel data (R, G, B) from the second latch array 50, and the first MUX array 54 A second MUX array 58 that controls the progress path of the pixel data R, G, and B, and a DAC that converts the pixel data R, G, and B from the second MUX array 58 into a pixel voltage signal. An array 62, a buffer array 68 for buffering and outputting pixel voltage signals from the DAC array 62, a third MUX array 80 for controlling the progress path of the output of the buffer array 68, and And a DEMUX array 84 for time division and outputting pixel voltage signals from the three MUX arrays 80 to the data lines D1 to D12. In addition, the data drive IC shown in FIG. 4 includes a data register 88 for relaying pixel data R, G, and B supplied from a timing control unit (not shown), and the data required by the DAC array 62. A gamma voltage unit 90 is further provided to supply polarity and negative gamma voltages.

The data drive IC having such a configuration uses n + 1 DACs 64 and 66 and buffers 70 by time-division driving the DAC array 62 using the first MUX array 54 and the DEMUX array 84. As a result, 2n data lines twice as much as the conventional ones are driven. The data drive IC has a data output of 2n channels to drive 2n data lines. However, in FIG. 4, only 12 channels (D1 to D12) are shown assuming n = 6.

The data register unit 88 relays the pixel data from the timing controller to supply the first latch array 46. In particular, the timing controller divides the pixel data into even pixel data RGBeven and odd pixel data RGBodd so as to reduce the transmission frequency and supplies the pixel data to the data register 88 through each transmission line. The data register 88 outputs the input even pixel data RGBeven and the odd pixel data RGBodd to the first latch array 46 through respective transmission lines. The even pixel data RGBeven and the odd pixel data RGBodd each include red (R), green (G), and blue (B) pixel data.

The gamma voltage unit 90 subdivides and outputs a plurality of gamma reference voltages inputted from a gamma reference voltage generator (not shown) for each gray.

The shift register array 42 generates a sequential sampling signal and supplies it to the first latch array 46, and includes 2n / 6 (here, n = 6) shift registers 44 for this purpose. The shift register 44 of the first stage shown in FIG. 4 shifts the source start pulse SSP input from the timing controller according to the source sampling clock signal SSC and outputs it as a sampling signal. 44 is supplied as a carry signal CAR. As shown in FIGS. 5A and 5B, the source start pulse SSP is supplied in units of horizontal periods, shifted for each source sampling clock signal SSC, and output as a sampling signal.

The first latch array 46 samples and latches pixel data RGBeven and RGBodd from the data register 88 by a predetermined unit in response to a sampling signal from the shift register array 42. The first latch array 46 is composed of 2n first latches 48 to latch 2n (where n = 6) pixel data R, G, and B, and the first latches 48 ) Each has a size corresponding to the number of bits (3 or 6 bits) of the pixel data R, G, and B. The first latch array 46 has the even pixel data RGBeven and the odd pixel for each sampling signal. The data RGBodd, that is, six pixel data are sampled, latched, and output simultaneously.

The second latch array 50 simultaneously latches and outputs the pixel data R, G, and B from the first latch array 46 in response to the source output enable signal SOE from the timing controller. The second latch array 50 has 2n (where n = 6) second latches 52 in the same manner as the first latch array 46. The source output enable signal SOE is generated in units of horizontal periods as shown in FIGS. 5A and 5B.

The first MUX array 54 receives 2n (where n = 6) pixel data from the second latch array 50 in response to the first and second selection control signals Θ1 and Θ2 from the timing controller. Time-division output by n units by 2 period. To this end, the first MUX array 54 is composed of n first MUXs 56. Each of the first MUXs 56 selects and outputs one of two second latches 52 in the second latch array 50. In other words, each of the first MUXs 56 supplies the outputs of the two second latches 52 in half horizontal periods.

In detail, for the dot inversion driving, the odd first MUX 56 selects and outputs any one of the outputs of the two odd second latches 52 in response to the first selection control signal Θ1. The even-numbered first MUX 56 selects and outputs any one of the outputs of the two even-numbered second latches 52 in response to the second selection control signal Θ2.

For example, the first first MUX 56 selects and outputs the first pixel data from the first second latch 52 in the first half of one horizontal period in response to the first selection control signal Θ1, and in the second half. The third pixel data from the third second latch 52 is selected and output. The second first MUX 56 selects and outputs the second pixel data from the second second latch 52 in the first half of the horizontal period in response to the second selection control signal Θ2, and the fourth second latch in the second half. The fourth pixel data from 52 is selected and output. The first and second selection control signals Θ1 and Θ2 have polarities opposite to each other, as shown in FIGS. 5A and 5B, and the polarities are inverted in units of horizontal periods.

The second MUX array 58 determines the progress path of the pixel data R, G, and B supplied from the first MUX array 54 in response to the polarity control signal POL from the polarity controller 92. . To this end, the second MUX array 54 includes n−1 second MUXs 60. Each of the second MUXs 60 inputs two adjacent first MUX 56 outputs to selectively output the second MUXs 60 according to the polarity control signal POL. Here, the outputs of each of the first MUXs 56 except for the first and last first MUXs 56 are shared and input to two adjacent second MUXs 60. The outputs of the first and last first MUXs 56 are shared and input to the PDAC 66 and the second MUX 60. The second MUX array 58 having such a configuration controls the pixel data R, G, and B from each of the first MUXs 56 to proceed to the DAC array 62 according to the polarity control signal POL. Or shifted one by one to the right to control the DAC array 62 to proceed. For the dot inversion driving, the polarity control signal POL is polarized inverted in each horizontal period as shown in FIGS. 5A and 5B. As a result, the second MUX array 58 includes the PDACs in which the pixel data R, G, and B from the first MUX array 54 are alternately arranged in the DAC array 62 in response to the polarity control signal POL. 64) or the NDAC 66 to control the polarity of the pixel data (R, G, B).

For example, the first and third pixel data sequentially output from the first first MUX 56 in the first horizontal period are supplied directly to the PDAC1 66 without passing through the second MUX 60, and the second second data. The second and fourth pixel data sequentially output from the first MUX 56 are supplied to the NDAC1 64 by the first second MUX 60. In the second horizontal period, the first and third pixel data are supplied to the NDAC1 64 by the first second MUX 60, and the second and fourth pixel data are supplied by the PDAC2 by the second second MUX 60. Supplied to (66).

The DAC array 62 uses the pixel data R, G, and B from the second MUX array 58 to convert the pixels using the positive and negative gamma voltages GH and GL from the gamma voltage unit 90. The voltage signal is converted and output. To this end, the DAC array 62 includes n + 1 PDACs 66 and NDACs 64, and the PDACs 66 and NDACs 64 are alternately arranged side by side for dot inversion driving. The PDAC 66 converts the pixel data R, G, and B from the second MUX array 58 into a positive pixel voltage signal using the positive gamma voltages GH. The NDAC 64 converts the pixel data R, G, and B from the second MUX array 18 into a negative pixel voltage signal using the negative gamma voltages GL. The PDAC 66 and the NDAC 64 perform an operation of converting digital pixel data input every 1/2 horizontal period into an analog pixel voltage signal.

For example, the PDAC1 66 converts and outputs the odd pixel data [1,1] and [1,3], which are time-divided and input in the first horizontal period, into pixel voltage signals as shown in FIGS. 5A and 5B. do. At the same time, the NDAC2 64 also converts the even pixel data [1, 2] and [1, 4], which are time-divided and input in each of the first horizontal periods, as shown in FIGS. 5A and 5B, and outputs the pixel voltage signals. . Next, in the second horizontal period, the NDAC2 64 converts the odd pixel data [2, 1] and [2, 3] inputted by time division into a pixel voltage signal and outputs it. At the same time, the PDAC2 66 converts the even pixel data [2, 2] and [2, 4], which are time-divided and input in the second horizontal period, into a pixel voltage signal and outputs them. By this DAC array 62, 2n pixel data are time-divided n times in units of 1/2 horizontal period, converted into pixel voltage signals, and output.

Each of the n + 1 buffers 70 included in the buffer array 68 is signal-buffered and outputs a pixel voltage signal output from each of the PDAC 66 and the NDAC 64 of the DAC array 62.

The third MUX array 80 determines the progress path of the pixel voltage signal supplied from the buffer array 68 in response to the polarity control signal POL from the timing controller. To this end, the third MUX array 80 includes n third MUXs 82, where n = 6. Each of the third MUXs 82 selects and outputs one of two adjacent buffers 70 in response to the polarity control signal POL. Here, the output terminals of the remaining buffers 70 except for the first and last buffers 70 are shared and input to two adjacent third MUXs 82. In the third MUX array 82 having the above configuration, the pixel voltage signal from each of the buffers 70 except for the last buffer 70 is in one-to-one correspondence with the DEMUXs 86 in response to the polarity control signal POL. To print. In addition, the third MUX array 82 may output pixel voltage signals from each of the remaining buffers 70 except for the first buffer 70 in a one-to-one correspondence with the DEMUXs 86 in response to the polarity control signal POL. do. The polarity control signal POL is inverted in polarity every horizontal period as shown in FIGS. 5A and 5B as is supplied to the second MUX array 58 for dot inversion driving. As such, the third MUX array 80 determines the polarity of the pixel voltage signal in response to the polarity control signal POL together with the second MUX array 58. As a result, the pixel voltage signal output from the third MUX array 80 has a polarity opposite to that of adjacent pixel voltage signals, and is inverted in units of horizontal periods.

The DEMUX array 84 receives 2n pixel voltage signals from the third MUX array 80 in response to the first and second selection control signals Θ1 and Θ2 from the timing controller, where n = 6 data. Supply to the lines selectively. To this end, the DEMUX array 84 has n DEMUX 86. Each of the DEMUXs 86 time-divides and supplies the pixel voltage signals supplied from each of the third MUXs 82 to two data lines. In detail, the odd-numbered DEMUX 86 time-divisionally supplies the output of the third-numbered MUX 82 to two odd-numbered data lines in response to the first selection control signal Θ1. The even-numbered DEMUX 86 time-divisions and supplies the outputs of the two even-numbered third MUXs 82 to two even-numbered data lines in response to the second selection control signal Θ2. As shown in FIGS. 5A and 5B, the first and second selection control signals Θ1 and Θ2 have polarities opposite to each other and are polarized inverted in each horizontal period as shown in FIGS. 5A and 5B.

For example, the first DEMUX 86 outputs the output of the first third MUX 82 in units of 1/2 horizontal period in response to the first selection control signal Θ1 as shown in FIGS. 5A and 5B. And selectively supply to the third data lines D1 and D3. As shown in FIGS. 5A and 5B, the second DEMUX 86 also outputs the second and fourth data outputs of the second third MUX 82 in units of 1/2 horizontal periods in response to the second selection control signal Θ2. Supply selectively to the lines D2 and D4.

Specifically, the first DEMUX 86 outputs the pixel voltage signal [1,1] in the first half of the first horizontal period during which the first gate line GL1 is activated in response to the first selection control signal Θ1. And the pixel voltage signals [1, 3] to the third data line D3 in the second half. At the same time, the second DEMUX 86 supplies the pixel voltage signals [1, 2] to the second data line D2 in the first half of the first horizontal period H1 in response to the second selection control signal Θ2, In the second half, the pixel voltage signals [1, 4] are supplied to the fourth data line D4. In addition, the first DEMUX 86 transmits the pixel voltage signals [2,1] and [3,1] to the first data line DL1 in the first half of each of the second and third horizontal periods H2 and H3. The pixel voltage signals [2, 3] and [3, 3] are supplied to the third data line DL3 in the second half. At the same time, the second DEMUX 86 transmits the pixel voltage signals [2, 2] and [3, 2] to the second data line DL2 even in the first half of each of the second horizontal period H2 and the third horizontal period H3. In the second half, the pixel voltage signals [2, 4] and [3, 4] are supplied to the fourth data line DL4.

The pixel voltage signal outputted to odd data lines such as DL1 and DL3 by the data drive IC having such a configuration and the pixel voltage signal outputted to even data lines such as DL2 and DL4 are shown in FIGS. 5A and 5B. Likewise, they have opposite polarities. The polarity of the odd data lines DL1, DL3, ... and even data lines DL2, DL4, ... is driven sequentially by the gate lines GL1, GL2, GL3, ... It is inverted every 1 horizontal period (1H), and is also inverted in units of frames.

6 and 7 illustrate a progress path of pixel data according to the polarity control signal POL in the data driver IC shown in FIG. 4.

When the polarity control signal POL is in a low state (or high state), the second MUX array 58 may include the first and second latch arrays 46 and 50 and the first MUX array 54 as shown in FIG. 6. ) The output six pixel data are supplied to each of the remaining PDAC1 (66) to NDAC3 (64) except the PDAC4 (66) to be converted into a pixel voltage signal. In this case, the output of the first first MUX 56 is supplied to the PDAC1 66 as it is and converted into a pixel voltage signal. The third MUX array 80 supplies pixel voltage signals supplied from the PDAC1 66 to the NDAC3 64 through the buffer array 68 in one-to-one correspondence with each of the DEMUXs 86. Each of the DEMUXs 86 selectively supplies a pixel voltage signal input from each of the third MUXs 82 to the twelve data lines DL1 to DL12.

On the other hand, when the polarity control signal POL is in a high state (or low state), the second MUX array 58 may have the first and second latch arrays 46 and 50 and the first MUX as shown in FIG. 7. The array 54 shifts the output six pixel data to the right to be supplied to each of the remaining NDAC1 64 to PDAC3 66 except the PDAC1 66 to be converted into a pixel voltage signal. In this case, the output of the first first MUX 56 is supplied to the PDAC4 66 as it is and converted into a pixel voltage signal. The third MUX array 82 shifts the pixel voltage signals supplied from each of the NDAC1 64 to the PDAC4 64 via the buffer array 68 to the left and supplies them in a one-to-one correspondence with each of the DEMUXs 86. Each of the DEMUXs 86 selectively supplies a pixel voltage signal input from each of the third MUXs 82 to the twelve data lines DL1 to DL12.

As described above, in the data drive IC according to the exemplary embodiment of the present invention, the DAC array is time-division-driven to drive 2n channel data lines using n + 1 DACs. In other words, each of the data drive ICs having n + 1 DACs drives 2n data lines, thereby reducing the number of DAC ICs by half.

8 is a block diagram illustrating a configuration of a data drive IC according to an exemplary embodiment of the present invention, and FIGS. 10A and 10B are driving waveform diagrams of odd and even frames of the data drive IC illustrated in FIG. 8. 9A and 9B are driving waveform diagrams of the m-1th horizontal period and the mth horizontal period of the data register unit 148 shown in FIG.

The data drive IC shown in FIG. 8 includes a shift register array 102 for supplying a sequential sampling signal, and first and second latch arrays for latching and outputting pixel data R, G, and B in response to the sampling signal. (106, 110), the first MUX array 114 for time division and outputting the pixel data (R, G, B) from the second latch array 110, and the pixel from the first MUX array 114 DAC array 122 for converting data R, G, and B into pixel voltage signals, buffer array 128 for buffering and outputting pixel voltage signals from DAC array 122, and buffer array 128 output And a second MUX array 140 for controlling the progress path of the signal, and a DEMUX array 144 for time division and outputting the pixel voltage signals from the second MUX array 140 to the data lines DL1 to D12. .

In addition, the data drive IC shown in FIG. 8 is required in the data register unit 148 and the DAC array 122 for rearranging and outputting pixel data R, G, and B supplied from a timing controller (not shown). A gamma voltage unit 150 for supplying positive and negative gamma voltages is further provided.

The data drive IC having such a configuration uses n + 2 DACs 64 and 66 and buffers 130 by time-division driving the DAC array 122 using the first MUX array 114 and the DEMUX array 144. As a result, 2n data lines twice as much as the conventional ones are driven. The data drive IC has a data output of 2n channels to drive 2n data lines. However, in FIG. 8, only 12 channels DL1 to D12 are shown assuming n = 6.

The gamma voltage unit 90 subdivides and outputs a plurality of gamma reference voltages inputted from a gamma reference voltage generator (not shown) for each gray.

The data register section 148 rearranges the pixel data from the timing control section to be suitable for dot inversion driving and supplies the pixel data from the timing control section to the first latch array 106. The data register unit 148 simultaneously inputs odd pixel data OR, OG, OB and even pixel data ER, EG, EB from the timing controller through the first to sixth input buses IB1 to IB6. The data register unit 148 rearranges the inputted odd pixel data OR, OG, OB and even-numbered pixel data ER, EG, EB through the first to sixth output buses OB1 to OB6. Will print.

In detail, as illustrated in FIGS. 9A and 9B, the data register unit 148 selects six pixel data OR, OG, OB, ER, EG, and EB from each of the first to sixth input buses IB1 to I. IB6) through each of them. In this case, the data register unit 148 inputs six pixel data OR, OG, OB, ER, EG, and EB per one cycle unit of the shift clock signal SSC based on the source start pulse SSP. Done.

In the m-1 th horizontal period, the data register unit 148 includes data of 4k-2 (where k is a positive integer) and 4k-1 of the pixel data of one horizontal line as shown in FIG. 9A. The data will be exchanged once. For example, as shown in FIG. 9A, data 2 and 3 are changed, data 7 and 8 are exchanged, data 10 and 11 are exchanged and output. This is for inputting a pair of pixel data to be converted into pixel voltage signals having the same polarity to each of the first MUXs 116. As such, the polarity control is performed between the first MUX array 114 and the DAC array 122 by rearranging and outputting pixel data OR, OG, OB, ER, EG, and EB input from the data register unit 148. According to the signal POL, it is possible to remove the MUX array which determines the progress path of the pixel data.

Further, in the m-th horizontal period, the data register unit 148 includes data of 4k-2 (where k is a positive integer) and 4k-1 of pixel data of one horizontal line as shown in FIG. 9B. Are exchanged and delayed by 2 channels for the polarity inversion, that is, shifted and output through the output buses OB1 to OB6. For example, the data register unit 148 may convert the first pixel data into the third output bus OB3, the replaced third pixel data into the fourth output bus OB4, and the second pixel data exchanged into the fifth output data. The pixel data No. 4 is shifted to the sixth output bus OB6 and outputted to the output bus OB5. In the next clock, the fifth pixel data is transferred to the first output bus OB1, the replaced seventh pixel data to the second output bus OB2, and the replaced sixth pixel data to the third output bus OB3. The output is shifted.

As such, the pixel data ORO, OGO, OBO, ERO, EGO, and EBO that are rearranged and output by the data register unit 148 are inputted to the pixel data OR, OG, and BO to secure the realignment time of the pixel data. , ER, EG, EB) is delayed by a specific time, for example, 2/3 clock output.

The shift register array 102 generates a sequential sampling signal and supplies it to the first latch array 106, and has 2n / 6 (where n = 6) shift registers 104 for this purpose. The shift register 104 of the first stage shown in FIG. 8 shifts the source start pulse SSP input from the timing controller according to the source sampling clock signal SSC and outputs it as a sampling signal. 104 is supplied as a carry signal CAR. As shown in FIGS. 10A and 10B, the source start pulse SSP is supplied in units of horizontal periods, shifted for each source sampling clock signal SSC, and output as a sampling signal.

The first latch array 106 samples six pixel data input from the data register 148 through the first through sixth output buses OB1 through OB6 in response to the sampling signal from the shift register array 102. To latch. The first latch array 106 is comprised of 2n first latches 108 for latching 2n (where n = 6) pixel data, each of which latches 108 has a bit of pixel data. It has a size corresponding to a number (6 bits or 8 bits). In addition, the first latch array 106 further includes two first latches (not shown) in preparation for shift input by two channels as shown in FIG. 9B.

For example, 1, 3, 2, 4, 5, 7, 6 rearranged in the data register section 148 in the first first latch 108 to the twelfth first latch 108 in the m-1 th horizontal period. , Pixel data are latched in the order of 8, 9, 11, 10, and 12. In the mth horizontal period, blank data is input to the first latch 108 and the second latch 108 as the pixel data rearranged in the data register unit 148 is shifted by two channels, and the third latches 108 to 12 are input. The pixel data is latched in the order of 1, 3, 2, 4, 5, 7, 6, 8, 9, and 11 shifted by the second latch 108. Here, the pixel data of Nos. 10 and 12 are latched in two latches, not shown, respectively.

The second latch array 110 simultaneously latches and outputs pixel data from the first latch array 106 in response to the source output enable signal SOE from the timing controller. The second latch array 110 has 2n (here n = 6) + two second latches 112 similarly to the first latch array 106. The source output enable signal SOE is generated in units of horizontal periods as shown in FIGS. 10A and 10B.

In response to the selection control signal Θ1 from the timing controller, the first MUX array 114 receives n n 2n pixel data from the second latch array 110 in units of H / 2 periods. Time division outputs. To this end, the first MUX array 114 is composed of n first MUXs 116. In addition, the first MUX array 114 further includes one first MUX (not shown) in consideration of the case where the pixel data is shifted by two channels. Each of the first MUXs 116 selects and outputs one of two second latches 112 in the second latch array 110. In other words, each of the first MUXs 116 supplies the outputs of the two second latches 112 in half horizontal periods.

In detail, for the dot inversion driving, the odd first MUX 116 selects one of the outputs of the two odd second latches 112 in response to the selection control signal Θ1 to perform the DAC array 122. ) Is output to the PDAC 124. The even-numbered first MUX 56 selects one of the outputs of the two even-numbered second latches 112 in response to the selection control signal Θ1 to the NDAC 126 of the DAC array 122. Output

For example, in the first half of the m−1 th horizontal period, the first first MUX 56 receives the first pixel data from the first second latch 112 in response to the selection control signal Θ1, and the second second in the second half. The pixel data 3 from the latch 112 is selected and output to the PDAC1 124. The second first MUX 116 receives the second pixel data from the third second latch 112 in the first half and the fourth pixel data from the fourth second latch 112 in the second half in response to the selection control signal Θ1. It selects and outputs to NDAC1 (126). In the first half of the m-th horizontal period, the second first MUX 56 receives the first pixel data from the third second latch 112 and the fourth second latch 112 in the second half in response to the selection control signal Θ1. Select pixel 3 data from &lt; RTI ID = 0.0 &gt; and output it to NDAC1 126. &lt; / RTI &gt; The fourth first MUX 116 receives the second pixel data from the fifth second latch 112 in the first half and the fourth pixel from the sixth second latch 112 in the second half in response to the selection control signal Θ1. The data is selected and output to the PDAC2 124. Here, as shown in Figs. 10A and 10B, the selection control signal Θ1 has its polarity reversed in units of 1/2 horizontal period (H / 2).

The DAC array 122 converts the pixel data from the first MUX array 114 into a pixel voltage signal by using the positive and negative gamma voltages GH and GL from the gamma voltage unit 150. . To this end, the DAC array 122 includes n + 1 PDACs 124 and NDACs 126, and the PDACs 124 and NDACs 126 are alternately arranged side by side for dot inversion driving. The PDAC 124 converts the pixel data from the first MUX array 114 into a positive pixel voltage signal using positive polarity (common voltage reference) gamma voltages GH. The NDAC 126 converts the pixel data R, G, and B from the first MUX array 114 into a negative pixel voltage signal using negative polarity (common voltage reference) gamma voltages GL. The PDAC 124 and the NDAC 126 convert the digital pixel data input every 1/2 horizontal period into an analog pixel voltage signal.

For example, the PDAC1 124 converts and outputs the odd pixel data [1,1] and [1,3], which are time-divided and input in the first horizontal period, into pixel voltage signals as shown in FIGS. 10A and 10B. do. At the same time, the NDAC2 126 also converts even pixel data [1, 2] and [1, 4], which are time-divided and input in each of the first horizontal periods, as shown in Figs. . Next, in the second horizontal period, the NDAC1 126 converts the odd pixel data [2,1] and [2,3] inputted by time division into a pixel voltage signal and outputs the pixel voltage signal. At the same time, the PDAC2 124 converts the even pixel data [2, 2] and [2, 4], which are time-divided and input in the second horizontal period, into a pixel voltage signal and outputs them. By the DAC array 122, 2n pixel data are time-divided by n units in 1/2 horizontal periods, converted into pixel voltage signals, and output.

Each of the n + 1 buffers 130 included in the buffer array 128 may buffer and output a pixel voltage signal output from each of the PDAC 124 and the NDAC 126 of the DAC array 122.

The second MUX array 140 determines the progress path of the pixel voltage signal supplied from the buffer array 128 in response to the polarity control signal POL from the timing controller. To this end, the second MUX array 140 has n (where n = 6) MUXs 142. Each of the MUXs 142 selects and outputs one of two adjacent buffers 70 in response to the polarity control signal POL. Here, the output terminals of the remaining buffers 130 except for the first and last buffers 130 are shared and input to two adjacent MUXs 142. In the third MUX array 142 having the above configuration, in response to the polarity control signal POL in the m−1 th horizontal period, the pixel voltage signal from each of the buffers 130 except for the last buffer 130 remains as DEMUX. One-to-one correspondence with the fields 146 to be output. Also, in the second MUX array 142, the pixel voltage signal from each of the remaining buffers 70 except for the first buffer 70 is in response to the polarity control signal POL in the mth horizontal period. One-to-one correspondence is output. The polarity control signal POL is polarized inverted every horizontal period as shown in FIGS. 10A and 10B for dot inversion driving. As described above, the second MUX array 140 determines the polarity of the pixel voltage signal in response to the polarity control signal POL. As a result, the pixel voltage signal output from the second MUX array 140 has a polarity opposite to that of adjacent pixel voltage signals, and is inverted in units of horizontal periods.

The DEMUX array 144 selectively supplies the pixel voltage signals from the second MUX array 140 to 2n data lines (where n = 6) in response to the selection control signal Θ1 from the timing controller. do. To this end, the DEMUX array 144 includes n DEMUXs 146. Each of the DEMUXs 146 time-divisions and supplies the pixel voltage signals supplied from each of the second MUXs 142 to two data lines.

For example, the first DEMUX 146 outputs the first and third data outputs of the first MUX 142 in units of 1/2 horizontal periods in response to the selection control signal Θ1 as shown in FIGS. 10A and 10B. Supply selectively to the lines D1 and D3. As shown in FIGS. 10A and 10B, the second DEMUX 146 also outputs the outputs of the second MUX 142 in units of 1/2 horizontal periods in response to the selection control signal Θ1 to the second and fourth data lines D2,. Supply selectively to D4).

In detail, the first DEMUX 146 transmits the pixel voltage signal [1,1] to the first data line D1 in the first half of the first horizontal period in which the first gate line GL1 is activated in response to the selection control signal Θ1. In the second half, the pixel voltage signals [1, 3] are supplied to the third data line D3. At the same time, the second DEMUX 146 supplies the pixel voltage signals [1, 2] to the second data line D2 in the first half of the first horizontal period H1 in response to the selection control signal Θ1. The pixel voltage signals [1, 4] are supplied to the fourth data line D4. In addition, the first DEMUX 86 transmits the pixel voltage signals [2,1] and [3,1] to the first data line DL1 in the first half of each of the second horizontal period H2 and the third horizontal period H3. In the second half, the pixel voltage signals [2, 3] and [3, 3] are supplied to the third data line DL3. At the same time, the second DEMUX 86 transmits the pixel voltage signals [2, 2] and [3, 2] to the second data line DL2 in the first half of each of the second horizontal period H2 and the third horizontal period H3. In the second half, the pixel voltage signals [2, 4] and [3, 4] are supplied to the fourth data line DL4.

The pixel voltage signal output to odd data lines such as DL1 and DL3 by the data drive IC having such a configuration and the pixel voltage signal output to even data lines such as DL2 and DL4 are shown in FIGS. 10A and 10B. Likewise, they have opposite polarities. The polarity of the odd data lines DL1, DL3, ... and even data lines DL2, DL4, ... is driven sequentially by the gate lines GL1, GL2, GL3, ... It is inverted every 1 horizontal period (1H), and is also inverted in units of frames.

11 and 12 illustrate a progress path of pixel data according to the polarity control signal POL in the data driving IC shown in FIG. 8.

The pixel data is latched in the order of 1, 3, 2, 4, 5, 7, 6, 8, 9, 11, 10, 12 in the first and second latch arrays 106 and 110 in the m-1th horizontal period. do. When the polarity control signal POL is in the low state (or the high state), that is, in the m-1th horizontal period, the first MUX array 114 has the second latch array 110 in the first half as shown in FIG. Select pixel data # 1, # 2, # 5, # 6, # 9, # 10 and pixel # 3, # 4, # 7, # 8, # 11, # 12 in the latter half and the PDAC1 124 through NDAC3 (126). Are supplied to each of the pixels) to be converted into pixel voltage signals. The second MUX array 142 supplies pixel voltage signals supplied from the PDAC1 124 to the NDAC3 126 via the buffer array 128 to each of the DEMUXs 146 in a one-to-one correspondence. Each of the DEMUXs 146 selectively supplies a pixel voltage signal input from each of the second MUXs 142 to twelve data lines DL1 to DL12.

In the m-th horizontal period, the first and second latch arrays 106 and 110 each contain two channels of pixel data in the order of 1, 3, 2, 4, 5, 7, 6, 8, 9, 11, 10, and 12. It is shifted and latched. In this case, valid pixel data is not supplied to the first latch 108 and the second latch 112, which are positioned at the front end, and blank data (not shown) is supplied. When the polarity control signal POL is in the high state (or low state), that is, in the mth horizontal period, the first MUXs 116 except for the first MUX 116 at the first stage are shown in FIG. 12. In the first half, the pixel data of 1, 2, 5, 6, 9, 10 are selected among the pixel data output from the second latch array 110, and in the second half, the pixel data of 3, 4, 7, 8, 11, 12 are selected. To the NDAC1 126 to the PDAC4 124 to be converted into pixel voltage signals. The second MUX array 142 shifts the pixel voltage signals supplied from each of the NDAC1 126 to the PDAC4 124 via the buffer array 128 one channel to the left to correspond one to one to each of the DEMUXs 146. Supply. Each of the DEMUXs 146 selectively supplies a pixel voltage signal input from each of the second MUXs 142 to twelve data lines DL1 to DL12.

As described above, in the data drive IC according to the exemplary embodiment of the present invention, the DAC array is time-division-driven to drive 2n channel data lines using n + 1 DACs. In other words, each of the data drive ICs having n + 1 DACs drives 2n data lines, thereby reducing the number of DAC ICs by half.

FIG. 13 schematically shows a configuration of a liquid crystal display device to which the data drive ICs shown in FIGS. 4 and 8 are applied. The liquid crystal display shown in FIG. 13 has data drive ICs 74 connected to the liquid crystal panel 72 through data TCP 76 and a gate drive connected to the liquid crystal panel 72 through gate TCP 80. ICs 78 are provided.

Each of the data drive ICs 74 is mounted on each of the data TCP 76 and electrically connected to data pads provided at the upper end of the liquid crystal panel 72 through the data TCP 76. Each of the gate drive ICs 78 is also mounted on each of the gate TCPs 80 and electrically connected to gate pads provided at one end of the liquid crystal panel 72 through the gate TCP 80. The gate drive ICs 78 sequentially drive the gate lines on the liquid crystal panel 72 by one gate line per horizontal period 1H. The data drive ICs 74 convert the pixel data signal, which is a digital signal, into a pixel voltage signal, which is an analog signal, and time-division and supply data lines on the liquid crystal panel 72 with a half horizontal period H / 2. Accordingly, the conventional data drive IC for driving n data lines for driving 8 n data lines requires eight, whereas the data drive IC 74 of the present invention for time-division driving 2 n data lines is four. Only a dog is needed.

On the other hand, when driving the data lines by time division, a difference occurs between the charge amount of the pixel voltage supplied to the first half and the charge amount of the pixel voltage supplied to the second half during one horizontal period 1H. This is because the charging time is different due to the difference in charging time between the pixel voltage supplied to the first half and the pixel voltage supplied to the second half. In other words, the pixel voltage supplied to the first half is charged in the corresponding liquid crystal cells in about one horizontal period (1H), while the pixel voltage supplied to the second half is corresponding to the liquid crystal cell in about one half of the horizontal period (H / 2). This is because it is charged in the field. Due to the difference in the charging time, the amount of charge of the pixel voltage is changed between the liquid crystal cells, and thus a flicker phenomenon is expected.

In order to prevent this, the pixel voltage charging amount difference is compensated by changing the charging order of the pixel voltage in a specific unit such as a line, a field, or a frame. For example, in the current frame, when a pixel voltage is supplied to a specific liquid crystal cell in the first half of one horizontal period (1H), and the pixel voltage is charged over one horizontal period (1H), in the next frame, the pixel voltage is supplied in the second half. The pixel voltage is charged over a 1/2 horizontal period (H / 2). By changing the pixel voltage charging order for each frame, the pixel voltage charge amount difference caused by the charging time difference can be compensated. In addition, even when the pixel voltage charging order is changed in line units or in a plurality of line units, the pixel voltage charge amount difference can be compensated for. In contrast, even when the pixel voltage charging order is changed in line units and frame units or in a plurality of line units and frame units, the difference in the pixel voltage charge amount can be compensated.

14A and 14B illustrate driving waveforms for driving the pixel voltages by changing the pixel voltage charging order in units of frames when time-division driving the data lines. In particular, FIG. 14A illustrates signal waveforms for driving the first to fourth data lines DL1 to DL4 in the data driving apparatus shown in FIGS. 4 and 8 in an odd frame, and FIG. The signal waveform is shown.

In FIG. 14A corresponding to the odd frame, the pixel data [1,1], [1,2] is applied by the selection control signals Θ1 and / or Θ2 in the first half of the first horizontal period H1. Is selected. The pixel data [1,1] is converted into a positive pixel voltage signal by a polarity control signal (not shown) and supplied to the first data line DL1, and the pixel data [1,2] is a negative pixel voltage signal. Is converted to and supplied to the second data line DL2. Subsequently, the pixel data [1, 3] and [1, 4] are selected by the selection control signals Θ1 and / or Θ2 in the second half of the H / 2 period. The pixel data [1, 3] is converted into a positive pixel voltage signal by a polarity control signal (not shown) and supplied to the third data line DL3, and the pixel data [1, 4] is a negative pixel voltage signal. Is converted to and supplied to the fourth data line DL4.

Similarly, the pixel data [2,1], [2,2] is selected by the selection control signals Θ1 and / or Θ2 in the first half of the second horizontal period H1. The pixel data [2,1] is converted into a negative pixel voltage signal by a polarity control signal (not shown) and supplied to the first data line DL1, and the pixel data [2,2] is a polarity control signal (not shown). Is converted into a positive pixel voltage signal and supplied to the second data line DL2. Subsequently, the pixel data [2, 3], [2, 4] is selected by the selection control signals Θ1 and / or Θ2 in the second half of the H / 2 period. The pixel data [2, 3] is converted into a negative pixel voltage signal by a polarity control signal (not shown) and supplied to the third data line DL3, and the pixel data [2, 4] is a positive pixel voltage signal. Is converted to and supplied to the fourth data line DL4.

As described above, in the odd frame, the data driving apparatus of the present invention performs time division driving of the data lines and also drives the dot inversion method.

In FIG. 13B corresponding to the even frame, the pixel data [1,3], unlike the odd frame, is selected by the selection control signals Θ1 and / or Θ2 in the H / 2 period of the first half of the first horizontal period H1. [1, 4] is selected. The pixel data [1, 3] is converted into a negative pixel voltage signal by a polarity control signal (not shown) and supplied to the third data line DL3, and the pixel data [1, 4] is a positive pixel voltage signal. Is converted to and supplied to the fourth data line DL4. Subsequently, the pixel data [1, 1] and [1, 2] are selected by the selection control signals Θ1 and / or Θ2 in the second half of the H / 2 period. The pixel data [1,1] is converted into a negative pixel voltage signal by a polarity control signal (not shown) and supplied to the first data line DL1, and the pixel data [1,2] is a positive pixel voltage signal. Is converted to and supplied to the second data line DL2.

Similarly, the pixel data [2, 3], [2, 4] is selected by the selection control signals Θ1 and / or Θ2 in the first half of the second horizontal period H1. The pixel data [2, 3] is converted into a positive pixel voltage signal by a polarity control signal (not shown) and supplied to the third data line DL3, and the pixel data [2, 4] is a negative pixel voltage signal. Is converted to and supplied to the fourth data line DL4. Subsequently, the pixel data [2, 1], [2, 2] is selected by the selection control signals Θ1 and / or Θ2 in the second half of the H / 2 period. The pixel data [2, 1] is converted into a positive pixel voltage signal by a polarity control signal (not shown) and supplied to the first data line DL1, and the pixel data [2, 2] is a negative pixel voltage signal. Is converted to and supplied to the second data line DL2.

As such, in the even frame, the data driving apparatus of the present invention time-division drives the data lines and drives the dot inversion method. In addition, the data driving device of the present invention drives the odd frame and the pixel voltage charging order in the even frame. Accordingly, it is possible to compensate the pixel voltage charge amount difference generated in the odd frame due to the difference in charge time according to the time division driving in the even frame. As a result, the flicker phenomenon due to the difference in the pixel voltage charge amount when the data lines are time-division driven can be prevented.

15A and 15B illustrate driving waveforms for driving the pixel voltage by changing the charging order of the pixel voltage in line units and frame units when time-division driving the data lines. In particular, FIG. 15A illustrates signal waveforms for driving the first to fourth data lines DL1 to DL4 in the data driving apparatus shown in FIGS. 4 and 8 in an odd frame, and FIG. The signal waveform is shown.

In FIG. 15A corresponding to the odd frame, pixel data [1,1] and [1,2] are selected by the selection control signals Θ1 and Θ2 in the first half of the first horizontal period H1. do. The pixel data [1,1] is converted into a positive pixel voltage signal by a polarity control signal (not shown) and supplied to the first data line DL1, and the pixel data [1,2] is a negative pixel voltage signal. Is converted to and supplied to the second data line DL2. Subsequently, the pixel data [1, 3] and [1, 4] are selected by the selection control signals Θ1 and / or Θ2 in the second half of the H / 2 period. The pixel data [1, 3] is converted into a positive pixel voltage signal by a polarity control signal (not shown) and supplied to the third data line DL3, and the pixel data [1, 4] is a negative pixel voltage signal. Is converted to and supplied to the fourth data line DL4.

The pixel data [2, 3], [2] differs from the first horizontal period H1 due to the selection control signals Θ1 and / or Θ2 in the first half of the second horizontal period H1. , 4] is selected. The pixel data [2, 3] is converted into a negative pixel voltage signal by a polarity control signal (not shown) and supplied to the third data line DL3, and the pixel data [2, 4] is a positive pixel voltage signal. Is converted to and supplied to the fourth data line DL4. Subsequently, the pixel data [2, 1], [2, 2] is selected by the selection control signals Θ1 and / or Θ2 in the second half of the H / 2 period. The pixel data [2, 1] is converted into a negative pixel voltage signal by a polarity control signal (not shown) and supplied to the first data line DL1, and the pixel data [2, 2] is a positive pixel voltage signal. Is converted to and supplied to the second data line DL2.

As described above, in the odd frame, the data driving apparatus of the present invention performs time division driving of the data lines and also drives the dot inversion method. In addition, the pixel voltage charging order is changed in units of lines.

In FIG. 14B corresponding to an even frame, the pixel data [1,3], unlike the aud frame due to the selection control signals Θ1 and / or Θ2 in the H / 2 period, which is the first half of the first horizontal period H1, Pixel data [1, 4] is selected. The pixel data [1, 3] is converted into a negative pixel voltage signal by a polarity control signal (not shown) and supplied to the third data line DL3, and the pixel data [1, 4] is a positive pixel voltage signal. Is converted to and supplied to the fourth data line DL4. Subsequently, the pixel data [1, 1] and [1, 2] are selected by the selection control signals Θ1 and / or Θ2 in the second half of the H / 2 period. The pixel data [1,1] is converted into a negative pixel voltage signal by a polarity control signal (not shown) and supplied to the first data line DL1, and the pixel data [1,2] is a positive pixel voltage signal. Is converted to and supplied to the second data line DL2.

The pixel data [2,1], [2] differs from the first horizontal period H1 due to the selection control signals Θ1 and / or Θ2 in the first half of the second horizontal period H1. , 2] is selected. The pixel data [2, 1] is converted into a positive pixel voltage signal by a polarity control signal (not shown) and supplied to the first data line DL1, and the pixel data [2, 2] is a negative pixel voltage signal. Is converted to and supplied to the second data line DL2. Subsequently, the pixel data [2, 3], [2, 4] is selected by the selection control signals Θ1 and / or Θ2 in the second half of the H / 2 period. The pixel data [2, 3] is converted into a positive pixel voltage signal by a polarity control signal (not shown) and supplied to the third data line DL3, and the pixel data [2, 4] is a negative pixel voltage signal. Is converted to and supplied to the fourth data line DL4.

As such, in the even frame, the data driving apparatus of the present invention time-division drives the data lines and drives the dot inversion method. In addition, the data driving device of the present invention changes the pixel voltage charging order on a line basis and drives the odd frame and the pixel voltage charging order in an even frame. Accordingly, it is possible to compensate for the pixel voltage charge amount difference generated due to the charge time difference according to the time division driving. Alternatively, the pixel voltage charging order can be compensated for even when the pixel voltage charging order is changed in units of a plurality of lines, for example, 2 lines, and the pixel voltage charging order is changed in units of frames. As a result, the flicker phenomenon due to the difference in the pixel voltage charge amount when the data lines are time-division driven can be prevented.

16A and 16B illustrate driving waveforms for driving the pixel voltage charging order by line unit and frame unit when time-division driving the data lines driven by the column inversion method. In particular, FIG. 16A illustrates signal waveforms for driving the first to fourth data lines DL1 to DL4 in the data driving apparatus shown in FIGS. 4 and 8 in an odd frame, and FIG. The signal waveform is shown.

In FIG. 16A corresponding to the odd frame, the pixel data [1,1], [1,2] is applied by the selection control signals Θ1 and / or Θ2 in the H / 2 period which is the first half of the first horizontal period H1. Is selected. The pixel data [1,1] is converted into a positive pixel voltage signal by a polarity control signal (not shown) and supplied to the first data line DL1, and the pixel data [1,2] is a negative pixel voltage signal. Is converted to and supplied to the second data line DL2. Subsequently, pixel data [1,3] and pixel data [1,4] are selected by the selection control signals Θ1 and / or Θ2, respectively, in the second half of the H / 2 period. The pixel data [1, 3] is converted into a positive pixel voltage signal by a polarity control signal (not shown) and supplied to the third data line DL3, and the pixel data [1, 4] is a negative pixel voltage signal. Is converted to and supplied to the fourth data line DL4.

The pixel data [2, 3], [2] differs from the first horizontal period H1 due to the selection control signals Θ1 and / or Θ2 in the first half of the second horizontal period H1. , 4] is selected. The pixel data [2, 3] is converted into a positive pixel voltage signal by a polarity control signal (not shown) and supplied to the third data line DL3, and the pixel data [2, 4] is a negative pixel voltage signal. Is converted to and supplied to the fourth data line DL4. Subsequently, pixel data [2,1] and pixel data [2,2] are selected by the selection control signals Θ1 and / or Θ2 in the second half of the H / 2 period. The pixel data [2, 1] is converted into a positive pixel voltage signal by a polarity control signal (not shown) and supplied to the first data line DL1, and the pixel data [2, 2] is a negative pixel voltage signal. Is converted to and supplied to the second data line DL2.

As described above, in the odd frame, the data driver of the present invention drives the data lines in a time-division manner as well as in a column inversion method. In addition, the pixel voltage charging order is changed in units of lines.

In FIG. 16B corresponding to the even frame, the pixel data [1,3], unlike the odd frame, is selected by the selection control signals Θ1 and / or Θ2 in the H / 2 period of the first horizontal period H1. [1, 4] is selected. The pixel data [1, 3] is converted into a negative pixel voltage signal by a polarity control signal (not shown) and supplied to the third data line DL3, and the pixel data [1, 4] is a positive pixel voltage signal. Is converted to and supplied to the fourth data line DL4. Subsequently, the pixel data [1, 1] and [1, 2] are selected by the selection control signals Θ1 and / or Θ2 in the second half of the H / 2 period. The pixel data [1,1] is converted into a negative pixel voltage signal by a polarity control signal (not shown) and supplied to the first data line DL1, and the pixel data [1,2] is a positive pixel voltage signal. Is converted to and supplied to the second data line DL2.

The pixel data [2,1], [2] differs from the first horizontal period H1 due to the selection control signals Θ1 and / or Θ2 in the first half of the second horizontal period H1. , 2] is selected. The pixel data [2, 1] is converted into a negative pixel voltage signal by a polarity control signal (not shown) and supplied to the first data line DL1, and the pixel data [2, 2] is a positive pixel voltage signal. Is converted to and supplied to the second data line DL2. Subsequently, the pixel data [2, 3], [2, 4] is selected by the selection control signals Θ1 and / or Θ2 in the second half of the H / 2 period. The pixel data [2, 3] is converted into a negative pixel voltage signal by a polarity control signal (not shown) and supplied to the third data line DL3, and the pixel data [2, 4] is a positive pixel voltage signal. Is converted to and supplied to the fourth data line DL4.

As described above, in the even frame, the data driving apparatus of the present invention time-division drives the data lines and drives the column inversion method. In addition, the data driving device of the present invention changes the pixel voltage charging order on a line basis and drives the odd frame and the pixel voltage charging order in an even frame. Accordingly, it is possible to compensate for the pixel voltage charge amount difference generated due to the charge time difference according to the time division driving. Alternatively, the pixel voltage charging order can be compensated for even when the pixel voltage charging order is changed in units of a plurality of lines, for example, 2 lines, and the pixel voltage charging order is changed in units of frames. As a result, the flicker phenomenon due to the difference in the pixel voltage charge amount when the data lines are time-division driven can be prevented.

As described above, in the data driving apparatus and method of the liquid crystal display according to the present invention, by time-division driving the DAC unit, at least 2n data lines can be driven using n + 1 DACs. Accordingly, according to the data driving device and method of the liquid crystal display according to the present invention, the number of data drive ICs can be reduced by half compared to the related art, thereby reducing manufacturing costs.

Further, in the data driving apparatus and method of the liquid crystal display according to the present invention, the pixel voltage charging order in time division driving is performed in line units, plural line units, frame units, line units and frame units, or plural line units and frame units. It will change and drive. Accordingly, the flicker phenomenon may be prevented by compensating for the difference in the amount of charge in the pixel voltage caused by the difference in the charging time according to the time division driving.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (49)

A first multiplexer array for time division and supplying input pixel data; A digital-analog conversion array for converting time division pixel data into a pixel voltage signal; And a demultiplexer array for time-dividing the data lines to supply the pixel voltage signal. The method of claim 1, A shift register array for sequentially generating sampling signals; A latch array for sequentially latching the pixel data in predetermined units in response to the sampling signal and simultaneously outputting the pixel data to the first multiplexer array; And a buffer array for buffering the pixel voltage signal and supplying the pixel voltage signal to the demultiplexer array. The method of claim 1, The first multiplexer array includes at least n (n is an integer) multiplexers to supply a plurality of input pixel data by time-division by at least n pieces, The digital-analog conversion array converts the n-time-divided pixel data into a pixel voltage signal, The demultiplexer array includes at least n demultiplexers to time-division a plurality of data lines at least n times to supply the pixel voltage signals. The method of claim 3, wherein The digital to analog conversion array At least n + 1 positive and negative digital-to-analog converters for converting the at least n time-division pixel data into pixel voltage signals, And the positive digital to analog converter and the negative digital to analog converter are alternately arranged. The method of claim 4, wherein In response to an input polarity control signal, a progress path of the at least n time-division pixel data is determined so that at least n positive and negative digital-to-analog converters of the at least n + 1 positive and negative digital-to-analog converters are used. A second multiplexer array to be input; And a third multiplexer array configured to determine a propagation path of the at least n pixel voltage signals in response to the polarity control signal and to input the demultiplexer array to the demultiplexer array. The method of claim 5, The second multiplexer array comprises at least n-1 second multiplexers for selecting any one of the outputs of at least two first multiplexers, The third multiplexer array comprises at least n third multiplexers for selecting any one of at least two outputs of the digital-to-analog converter, An output of each of the first multiplexers is shared as an input of the at least two second multiplexers, And an output of each of the digital-analog converters is shared with the inputs of the at least two third multiplexers. The method of claim 3, wherein The odd-numbered multiplexer of the at least n first multiplexers time-divisions even-numbered pixel data in response to the input first selection control signal, and the even-numbered multiplexer outputs the even-numbered pixel data in response to the input second selection control signal. A data driving device of a liquid crystal display device, characterized in that. The method of claim 7, wherein The odd-numbered demultiplexer of the at least n demultiplexers time-divisionally drives odd-numbered data lines in response to the first selection control signal, and the even-numbered demultiplexer performs time-division driving of even-numbered data lines in response to the second selection control signal. A data drive device for a liquid crystal display device. The method of claim 8, And the first and second selection control signals have opposite logic states, and the logic states are inverted at least every 1/2 horizontal period. The method of claim 5, And the polarity control signal is inverted in a logic state every at least one horizontal period. The method of claim 7, wherein The first multiplexer array and the demultiplexer array And supplying the time-divided pixel data and the pixel voltage signal in alternating order for each specific unit in response to the first and second selection control signals. The method of claim 11, The first multiplexer array and the demultiplexer array And a supply order of the time-division pixel data and the pixel voltage signal in response to the first and second selection control signals at least in units of frames. The method of claim 11, The first multiplexer array and the demultiplexer array And a supply order of the time-division pixel data and the pixel voltage signal in response to the first and second selection control signals by at least one or more lines. The method of claim 11, The first multiplexer array and the demultiplexer array And a supply order of the time-division pixel data and the pixel voltage signal in response to the first and second selection control signals in at least one line unit and frame unit. The method of claim 4, wherein A data register unit for rearranging input pixel data and outputting the input pixel data to the first multiplexer array; And a second multiplexer array configured to determine a propagation path of the at least n pixel voltage signals output from the digital-analog conversion array in response to the polarity control signal and to input the demultiplexer array. Data drive device of display device. The method of claim 15, The data register section And rearranging the input pixel data by replacing 4k-3 (k is a positive integer) pixel data and 4k-2 pixel data among them. The method of claim 15, The data register section Outputting the rearranged pixel data to the first multiplexer array in a first horizontal period, In the second horizontal period, the rearranged pixel data are delayed by two channels and outputted to the first multiplexer array. And the first and second horizontal periods alternate. The method of claim 17, The second multiplexer array comprises at least n second multiplexers for selecting any one of at least two outputs of the positive and negative digital-to-analog converters, And an output of each of the positive and negative digital-to-analog converters is shared with the inputs of the at least two second multiplexers. The method of claim 17, The odd-numbered multiplexer of the at least n first multiplexers outputs the odd-numbered pixel data in response to an input selection control signal and the even-numbered multiplexer outputs the even-numbered pixel data by time division. . The method of claim 19, And an odd-numbered demultiplexer of the at least n demultiplexers drives time division of odd-numbered data lines and an even-numbered demultiplexer time-divisionally divide even-numbered data lines in response to the selection control signal. The method of claim 20, And wherein said selection control signal is inverted in its logic state at least every one-half horizontal period. The method of claim 15, And said polarity control signal is inverted in a logic state every one horizontal period. The method of claim 19, The first multiplexer array and the demultiplexer array And supplying the time-divided pixel data and the supply voltage of the pixel voltage signal alternately for each specific unit in response to the selection control signal. The method of claim 23, The first multiplexer array and the demultiplexer array And the supply order of the time-division pixel data and the pixel voltage signal is changed at least in units of frames in response to the selection control signal. The method of claim 23, The first multiplexer array and the demultiplexer array And a supply order of the time-division pixel data and the pixel voltage signal in at least one line unit in response to the selection control signal. The method of claim 23, The first multiplexer array and the demultiplexer array And a supply order of the time-division pixel data and the pixel voltage signal in response to the selection control signal in at least one line unit and frame unit. The method of claim 1, The digital to analog conversion array And the adjacent pixel data are converted into pixel voltage signals having opposite polarities in response to the input polarity control signal. Time division and supplying input pixel data; Converting the pixel data into a pixel voltage signal; Supplying the pixel voltage signal by time-division driving data lines. The method of claim 28, Sequentially generating sampling signals; Sequentially latching and simultaneously supplying the pixel data in predetermined units in response to the sampling signal before the time division of the pixel data; And buffering the pixel voltage signal prior to time-dividing the data lines. The method of claim 28, Converting to the pixel voltage signal And converting each of the pixel data into a pixel voltage signal having a different polarity from the adjacent pixel data. The method of claim 28, Determining an input path for inputting to the positive and negative digital-to-analog converters arranged in alternating time-division pixel data in response to an input polarity control signal prior to converting to the pixel voltage signal; And after the converting into the pixel voltage signal, determining an output path of the pixel voltage signal in response to the polarity control signal to determine the polarity of the pixel voltage signal. Data driving method. The method of claim 31, wherein And the polarity control signal is inverted in a logic state every at least one horizontal period. The method of claim 28, Time-dividing the pixel data A step-wise multiplexing of the pixel data into odd-numbered pixel data in response to an input first selection control signal by an odd-numbered multiplexer, and an even-number multiplexer time-dividing even-numbered pixel data in response to an input second selection control signal The data driving method of the liquid crystal display device characterized by the above-mentioned. The method of claim 33, wherein Time-division driving of the data lines An odd-numbered demultiplexer of the at least n demultiplexers time-divisionally drives odd-numbered data lines in response to the first selection control signal, and an even-numbered demultiplexer times-divide even-numbered data lines in response to the second selection control signal. A data driving method of a liquid crystal display device. The method of claim 34, wherein And the first and second selection control signals have opposite logic states, and the logic states are inverted at least every 1/2 horizontal period. The method of claim 33, wherein In the step of time-dividing the pixel data, the supply order of the time-divided pixel data is alternately changed for each specific unit, And in step of time-dividing the data lines, the supply order of the pixel voltage signals is alternately changed for each specific unit. The method of claim 36, And supplying the time-divided pixel data and the pixel voltage signal alternately at least in units of frames in response to the first and second selection control signals. The method of claim 36, And supplying the time-divided pixel data and the pixel voltage signal to at least one or more lines in response to the first and first selection control signals. The method of claim 36, And changing the supply order of the time-division pixel data and the pixel voltage signal into at least one line unit and frame unit in response to the first and first selection control signals. The method of claim 28, Rearranging the input pixel data prior to time division of the pixel data; And converting the pixel voltage signal to an output path of the pixel voltage signal in response to an input polarity control signal after converting the pixel voltage signal to the pixel voltage signal. Data driving method. The method of claim 40, Reordering the data And rearranging the input pixel data by exchanging 4k-3 (k is a positive integer) pixel data and 4k-2 pixel data among them. 42. The method of claim 41 wherein Output the rearranged pixel data in a first horizontal period; In the second horizontal period, the rearranged pixel data are delayed by two channels and outputted. And driving the first and second horizontal periods alternately. The method of claim 40, Time-dividing the pixel data Wherein the odd-numbered multiplexer divides the pixel data into odd-numbered pixel data and the even-numbered multiplexer divides the even-numbered pixel data among the at least n multiplexers in response to an input selection control signal. Way. The method of claim 43, Time-division driving of the data lines And an odd-numbered demultiplexer time-division-drives the odd-numbered data lines and the even-numbered demultiplexer time-divisionally divides the even-numbered data lines in response to the selection control signal. The method of claim 44, And wherein said selection control signal is inverted in its logic state at least every 1/2 horizontal period. The method of claim 44, In the step of time-dividing the pixel data, the supply order of time-divided pixel data is alternately changed for each specific unit in response to the selection control signal, And in step of time-dividing the data lines, the supply order of the pixel voltage signals is alternately changed for each specific unit in response to the selection control signal. The method of claim 46, And supplying the time-divided pixel data and the pixel voltage signal alternately at least in units of frames in response to the selection control signal. The method of claim 46, And supplying the time-divided pixel data and the pixel voltage signal in order of at least one line in response to the selection control signal. The method of claim 46, And supplying the time-divided pixel data and the pixel voltage signal in order of at least one line unit and frame unit in response to the selection control signal.