KR101174783B1 - Apparatus and method for driving of liquid crystal display device - Google Patents

Abstract

The present invention relates to a two-dot inversion driving liquid crystal display device capable of preventing a luminance difference between scanning lines supplied with data voltages having the same polarity in the two-dot inversion driving method.

The driving apparatus of the liquid crystal display according to the present invention includes a plurality of gate lines formed side by side in a first direction, a plurality of data lines formed side by side in a second direction so as to cross the first direction, and A liquid crystal panel including liquid crystal cells formed in regions provided at intersections of data lines; A gate driver for supplying scan pulses to the gate lines; A data driver for supplying an analog pixel signal to the data lines; The gate driver and the data driver are controlled to be driven by a vertical 2-dot inversion driving method in which the polarity of the pixel signal in the liquid crystal panel is inverted by 2 dots in the first direction and inverted by dots in the second direction. A timing controller; And a common voltage generator for supplying different common voltages to vertically adjacent liquid crystal cells to which pixel signals of the same polarity are supplied.

2 dot inversion, multiplexer, horizontal line, common voltage

Description

Driving apparatus and driving method of liquid crystal display device {APPARATUS AND METHOD FOR DRIVING OF LIQUID CRYSTAL DISPLAY DEVICE}

1 is a view showing a driving device of a liquid crystal display according to the prior art.

2A and 2B illustrate polar patterns of pixel signals supplied to liquid crystal cells of a liquid crystal panel by a vertical two-dot inversion driving method.

3A and 3B are diagrams showing a horizontal line phenomenon caused by a vertical two-dot inversion driving method according to the prior art.

4 is a waveform diagram showing a method of driving a liquid crystal display device according to the prior art;

FIG. 5 is a waveform diagram illustrating pixel signal charging characteristics of liquid crystal cells driven by a 2-dot inversion driving method according to the related art. FIG.

6 is a view illustrating a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 7 is a block diagram illustrating a common voltage generator shown in FIG. 6.

8A and 8B are waveform diagrams illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

9 is a block diagram illustrating a data driver in a driving device of a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 10 illustrates the multiplexer array shown in FIG. 9. FIG.

11A and 11B are waveform diagrams illustrating a method of driving a liquid crystal display according to another exemplary embodiment of the present invention.

<Explanation of Signs of Major Parts of Drawings>

102: liquid crystal panel 104: gate driver

106: data driver 110: timing control unit

120: common voltage generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a method and apparatus for driving a liquid crystal display capable of minimizing a horizontal line phenomenon generated in a vertical two-dot inversion driving method.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a cross shape, and a driving circuit for driving the liquid crystal panel.

In fact, as shown in FIG. 1, the liquid crystal display device includes a liquid crystal panel 2 in which liquid crystal cells are arranged in an intersection region of the gate lines GL1 to GLn and the data lines DL1 to DLm, and the gate lines (eg, a liquid crystal display). Gate driver 4 for driving GL1 to GLn, data driver 6 for driving data lines DL1 to DLm, timing for controlling gate driver 4 and data driver 6 The control unit 10 is provided.

The liquid crystal panel 2 includes a thin film transistor TFT formed at each intersection of the gate lines GL1 to GLn and the data lines DL1 to DLm and connected to each of the liquid crystal cells.

The thin film transistor TFT is turned on when the scan signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data line DL to the liquid crystal cell. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell.

The liquid crystal cell is equivalently represented by a liquid crystal capacitor Clc, and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell further includes a storage capacitor Cst so that the charged pixel signal is stably maintained until the next pixel signal is charged. The storage capacitor Cst is formed between the pixel electrode and the previous gate line. The liquid crystal cell realizes gray scale by adjusting light transmittance by changing an arrangement state of liquid crystal having dielectric anisotropy according to a pixel signal charged through a thin film transistor (TFT).

The timing controller 10 generates gate control signals GSP, GSC, and GOE to control the gate driver 4, and generates data control signals SSP, SSC, SOE, and POL to generate the data driver 6. To control. In addition, the timing controller 10 aligns the pixel data RGB to the data driver 6.

The gate driver 4 sequentially supplies the gate high voltage VGH to the gate lines GL1 to GLn in response to the gate control signals GSP, GSC, and GOE from the timing controller 10. Accordingly, the gate driver 4 causes the thin film transistor TFT connected to the gate lines GL1 to GLn to be driven in units of the gate line GL.

The data driver 6 outputs a pixel signal of one line for each horizontal period H1, H2, ... in response to the data control signals SSP, SSC, SOE, and POL from the timing controller 10. To DL1 to DLm. In particular, the data driver 6 converts and supplies the pixel data RGB from the timing controller 10 into an analog pixel signal using a gamma voltage from a gamma voltage generator (not shown).

Specifically, the data driver 6 shifts the source start pulse SSP according to the source shift clock SSC to generate a sampling signal. Subsequently, the data driver 6 sequentially inputs and latches the pixel data RGB in predetermined units in response to the sampling signal. The data driver 6 converts the latched pixel data RGB for one line into an analog pixel signal and supplies the same to the data lines DL1 to DLm. In this case, the data driver 6 converts the positive and negative pixel signals in response to the polarity control signal POL.

As such, the liquid crystal display uses an inversion method to prevent degradation of the liquid crystal cells and to improve image quality.

In particular, the liquid crystal display provides superior image quality compared to other inversion schemes, but uses a vertical two-dot inversion scheme to compensate for the dot inversion scheme, which consumes a lot of power. In other words, the dot inversion method causes flicker when the frame frequency is lowered from 60 Hz to 50 to 30 Hz in order to reduce power consumption. In order to compensate for this, two vertical dots as shown in FIGS. 2A and 2B are provided. The inversion method is used.

2A and 2B illustrate a pixel signal polarity supplied to liquid crystal cells in a vertical 2-dot inversion scheme divided into odd and even frames.

In the odd and even frames shown in Figs. 2A and 2B, the vertical two-dot inversion scheme changes the polarity of the pixel signal in dots in the horizontal direction as in the conventional dot inversion scheme, while in the vertical direction. You can see that it is driven to change by 2 dots. The vertical two-dot inversion method has the advantage that the flicker phenomenon is reduced in comparison with the dot inversion method in a commercial screen driven at a frame frequency of 50 Hz, but has a problem in that horizontal lines are generated according to the luminance difference every two scanning lines. .

3A and 3B show horizontal lines in the odd and even frames, which are represented by the vertical two-dot inversion method.

3A and 3B, when the polarity of the liquid crystal cell is changed in units of 2 dots vertically, a horizontal line phenomenon occurs due to a luminance difference between the odd scan lines G1 and the even scan lines G2. In the case of the vertical 2-dot inversion scheme, the parasitic capacitor Cpp is formed between the odd-numbered scan lines G1 and the pixel electrodes vertically adjacent to each other in the even-numbered scan lines G2 to which pixel signals of the same polarity are supplied. This is because the charging characteristics of the pixel signal Vd are different from each other due to the coupling effect difference.

In other words, due to the parasitic capacitor Cpp between the pixel electrodes vertically adjacent to each other, as shown in FIG. 4, the charge amount A of the pixel signal Vd during the horizontal period H1, H3,. This is because the charge amount B of the pixel signal Vd in the even-numbered horizontal periods H2, H4, ... is different.

5 shows the [m, n] th and [m + 1, n] th liquid crystal cells and the [m, n + 1] th of the next line in response to the scan pulses GL [n] and GL [n + 1]. And pixel signals Vd [m, n], Vd [m + 1, n], Vd [m, n + 1], and Vd [m + 1, charged in the [m + 1, n + 1] th liquid crystal cell. n + 1]).

In FIG. 5, ΔVp is changed until the pixel signal Vd charged in the liquid crystal cell is supplied to the pixel frame Vd of the next frame M + 1 in the supply period of the gate high voltage Vgh in the current frame M. In FIG. The feed through voltage is generated by the coupling effect of parasitic capacitors Cgs and Cgd formed in the thin film transistor. ΔVpp is added to the feed throw voltage ΔVp and is generated by the coupling effect of the parasitic capacitor Cpp formed between the vertically adjacent pixel electrodes as shown in FIG. 1.

Referring to FIG. 5, the pixel signals Vd [m, n] and Vd [m, which are positive (+) in the [m, n] th and [m, n + 1] th liquid crystal cells in the current frame M n + 1]) is charged, and the negative pixel signals Vd [m + 1, n], Vd are stored in the [m + 1, n] -th and [m + 1, n + 1] -th liquid crystal cells. [m + 1, n + 1] is charged, and in the next frame M + 1, the pixel signals Vd [m, n], Vd [m + 1, n], and Vd [m, n + 1]. , Vd [m + 1, n + 1]) is reversed. In other words, in the liquid crystal cells [m, n] and [m + 1,) included in the odd scan line G1, the liquid crystal cells [m, n + 1] and [m + adjacent to each other in the vertical direction. 1, n + 1]) is applied with a pixel signal of the same polarity. Accordingly, in the liquid crystal cells [m, n] and [m, n + 1], the voltage variation ΔVpp1 is generated in the same direction as the polarity of the pixel signal currently charged by the parasitic capacitor Cpp. However, in the liquid crystal cells [m, n + 1], [m + 1, n + 1] included in the even-numbered scan line G2, an opposite polarity pixel signal is applied to the liquid crystal cells adjacent in the vertical direction. do. Accordingly, in the liquid crystal cells [m, n + 1], [m + 1, n + 1], the voltage variation ΔVpp2 is changed in a direction opposite to the polarity of the pixel signal currently charged by the parasitic capacitor Cpp. Occurs.

As described above, as the voltage fluctuation values ΔVpp1 and ΔVpp2 due to the parasitic capacitor Cpp are different in the odd scan line G1 and the even scan line G2, the odd scan line G1 and the even scan line are different. The luminance difference occurs between (G2).

In detail, in the normal white mode, the odd scan lines G1 in which the pixel signal charged by the voltage variation ΔVpp1 relative to the common voltage Vcom are raised due to the charging of the same polarity voltage as the next scan line appear dark, and then The even-numbered scan lines G2 in which the pixel signal charged by the voltage change value ΔVpp1 with respect to the common voltage Vcom are lowered due to the charging of the polarity voltage opposite to the scan line are bright.

As described above, in the conventional two-dot inversion liquid crystal display, a difference in luminance is generated between scan lines due to a difference in the parasitic capacitor (Cpp) coupling effect, thereby causing a horizontal line phenomenon to deteriorate display quality.

Accordingly, an object of the present invention is to provide a driving device and a driving method of a liquid crystal display device which can minimize the horizontal line phenomenon generated in the vertical two-dot inversion driving method.

In order to achieve the above object, the driving apparatus of the liquid crystal display according to the present invention includes a plurality of gate lines formed in parallel in the first direction and a plurality of data lines formed in parallel in the second direction to intersect the first direction. A liquid crystal panel including liquid crystal cells formed at regions formed at the intersections of the gate lines and the data lines; A gate driver for supplying scan pulses to the gate lines; A data driver for supplying an analog pixel signal to the data lines; The gate driver and the data driver are controlled to be driven by a vertical 2-dot inversion driving method in which the polarity of the pixel signal in the liquid crystal panel is inverted by 2 dots in the first direction and inverted by dots in the second direction. A timing controller; And a common voltage generator for supplying different common voltages to vertically adjacent liquid crystal cells to which pixel signals of the same polarity are supplied.

A driving method of a liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of gate lines formed in parallel in a first direction, a plurality of data lines formed in parallel in a second direction to cross the first direction, and the gate. A method of driving a liquid crystal panel including liquid crystal cells formed at regions provided at intersections of lines and data lines; Sequentially supplying scan pulses to the gate lines; Converting pixel data from the outside into a pixel signal to be driven by a vertical two-dot inversion driving method inverted in units of two dots in the first direction and in units of dots in the second direction; Supplying a pixel signal to the liquid crystal cell so as to be synchronized with the scan pulse; And supplying different common voltages to vertically adjacent liquid crystal cells to which pixel signals of the same polarity are supplied.

A driving method of a liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of gate lines formed in parallel in a first direction, a plurality of data lines formed in parallel in a second direction to cross the first direction, and the gate. A method of driving a liquid crystal panel including liquid crystal cells formed at regions provided at intersections of lines and data lines; Sequentially supplying scan pulses to the gate lines; Converting pixel data from the outside into a pixel signal to be driven by a vertical 2-dot inversion driving method inverted by 2 dots in the first direction and inverted by dots in the second direction; Generating a charge sharing voltage that prevents a voltage variation of the data line; Sequentially supplying the charge sharing voltage and the pixel signal to the data line according to a voltage control signal; And supplying different common voltages to vertically adjacent liquid crystal cells to which pixel signals of the same polarity are supplied.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

6 is a schematic view of a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 6, a driving device of a liquid crystal display according to an exemplary embodiment of the present invention is parallel to a plurality of gate lines GL1 to GLn formed in parallel in a first direction and to a second direction so as to cross the first direction. The liquid crystal panel includes a plurality of data lines DL1 to DLm, and liquid crystal cells PE formed at respective regions formed at intersections of the gate lines GL1 to GLn and the data lines DL1 to DLm. 102; A gate driver 104 for supplying scan pulses to the gate lines GL1 to GLn; A data driver 106 for supplying an analog pixel signal to the data lines DL1 to DLm; In the liquid crystal panel 102, the gate driver 104 is driven in a vertical 2-dot inversion driving method in which the polarity of the pixel signal is inverted by 2 dots in the first direction and in dots in the second direction. A timing controller 110 controlling the data driver; The common voltage generator 120 supplies different common voltages to vertically adjacent liquid crystal cells PE to which pixel signals having the same polarity are supplied.

The liquid crystal panel 102 includes a plurality of gate lines GL1 to GLn formed in parallel in a first direction, that is, in a horizontal direction, and a plurality of data lines DL1 through DLm formed in parallel in a second direction, that is, in a vertical direction. And liquid crystal cells PE formed at regions formed by intersections of the gate lines and the data lines, any one of the gate lines GL1 to GLn, and one of the data lines DL1 to DLm. A thin film transistor (TFT) is provided.

The thin film transistor TFT supplies the pixel signals from the data lines DL1 to DLm to the liquid crystal cell in response to the scan pulses from the gate lines GL1 to GLn.

The liquid crystal cell PE may be equivalently represented by a liquid crystal capacitor Clc including a common electrode (not shown) facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor. In the liquid crystal cell, a storage capacitor (not shown) is further formed to maintain the pixel signal charged in the liquid crystal capacitor Clc until the next pixel signal is charged.

In addition, the liquid crystal panel 102 includes a plurality of first common lines VL1 formed in a zigzag form between two adjacent liquid crystal cells so as to be connected to odd-numbered liquid crystal cells in the horizontal direction and even-numbered liquid crystal cells in the vertical direction, and horizontally. And a plurality of second common lines VL2 formed in a zigzag form between two adjacent liquid crystal cells to be connected to the even-numbered liquid crystal cells in the direction and the odd-numbered liquid crystal cells in the vertical direction.

The plurality of first common lines VL1 are alternately connected to the odd-numbered liquid crystal cell and the even-numbered liquid crystal cell in the horizontal direction for each horizontal line. On the other hand, the plurality of second common lines VL2 are alternately connected to the even-numbered liquid crystal cell and the odd-numbered liquid crystal cell in the horizontal direction for each horizontal line.

The timing controller 110 arranges the pixel data RGB from the outside into the data signal Data so as to be suitable for driving the liquid crystal panel 102, and supplies the pixel data RGB to the data driver 106.

In addition, the timing controller 110 is a vertical two-dot inversion driving method in which the polarity of the pixel signal in the liquid crystal panel 102 is inverted by 2 dots in the first direction and in dots in the second direction. The gate driver 104 is controlled by generating gate control signals GSP, GSC, and GOE to be driven, and the data driver 106 is controlled by generating data control signals SSP, SSC, SOE, and POL.

The gate driver 104 sequentially supplies scan pulses to the gate lines GL1 to GLn supplied from the timing controller 110. Accordingly, the gate driver 104 causes the thin film transistor TFT connected to the gate lines GL1 to GLn to be driven in units of the gate line GL.

The data driver 106 receives the horizontal periods H1, H2, ... in response to the data control signals SSP, SSC, SOE, and POL according to the vertical two-dot inversion driving scheme supplied from the timing controller 110. One pixel signal is supplied to the data lines DL1 through DLm every time. In particular, the data driver 106 converts and supplies the data signal Data from the timing controller 110 to an analog pixel signal using a gamma voltage from a gamma voltage generator (not shown).

Specifically, the data driver 106 shifts the source start pulse SSP according to the source shift clock SSC to generate a sampling signal. Subsequently, the data driver 106 sequentially inputs and latches the data signal RGB by a predetermined unit in response to the sampling signal. The data driver 106 converts the latched pixel data RGB for one line into an analog pixel signal and supplies the same to the data lines DL1 to DLm. In this case, the data driver 106 converts the pixel data RGB into the positive and negative pixel signals in response to the polarity control signal POL to have the polarity of the vertical 2-dot inversion driving method.

The common voltage generator 120 is connected to a vertically adjacent liquid crystal cell PE to which pixel signals having the same polarity are supplied in response to an input power Vin from an external source, a vertical synchronization signal Vsync, and a selection signal SS. Supply another common voltage.

To this end, the common voltage generator 120 may include the first common voltage generator 122 generating the first common voltage Vcom1 and a second lower than the first common voltage Vcom1. The second common voltage generator 124 generating the common voltage Vcom2 and the first and second common voltages Vcom1 and Vcom2 are sequentially selected according to the selection signal SS to form the first common wiring VL1. The first and second selectors 126 to be supplied to the inverter, an inverting unit 127 for inverting in accordance with the selection signal SS, and a first and second in accordance with the selection signal SS inverted by the inverting unit 127. A second selector 128 is provided to sequentially select the common voltages Vcom1 and Vcom2 and supply them to the second common wiring VL2.

The selection signal SS is a pulse in which the logic state is inverted for each horizontal section. The selection signal SS becomes a high state in the odd horizontal section and a low state in the even horizontal section.

The second common voltage generator 124 generates a first common voltage Vcom2 for equalizing charging characteristics by parasitic capacitors between vertically adjacent liquid crystal cells PE to which pixel signals of the same polarity are supplied. Supply to selector 126.

The first selector 126 supplies the first common voltage Vcom1 from the first common voltage generator 122 to the first common line VL1 in the high period of the select signal SS, and selects the signal ( The second common voltage Vcom2 from the second common voltage generator 124 is supplied to the first common line VL1 in the low period of SS.

The second selector 128 supplies the second common voltage Vcom2 from the second common voltage generator 122 to the second common line VL2 in the low period of the inverted selection signal SS, and inverts the second selector SS. The first common voltage Vcom1 from the first common voltage generator 122 is supplied to the second common wiring VL2 in the high period of the selected selection signal SS.

The common voltage generator 120 alternately inverts the first and second common voltages Vcom1 and Vcom2 supplied to the first and second common lines VL1 and VL2 in units of frames. That is, since the polarity of the pixel signal supplied to the liquid crystal panel 102 is inverted in units of frames, the first and second common voltages Vcom1 and Vcom2 supplied to the first and second common lines VL1 and VL2 are also inverted. You must invert frame by frame.

As described above, in the driving apparatus of the liquid crystal display according to the exemplary embodiment of the present invention, when the same positive polarity (+) pixel signal Vd is supplied as illustrated in FIG. The first common voltage Vcom1 is supplied through the common wiring VL1, and the second common voltage Vcom2 is supplied through the second common wiring VL2 in the even-numbered horizontal section H2. Accordingly, the horizontal line phenomenon due to the luminance difference between the scanning lines can be prevented by making the charging conditions between two vertically adjacent liquid crystal cells A and B the same.

In addition, the driving device of the liquid crystal display according to the exemplary embodiment of the present invention may have a first common value in the odd horizontal section H1 when the same negative pixel signal Vd is supplied as shown in FIG. 8B. The second common voltage Vcom2 is supplied through the wiring VL1, and the first common voltage Vcom1 is supplied through the second common wiring VL2 in the even-numbered horizontal section H2. Accordingly, the horizontal line phenomenon due to the luminance difference between the scanning lines can be prevented by making the charging conditions between two vertically adjacent liquid crystal cells A and B the same.

9 is a block diagram illustrating only a data driver in a driving device of a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 9, the data driver 216 latches and outputs a shift register array 222 that sequentially generates a sampling signal, and latches and outputs pixel data RGB from the timing controller 110 in response to the sampling signal. An array 224, a digital-to-analog converter array 226 for converting the pixel data RGB from the latch array 224 into a pixel signal whose polarity is reversed by a vertical 2-dot inversion driving method, and a digital-to-analog converter The buffer array 229 which buffers and outputs the pixel signals output from the array 226, the charge sharing voltage Vc and the buffer array 229 set according to the voltage control signal CS from the timing controller 210. A multiplexer array 232 is provided to sequentially supply the pixel signal Vd supplied from the data lines DL.

The shift register array unit 222 sequentially shifts and samples the source start pulse SSP according to the source shift clock SSC among the data control signals SSP, SSC, SOE, and POL supplied from the timing controller 110. The signals are sequentially generated and supplied to the latch array 224.

The latch array 224 sequentially samples and latches the pixel data RGB supplied from the timing controller 110 according to a sampling signal from the shift register array unit 222. At this time, the latch array 224 latches the pixel data RGB for one horizontal line.

The digital-analog converter array 226 converts the pixel data RGB from the latch array 224 into the pixel signal Vd using a plurality of gamma voltages supplied from a gamma voltage unit (not shown). At this time, the digital-to-analog converter array 226 causes the polarity of the pixel signal Vd to be inverted in the vertical 2-dot inversion driving method in response to the polarity control signal POL.

The buffer array 229 buffers the data signals supplied from the digital-to-analog converter array 226 and supplies them to the multiplexer array 232.

As illustrated in FIG. 10, the multiplexer array 232 includes a plurality of multiplexers that sequentially supply the charge sharing voltage Vc and the pixel signal Vd set to the data lines DL according to the voltage control signal CS. MUX).

The voltage control signal CS may be a source output enable signal SOE.

The charge sharing voltage Vc is an intermediate level between the positive (+) and the negative (-) pixel signals Vd according to the vertical 2-dot inversion driving method so that the voltage fluctuation range of the data lines DL1 to DLm is not large. The voltage supplied to the data lines D1 to Dm is controlled. In other words, the charge sharing voltage Vc reduces the voltage fluctuation of the data lines DL1 to DLm, thereby reducing power consumption.

Each of the multiplexers MUX selects the charge sharing voltage Vc according to the voltage control signal CS in the high state and supplies the charge sharing voltage Vc to the data lines DL1 through DLm, and in accordance with the voltage control signal CS in the low state. The pixel signal Vd is selected and supplied to the data line DL.

As described above, in the driving apparatus of the liquid crystal display according to another exemplary embodiment of the present invention, when the same positive polarity (+) pixel signal Vd is supplied as shown in FIG. The charge sharing voltage Vc is supplied to the data lines DL1 to DLm in the high period of the output enable signal SOE. The first common voltage Vcom1 is supplied to the low period of the source output enable signal SOE through the first common line VL1, and the second common line VL2 is supplied to the even-numbered horizontal section H2. Through the second common voltage (Vcom2) is supplied. Accordingly, the horizontal line phenomenon due to the luminance difference between the scanning lines can be prevented by making the charging conditions between two vertically adjacent liquid crystal cells A and B the same.

In addition, the driving device of the liquid crystal display according to the exemplary embodiment of the present invention is a source output in the odd horizontal section H1 when the same negative pixel signal Vd is supplied as shown in FIG. 11B. The charge sharing voltage Vc is supplied to the data lines DL1 to DLm in the high period of the enable signal SOE. The second common voltage Vcom2 is supplied to the low period of the source output enable signal SOE through the first common line VL1, and the second common line VL2 is supplied to the even-numbered horizontal section H2. Through the first common voltage Vcom1 is supplied. Accordingly, the horizontal line phenomenon due to the luminance difference between the scanning lines can be prevented by making the charging conditions between two vertically adjacent liquid crystal cells A and B the same.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

As described above, the two-dot inversion liquid crystal display and the driving method thereof according to the present invention apply different common voltages to two vertically adjacent liquid crystal cells to which data signals are supplied with the same polarity in the vertical two-dot driving method. The charging conditions of the two liquid crystal cells are the same to prevent the horizontal line phenomenon caused by the luminance difference between the scan lines.

Claims (16)

A plurality of gate lines formed side by side in a first direction, a plurality of data lines formed side by side in a second direction so as to cross the first direction, and a liquid crystal cell formed in each region provided at the intersection of the gate lines and the data lines And a liquid crystal panel comprising a; A gate driver for supplying scan pulses to the gate lines; A data driver for supplying an analog pixel signal to the data lines; The gate driver and the data driver are controlled to be driven by a vertical 2-dot inversion driving method in which the polarity of the pixel signal in the liquid crystal panel is inverted by 2 dots in the first direction and inverted by dots in the second direction. A timing controller; And a common voltage generator for supplying different common voltages to vertically adjacent liquid crystal cells to which pixel signals of the same polarity are supplied. The method of claim 1, The liquid crystal panel, A plurality of first common wirings formed in a zigzag form between two adjacent liquid crystal cells connected to the odd-numbered liquid crystal cells in the first direction and the even-numbered liquid crystal cells in the second direction; And a plurality of second common lines zigzag formed between two adjacent liquid crystal cells to be connected to the even-numbered liquid crystal cells in the first direction and the odd-numbered liquid crystal cells in the second direction. Drive of the device. The method of claim 2, The common voltage generator, A first common voltage generator for generating a first common voltage; A second common voltage generator configured to generate a second common voltage lower than the first common voltage; A first selector which sequentially supplies the first common voltage and the second common voltage to the first common line according to a selection signal in which logic states are inverted in a horizontal section unit; An inverting unit for inverting the selection signal; And a second selector for sequentially supplying the second common voltage and the first common voltage to the second common line according to the selection signal inverted by the inverter. The method of claim 3, wherein And the common voltage generator inverts the order of the common voltages supplied to each of the first and second common lines on a frame-by-frame basis. The method of claim 1, And the data driver supplies a charge sharing voltage that prevents a voltage variation of the data line before the pixel signal is supplied. 6. The method of claim 5, The data driver, A shift register array for generating a sampling signal sequentially; A latch array for latching pixel data from the timing controller in response to the sampling signal; A digital-to-analog converter array for converting pixel data from the latch array into the pixel signal whose polarity is inverted in the vertical 2-dot inversion driving scheme; And a multiplexer array sequentially supplying the charge sharing voltage and the pixel signal supplied from the digital-analog converter array to the data lines according to a voltage control signal. The method of claim 6, And the voltage control signal is a source output enable signal for outputting the pixel signal from the data driver to the data line. The method of claim 7, wherein The multiplexer array includes a plurality of multiplexers that supply the charge sharing voltage to the data line according to a high voltage control signal and supply the pixel signal to the data line according to a low voltage control signal. A drive device for a liquid crystal display device. A plurality of gate lines formed side by side in a first direction, a plurality of data lines formed side by side in a second direction so as to cross the first direction, and a liquid crystal cell formed in each region provided at the intersection of the gate lines and the data lines In the driving method of the liquid crystal panel comprising; Sequentially supplying scan pulses to the gate lines; Converting the pixel data from the outside into a pixel signal so as to be driven by a vertical 2-dot inversion driving method inverted in units of 2 dots in the first direction and in units of dots in the second direction; Supplying a pixel signal to the liquid crystal cell so as to be synchronized with the scan pulse; And supplying different common voltages to vertically adjacent liquid crystal cells to which pixel signals of the same polarity are supplied. The method of claim 9, Supplying the common voltage, Generating a first common voltage; Generating a second common voltage lower than the first common voltage; A plurality of zigzag formed in zigzag form between the adjacent liquid crystal cells in the first direction and the even liquid crystal cells in the second direction according to the selection signal in which the logic state is inverted in the horizontal section unit; Sequentially supplying the first common voltage and the second common voltage to one common wiring; According to the inverted selection signal, the second plurality of second common lines formed in a zigzag pattern are formed between two adjacent liquid crystal cells to be connected to the even-numbered liquid crystal cells in the first direction and the odd-numbered liquid crystal cells in the second direction. And sequentially supplying a common voltage and the first common voltage. 11. The method of claim 10, The supplying of the common voltage inverts the order of the common voltage supplied to each of the first and second common lines in units of frames. A plurality of gate lines formed side by side in a first direction, a plurality of data lines formed side by side in a second direction so as to cross the first direction, and a liquid crystal cell formed in each region provided at the intersection of the gate lines and the data lines In the driving method of the liquid crystal panel comprising; Sequentially supplying scan pulses to the gate lines; Converting the pixel data from the outside into a pixel signal so as to be driven by a vertical 2-dot inversion driving method inverted in units of 2 dots in the first direction and in units of dots in the second direction; Generating a charge sharing voltage that prevents a voltage variation of the data line; Sequentially supplying the charge sharing voltage and the pixel signal to the data line according to a voltage control signal; And supplying different common voltages to vertically adjacent liquid crystal cells to which pixel signals of the same polarity are supplied. 13. The method of claim 12, Supplying the common voltage, Generating a first common voltage; Generating a second common voltage lower than the first common voltage; A plurality of zigzag formed in zigzag form between the adjacent liquid crystal cells in the first direction and the even liquid crystal cells in the second direction according to the selection signal in which the logic state is inverted in the horizontal section unit; Sequentially supplying the first common voltage and the second common voltage to one common wiring; According to the inverted selection signal, the second plurality of second common lines formed in a zigzag pattern are formed between two adjacent liquid crystal cells to be connected to the even-numbered liquid crystal cells in the first direction and the odd-numbered liquid crystal cells in the second direction. And sequentially supplying a common voltage and the first common voltage. The method of claim 13, The supplying of the common voltage inverts the order of the common voltage supplied to each of the first and second common lines in units of frames. 13. The method of claim 12, And the voltage control signal is a source output enable signal for supplying the pixel signal to the data line in a data driver. 16. The method of claim 15, The step of sequentially supplying the charge sharing voltage and the pixel signal to the data line, Supplying the charge sharing voltage to the data line according to a high voltage control signal; And supplying the pixel signal to the data line according to a voltage control signal in a low state.

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