KR100947782B1 - Apparatus and method for driving of liquid crystal display device - Google Patents

Abstract

In accordance with another aspect of the present invention, a driving apparatus of a liquid crystal display device includes: a liquid crystal panel in which a liquid crystal cell is formed at each intersection of gate lines and data lines; A timing controller which generates a polarity control signal according to a frame frequency and controls a polar pattern of a data signal supplied to the liquid crystal panel; And a data driver for generating a polar pattern of the data signal in response to the polarity control signal from the timing controller and supplying the polarity pattern to the data lines, wherein the timing controller includes a reference clock and the frame supplied from an external device. A comparator for comparing the frequencies to generate a detection signal, and a frequency detection / generation section including a polarity control signal generation section for generating the polarity control signal based on the detection signal from the comparator, wherein the polarity control signal generation The controller may generate the polarity control signal to generate a polar pattern of the data signal inverted in units of the liquid crystal cell when the frame frequency is higher than the reference clock.

Description

Driving apparatus and driving method of liquid crystal display device {APPARATUS AND METHOD FOR DRIVING OF LIQUID CRYSTAL DISPLAY DEVICE}             

1 is a block diagram schematically illustrating a driving device of a liquid crystal display according to the related art.

FIG. 2A illustrates a polar pattern of data signals supplied to liquid crystal cells of a liquid crystal panel during an odd frame by a one dot inversion method. FIG.

FIG. 2B is a diagram showing polar patterns of data signals supplied to liquid crystal cells of a liquid crystal panel during an even frame by a one dot inversion method; FIG.

3 is a view showing flicker generation by a one dot inversion method when a frame frequency is 60 Hz or less in a method of driving a liquid crystal display according to the related art.

4A is a diagram showing polar patterns of data signals supplied to liquid crystal cells of a liquid crystal panel during an odd frame by a 2-dot inversion scheme.

4B is a diagram showing a polar pattern of data signals supplied to liquid crystal cells of a liquid crystal panel during an even frame by a 2-dot inversion method.

FIG. 5 is a diagram illustrating a horizontal line phenomenon by a 2-dot inversion method when a frame frequency is 60 Hz or less in a method of driving a liquid crystal display according to the related art. FIG.                 

6 is a block diagram schematically illustrating a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 7 is a block diagram schematically illustrating a frequency detection / generation unit illustrated in FIG. 6.

FIG. 8 is a waveform diagram illustrating a polarity control signal and a source output enable signal when a frame frequency is 60 Hz or higher in a method of driving a liquid crystal display according to an exemplary embodiment of the present invention. FIG.

9 is a waveform diagram illustrating a polarity control signal and a source output enable signal when a frame frequency is 60 Hz or less in the method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

10 is a view showing the image quality by the one-dot inversion method when the frame frequency is 60Hz or more in the driving method of the liquid crystal display device according to an embodiment of the present invention.

FIG. 11 is a view illustrating image quality by a 2-dot inversion method when a frame frequency is 60 Hz or less in a method of driving a liquid crystal display according to an exemplary embodiment of the present invention. FIG.

<Description of Symbols for Main Parts of Drawings>

2, 102 liquid crystal panel 4, 104 gate driver

6, 106: data driver 10, 110: timing control unit

112: frequency detection / generation unit 116: comparator

118: polarity control signal generator

The present invention relates to a driving device and a driving method of a liquid crystal display device, and more particularly to a driving device and a driving method of a liquid crystal display device to improve the image quality.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In fact, the liquid crystal display device includes a liquid crystal panel 2 in which liquid crystal cells are arranged in a matrix as shown in FIG. 1, and a gate driver 4 for driving gate lines GL0 to GLn of the liquid crystal panel 2. ), A data driver 6 for driving the data lines DL1 to DLm of the liquid crystal panel 2, and a timing controller 10 for controlling the gate driver 4 and the data driver 6. do.

The liquid crystal panel 2 is formed at each intersection of the liquid crystal cells arranged in a matrix form and the gate lines GL1 to GLn and the data lines DL1 to DLm, and is connected to each of the liquid crystal cells TFT. ).

The thin film transistor TFT is turned on when the scan signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data line DL to the liquid crystal cell. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell.

The liquid crystal cell is equivalently represented by a liquid crystal capacitor Clc, and includes a common electrode facing the liquid crystal and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell further includes a storage capacitor Cst to maintain the charged pixel signal stably until the next pixel signal is charged. The storage capacitor Cst is formed between the previous gate line and the pixel electrode. The liquid crystal cell realizes gray scale by controlling light transmittance by changing an arrangement state of liquid crystal having dielectric anisotropy according to a pixel signal charged through a thin film transistor (TFT).

The gate driver 4 sequentially supplies the gate high voltage VGH to the gate lines GL1 to GLn in response to the gate control signals GSP, GSC, and GOE from the timing controller 10. Accordingly, the gate driver 4 causes the thin film transistor TFT connected to the gate lines GL1 to GLn to be driven in units of the gate line GL.

Specifically, the gate driver 4 shifts the gate start pulse GSP according to the gate shift pulse GSC to generate a shift pulse. The gate driver 4 supplies the gate high voltage VGH to the corresponding gate line GL for each horizontal period H1, H2,... In response to the shift pulse. In this case, the gate driver 4 supplies the gate high voltage VGH only in the enable period in response to the gate output enable signal GOE. The gate driver 4 supplies the gate low voltage VGL to the gate lines GL1 through GLn in the remaining periods when the gate high voltage VGH is not supplied. In addition, the gate driver 4 supplies the gate low voltage VGL to the gate line GL0 formed at the uppermost side for the storage capacitor Cst of the first scan line.

The data driver 6 outputs a pixel data signal of one line for each horizontal period H1, H2, ... in response to the data control signals SSP, SSC, SOE, and POL from the timing controller 10. Supply to the lines DL1 to DLm. In particular, the data driver 6 converts the digital pixel data R, G, and B from the timing controller 10 into an analog pixel signal using a gamma voltage from a gamma voltage generator (not shown). .

Specifically, the data driver 6 shifts the source start pulse SSP according to the source shift clock SSC to generate a sampling signal. Subsequently, the data driver 6 sequentially inputs and latches the video data signals R, G, and B in predetermined units in response to the sampling signal. The data driver 6 converts the latched pixel data R, G, and B for one line into an analog pixel signal and supplies the same to the data lines DL1 to DLm. In this case, the data driver 6 converts the positive and negative pixel signals in response to the polarity control signal POL.

The timing controller 10 generates gate control signals GSP, GSC, and GOE to control the gate driver 4, and generates data control signals SSP, SSC, SOE, and POL to generate the data driver 6. To control. In addition, the timing controller 10 aligns the pixel data R, G, and B and supplies them to the data driver 6.

As described above, the liquid crystal display device includes a frame inversion system, a line column inversion system, and a dot inversion method in order to prevent degradation of the liquid crystal cells and to improve image quality. Inversion driving methods such as Inversion System are used.

The frame inversion type liquid crystal panel driving method inverts the polarity of the pixel data signal supplied to the liquid crystal cells on the liquid crystal panel every time the frame is changed. In the liquid crystal panel driving method of the line inversion method, polarities of pixel data signals supplied to liquid crystal cells are inverted according to a line (column) on the liquid crystal panel. The dot inversion scheme allows each of the liquid crystal cells on the liquid crystal panel to be supplied with pixel data signals having a polarity opposite to that of the pixel data signals supplied to adjacent liquid crystal cells in the vertical and horizontal directions. The polarities of the pixel data signals supplied to the liquid crystal cells are reversed. Of these inversion driving methods, the dot inversion method provides an image having excellent image quality compared to the frame and line inversion methods. The inversion driving is performed in response to the data driver 6 in response to the polarity control signal supplied from the controller 10 to the data driver 6.

Accordingly, the dot inversion method is mainly used in recent years. The dot inversion method is divided into a 1 dot inversion method and a 2 dot inversion method.

2A and 2B illustrate polarities of pixel data signals supplied to liquid crystal cells of a liquid crystal panel by using a one dot inversion liquid crystal panel, divided into odd frames and even frames. In the odd frame and even frame shown in FIGS. 2A and 2B, it can be seen that the one-dot inversion scheme is driven so that the polarity of the pixel data signal is changed in the liquid crystal cell, that is, in units of one dot. This one-dot inversion method provides the best picture quality among the inversion methods because the polarity of the data signal is changed in units of one dot.

However, the 1 dot inversion method provides the best image quality among the inversion methods when the frame frequency is 60 Hz or more. On the other hand, since the polarity of all adjacent liquid crystal cells is different, the one dot inversion method consumes a lot of power, and when the frame frequency is 60 Hz or less, flicker occurs as shown in FIG. 3. Accordingly, the 1-dot inversion method causes flicker when the frame frequency is lowered from 60 Hz to 50 to 30 Hz in order to reduce power consumption according to the low power consumption trend.

Accordingly, the vertical two-dot inversion method as shown in FIGS. 4A and 4B has been used to provide an excellent image quality among the inversion methods but to compensate for the dot inversion method with high power consumption.

4A and 4B illustrate polarities of pixel data signals supplied to liquid crystal cells of a liquid crystal panel divided into odd frames and even frames by a two dot inversion liquid crystal panel driving method.

In the odd frame and even frame shown in FIGS. 4A and 4B, the two-dot inversion scheme changes the polarity of the pixel data signal in the horizontal direction in the liquid crystal cell, that is, in units of dots, as in the conventional dot inversion scheme. It can be seen that it is driven to be changed in units of 2 dots in the vertical direction. While the two-dot inversion method has the advantage that the flicker phenomenon is reduced in comparison with the one-dot inversion method in a commercial screen driven at a frame frequency of 60 Hz or less, the use screen driven at a frame frequency of 60 Hz or more is shown in FIG. As described above, the horizontal line phenomenon occurs at two scan line cycles according to the luminance difference between scan lines.

In the two-dot inversion scheme, when the polarity of the liquid crystal cell is changed in units of two dots in the vertical direction, a horizontal line phenomenon occurs due to a luminance difference between the odd scan lines and the even scan lines. That is, in the case of the 2-dot inversion method, since the data voltage charging characteristics of the even-numbered scan lines and the even-numbered scan lines to which the data voltage signal of the same polarity is supplied are different from each other, a horizontal line phenomenon occurs and display quality is deteriorated. do.

Accordingly, an object of the present invention is to provide a driving device and a driving method of a liquid crystal display device capable of improving image quality.

In order to achieve the above object, a driving apparatus of a liquid crystal display according to an embodiment of the present invention includes a liquid crystal panel in which a liquid crystal cell is formed at each intersection of gate lines and data lines; A timing controller which generates a polarity control signal according to a frame frequency and controls a polar pattern of a data signal supplied to the liquid crystal panel; And a data driver for generating a polar pattern of the data signal in response to the polarity control signal from the timing controller and supplying the polarity pattern to the data lines, wherein the timing controller includes a reference clock and the frame supplied from an external device. A comparator for comparing the frequencies to generate a detection signal, and a frequency detection / generation section including a polarity control signal generation section for generating the polarity control signal based on the detection signal from the comparator, wherein the polarity control signal generation The controller may generate the polarity control signal to generate a polar pattern of the data signal inverted in units of the liquid crystal cell when the frame frequency is higher than the reference clock.

The driving device may further include a gate driver for driving the gate lines.

The frequency of the reference clock in the drive device is characterized in that 60Hz.

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The polarity control signal generation unit in the driving device may generate the polarity control signal for generating a polar pattern of the data signal inverted in units of the two liquid crystal cells when the frame frequency is lower than the reference clock. .

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According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method including: providing a liquid crystal panel having a liquid crystal cell formed at each intersection of gate lines and data lines; Generating a polarity control signal according to the frame frequency; Generating a polar pattern of a data signal supplied to the liquid crystal panel based on the polarity control signal; And supplying a polarity pattern of the data signal to the data lines, wherein generating the polarity control signal comprises: generating a detection signal by comparing the frame frequency with a reference clock supplied from the outside; And generating the polarity control signal based on the detection signal, wherein generating the polarity control signal in the driving method includes the data signal inverted by the liquid crystal cell when the frame frequency is higher than the reference clock. And generating the polarity control signal to generate the polarity pattern.

The driving method may further include supplying a scan pulse to the gate lines.

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The generating of the polarity control signal in the driving method may include generating the polarity control signal for generating a polar pattern of the data signal inverted in units of two liquid crystal cells when the frame frequency is lower than the reference clock. It is done.

In the driving method, the frequency of the reference clock is 60 Hz.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 11.                     

Referring to FIG. 6, a driving device of an LCD according to an exemplary embodiment of the present invention includes a liquid crystal panel 102 in which liquid crystal cells are arranged in a matrix, and gate lines GL0 to GLn of the liquid crystal panel 102. Controlling the gate driver 104 for driving, the data driver 106 for driving the data lines DL1 to DLm of the liquid crystal panel 102, the gate driver 104 and the data driver 106; In addition, the timing controller 110 is configured to supply a polarity control signal POL to the data driver 106 for controlling the polarity of the pixel data signal according to the frequency of the frame frequency Vsync.

The liquid crystal panel 102 is formed at each intersection of the liquid crystal cells arranged in a matrix form and the gate lines GL1 to GLn and the data lines DL1 to DLm, and is connected to each of the liquid crystal cells TFT. ).

The thin film transistor TFT is turned on when the scan signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data line DL to the liquid crystal cell. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell.

The liquid crystal cell is equivalently represented by a liquid crystal capacitor Clc, and includes a common electrode facing the liquid crystal and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell further includes a storage capacitor Cst to maintain the charged pixel signal stably until the next pixel signal is charged. The storage capacitor Cst is formed between the previous gate line and the pixel electrode. The liquid crystal cell realizes gray scale by controlling light transmittance by changing an arrangement state of liquid crystal having dielectric anisotropy according to a pixel signal charged through a thin film transistor (TFT).

The gate driver 104 sequentially supplies the gate high voltage VGH to the gate lines GL1 to GLn in response to the gate control signals GSP, GSC, and GOE from the timing controller 110. Accordingly, the gate driver 104 causes the thin film transistor TFT connected to the gate lines GL1 to GLn to be driven in units of the gate line GL.

Specifically, the gate driver 104 shifts the gate start pulse GSP according to the gate shift pulse GSC to generate a shift pulse. The gate driver 4 supplies the gate high voltage VGH to the corresponding gate line GL for each horizontal period H1, H2,... In response to the shift pulse. In this case, the gate driver 104 supplies the gate high voltage VGH only in the enable period in response to the gate output enable signal GOE. The gate driver 104 supplies the gate low voltage VGL to the gate lines GL1 through GLn in the remaining periods in which the gate high voltage VGH is not supplied. In addition, the gate driver 104 supplies the gate low voltage VGL to the gate line GL0 formed at the uppermost side for the storage capacitor Cst of the first scan line.

The timing controller 110 generates gate control signals GSP, GSC, and GOE to control the gate driver 104, and generates data control signals SSP, SSC, SOE, and POL to generate the data driver 106. Will be controlled. In addition, the timing controller 110 aligns the pixel data R, G, and B and supplies them to the data driver 106.

In addition, when the frame frequency Vsync is 60 Hz or more by receiving the frame frequency Vsync, the timing controller 110 may drive the polarity control signal POL for driving the data polar pattern of the pixel data signals in a one-dot inversion scheme. And a polarity control signal POL for driving the data polarity pattern of the pixel data signals in a 2-dot inversion manner when the data polarity is 60 Hz or less, and supplies it to the data driver 106.

To this end, the timing controller 110 includes a frequency detector / generator 112 that detects a frequency of the frame frequency Vsync and generates a polarity control signal POL based on the detected frequency.

As shown in FIG. 7, the frequency detector / generator 112 receives a frame frequency Vsync and detects a frequency of the frame frequency Vsync by comparing with a reference clock Cref and a comparator ( And a polarity control signal generator 118 for generating a polarity control signal POL based on the detection signal DS from 116.

The comparator 116 receives a reference clock Cref of 60 Hz and receives a frame frequency Vsync to detect a frequency of the frame frequency Vsync. For example, the comparator 116 supplies a logic signal of a high state to the polarity control signal generator 118 when the frame frequency Vsync is 60 Hz or more, and a low state of LOW when the frame frequency Vsync is 60 Hz or less. The logic signal is supplied to the polarity control signal generator 118.                     

The comparator 116 may count the frame frequency Vsync to detect the frequency of the frame frequency Vsync.

The polarity control signal generator 118 generates the polarity control signal POL based on the detection signal DS of the frame frequency Vsync supplied from the comparator 116 and supplies it to the data driver 106.

In detail, the polarity control signal generation unit 118 is shown in FIG. 8 when the detection signal DS supplied from the comparator 116 is a logic signal in a high state corresponding to a frame frequency Vsync of 60 Hz or more. Likewise, the polarity control signal POL of the one-dot inversion method, which is driven to change the polarity of the pixel data signal in units of one dot, is generated and supplied to the data driver 106.

On the other hand, the polarity control signal generator 118 is a pixel as shown in FIG. 9 when the detection signal DS supplied from the comparator 116 is a logic signal of a low state corresponding to a frame frequency Vsync of 60 Hz or less. The polarity control signal (POL) of the 2-dot inversion type in which the polarity of the data signal is driven in the horizontal direction by the liquid crystal cell, that is, the dot unit, as in the conventional dot inversion method, but in the vertical direction by 2 dots. Is generated and supplied to the data driver 106.

The data driver 106 outputs a pixel signal of one line for each horizontal period H1, H2, ... in response to the data control signals SSP, SSC, SOE, and POL from the timing controller 110. To DL1 to DLm. In particular, the data driver 106 converts the digital pixel data R, G, and B from the timing controller 110 into an analog pixel signal using a gamma voltage from a gamma voltage generator (not shown). .

Specifically, the data driver 106 shifts the source start pulse SSP according to the source shift clock SSC to generate a sampling signal. Subsequently, the data driver 106 sequentially inputs and latches the video data signals R, G, and B in predetermined units in response to the sampling signal. The data driver 106 converts the latched pixel data R, G, and B for one line into an analog pixel signal and supplies the same to the data lines DL1 through DLm. In this case, the data driver 106 converts the polarities of the positive and negative pixel data signals to the one dot inversion method or the two dot inversion method in response to the polarity control signal POL supplied from the timing controller 110. Done.

The data driver 106 operates in a mode using only the data enable signal DE supplied from the timing controller 110 when the polarity control signal POL supplied from the timing controller 106 is a one-dot inversion scheme. It will work. On the other hand, the data driver 106 uses only the vertical synchronization signal and the horizontal synchronization signal supplied from the timing controller 110 when the polarity control signal POL supplied from the timing controller 106 is a 2-dot inversion scheme. Will work. Herein, since the timing varies when the data driver 106 supplies the pixel data signal to the data lines according to the inversion method, a mode using only the data enable (DE) signal is advantageous in timing. In the 2-dot inversion, a mode using only the vertical synchronization signal and the horizontal synchronization signal is advantageous in timing.                     

As described above, the driving device and driving method of the liquid crystal display according to an exemplary embodiment of the present invention detect a frequency of the frame frequency Vsync using the frequency detector / generator 112 of the timing controller 110. When the frequency Vsync is 60 Hz or more, as illustrated in FIG. 6, a pixel data signal having a polar pattern of one dot inversion is supplied to the data lines DL of the liquid crystal panel 102. Accordingly, the driving device of the liquid crystal display according to the exemplary embodiment of the present invention is driven by a one-dot inversion method that provides the best image quality among the inversion methods when the frame frequency Vsync is 60 Hz or more. It can prevent the occurrence of the image quality can be improved as shown in FIG.

In addition, in the driving apparatus and driving method of the liquid crystal display according to the exemplary embodiment of the present invention, the frame frequency detected by detecting the frequency of the frame frequency Vsync using the frequency detector / generator 112 of the timing controller 110. When Vsync is 60 Hz or less, as illustrated in FIG. 9, a pixel data signal having a polar pattern of a 2-dot inversion type is supplied to the data lines DL of the liquid crystal panel 102. Accordingly, the driving device of the liquid crystal display according to the exemplary embodiment of the present invention provides a 2 dot inversion method that provides the best image quality among the inversion methods and monitors the power consumption when the frame frequency Vsync is 60 Hz or less. As a result, the image quality can be improved as shown in FIG. 11 by preventing a horizontal line phenomenon (luminance difference between lines) as in the prior art.

The driving apparatus and driving method of the liquid crystal display according to the exemplary embodiment of the present invention may improve the image quality by selectively selecting and driving one dot inversion or two dot inversion according to the frame frequency Vsync.

As described above, the driving apparatus and driving method of the liquid crystal display according to the exemplary embodiment of the present invention detect a frame frequency and output a polarity control signal corresponding to one dot inversion or two dot inversion based on the detected frame frequency. A timing control part is produced. The driving device and driving method of the liquid crystal display according to the exemplary embodiment of the present invention by using the timing controller are to drive the liquid crystal panel in a 2-dot inversion method at a frame frequency of 60 Hz or less and 1 at a frame frequency of 60 Hz or more. The liquid crystal panel is driven by a dot inversion method. Therefore, the present invention can improve image quality by preventing image degradation due to flicker in one dot inversion and horizontal lines in two dot inversion by changing the inversion method according to the frame frequency.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (13)

A liquid crystal panel in which a liquid crystal cell is formed at each intersection of the gate lines and the data lines; A timing controller which generates a polarity control signal according to a frame frequency and controls a polar pattern of a data signal supplied to the liquid crystal panel; And A data driver for generating a polar pattern of the data signal in response to the polarity control signal from the timing controller and supplying the polarity pattern to the data lines; The timing controller, A frequency detection / generation unit comprising a comparator for comparing a reference clock supplied from the outside with the frame frequency to generate a detection signal, and a polarity control signal generation unit for generating the polarity control signal based on the detection signal from the comparator Includes wealth, The polarity control signal generator, And driving the polarity control signal to generate the polarity pattern of the data signal inverted by the liquid crystal cell when the frame frequency is higher than the reference clock. The method of claim 1, And a gate driver for driving the gate lines. delete delete The method of claim 1, And a frequency of said reference clock is 60 Hz. delete The method of claim 1, The polarity control signal generator, And a polarity control signal for generating a polarity pattern of the data signal inverted in units of two liquid crystal cells when the frame frequency is lower than the reference clock. Providing a liquid crystal panel in which a liquid crystal cell is formed at each intersection of the gate lines and the data lines; Generating a polarity control signal according to the frame frequency; Generating a polar pattern of a data signal supplied to the liquid crystal panel based on the polarity control signal; And Supplying a polarity pattern of the data signal to the data lines; Generating the polarity control signal, Generating a detection signal by comparing the frame frequency with a reference clock supplied from an outside, and generating the polarity control signal based on the detection signal, wherein the frame frequency is higher than the reference clock. And generating the polarity control signal for generating the polarity pattern of the data signal inverted in units of liquid crystal cells. The method of claim 8, And supplying scan pulses to the gate lines. delete delete The method of claim 8, Generating the polarity control signal, And generating a polarity control signal for generating a polarity pattern of the data signal inverted in units of two liquid crystal cells when the frame frequency is lower than the reference clock. The method of claim 8, And a frequency of the reference clock is 60 Hz.

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