KR20070071496A - Apparatus and method for driving of liquid crystal display device - Google Patents

Abstract

An apparatus and a method for driving an LCD device are provided to prevent degradation of image quality by maintaining a constant data charge period even when a frame frequency is varied. An apparatus for driving an LCD(Liquid Crystal Display) device includes a liquid crystal panel(12), a data driver(14), a gate driver(16), and a timing controller(18). The liquid crystal panel includes liquid crystal cells, which are formed on regions defined by data and gate lines(DL1~DLm,GL1~GLn). The data driver supplies image signal to the data lines. The gate driver supplies scan pulse to the gate lines. The timing controller generates data control signals(SSP,SSC,POL) including a source output enable signal(SOE) whose width is varied according to a frame frequency to control the data driver, and generates a gate control signal to control the gate driver.

Description

Driving apparatus and driving method of liquid crystal display device {APPARATUS AND METHOD FOR DRIVING OF LIQUID CRYSTAL DISPLAY DEVICE}

1 is a view schematically showing a liquid crystal display device according to the prior art.

Figure 2 is a waveform diagram showing a data charging section of the prior art according to 60Hz driving.

Figure 3 is a waveform diagram showing a data charging section of the prior art according to 50Hz driving.

4 is a schematic view of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 5 is a block diagram illustrating a source output enable signal generator for supplying data to the liquid crystal panel shown in FIG. 4.

6 is a block diagram illustrating a source output enable width control unit illustrated in FIG. 5.

7 is a waveform diagram showing a data charging section of the present invention according to 60 Hz driving.

8 is a waveform diagram showing a data charging section of the present invention according to a 50 Hz drive.

<Explanation of Signs of Major Parts of Drawings>

2,12 LCD panel 4,14 Data driver

6,16: Gate Driver 8,18: Timing Controller

50: SOE generation unit 52: reference SOE generation unit

54: SOE width control section 56: SOE width setting section

60: phase detector 62: converter

64: pulse width control signal generator

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an image display device, and more particularly, to a driving device and a driving method of a liquid crystal display device which can prevent a deterioration in image quality by making the data charging section the same even if the frame frequency varies.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELDs), and vacuum fluorescents (VFDs) have been developed. Various flat panel display devices have been studied, and some of them are already used as display devices in various devices.

Referring to FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 2 including a liquid crystal cell formed in a region defined by a plurality of data lines DL1 through DLm and a plurality of gate lines GL1 through GLn; A data driver 4 for supplying an image signal to the data lines DL1 to DLm, a gate driver 6 for supplying scan pulses to the gate lines GL1 to GLn, a data driver 4 and a gate driver 6 ) Is provided with a timing controller 8.

The liquid crystal panel 2 has a liquid crystal formed between two glass substrates, and the data lines DL1 through DLm and the gate lines GL1 through GLn intersect on the lower glass substrate. The TFT formed at the intersection of the data lines DL1 to DLm and the gate lines GL1 to GLn supplies the data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to a scanning pulse. For this purpose, the gate electrodes of the TFTs are connected to the gate lines GL1 to GLn, and the source electrodes are connected to the data lines DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc.

The timing controller 8 arranges the input data RGB supplied from the outside so as to be suitable for driving the liquid crystal panel 2 and supplies the input data RGB to the data driver 4.

In addition, the timing controller 8 may control the gate control signals GSP, GSC, and GOE according to a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a frame frequency Vsync. ) To control the gate driver 6 and to generate data control signals SSP, SSC, SOE, and POL to control the data driver 4.

The gate driver 6 generates a shift register that sequentially generates a scan pulse, that is, a gate high pulse, according to the gate control signals GSP, GSC, and GOE supplied from the timing controller 8, and the voltage of the scan pulse is determined by the liquid crystal cell. And a level shifter for shifting to a level suitable for driving (Clc). The TFT is turned on in response to this scan pulse. When the TFT is turned on, the image signal on the data line is supplied to the pixel electrode of the liquid crystal cell Clc.

The data driver 4 converts the data signal Data aligned from the timing controller 8 into an image signal as an analog signal according to the data control signals SSP, SSC, SOE, and POL supplied from the timing controller 8. An image signal for one horizontal line is supplied to the data lines DL1 to DLm every one horizontal period in which scan pulses are supplied to the gate lines GL1 to GLn. That is, the data driver 4 selects a gamma voltage having a predetermined level according to the gray value of the data signal Data, and supplies the selected gamma voltage to the data lines DL1 to DLm. At this time, the data driver 4 inverts the polarity of the image signal according to the polarity control signal POL.

As such, the liquid crystal display uses an inversion method to prevent degradation of the liquid crystal cells and to improve image quality. The liquid crystal display has a problem in that power consumption is high because the polarity of the image signal is reversed to the positive or negative polarity according to the inversion method.

Accordingly, the conventional liquid crystal display reduces power consumption by driving the frame frequency at a frame frequency of 50 Hz instead of the usual 60 Hz. However, if the frame frequency is changed to 60 Hz or less, poor image quality such as flicker and wave noise may occur. This is because the data charging section according to the frame frequency of 60 Hz and the data charging section according to the frame frequency of 60 Hz are different.

Specifically, when the liquid crystal panel 2 having a resolution of 1920x1080 is driven at a frame frequency of 60Hz, one horizontal section H becomes 1 / (60Hzx1080), thereby being 15.4 GHz.

When the liquid crystal panel 2 having a resolution of 1920 x 1080 is driven at a frame frequency of 50 Hz, one horizontal section H becomes 1 / (50 Hz x 1080), thereby becoming 18.5 Hz.

On the other hand, the data driver 4 outputs the image signal converted in the row section of the source output enable signal SOE to each data line DL. In this case, the high section of the source output enable signal SOE is set to a constant width, and the low section varies according to the frame frequency.

As shown in FIG. 2, when the liquid crystal panel 2 is driven at a frame frequency Vsync of 60 Hz, the source output enable signal SOE at the time of polling the horizontal sync signal Hsync in one horizontal section H is performed. 1 horizontal section (H) excluding the section (t1) up to the polling time and the section (t2) from the rising time of the gate output enable (GOE) to the polling time of the horizontal synchronization signal (Hsync) is the data charging period ( 1H-t1-t2) (hatched area).

Similarly, as shown in FIG. 3, when the liquid crystal panel 2 is driven at a frame frequency Vsync of 50 Hz, the source output enable signal SOE at the time when the horizontal synchronization signal Hsync is polled in one horizontal section H. FIG. 1 horizontal section (H) excluding the section (t1) up to the polling time and the section (t2) from the rising time of the gate output enable (GOE) to the polling time of the horizontal synchronization signal (Hsync) is the data charging period ( 1H-t1-t2) (hatched area).

As a result, in the conventional liquid crystal display, when the frame frequency is changed from 50 Hz to 60 Hz, the data charging section is changed according to the changed frame frequency, thereby degrading image quality.

Accordingly, an object of the present invention is to provide a driving apparatus and a driving method of a liquid crystal display device which can prevent the deterioration of image quality by making the data charging section the same even if the frame frequency is variable.

A driving device of a liquid crystal display according to an embodiment of the present invention for achieving the above object is a liquid crystal panel including a liquid crystal cell formed in a region defined by a plurality of data lines and a plurality of gate lines, and the data line Generating a data control signal including a data driver for supplying an image signal to each of them, a gate driver for supplying scan pulses to the gate lines, and a source output enable signal having a width varying according to a frame frequency. And a timing controller for controlling the gate driver by generating a gate control signal while controlling the driver.

A driving method of a liquid crystal display according to an exemplary embodiment of the present invention is a method of driving a liquid crystal panel including a liquid crystal cell formed in a region defined by a plurality of data lines and a plurality of gate lines, the width of which varies depending on the frame frequency. Generating a data control signal and a gate control signal including a source output enable signal, supplying a scan pulse to the gate line according to the gate control signal, and synchronizing the scan pulse with the data control signal And converting the input data into an image signal and supplying the input data to the data line.

The varying of the source output enable signal may include generating a reference source output enable signal using a synchronization signal supplied from an external source, and generating a pulse width control signal by detecting a phase difference between a reference frequency and the frame frequency. And generating a source output enable signal by setting a pulse width of the reference source output enable signal according to the pulse width control signal.

The generating of the pulse width control signal may include generating a phase detection signal by detecting a phase difference between the frame frequency and the reference frequency, generating a pulse voltage corresponding to the phase detection signal, and generating the pulse voltage. And generating a pulse width control signal in comparison with the plurality of reference voltages.

The generating of the pulse voltage may include generating the pulse voltage corresponding to the phase detection signal by integrating the phase detection signal.

The generating of the source output enable signal may include setting a pulse width of the source output enable signal by varying a rising time of the reference source output enable signal according to the pulse width control signal.

The reference frequency is characterized in that 50Hz or 60Hz.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

4 is a schematic view of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel including liquid crystal cells formed in regions defined by a plurality of data lines DL1 through DLm and a plurality of gate lines GL1 through GLn. 12, a data driver 14 for supplying an image signal to each of the data lines DL1 to DLm, a gate driver 16 for supplying scan pulses to the gate lines GL1 to GLn, and a frame frequency. The data driver 14 is controlled by generating a data control signal SSP, SSC, POL, or SOE including a source output enable signal SOE whose width varies according to Vsync. ) Is provided with a timing controller 18.

The liquid crystal panel 12 has a liquid crystal formed between two glass substrates, and the data lines DL1 through DLm and the gate lines GL1 through GLn intersect on the lower glass substrate. The TFT formed at the intersection of the data lines DL1 to DLm and the gate lines GL1 to GLn supplies the data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to a scanning pulse. For this purpose, the gate electrodes of the TFTs are connected to the gate lines GL1 to GLn, and the source electrodes are connected to the data lines DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc.

The timing controller 18 arranges the input data RGB, which is supplied from the outside, to the data driver 14 in alignment with the driving of the liquid crystal panel 12.

In addition, the timing controller 18 may control the gate control signals GSP, GSC, and GOE according to a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a frame frequency Vsync. ) To control the gate driver 16, and generate data control signals SSP, SSC, SOE, and POL to control the data driver 4.

Here, the source output enable signal SOE of the data control signals SSP, SSC, SOE, and POL has a variable width according to the frame frequency Vsync.

To this end, the timing controller 18 includes an SOE generator 50 for generating a source output enable signal SOE according to the frame frequency Vsync shown in FIG. 5.

The SOE generator 50 generates a reference SOE for generating a reference source output enable signal Ref_SOE according to a dot clock DCLK, a data enable signal DE, a horizontal sync signal Hsync, and a frame frequency Vsync. The unit 52, the SOE width control unit 54 for detecting the phase difference between the frame frequency Vsync and the reference frequency Fref to generate the pulse width control signal WCS, and the reference according to the pulse width control signal WCS. And a SOE width setting unit 56 for setting a pulse width of the source output enable signal Ref_SOE to generate a source output enable signal SOE.

The reference SOE generation unit 52 has a reference source output enable signal having a pulse width of a high state set according to the dot clock DCLK, the data enable signal DE, the horizontal synchronization signal Hsync, and the frame frequency Vsync. Ref_SOE is generated and supplied to the SOE width setting unit 56.

As illustrated in FIG. 6, the SOE width control unit 54 detects a phase difference between the frame frequency Vsync and the reference frequency Fref to generate a phase detection signal PDS, and a phase detection signal ( The converter 62 generating the pulse voltage Vw corresponding to the PDS, and the pulse width for generating the pulse width control signal WCS by comparing the pulse voltage Vw with the plurality of reference voltages Vref1 to Vrefn. The control signal generator 64 is provided.

The phase detector 60 generates a phase detection signal PDS corresponding to the phase difference between the two frequencies Vsync and Fref by comparing the phase of the frame frequency Vsync with the reference frequency Fref. At this time, the reference frequency (Fref) may be 60Hz or 50Hz, it will be assumed below 60Hz.

The phase detector 60 generates a phase detection signal PDS of a positive pulse corresponding to a positive phase difference when the frame frequency Vsync is greater than the reference frequency Fref, and in the opposite case, corresponds to a negative phase difference. A phase detection signal PDS of a negative pulse to be generated is generated.

The converter 62 generates a pulse voltage Vw corresponding to the phase detection signal PDS by integrating the phase detection signal PDS supplied from the phase detection unit 60 using a charge pump circuit (not shown).

For example, when the phase detection signal PDS is a positive pulse, the converter 62 pushes out a charge amount corresponding to a width corresponding to the positive pulse in the charge pump circuit, and outputs more charge to the capacitor to output a pulse voltage. Produces (Vw). In addition, when the phase detection signal PDS is a negative pulse, the converter 62 pulls the charge amount corresponding to the negative pulse width from the charge pump circuit to reduce the charge accumulated in the capacitor to generate the pulse voltage Vw. do.

The pulse width control signal generator 64 compares the pulse voltage Vw supplied from the converter 62 with a plurality of reference voltages Vref1 to Vrefn and compares the pulse width control signal WCS corresponding to the comparison result. It generates and supplies it to the SOE width setting part 56.

For example, assuming that the pulse width control signal generator 64 generates the pulse width control signal WCS by comparing the pulse voltage Vw with the first to third reference voltages Vref3, the pulse voltage ( When Vw is equal to or less than the first reference voltage Vref1, the first pulse width control signal WCS is generated, and the pulse voltage Vw is between the first reference voltage Vref1 and the second reference voltage Vref2. In this case, the second pulse width control signal WCS is generated, and when the pulse voltage Vw is between the second reference voltage Vref2 and the third reference voltage Vref3, the third pulse width control signal WCS is generated. do.

In FIG. 5, the SOE width setting unit 56 is supplied from the reference SOE generation unit 52 according to the pulse width control signal WCS supplied from the pulse width control signal generation unit 64 of the SOE width control unit 54. The pulse width of the reference source output enable signal Ref_SOE is set and supplied to the data driver 14. That is, the SOE width setting unit 56 varies the rising time of the reference source output enable signal Ref_SOE according to the pulse width control signal WCS, so that the source output enable signal SOE corresponding to the frame frequency Vsync is changed. Is supplied to the data driver 14.

As such, when the reference frequency Fref is set to 60 Hz and the input frame frequency Vsync is 60 Hz, the SOE generator 50 has a reference frequency Fref and the frame frequency Vsync as zero. Therefore, as illustrated in FIG. 7, the data driver 14 receives the source output enable signal SOE having the same first pulse width W1 as the first pulse width W1 of the reference source output enable signal Ref_SOE. To feed.

On the other hand, when the reference frequency (Fref) is set to 60 Hz and the input frame frequency (Vsync) is 50 Hz, the SOE generator 50 has a higher reference frequency (Fsync) than the reference frequency (Fref). The rising time of the reference source output enable signal Ref_SOE is varied as shown in FIG. 8 according to the pulse width control signal WCS corresponding to the positive phase difference between Fref and the frame frequency Vsync. That is, the SOE generation unit 50 performs the first pulse of the reference source output enable signal Ref_SOE so that the data charging section according to the frame frequency Vsync of 50 Hz is the same as the data charging section according to the frame frequency Vsync of 60 Hz. The width W1 is varied to supply the source output enable signal SOE having the second pulse width W2 to the data driver 14.

In FIG. 4, the gate driver 16 includes a shift register that sequentially generates scan pulses, that is, gate high pulses, according to gate control signals GSP, GSC, and GOE supplied from the timing controller 18. And a level shifter for shifting the voltage to a level suitable for driving the liquid crystal cell Clc. The TFT is turned on in response to this scan pulse. When the TFT is turned on, the image signal on the data line is supplied to the pixel electrode of the liquid crystal cell Clc.

The data driver 14 converts the data signal Data arranged from the timing controller 18 into an image signal as an analog signal according to the data control signals SSP, SSC, SOE, and POL supplied from the timing controller 18. An image signal for one horizontal line is supplied to the data lines DL1 to DLm every one horizontal period in which scan pulses are supplied to the gate lines GL1 to GLn. That is, the data driver 14 selects a gamma voltage having a predetermined level according to the gray value of the data signal Data, and supplies the selected gamma voltage to the data lines DL1 to DLm. At this time, the data driver 14 inverts the polarity of the image signal according to the polarity control signal POL.

As described above, in the driving apparatus and driving method of the liquid crystal display according to the exemplary embodiment, the rising time of the reference source output enable signal Ref_SOE is varied according to the frame frequency Vsync.

Therefore, the driving apparatus and driving method of the liquid crystal display according to the exemplary embodiment of the present invention can prevent deterioration in image quality by making the data charging period the same even when the frame frequency Vsync is changed.

On the other hand, it will be understood by those skilled in the art that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, the driving apparatus and driving method of the liquid crystal display according to the exemplary embodiment of the present invention vary the pulse width of the source output enable signal according to the frame frequency so that the data charging period is the same even if the frame frequency is changed. The fall can be prevented.

Claims (12)

A liquid crystal panel comprising a liquid crystal cell formed in a region defined by a plurality of data lines and a plurality of gate lines; A data driver for supplying an image signal to each of the data lines; A gate driver supplying scan pulses to the gate lines; And a timing controller for generating a data control signal including a source output enable signal having a variable width according to a frame frequency to control the data driver, and generating a gate control signal to control the gate driver. Driving device of the liquid crystal display device. The method of claim 1, The timing controller has an SOE generator for generating the source output enable signal. The SOE generation unit, A reference SOE generation unit for generating a reference source output enable signal using a synchronization signal supplied from an outside; A SOE width control unit for detecting a phase difference between a reference frequency and the frame frequency to generate a pulse width control signal; And an SOE width setting unit configured to generate the source output enable signal by setting a pulse width of the reference source output enable signal according to the pulse width control signal. The method of claim 2, The SOE width control unit, A phase difference detector for detecting a phase difference between the frame frequency and the reference frequency to generate a phase detection signal; A converter configured to generate a pulse voltage corresponding to the phase detection signal; And a pulse width control signal generator for generating a pulse width control signal by comparing the pulse voltage with a plurality of reference voltages. The method of claim 3, wherein And the converting unit integrates the phase detection signal to generate the pulse voltage corresponding thereto. The method of claim 3, wherein And the SOE width setting unit sets a pulse width of the source output enable signal by varying a rising time point of the reference source output enable signal according to the pulse width control signal. The method of claim 2, The reference frequency is a driving device of the liquid crystal display, characterized in that 50Hz or 60Hz. In the driving method of a liquid crystal panel comprising a liquid crystal cell formed in a region defined by a plurality of data lines and a plurality of gate lines, Generating a data control signal and a gate control signal including a source output enable signal whose width varies according to the frame frequency; Supplying a scan pulse to the gate line according to the gate control signal; And converting input data into an image signal according to the data control signal and supplying the input data to the data line so as to be synchronized with the scan pulse. The method of claim 7, wherein The step of varying the source output enable signal, Generating a reference source output enable signal using a synchronization signal supplied from an outside; Generating a pulse width control signal by detecting a phase difference between a reference frequency and the frame frequency; And generating the source output enable signal by setting a pulse width of the reference source output enable signal according to the pulse width control signal. The method of claim 8, Generating the pulse width control signal, Generating a phase detection signal by detecting a phase difference between the frame frequency and the reference frequency; Generating a pulse voltage corresponding to the phase detection signal; And generating a pulse width control signal by comparing the pulse voltage with a plurality of reference voltages. The method of claim 9, The generating of the pulse voltage may include generating the pulse voltage corresponding to the phase detection signal by integrating the phase detection signal. The method of claim 9, The generating of the source output enable signal may include setting a pulse width of the source output enable signal by varying a rising time of the reference source output enable signal according to the pulse width control signal. Method of driving the device. The method of claim 8, And the reference frequency is 50Hz or 60Hz.

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