KR101030542B1 - Apparatus for providing power of liquid crystal display and the method for providing power using the same - Google Patents

Abstract

The present invention relates to a power supply of a liquid crystal display device and a power supply method thereof, which can reduce power consumption. A decompression circuit for decompressing; A digital circuit device driven by the reduced first power supply voltage to process a digital signal; A DC-AC converter for receiving an external AC voltage and converting the same to a second power supply voltage; And a DC-DC converter for receiving a second power supply voltage from the AC-DC converter to reduce or boost the second power supply voltage.

LCD, Power supply voltage, DC-DC converter, Pressure reducing part, Power consumption

Description

Power supply of LCD and power supply method {APPARATUS FOR PROVIDING POWER OF LIQUID CRYSTAL DISPLAY AND THE METHOD FOR PROVIDING POWER USING THE SAME}

1 is a schematic block diagram of a conventional liquid crystal display device

2 is a block diagram showing a transmission path with respect to the power supply voltage of FIG.

3 is a schematic block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a block diagram illustrating a transmission path for first, second and third power supply voltages of FIG.

5 is a circuit diagram of the pressure reducing circuit of FIG.

* Explanation of symbols on the main parts of the drawings

110: system 111: interface circuit

112: timing controller 113: data driver

114: gate driver 115: liquid crystal panel

116: DC-DC converter 117: decompression circuit

200: AC-DC converter 500: external voltage power

The present invention relates to a liquid crystal display device, and more particularly, to a power supply device for a liquid crystal display device and a power supply method thereof, which can reduce power consumption.

As the information society develops, the demand for display devices is increasing in various forms.In recent years, liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), and vacuum fluorescent display (VFD) have been developed. Various flat panel display devices have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as a substitute for CRT (Cathode Ray Tube) for the use of mobile image display device because of the excellent image quality, light weight, thinness and low power consumption. In addition, it is being developed in various ways, such as a television for receiving and displaying broadcast signals, and a monitor of a computer.

As described above, although various technical advances have been made in order for the liquid crystal display device to serve as a screen display device in various fields, the task of improving the image quality as the screen display device has many advantages and disadvantages.

Therefore, in order to use a liquid crystal display device in various parts as a general screen display device, the key to development is how much high definition images such as high definition, high brightness, and large area can be realized while maintaining the characteristics of light weight, thinness, and low power consumption. It can be said.                         

Such a liquid crystal display device may be classified into a liquid crystal display panel displaying an image and a driving unit for applying a driving signal to the liquid crystal display panel, wherein the liquid crystal display panel has a space between two glass substrates bonded to each other. It consists of the injected liquid crystal layer.

Hereinafter, a liquid crystal display according to the related art will be described in detail with reference to the accompanying drawings.

1 is a schematic view of a conventional liquid crystal display

In the conventional liquid crystal display, as shown in FIG. 1, m × n liquid crystal cells Clc are arranged in a matrix type, m data lines D1 to Dm and n gate lines G1 to Gn. The liquid crystal panel 15 having vertical intersections and TFTs formed at intersections thereof, a data driver 13 for supplying data to the data lines D1 to Dm of the liquid crystal panel 15, and the gate line G1. To Gn), a gate driver 14 for supplying a scan signal, and a timing controller 12 for controlling the data driver 13 and the gate driver 14 using a synchronization signal from the interface circuit 11. And a DC-DC converter 16 for generating voltages supplied to the liquid crystal panel 15.

The system 10 supplies a vertical / horizontal synchronization signal, a clock signal, and data (RGB) to the interface circuit 11 through a low voltage differential signaling (LVDS) transmitter of a graphic controller. The VCC voltage is supplied to the digital circuit elements 11, 12, 13, 14 and the DC-DC converter 16 as the power supply voltage.

On the other hand, the liquid crystal panel 15 is a liquid crystal is injected between the two glass substrates. The data lines D1 to Dm and the gate lines G1 to Gn formed on the lower glass substrate of the liquid crystal panel 15 are perpendicular to each other. The TFT formed at the intersection of the data lines D1 to Dm and the gate lines G1 to Gn may read data on the data lines D1 to Dn in response to a scan signal from the gate lines G1 to Gn. Supply to the liquid crystal cell (Clc). For this purpose, the gate electrodes of the TFTs are connected to the corresponding gate lines G1 to Gn, and the source electrodes are connected to the corresponding data lines D1 to Dm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc.

Although not shown in the drawing, a black matrix layer, a color filter layer, and a common electrode are formed on the upper glass substrate of the liquid crystal panel 15. On the upper glass substrate and the lower glass substrate of the liquid crystal panel 15, a polarizing plate having an optical axis orthogonal to each other is attached, and an alignment layer for setting the pretilt angle of the liquid crystal is formed on the inner surface of the liquid crystal panel 15. In addition, a storage capacitor Cst is formed in each of the liquid crystal cells Clc of the liquid crystal panel 15. The storage capacitor Cst is formed between the pixel electrode of the liquid crystal cell Clc and the front gate line, or is formed between the pixel electrode of the liquid crystal cell Clc and the common electrode line (not shown) to form a voltage of the liquid crystal cell Clc. It keeps constant.

The data driver 13 converts the digital video data RGB into an analog gamma voltage corresponding to the gray scale value in response to the data control signal DDC from the timing controller 12 and converts the analog gamma voltage into the data. Supply to the lines D1 to Dm. The VCC voltage of 3.3 V is supplied as a power supply voltage to the data drive integrated circuit in which the data driver 13 is integrated.                         

The gate driver 14 sequentially supplies scan pulses to the gate lines G1 to Gn in response to the gate control signal GDC from the timing controller 12 to supply data. Select the horizontal line. The gate driver integrated circuit in which the gate driver 14 is integrated is supplied with a VCC voltage of 3.3 V as a power supply voltage.

The timing controller 12 controls a gate control signal (GDC) for controlling the gate driver 14 using a vertical / horizontal synchronization signal and a clock signal input from the graphic controller of the system 10 via the interface circuit 11. ) And a data control signal DDC for controlling the data driver 13.

The gate control signal GDC includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), and the data control. The signal DDC includes a source start pulse (GSP), a source shift clock (SSC), a source output signal (SOC), a polarity signal (POL), and the like. The timing controller 12 realigns the digital video data RGB inputted from the graphic controller of the system 10 via the interface circuit 11 and supplies the rearranged digital video data RGB to the data driver 13. The power supply voltage for driving the timing controller 12 is a VCC voltage of 3.3V input from the power supply of the system 10.

In addition, the VCC voltage is supplied to a power supply voltage of a phase lock loop (PLL) provided in the timing controller 12. The phase locked loop PLL compares a clock signal input to the timing controller 12 with a reference frequency generated from an oscillator (not shown) and adjusts the frequency of the clock signal by the error to adjust the digital video data RGB. Generates a clock signal for sampling

The interface circuit 11 includes a low voltage differential signaling (LVDS) receiver to reduce the voltage level and increase the frequency of signals input from the graphic controller of the system 10, thereby increasing the frequency between the system 10 and the timing controller 12. This reduces the number of signal wires required. The power supply voltage for driving the interface circuit 11 is a VCC voltage of 3.3 V input from the power supply of the system 10.

In order to reduce the electromagnetic interference (hereinafter referred to as EMI) caused by the high frequency component and the high voltage of the signal supplied from the interface circuit 11 to the timing controller 12, the interface circuit 11 and An EMI filter (not shown) is provided between the timing controllers 12.

On the other hand, the DC-DC converter 16 generates a voltage supplied to the liquid crystal panel 15 by increasing or reducing the VCC voltage of 3.3 V input from the power supply of the system 10 via a connector (not shown). do. To this end, the DC-DC converter 16 outputs an output switch element for switching the output voltage to an output terminal, and a pulse for boosting or reducing the output voltage by controlling the duty ratio or frequency of the control signal of the output switch element. Pulse Width Modulator (PWM) or Pulse Frequency Modulator (PFM). The pulse width modulator increases the control signal duty ratio of the output switch element to increase the output voltage of the DC-DC converter 16 or lowers the duty ratio of the control signal of the output switch element to the DC-DC converter 16. Decrease the output voltage.

The pulse frequency modulator increases the control signal frequency of the output switch element to increase the output voltage of the DC-DC converter 16 or lowers the frequency of the output switch element to lower the output voltage of the DC-DC converter 16. .

Here, the output voltage of the DC-DC converter 16 is a VDD voltage of 6V or more, a gamma reference voltage (GMA1-10) of less than 10 steps, a VCOM voltage of 2.5 to 3.3V, a VGH voltage of 15V or more, and a VGL of -4V or less. Voltage. The gamma reference voltages GMA1 to 10 are voltages generated by the divided voltage of the VDD voltage. The VDD voltage and the gamma reference voltage are supplied to the data driver 13 as an analog gamma voltage. The VCOM voltage is a voltage supplied to the common electrode formed in the liquid crystal panel 15 via the data driver 13. The VGH voltage is supplied to the gate driver 14 as the high logic voltage of the scan pulse set above the threshold voltage of the TFT and the VGL voltage is supplied to the gate driver 14 as the low logic voltage of the scan pulse set to the OFF voltage of the TFT. .

However, the conventional liquid crystal display device has a disadvantage in that power consumption of the driving circuits of the system 10 and the liquid crystal display device is high because the voltage input from the system 10 to the driving circuits of the liquid crystal display device is relatively high as 3.3V.

In addition, the DC-DC converter 16 decompresses or boosts the voltage of 3.3V to provide a VDD voltage of 6V or more, a gamma reference voltage of less than 10 steps (GMA1 to 10), a VCOM voltage of 2.5 to 3.3V, and a VGH of 15V or more. Since various voltages, such as voltage and VGL voltage of -4V or less, must be outputted, there is a problem in that power consumption increases due to the large voltage width reduction and boost.

The present invention has been made to solve the above problems, the power supply voltage having a large voltage voltage by receiving an AC voltage from a decompression circuit capable of reducing the power supply voltage from the system and an external voltage power supply By supplying the voltage provided from the AC-DC converter to the DC-DC converter having an AC-DC converter that can be converted to the power supply, a power supply device and a power supply method of the liquid crystal display device that can reduce the power consumption The purpose is to provide.

A power supply device for a liquid crystal display device according to the present invention for achieving the above object, in the power supply device for supplying power to the driving circuit portion of the liquid crystal panel, pressure reduction for reducing the first power voltage from the system Circuits; A digital circuit device driven by the reduced first power supply voltage to process a digital signal; A DC-AC converter for receiving an external AC voltage and converting the same to a second power supply voltage; And a DC-DC converter configured to receive a second power supply voltage from the AC-DC converter to reduce or boost the second power supply voltage.

Here, the first power supply voltage input from the system is characterized in that more than 3.0V.

A battery which receives a second power supply voltage from the AC-DC converter and stores a third power supply voltage; And a switch for selectively switching any one of the second power supply voltage of the AC-DC converter and the third power supply voltage of the battery to output the DC-DC converter.

The AC-DC converter is characterized by using a system adapter of the liquid crystal display.

The digital circuit device includes an interface circuit for receiving a synchronization signal, a clock signal, and digital video data from the system, a data driver circuit for supplying data to the liquid crystal panel, and a gate driver for supplying scan pulses to the liquid crystal panel. And a timing controller for controlling the data driver and the gate driver by using a synchronization signal and a clock signal from the interface circuit.

The reduced first power supply voltage is characterized in that less than 3.0V.

The DC-DC converter is characterized by generating a VDD voltage of 6V or more, a gamma reference voltage generated by dividing the VDD voltage, and a VCOM voltage of 2.5 to 3.3V.

The decompression circuit includes an output switch element; A control signal generator for generating a control signal of the output switch element; And a pulse width modulator for adjusting the duty ratio of the control signal.

In addition, the power supply method of the liquid crystal display according to the present invention, the step of reducing the first power supply voltage from the system, and supplying the reduced first power supply voltage to the digital circuit elements for processing the digital signal Wow; Converting an external voltage into a second power supply voltage or a third power supply voltage; And depressurizing or boosting the second voltage source or the third source voltage to apply one of the reduced or boosted second and third power source voltages to the digital circuit elements.

Here, the first power supply voltage input from the system is characterized in that more than 3.0V.

The reduced first power supply voltage is characterized in that less than 3.0V.

Hereinafter, a power supply device of a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a schematic block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 4 is a block diagram showing a transmission path with respect to the first, second, and third power voltages of FIG.

In the liquid crystal display according to the exemplary embodiment of the present invention, as shown in FIGS. 3 and 4, the liquid crystal panel 115 is configured to supply data to the liquid crystal panel 115 and the data lines D1 to Dm of the liquid crystal panel 115. The data driver 113 and the gate driver using a data driver 113, a gate driver 114 for supplying scan signals to the gate lines G1 to Gn, and a synchronization signal from the interface circuit 111. A timing controller 112 for controlling the 114 and a decompression circuit 117 for depressurizing the first power voltage VCC1 supplied from the system 110; AC-DC converter 200 for receiving an AC voltage from an external voltage power supply 500 and converting the AC voltage into a second power supply voltage VCC2, and a second output from the AC-DC converter 200. It is configured to include a DC-DC converter 116 for applying a power supply voltage (VCC2) to reduce or increase the pressure.

In addition, as shown in FIG. 4, the liquid crystal display device includes a battery 300 that receives a second power supply voltage VCC2 from the AC-DC converter 200 and is charged with a third power supply voltage VCC3. ; Selectively switching one of the second power supply voltage VCC2 of the AC-DC converter 200 and the third power supply voltage VCC3 of the battery 300 to output the DC-DC converter 116 to the DC-DC converter 116. It can be configured to further include a switch (S).

The system 110 supplies the vertical / horizontal synchronization signal, the clock signal, and the data RGB to the interface circuit 111 through the LVDS transmitter of the graphic controller.

Meanwhile, the liquid crystal panel 115 has the same structure and configuration as a conventional liquid crystal panel, and thus description thereof will be omitted.

The data driver 113 converts the digital video data RGB into an analog gamma voltage corresponding to the gray scale value in response to the data control signal DDC from the timing controller 112, and converts the analog gamma voltage into an analog gamma voltage. Supply to data lines D1 to Dm.

Here, the CVCC voltage of 3.3 V or less than 3.0 V, which is the first power supply voltage VCC1 decompressed through the decompression circuit 117, is supplied to the data driver integrated circuit in which the data driver 113 is integrated. Therefore, the data driver 113 may be driven at a low voltage of less than 3.0V.                     

The gate driver 114 sequentially supplies scan pulses to the gate lines G1 to Gn in response to the gate control signal GDC from the timing controller 112 to supply data. Select the horizontal line. The gate driver integrated circuit in which the gate driver 114 is integrated is supplied with a CVCC voltage of less than 3.3V or 3.0V, which is the first power supply voltage VCC1 decompressed through the decompression circuit 117. Thus, the gate driver 114 may be driven at a low voltage of less than 3.0V.

In addition, the timing controller 112 controls the gate driver 114 to control the gate driver 114 using a vertical / horizontal synchronization signal and a clock signal input from the graphic controller of the system 110 via the interface circuit 111. A data control signal DDC for controlling the signal GDC and the data driver 113 is generated. The timing controller 112 rearranges the digital video data RGB inputted from the graphic controller of the system 110 via the interface circuit 111 and supplies the rearranged digital video data RGB to the data driving circuit 113.

Here, the power supply voltage for driving the timing controller 112 is a CVCC voltage of 3.3V or less than 3.0V, which is the first power supply voltage VCC1 decompressed through the decompression circuit 117. In addition, the CVCC voltage is supplied to a power supply voltage of a phase locked loop (PLL) installed in the timing controller 112. Therefore, the timing controller 112 may be driven at a low voltage of less than 3.0V.

The interface circuit 111, including the LVDS receiver, reduces the voltage level of the signals input from the graphic controller of the system 110 and increases the frequency so that the number of signal wirings required between the system 110 and the timing controller 112 is increased. Will be reduced. The interface circuit 111 is supplied with a CVCC voltage of 3.3V or less than 3.0V, which is the first power supply voltage VCC1 decompressed through the decompression circuit 117. Therefore, the interface circuit 111 may be driven at a low voltage of less than 3.0V. In addition, the interface circuit 111 may be embedded in the timing controller 112.

As described above, the decompression circuit 117 decompresses the VCC voltage of 3.3 V supplied from the power supply of the system 110 to less than 3.0 V so that the interface circuit 111, the timing controller 112, the data driving circuit 113, and the like. Like the gate driving circuit 114, a digital signal is input to generate a power supply voltage of a digital circuit element that recognizes a high logic value and a low logic value of the digital signal.

To this end, the decompression circuit 117, as shown in Figure 5, the output switch element (Q) for switching the output voltage and the duty of the control signal supplied to the control terminal of the output switch element (Q) A pulse width modulator 151 for controlling the ratio to reduce the output voltage, an oscillator 153 for generating a reference frequency, and a PWM controller 152 for controlling the pulse width modulator 151 are provided.

Here, the pulse width modulator 151 controls the on / off timing of the switch element Q by adjusting the duty ratio of the reference frequency input from the oscillator 153 under the control of the PWM controller 152 to control the voltage of the CVCC voltage. Adjust the level. When the duty ratio of the control signal is lowered, the voltage level of the CVCC voltage is lowered.                     

The PWM controller 152 controls the pulse width modulator 151 by supplying a control signal indicating the duty ratio to the pulse width modulator 151.

The capacitor C is connected to the output terminal to store the CVCC voltage and suppress the voltage variation of the output terminal.

Meanwhile, the DC-DC converter 116 selectively selects the second power voltage VCC2 or the third power voltage VCC3 output from the AC-DC converter 200 or the battery 300 through the switch S. FIG. The second power supply voltage VCC2 or the third power supply voltage VCC3 is boosted or decompressed to receive a VDD voltage of 6 V or more, a VCOM voltage of 2.5 to 3.3 V, a gamma reference voltage GMA1 to 10, or 15 V or more. Outputs a VGH voltage and a VGL voltage of -4V or less.

Here, the second power supply voltage VCC2 output from the AC-DC converter 200 is about 15V, and the third power supply voltage VCC3 stored in the battery 300 has about 3V.

Accordingly, the VDD voltage of 6V or more, the VCOM voltage of 2.5 to 3.3V, the gamma reference voltages GMA1 to 10, and the VGL voltage of -4V or less may reduce the power supply voltage output from the AC-DC converter 200, or It is used by stepping up, and the VGH voltage of 15V or more is boosted by using the third power supply voltage VCC3 stored in the battery 300, and is consumed by reducing the decompression and step-up width of the DC-DC converter 116. Power can be reduced.

Here, the DC-DC converter 116 is an output switch element for switching the output voltage to the output terminal, and a pulse width modulator for boosting or reducing the output voltage by controlling the duty ratio or frequency of the control signal of the output switch element (PWM) or pulse frequency modulator (PFM).

The VDD voltage, the VCOM voltage, the gamma reference voltages GMA1 to 10, the VGH voltage, and the VGL voltage output from the DC-DC converter 116 are voltages supplied to the liquid crystal panel 115.

That is, the VDD voltage is a voltage corresponding to the highest gray level or the lowest gray level of data and is supplied to the pixel electrode of the liquid crystal cell Clc via the data lines D1 to Dm. The gamma reference voltages GMA1 to 10 are voltages corresponding to intermediate gray levels of data and are supplied to the pixel electrodes of the liquid crystal cell Clc via the data lines D1 to Dm. The VGH voltage is supplied to each gate line G1 to Gn of the liquid crystal panel 5 as the high logic voltage of the scan pulse, and the VGL voltage is the low logic voltage of the scan pulse to each gate line of the liquid crystal panel 5. G1 to Gn).

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The power supply of the liquid crystal display device according to the present invention described above has the following effects.

 In the liquid crystal display according to the present invention, a power supply voltage of 3.3V is reduced to less than 3.0V, and the reduced power supply voltage is supplied to digital circuit elements for processing digital signals or a voltage of less than 3.0V generated from the power supply of the system. Is supplied to the digital circuit elements and the DC-DC converter using the power supply voltage of the liquid crystal display device. Therefore, the power supply method and apparatus of the liquid crystal display according to the present invention can drive the liquid crystal display with low power consumption as the power supply voltage is lowered.

In addition, by providing a voltage having various widths to the DC-DC converter using an external voltage power supply, power consumption due to the step-up and pressure reduction of the DC-DC converter can be reduced.

Claims (11)

In the power supply for supplying power to the driving circuit portion of the liquid crystal panel, A decompression circuit for depressurizing a first power supply voltage from the system; A digital circuit device driven by the reduced first power supply voltage to process a digital signal; An AC-DC converter for receiving an external AC voltage and converting the same to a second power supply voltage; A battery which receives a second power supply voltage from the AC-DC converter and stores a third power supply voltage; A switch for selectively switching any one of a second power supply voltage of the AC-DC converter and a third power supply voltage of the battery; And a DC-DC converter configured to receive one of the second voltage power and the third power voltage output from the switch to reduce or boost the voltage. The method of claim 1, The power supply of the liquid crystal display device, characterized in that the first power supply voltage input from the system is more than 3.0V. delete The method of claim 1, And the AC-DC converter uses a system adapter of the liquid crystal display device. The method of claim 1, The digital circuit device, An interface circuit for receiving a synchronization signal, a clock signal, and digital video data from the system; A data driving circuit for supplying data to the liquid crystal panel; A gate driver for supplying scan pulses to the liquid crystal panel; And a timing controller for controlling the data driver and the gate driver using the synchronization signal and the clock signal from the interface circuit. The method of claim 1, Wherein the reduced first power supply voltage is less than 3.0V. The method of claim 1, The DC-DC converter is configured to generate a VDD voltage of 6 V or more, a gamma reference voltage generated by dividing the VDD voltage, and a VCOM voltage of 2.5 to 3.3 V. The method of claim 1, The decompression circuit includes an output switch element; A control signal generator for generating a control signal of the output switch element; And a pulse width modulator for adjusting the duty ratio of the control signal. Reducing the first power supply voltage from the system; Supplying the reduced first power supply voltage to digital circuit elements for processing a digital signal; Converting an external voltage into a second power supply voltage; Supplying the second power voltage to a battery and storing a third power voltage in the battery; Switching one of the second power voltage and the third power voltage by using a switch to output the switching power; Decompressing or boosting any one of the second voltage power source and the third power source voltage output from the switch to apply any one of the reduced or boosted second voltage power source and the third power source voltage to the digital circuit elements. Power supply method of the liquid crystal display device comprising a. The method of claim 9, And a first power supply voltage input from the system is 3.0V or more. The method of claim 9, The reduced power supply voltage is less than 3.0V power supply method of the liquid crystal display device.

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