KR101097643B1 - Liquid crystal display device and method for driving the same - Google Patents

Abstract

A liquid crystal display device having improved image quality is disclosed.

A liquid crystal display of the present invention includes a control unit for generating first and second GOE signals having different periods; A gate driver configured to supply first and second scan signals having different widths in response to the first and second GOE signals; A data driver for supplying predetermined data; And a liquid crystal panel for displaying an image corresponding to the data.

Vertical 2-dot inversion method, data charging amount, GOE signal

Description

 Liquid crystal display device and method for driving the same

1 is a view showing a conventional liquid crystal display device.

FIG. 2 is a driving waveform diagram of the liquid crystal display shown in FIG.

3A and 3B illustrate polar patterns of data signals supplied to liquid crystal cells of a liquid crystal panel by a 2-dot inversion method.

4A and 4B are diagrams showing a horizontal line phenomenon by a 2-dot inversion driving method.

5 is a diagram illustrating a two-dot inversion liquid crystal display device according to an exemplary embodiment of the present invention.

FIG. 6 is a detailed circuit diagram of generating a shifted GOE signal using a GOE signal in the liquid crystal display shown in FIG. 5;

FIG. 7 is a generation waveform diagram and a GOE_B signal generation waveform diagram of the 2-dot inversion liquid crystal display shown in FIG. 5; FIG.

FIG. 8 is a driving waveform diagram of the liquid crystal display shown in FIG. 5;

Description of the Related Art [0002]

32: liquid crystal panel 34: gate driver                 

36: data driver 40: control unit

41: data alignment unit 42: timing controller

43: GOE generation unit 43a: First GOE generation unit

43b: second GOE generation unit 45: control signal generation unit

51: first D flip-flop 52: second D flip-flop

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having improved image quality and a driving method thereof.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. The liquid crystal display device includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

As shown in FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 2 in which liquid crystal cells are arranged in a matrix, and a gate driver for driving gate lines GL1 to GLn of the liquid crystal panel 2. (4), a data driver 6 for driving the data lines DL1 to DLn of the liquid crystal panel 2, a timing controller for controlling the gate driver 4 and the data driver 6 (10) is provided.

The liquid crystal panel 2 is formed at each intersection of the liquid crystal cells arranged in a matrix form and the gate lines GL1 to GLn and the data lines DL1 to DLm, and is connected to each of the liquid crystal cells. (TFT).

The thin film transistor TFT is turned on when the scan signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data lines DL1 to DLm to the liquid crystal cell. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate lines GL1 to GLn to maintain the pixel signal charged in the liquid crystal cell.

The liquid crystal cell is equivalently represented by a liquid crystal capacitor Clc, and includes a common electrode facing the liquid crystal and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell further includes a storage capacitor Cst so that the charged pixel signal is stably maintained until the next pixel signal is charged. The liquid crystal cell realizes gradation by adjusting light transmittance by varying an arrangement state of liquid crystal having dielectric anisotropy according to a pixel signal charged through a thin film transistor (TFT).

The gate driver 4 sequentially supplies the gate high voltage VGH to the gate lines GL1 to GLn in response to the gate control signals GSP, GSC, and GOE from the timing controller 10. Accordingly, the gate driver 4 causes the thin film transistor TFT connected to the gate lines GL1 to GLn to be driven in units of the gate lines GL1 to GLn.

The data driver 6 outputs a pixel signal of one line for each horizontal section H1, H2, H3 .. in response to the data control signals SSP, SSC, SOE, and POL from the timing controller 10. Supply to the data lines DL1 to DLm. In particular, the data driver 6 converts the digital pixel data R, G and B from the timing controller 10 into an analog pixel signal and supplies the same.

As such, the liquid crystal display uses an inversion method to prevent degradation of the liquid crystal cells and to improve image quality. In particular, a vertical two-dot inversion scheme as shown in FIGS. 3A and 3B is used.

3A and 3B illustrate a pixel signal polarity supplied to liquid crystal cells in a vertical 2-dot inversion scheme divided into odd frames and even frames.

In the odd and even frames shown in Figs. 3A and 3B, the vertical two-dot inversion scheme changes the polarity of the pixel signal in the unit of dots in the horizontal direction as in the conventional dot inversion scheme, while in the vertical direction. You can see that it is driven to change by 2 dots. The vertical two-dot inversion method has the advantage that the flicker phenomenon is reduced in comparison with the dot inversion method in a commercial screen driven at a frame frequency of 60 Hz, but has a problem in that horizontal lines are generated according to the luminance difference every two scanning lines. .

4A and 4B illustrate horizontal lines in the odd and even frames, which are represented by the vertical two-dot inversion method.

4A and 4B, when the polarity of the liquid cell is changed in units of 2 dots vertically, a horizontal phenomenon occurs due to a luminance difference between the odd scan lines G1 and the even scan lines G2. This is because the charging characteristics of the pixel signal Vd in the even-numbered scan line G2 to which the odd-numbered scan line is adjacent and the data voltage signal of the same polarity supplied thereto are different from each other in the vertical 2-dot inversion scheme.                         

In detail, as illustrated in FIG. 2, the pixel signal supplied to the data line DL in the radix horizontal periods H1, H3, H5 .. is relatively long as the polarity of the pixel signal of the previous horizontal period is opposite to that of the previous horizontal period. It is charged with rising (or falling). However, the pixel signal supplied to the data line DL in the even horizontal periods H2, H4, H6 .. maintains the same polarity as the pixel signal of the previous horizontal period and is thus charged with almost no rising (or falling) period. As described above, the conventional vertical two-dot inversion driving method has the same polarity and the charging amount for the same luminance is changed according to different charging conditions of the pixel signals supplied to the odd scan line and the even scan line. Specifically, the pixel signal charged in the even scan line has a larger charging amount with a relatively long rise (fall) period and almost no rise (fall) period than the pixel signal charged in the odd scan line. As a result, a horizontal line phenomenon occurs in which the even scan line is brighter than the odd scan line, thereby degrading the image quality.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of preventing the horizontal line phenomenon by equalizing the odd-numbered data charging amount and the even-numbered data charging amount.

According to a preferred embodiment of the present invention for achieving the above object, the liquid crystal display device includes a control unit for generating the first and second GOE signals having different periods; A gate driver configured to supply first and second scan signals having different widths in response to the first and second GOE signals; A data driver for supplying predetermined data; And a liquid crystal panel for displaying an image corresponding to the data.

According to another preferred embodiment of the present invention, a method of driving a liquid crystal display device comprises the steps of: generating first and second GOE signals having different periods; Supplying first and second scan signals having different widths in response to the first and second GOE signals; Supplying predetermined data; And displaying an image corresponding to the data.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

5 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 5, the liquid crystal display according to the present invention generates a GSP, a GSC, a GOE, etc. (hereinafter, referred to as a first control signal), and generates an SSP, SSC, SOE, and POL. The first GOE signal GOE_A and the second GOE signal GOE_B having different periods from each other using the control signal generation unit 45 and the GOE which generate a back light (hereinafter referred to as a second control signal). A control unit 40 including a GOE generation unit 43 for generating a plurality of gates, a gate driver 34 for supplying scan signals having different widths in response to the first control signal and the first and second GOE signals; And a data driver 36 for supplying a data signal whose polarity is inverted in units of 2 dots in response to the second control signal, and a liquid crystal panel 32 for displaying the data signal.

In the liquid crystal panel 32, gate lines GL1 to GLn and data lines DL1 to DLm are arranged to cross each other, and intersections of the gate lines GL1 to GLn and the data lines DL1 to DLm are arranged. Liquid crystal cells provided are positioned.                     

The data driver 36 shifts the source start pulse SSP according to the source shift clock SSC to generate a sampling signal. Subsequently, the data driver 16 sequentially inputs and latches the video data signals R, G, and B in predetermined units in response to the sampling signal. The data driver 36 converts the latched pixel data R, G, and B for one line into an analog pixel signal and supplies the same to the data lines DL1 through DLm. In this case, the data driver 36 converts the positive and negative pixel signals in response to the polarity control signal POL. For example, as illustrated in FIG. 8, the data driver 36 inverts the polarity of the pixel signal Source Output in a vertical two-dot inversion scheme in response to the polarity control signal POL that is polarized inverted every two horizontal periods. To be. The data driver 36 supplies the pixel signals to the data lines DL through DLm only during the enable period under the control of the source output enable signal SOE as shown in FIG. 8.

The gate driver 34 sequentially supplies scan signals (ie, gate high voltages) to the gate lines GL1 to GLm in response to the first control signals GSP, GSC, and GOE from the controller 40. do. Accordingly, the gate driver 34 causes the thin film transistor TFT connected to the gate lines GL1 to GLn to be driven in units of the gate lines GL1 to GLn.

Specifically, the gate driver 34 shifts the gate start pulse GSP according to the gate shift pulse GSC and is output by the control of the gate output enable signal GOE. In response to the gate shift pulse GSP, the gate driver 34 scans a gate signal GL (ie, a gate high) at a corresponding gate line GL for each horizontal section H1, H2, H3 .. as shown in FIG. 8. Voltage VGH). In this case, the gate driver 34 supplies the gate high voltage VGH under the control of the GOE as shown in FIG. 8. The gate driver 34 supplies the gate low voltage VGL to the gate lines GL1 through GLn in the remaining periods in which the scan signal (that is, the gate high voltage VGH) is not supplied. The gate driver 34 supplies the gate low voltage VGL to the gate line GL0 formed at the uppermost side for the storage capacitor Cst of the first scan line.

The control unit 40 aligns the digital data signals R, G, and B, and supplies the data alignment unit 41 to the data driver 36, the first control signals GSP, GSC, GOE, and the second. And a timing controller 42 for generating control signals SOE, SSC, SSP, and POL. The timing controller 42 includes a control signal generator 45 for generating the first control signals GSP, GSC, and GOE and the second control signals SOE, SSC, SSP, and POL, and the control signal generator. And a GOE generator 43 for generating a first GOE signal and a second GOE signal by using the GOE signal generated at 45.

The GOE generation unit 23 includes a first GOE generation unit 43a for generating the first GOE signal GOE_A and a second GOE generation unit 43b for generating the second GOE signal GOE_B. .

As shown in (1) of FIG. 7, the first GOE generation unit 43a multiplies the first masking signal by the GOE signal generated by the control signal generation unit 45 and the signal values of the first GOE generation unit 43 are high. All outputs are low except for. For example, when the GOE signal and the first masking signal are High, the first GOE signal GOE_A outputs High. In addition, when the GOE signal is High and the first masking signal is Low, the first GOE signal GOE_A may be output low. Therefore, the first GOE signal GOE_A is output every odd number.

As shown in (2) of FIG. 7, the second GOE generation unit 43b shifts the GOE signal generated by the control signal generation unit 45 to a certain degree, and then the second masking signal and the shifted signal. Multiply the GOE signal to make all outputs low except when the signal values are high. For example, when the GOE signal and the second masking signal are High, the second GOE signal GOE_A outputs High. In addition, when the GOE signal is High and the second masking signal is Low, the second GOE signal GOE_B may be output low.

As shown in (2) of FIG. 7, the second GOE signal GOE_B generated by the shift GOE generation unit 43b is configured to generate the GOE signal generated by the control signal generation unit 45. It may be set to be shifted by a predetermined time from one GOE signal GOE_A. To this end, the second GOE generation unit 43b shifts the GOE signal generated by the control signal generation unit 45 by a predetermined time. In this case, it is preferable that the first masking signal and the second masking signal have opposite polarities. Therefore, the second GOE signal GOE_B is output every even-numbered second.

As shown in FIG. 6, the second GOE generator 43b shifts the GOE signal generated by the control signal generator 45 using a D-flip flop. For example, if it is desired to shift by two clock signals, as shown in FIG. 6, the GOE signal generated by the control signal generator 45 is shifted by two clock signals using two D-flip flops. I can let you. When the first clock signal is applied to the first D-flop flop 51, the GOE signal generated by the control signal generator 45 is supplied to the input terminal of the first D-flip flop 51 and 1 is output to the output terminal. The GOE signal shifted by a clock is output. When the next second clock signal is applied to the second D flip-flop 52, the GOE signal output from the first D flip-flop 51 is input to an input terminal of the second D flip-flop 52. do. A GOE signal shifted by one clock is output to the output terminal of the second D flip-flop.

Using two D flip-flops, the GOE signal can be shifted by that clock.

In this case, the gate driver 34 has the first control signal (the GOE signal does not exist) from the control signal generator 45 and the odd-numbered and second signals from the first and second GOE generators 43a and 43b. The first GOE signal GOE_A and the second GOE signal GOE_B are supplied in the order of the even number.

The gate driver 34 generates a first scan signal in response to the first control signal GSP, GSC, etc., and the first GOE signal GOE_A, and the first control signal and the second GOE signal shifted to some extent. In response to GOE_B, a second scan signal is generated. The first and second scan signals generated in this way are sequentially supplied to the gate lines GL1 to GLn of the liquid crystal panel 32.                     

Widths of the first and second scan signals are different from each other. That is, the second scan signal is controlled by the shifted GOE signal, wherein the width of the shifted GOE second signal is equal to the width of the first GOE signal and is set to be shifted by a predetermined time. . Here, the width of the first GOE signal GOE_A output at every odd number and the second GOE signal GOE_B output at every even number is the same. As shown in FIG. 8, after the first GOE signal GOE_A is output, a period a before the second GOE signal GOE_B is output, and the second GOE signal GOE_B is output. Next, the period b before the first GOE signal GOE_A is output differs by a predetermined time.

FIG. 8 is a driving waveform diagram of the liquid crystal display shown in FIG. 5.

As shown in FIG. 8, data charged on each gate line due to the scan signal (Gate output) applied to the odd and even gate lines and the data signal (Source output) applied to the data lines. The same amount of charging can be implemented by improving the problems such as the horizontal line phenomenon.

The widths of the first GOE signal GOE_A output at every odd number and the second GOE signal GOE_B output at every even number are the same. Here, the second GOE signal GOE_B is generated by shifting the first GOE signal GOE_A by a predetermined time. Accordingly, the first GOE signal GOE_A and the second GOE signal GOE_B have different periods from each other. That is, the period (a) before the first GOE signal GOE_A is output and then the second GOE signal GOE_B and the second GOE signal GOE_B are output, followed by the first GOE. The period b before the signal GOE_A is output differs. This is because, as described above, the second GOE signal GOE_B is shifted by a predetermined time than the first GOE signal GOE_A using a D-flip flop. Therefore, although the widths of the first and second GOE signals GOE_A and GOE_B are the same, the period a and the second before the first GOE signal GOE_A is output and the second GOE signal GOE_B is output. The period b before the GOE signal GOE_B is output and the first GOE signal GOE_A is output is different from each other.

Accordingly, a first scan signal (ie, a gate) of the scan signals supplied to the gate driver 34 during the period a after the first GOE signal GOE_A is output and before the second GOE signal GOE_B is output. High voltage). The second scan signal (ie, gate) of the scan signals supplied to the gate driver 34 during the transition period b after the second GOE signal GOE_B is output and before the first GOE signal GOE_A is output. High voltage). Accordingly, the widths of the first scan signal and the second scan signal are different from each other.

As described above, the widths of the first scan signal and the second scan signal are different from each other so that the data charging amount A and the even-numbered gate lines charged by the first scan signal applied to the odd-numbered gate lines are different. Since the data charging amount B charged by the applied second scan signal becomes the same, the horizontal line phenomenon and the like can be improved. Accordingly, the image quality can be improved by preventing the horizontal line phenomenon.

As described above, the liquid crystal display according to the present invention generates the first GOE signal GOE_A and the second GOE signal GOE_B by using the GOE signal generated by the control signal generator. Here, the widths of the first GOE signal GOE_A and the second GOE signal GOE_B are the same. However, the period before the first GOE signal GOE_A is output, the second GOE signal GOE_B and the second GOE signal GOE_B are output, and the first GOE signal GOE_A is output. The preceding periods are different from each other. Therefore, the width of the first scan signal supplied from the gate driver to the odd gate line and the second scan signal supplied from the gate driver to the even gate line differ by a predetermined width. Therefore, the data charging amount A charged by the first scan signal applied to the odd-numbered gate line and the data charging amount B charged by the second scan signal applied to the even-numbered gate line are equal to each other. The phenomenon can be prevented.

As described above, in the liquid crystal display according to the present invention, the first GOE signal using the GOE signal generated by the control signal generation unit and the second GOE generated by shifting the GOE signal by a predetermined time with a D-flip flop. By supplying the first scan signal and the second scan signal having different widths controlled by the signals, the data charging amount of each of the odd-numbered gate line and the even-numbered gate line is equalized, thereby eliminating horizontal lines. It has the effect of improving the image quality.

Claims (12)

A controller for generating first and second GOE signals having different periods from each other; A gate driver configured to supply first and second scan signals having different widths in response to the first and second GOE signals; A data driver for supplying predetermined data; And A liquid crystal panel for displaying an image corresponding to the data; A period after the first GOE signal is output and before the second GOE signal is output, and a period after the second GOE signal is output and before the first GOE signal is output, are different from each other Display. The method of claim 1, And the second GOE signal is shifted by a certain degree from the first GOE signal. The method of claim 1, And the first scan signal is supplied to an odd gate line, and the second scan signal is supplied to even-numbered gate line. The method of claim 1, And the first and second GOE signals are alternately generated. delete The method of claim 1, And the first and second GOE signals are generated from a GOE signal generated from the controller.  The method according to claim 1 or 6, And the first GOE signal is generated every odd number by the product of the GOE signal and the first masking signal. The method according to claim 1 or 6, And the second GOE signal is generated every even-numbered time by a product of the second masking signal having an opposite polarity of the GOE signal and the first masking signal. Generating first and second GOE signals having different periods from each other; Supplying first and second scan signals having different widths in response to the first and second GOE signals; Supplying predetermined data; And Displaying an image corresponding to the data; A period after the first GOE signal is output and before the second GOE signal is output, and a section after the second GOE signal is output and before the first GOE signal is output, are different from each other Method of driving display device. The method of claim 9, And the second GOE signal is shifted by a predetermined amount from the first GOE signal. The method of claim 9, And the first and second GOE signals are alternately generated. delete

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