KR101683469B1 - liquid crystal display device and method of driving the same - Google Patents

Abstract

The present invention provides a liquid crystal display device comprising: a liquid crystal panel including a plurality of pixels arranged in a matrix form along a row line and a column line; A driving mode selector for comparing a received video data signal with a resolution of the liquid crystal panel to generate a driving mode signal; Wherein the normal mode is a mode in which the timing controller operates when the resolution of the liquid crystal panel and the image data signal are the same, Is a mode in which the timing controller operates when the resolution of the liquid crystal panel and the image data signal are different.

Description

[0001] The present invention relates to a liquid crystal display device and a method of driving the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof.

2. Description of the Related Art [0002] With the development of an information society, demands for a display device for displaying images have been increasing in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various flat display devices such as an organic light emitting diode (OLED) have been utilized.

Of these flat panel display devices, liquid crystal display devices are widely used today because they have advantages of miniaturization, weight reduction, thinness, and low power driving. On the other hand, an active matrix type liquid crystal display device in which a large number of pixels are arranged in a matrix and a switching thin film transistor is formed in each of these pixels is widely used today.

In recent years, a liquid crystal display device realizes ultra-high picture quality of a large screen of a large screen.

However, the liquid crystal display device implements a clearer high-definition image more quickly due to rapid technological advancement, whereas the image contents do not fully reflect the rapid technological development. That is, image contents that can be implemented in such a super high-definition liquid crystal display device are rare. Therefore, a separate scaler board must be provided to convert the image data of the conventional image contents to fit the size of the ultra-high quality liquid crystal display device.

That is, there is a problem that a conversion board such as a scaler must be provided in order to drive conventional image contents in an ultra high image quality liquid crystal display device. In addition, since a separate scaler must be provided, there is a problem that the circuit configuration and the driving method become complicated.

The present invention has a problem to reproduce a liquid crystal display device without a separate scaler and a method of driving the liquid crystal display device when displaying image data on a liquid crystal panel of a clearer high image quality.

According to an aspect of the present invention, there is provided a liquid crystal display comprising: a liquid crystal panel including a plurality of pixels arranged in a matrix form along a row line and a column line; A driving mode selector for comparing a received video data signal with a resolution of the liquid crystal panel to generate a driving mode signal; Wherein the normal mode is a mode in which the timing controller operates when the resolution of the liquid crystal panel and the image data signal are the same, Is a mode in which the timing controller operates when the resolution of the liquid crystal panel and the image data signal are different.

Wherein the timing control unit includes: a control signal generation unit that generates a gate control signal and a data control signal; And a data conversion unit for sorting, converting, and arranging the image data signals.

Wherein the control signal generator generates the gate output enable signal and the pulse of the source output enable signal to correspond one to one when the drive mode signal corresponds to the general mode signal, A plurality of the gates of the gate output enable signal and a pulse of the one source output enable signal are generated to correspond to each other.

Wherein the data conversion unit aligns the image data signal and outputs the image data signal to the data driver when the drive mode signal corresponds to the normal mode signal, and when the drive mode signal corresponds to the conversion mode signal, To the number of pixels of the row line of the liquid crystal panel, and outputs the converted data to the data driver.

A method of driving a liquid crystal display including a liquid crystal panel including a plurality of pixels arranged in a matrix form along a row line and a column line and a timing controller operating in a normal mode or a conversion mode, Comparing the resolution of the liquid crystal panel and operating in the normal mode or the conversion mode in the timing control unit, wherein the normal mode is a mode in which the liquid crystal panel operates when the resolution of the image data signal is equal to the resolution of the liquid crystal panel And the conversion mode is a mode in which the liquid crystal panel is operated when the resolution of the image data signal is different from that of the liquid crystal panel.

Wherein the timing controller generates the gate output enable signal and the source output enable signal so that the pulses of the gate output enable signal and the source output enable signal are in a one-to-one correspondence, and in the conversion mode operation, The pulse of the enable signal and the pulse of one of the source output enable signals correspond to each other.

Wherein the timing control unit arranges the image data signal and outputs the image data signal to the data driver, and when the image data signal is operated in the conversion mode, the timing control unit supplies the image data signal to the row And outputs the converted data to the data driver.

The liquid crystal display device according to the present invention is capable of driving not only a UD image but also an FHD image without a scaler in a UD class liquid crystal panel.

In addition, it provides an effect of facilitating the 3D implementation of the PR type.

1 is a schematic cross-sectional view illustrating a liquid crystal display device according to an embodiment of the present invention.
2 is a schematic sectional view showing a timing control unit according to an embodiment of the present invention;
3 is a block diagram illustrating a process of processing a video data signal in a timing controller according to an embodiment of the present invention.
4 is a waveform diagram showing a signal when the timing controller operates in the normal mode according to the embodiment of the present invention.
5 is a waveform diagram showing a signal when the timing control unit operates in the conversion mode according to the embodiment of the present invention.
6 is a cross-sectional view schematically showing a video data conversion when the timing control unit operates in a conversion mode according to an embodiment of the present invention;
7 is a view schematically showing image data displayed on a liquid crystal panel in a 3D implementation of a PR type according to an embodiment of the present invention.
FIG. 8 and FIG. 9 are diagrams schematically showing image data represented on a liquid crystal panel and a method thereof in a 3D implementation of a conventional PR type. FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 is a view schematically showing a liquid crystal display device according to an embodiment of the present invention.

As shown in the figure, a liquid crystal display device 100 according to an embodiment of the present invention includes a liquid crystal panel 200, a backlight 700, and a driving circuit.

The liquid crystal panel 200 is provided with a plurality of gate lines GL extending along a row line direction and a plurality of data lines DL extending along a column line direction. The gate wiring GL and the data wiring DL intersect with each other to define a pixel P in the form of a matrix.

Each pixel P includes a switching thin film transistor T, a pixel electrode, a common electrode, a liquid crystal capacitor Clc, and a storage capacitor Cst.

The switching thin film transistor T is formed at the intersection of the gate line GL and the data line DL. The switching thin film transistor T is connected to the pixel electrode. On the other hand, a common electrode is formed corresponding to the pixel electrode. When a data voltage is applied to the pixel electrode and a common voltage is applied to the common electrode, an electric field is formed therebetween to drive the liquid crystal. The pixel electrode, the common electrode, and the liquid crystal located between these electrodes constitute a liquid crystal capacitor Clc. Each pixel P further includes a storage capacitor Cst, which serves to store the data voltage applied to the pixel electrode until the next frame.

In the liquid crystal panel 200, the resolution varies depending on the number of pixels P represented in 1 inch (1 inch). Here, the resolution can be expressed by the product of the number of pixels P in the horizontal direction and the number of pixels P in the vertical direction (the pixel P is, for example, an R subpixel, a G subpixel, That is, the pixel P means a pixel P unit composed of a plurality of sub-pixels). For example, the VGA may be expressed as 640 x 480, and the XGA as 1024 x 768 or the like. Further, as the super high definition liquid crystal panel 200, there are a FHD (full high definition) class, UD (ultra definition) class liquid crystal panel 200, and the like. The UD class liquid crystal panel 200 can be represented by 3840 × 2160 and the FHD class by 1920 × 1080. Therefore, the UD-class liquid crystal panel 200 has twice as many pixels P in the horizontal and vertical directions as the FHD-class liquid crystal panel 200, and can provide four times brighter image quality.

Here, UD class liquid crystal panel 200 may be used in the embodiment of the present invention. Of course, those skilled in the art will appreciate that the liquid crystal panel 200 having different resolutions can be used.

The backlight 700 serves to supply light to the liquid crystal panel 200. As the backlight 700, a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), a light emitting diode (LED), or the like can be used.

The driving circuit unit may include a driving mode selection unit 300, a timing control unit 400, a gate driving unit 500, and a data driving unit 600.

Here, the drive mode selection unit 300 receives the image data signal Din from an external system such as a TV system or a video card, and generates a corresponding drive mode signal MS. And outputs the video data signal Din and the driving mode signal MS to the timing controller 400. [ Here, the drive mode signal MS may correspond to a signal indicating a normal mode or a conversion mode. The drive mode signal MS will be described later in more detail.

The timing controller 400 receives the video data signal Din and the driving mode signal MS from the driving mode selector 300 and receives a vertical synchronizing signal and a horizontal synchronizing signal from an external system such as a TV system or a video card And receives a clock signal and a control signal (TCS) such as data enable.

The timing controller 400 operates in a mode corresponding to the input drive mode signal MS. When the drive mode signal MS is a signal corresponding to the normal mode, for example, the timing controller 400 operates in the normal mode. When the drive mode signal MS is a signal corresponding to the conversion mode, the timing controller 400 ) Operates in the conversion mode. The normal mode and the conversion mode will be described later in more detail.

The timing controller 400 generates a gate control signal GCS for controlling the gate driver 500 and a data driver 600 for controlling the gate driver 500 in response to the input control signal TCS and the drive mode signal MS, And a data control signal DCS for controlling the data control signal DCS.

The timing controller 400 also arranges or converts and aligns the scale of the video data signal Din in accordance with the resolution of the liquid crystal panel 200 in response to the driving mode signal MS and supplies the data to the data driver 600). Hereinafter, an image data signal arranged to match the resolution of the liquid crystal panel 200 is referred to as an output data signal Dout.

The data driver 600 supplies the data voltages to the plurality of data lines DL in response to the data control signal DCS and the output data signal Dout supplied from the timing controller 400. [ That is, the data voltage corresponding to the output data signal Dout is generated using the gamma reference voltage, and the generated data voltage is output to the data line DL.

The gate driver 500 sequentially scans a plurality of gate lines GL in response to a gate control signal GCS supplied from the timing controller 400. [ For example, a plurality of gate lines GL are sequentially selected for each frame, and a gate voltage is output to the selected gate line GL. By the gate voltage, the switching thin film transistor T located on the row line is turned on. On the other hand, a turn-off voltage is supplied to the gate line GL until the scan of the next frame, so that the switching thin film transistor T maintains the turn-off state.

Hereinafter, the drive mode selection unit 300 according to the embodiment of the present invention will be described in detail.

The drive mode selection unit 300 receives the image data signal Din from an external system and compares it with the resolution of the liquid crystal panel 200 to generate a drive mode signal MS.

Here, the drive mode signal MS is a signal for selecting the drive mode of the timing control unit 400. More specifically, when the resolution of the image data signal Din is equal to the resolution of the liquid crystal panel 200, the timing controller 400 operates in the normal mode. On the other hand, when the resolution of the image data signal Din is not equal to the resolution of the liquid crystal panel 200, the signal is a signal for causing the timing controller 400 to operate in the conversion mode.

More specifically, for example, when the liquid crystal panel 200 is a UD-class liquid crystal panel 200, the driving mode signal MS is generated if the video data signal Din has a resolution of 3840x2160 (i.e., a UD resolution) The timing control unit 400 is operated to operate in the normal mode. On the other hand, if the image data signal Din has a resolution of 1920 x 1080 (i.e., FHD resolution), the drive mode signal MS becomes a signal for causing the timing controller 400 to operate in the conversion mode.

The drive mode signal MS generated by the drive mode selection unit 300 is output to the timing control unit 400.

Hereinafter, the timing controller 400 according to the embodiment of the present invention will be described in detail with reference to FIGS. 2 to 5. FIG.

FIG. 2 is a view schematically showing a timing controller 400 according to an embodiment of the present invention. FIG. 3 is a flowchart schematically illustrating a signal processing process of the timing controller 400 according to an embodiment of the present invention.

4 is a waveform diagram of signals applied when the timing controller 400 operates in a normal mode according to an embodiment of the present invention. FIG. 5 is a timing chart of a timing controller 400 according to an embodiment of the present invention, Lt; RTI ID = 0.0 > of < / RTI > applied signals.

As shown in FIG. 2, the timing controller 400 according to the embodiment of the present invention may include a control signal generator 410 and a data converter 420.

The control signal generator 410 receives a control signal TCS from an external system and generates a gate control signal GCS and a data control signal DCS in response to the drive mode signal MS. That is, when the drive mode signal MS is a signal corresponding to the normal mode, the gate control signal GCS and the data control signal DCS corresponding to the normal mode are generated. On the other hand, when the drive mode signal MS is a signal corresponding to the conversion mode, the gate control signal GCS and the data control signal DCS corresponding to the conversion mode are generated.

Here, the gate control signal GCS may include a gate start pulse (GST), a gate shift clock (GSC), a gate output enable (GOE) have. The data control signal DCS includes a source start pulse (SSP), a source shift clock (SSC), a source output enable (SOE), a polarity (POL) And the like.

The gate shift clock GSP serves to notify the start line of the screen in one vertical direction and the gate shift clock GSC serves to inform the first thin line of the switching thin film formed in the pixel P of the liquid crystal panel 200 And specifies the time when the transistor T is turned on. In addition, the gate output enable signal GOE serves to control the output of the gate driver 500.

The source start pulse SSP serves to notify the start point of the data in the horizontal direction, that is, the first pixel P, and the source shift clock SSC latches the data based on the rising and falling edges. (not shown). In addition, the embedded signal SOE, which is a source output, controls the output of the data driver 600, and the polarity signal POL is a polarity signal to drive the liquid crystal in the positive polarity or the negative polarity. .

A gate voltage is sequentially applied from the gate driver 500 to the gate line GL so that the switching thin film transistor T connected to the gate line GL is turned on, do.

Here, the gate voltage is applied to one gate line GL by one gate output enable signal GOE. That is, the gate voltage is sequentially applied to the gate line GL by the sequentially generated gate output enable signal GOE.

4 and 5, a data signal for image output from the data driver 600 on the basis of the rising (or falling) edge of the source output enable signal SOE during each frame, (Data) to sequentially display the image on the liquid crystal panel 200.

4, when the timing controller 400 operates in the normal mode, a gate control signal GCS, for example, a gate output enable signal GOE and a data control signal DCS, for example, a source output The enable signal SOE will be described in more detail.

When the drive mode signal MS corresponds to the normal mode, the control signal generation unit 410 operates in the normal mode. Here, the general mode is a mode in which the timing controller 400 operates when the image data signal Din inputted from the external system is equal to the resolution of the liquid crystal panel 200. [ Specifically, for example, when the resolution of the liquid crystal panel 200 is UD-level, the timing controller 400 operates in the normal mode if the video data signal Din has a UD-level resolution.

In the normal mode, the pulse of the gate output enable signal GOE and the source output enable signal SOE may correspond one-to-one. For example, one gate output enable signal GOE to which a gate high voltage is sequentially applied, and one source output enable signal SOE has a rising (or falling) edge. That is, it has a pulse of one gate output enable signal GOE and a pulse of one source output enable signal SOE. As a result, new data Data is output to each of the gate lines GL.

Specifically, referring to FIG. 4, for example, when the first gate output enable signal has, for example, a high voltage, the first source output enable signal has a rising (or falling) edge (pulse). Thus, the first data D1 is output.

When the liquid crystal panel 200 has a UD-level resolution (for example, 2160 pixels (P) in number of columns) and the video data signal Din has a UD-level resolution, The data voltage corresponding to 2160 number of the image data signal Din is output to the data line DL every time the gate voltage is applied to the data line GL.

That is, the gate lines GL are sequentially scanned in units of one horizontal period (1H), and gate voltages are applied to the scanned gate lines GL. Further, the source output enable signal SOE rises (or falls) in units of one horizontal period (1H) (i.e., has one pulse).

5, when the timing controller 400 operates in the conversion mode, a gate control signal GCS, for example, a gate output enable signal GOE and a data control signal DCS, for example, a source output The enable signal SOE will be described in more detail.

When the drive mode signal MS corresponds to the conversion mode, the control signal generation unit 410 operates in the conversion mode. Here, the conversion mode is a mode in which the timing controller 400 operates when the resolution of the liquid crystal panel 200 is not the same as the video data signal Din input from the external system. Specifically, for example, when the resolution of the liquid crystal panel 200 is UD-level, the timing controller 400 operates in the conversion mode if the image data signal Din has the FHD resolution.

In the conversion mode, the pulses of the plurality of gate output enable signals GOE correspond to the pulses of one source output enable signal SOE. For example, one source output enable signal SOE has a rising (or falling) edge to a certain number of gate output enable signals GOE to which a gate high voltage is sequentially applied. That is, a pulse of a certain number of gate output enable signals GOE and a pulse of one source output enable signal SOE are provided. As a result, new data Data is output for each constant gate line GL.

Specifically, referring to FIG. 5, for example, when the first and second gate output enable signals have, for example, a high voltage, the first source output enable signal has a rising (or falling) edge do. Thus, the first data D1 is output. Therefore, the same data Data, for example, the first data D1 is output to the pixel P connected to the two gate lines GL.

The liquid crystal panel 200 has, for example, UD resolution (i.e., 2160 pixels (P) in number of columns), and the image data signal Din has FHD resolution , The data Data is outputted for each of the two gate lines GL when a gate voltage is sequentially applied to the gate line GL. A data voltage corresponding to 1080 of the video data signal Din is output to the data line DL for each of the two gate lines GL. Accordingly, the image data signal Din having a number of 1080 along the column line may correspond to the liquid crystal panel 200 having the number of 2160 along the column line.

That is, the gate lines GL are sequentially scanned in units of one horizontal period (1H), and gate voltages are applied to the scanned gate lines GL. At this time, the source output enable signal SOE rises (or falls) in units of two horizontal periods (2H) (i.e., has one pulse).

As described above, the control signal generator 410 generates pulses of the gate output enable signal GOE and the source output enable signal SOE in response to the drive mode signal MS. That is, when the liquid crystal panel 200 and the image data signal Din have the same resolution, for example, the gate output enable signal GOE and the pulse of the source output enable signal SOE correspond one to one . On the other hand, when the resolution of the video data signal Din is lower than that of the liquid crystal panel 200, a pulse of the source output enable signal SOE is generated for each predetermined number of gate output enable signals GOE, do.

Accordingly, by adjusting the source output enable signal SOE without providing a separate scaler board or the like, it is possible to easily extend the image data signal Din of a low resolution in the vertical direction in accordance with the liquid crystal panel 200 of high resolution do.

That is, the control signal generator 410 vertically expands the image data signal Din to match the high-resolution liquid crystal panel 200 with the low-resolution image data signal Din.

The data converter 420 receives the driving mode signal MS and the video data signal Din from the driving mode selector 300 and outputs the video data signal Din in accordance with the driving mode signal MS Or < / RTI > And outputs the converted and arranged image data signal Din to the data driver 600 as an output data signal Dout. That is, when the drive mode signal MS is a signal corresponding to the normal mode, the image data signal Din is aligned so as to correspond to the normal mode. On the other hand, when the driving mode corresponds to the conversion mode, the image data signal Din is converted and aligned to correspond to the conversion mode.

First, a case where the data conversion unit 420 operates in the normal mode will be described.

If the drive mode signal MS is a signal corresponding to the normal mode, the data converter 420 operates in the normal mode. At this time, the data converter 420 aligns the input image data Din without conversion and outputs the data as an output data signal Dout to the data driver 600.

For example, when the liquid crystal panel 200 has the UD resolution and the received image data signal Din has the UD resolution, it is necessary to expand the image data signal Din to the line line none. Accordingly, the transmitted image data signal Din is sorted and output to the data driver 600. [

That is, in the normal mode, the image data signal Din is aligned without being subjected to the expansion conversion in the row line direction so as to correspond to the row line of the liquid crystal panel 200.

Hereinafter, the case where the data conversion unit 420 operates in the conversion mode will be described.

When the drive mode signal MS is a signal corresponding to the conversion mode, the data conversion unit 420 operates in the conversion mode. At this time, the data converter 420 converts and arranges the received image data signal Din and outputs it to the data driver 600 as an output data signal Dout.

For example, when the liquid crystal panel 200 has the UD resolution and the image data signal Din has the FHD resolution, the image data signal Din needs to be converted to a line-by-line. More specifically, the number of pixels P in the row line direction of the liquid crystal panel 200 is 3840, the resolution in the row line direction of the image data signal Din is 1920, Din, which is twice as large as the pixel P. Accordingly, the received image data signal Din is converted so as to match the resolution of the liquid crystal panel 200, aligned and output to the data driver 600.

That is, in the case of the conversion mode, the image data signal Din is to be expanded and converted in the row line direction so as to correspond to the row line of the liquid crystal panel 200 and aligned.

For example, the data conversion unit 420 may include at least one line memory or a frame memory in order to expand and convert the image data signal Din.

A concrete example will be described with reference to FIG. FIG. 6 is a diagram schematically showing the video data signal Din and the output data signal Dout.

6, when the video data signal Din is D1 + D2 + D3, the output data signal Dout is represented by D1 + D1 + D2 + D2 + D3 + D3. In this case, the number of pixels P in the row line direction of the liquid crystal panel 200 is, for example, 3840 (that is, UD resolution) and the image data signal Din has a resolution of 1920 in the row line direction. Therefore, the same data (Data) signal should be output to the data line DL connected to the two pixels P, since it has to be extended twice in the row line direction.

As described above, the data converter 420 aligns, converts, and arranges the video data signals Din in response to the driving mode. That is, when the liquid crystal panel 200 and the image data signal Din have the same resolution, the image data signals Din are sorted and outputted to the data driver 600. [ On the other hand, when the resolution of the image data signal Din is lower than that of the liquid crystal panel 200, the image data signal Din is converted to match the resolution of the liquid crystal panel 200, do.

Therefore, by providing a line memory, for example, for converting the image data signal Din into the timing controller 400 without providing a separate scaler board or the like, the image data signal Din of a low resolution can be easily converted into a high- It is possible to extend in the horizontal direction in conformity with the panel 200.

That is, the data converter 420 horizontally expands the image data signal Din to fit the high-resolution liquid crystal panel 200 with the low-resolution image data signal Din.

The operation of the timing controller 400 will be described with reference to FIG. Here, for convenience of explanation, it is assumed that the resolution of the liquid crystal panel 200 is UD-class.

First, it receives a video data signal Din and determines whether the resolution of the video data signal Din is the same as the resolution of the liquid crystal panel 200. (s1)

For example, when the resolution of the liquid crystal panel 200 and the video data signal Din is the same, for example, when the video data signal Din is a UD-level resolution,

Here, in the case of driving in the normal mode, the video data signal Din is aligned and output to the data driver 600 without having to convert the video data signal Din into the row line direction.

In addition, the pulse of one gate output enable signal GOE has a pulse of one source output enable signal SOE.

When the resolution of the liquid crystal panel 200 is different from that of the image data signal Din, for example, the image data signal Din is driven in the conversion mode when the resolution is FHD. (S3)

Here, when driven in the conversion mode, the image data signal Din is converted into the row line direction. That is, the resolution of the liquid crystal panel 200, aligns them, and outputs them to the data driver 600.

In addition, a pulse of a certain number of gate output enable signals GOE has a pulse of one source output enable signal SOE.

In this way, the image data signal Din arranged or converted and arranged is output to the data driver 600 as the output data signal Dout.

In the liquid crystal display device 100 according to the embodiment of the present invention, 3D implementation of the PR type (patterned retarder type) can be facilitated.

This will be described in more detail with reference to FIG. 7 is a view schematically showing a method of displaying an image on the liquid crystal panel 200 in the 3D implementation of the PR type.

7, the PR type 3D is divided into a left image data signal L that can be recognized by the left eye on the row line of the liquid crystal panel 200 and a right image data signal (R) are alternately outputted.

At this time, when the low resolution image data Din is outputted to the high resolution liquid crystal panel 200, the left image data signal L and the left image data signal L are supplied to the pixels P connected to the gate line GL corresponding to the row line, The right video data signal R can be outputted without being mixed with each other.

Specifically, for example, when the image data signal Din is the FHD-level resolution and the liquid crystal panel 200 is the UD-level resolution, the left image data signal L and the right image data signal R are output twice , It is possible to facilitate the 3D implementation of the PR type.

8 and 9, in the prior art, a separate scaler board must be provided in the 3D implementation of the PR type. In this case, due to the characteristics of the scaler board, the pixel P is formed in a predetermined row line on the liquid crystal panel 200, The left image data signal L and the right image data signal R are mixed and the data signals are mixed together.

The liquid crystal display 200 according to the embodiment of the present invention may control the timing controller 400 to provide the FHD-level image data signal Din to the UD-level liquid crystal panel 200, for example, It is possible to easily realize the PR type 3D.

The embodiment of the present invention described above is an example of the present invention, and variations are possible within the spirit of the present invention. Accordingly, the invention includes modifications of the invention within the scope of the appended claims and equivalents thereof.

100: liquid crystal display device 200: liquid crystal panel
300: drive mode selection unit 400: timing control unit
410: Control signal generation unit 420: Data conversion unit
Din: image data signal MS: drive mode signal

Claims (7)

A liquid crystal panel including a plurality of pixels arranged in a matrix form along a row line and a column line;
A driving mode selector for comparing a received video data signal with a resolution of the liquid crystal panel to generate a driving mode signal;
And a timing controller for operating in a normal mode or a conversion mode in response to the drive mode signal,
Wherein the general mode is a mode in which the timing controller operates when the resolution of the liquid crystal panel and the video data signal are the same,
Wherein the conversion mode is a mode in which the timing controller operates when the resolution of the liquid crystal panel and the image data signal are different,
Wherein the timing control unit generates the plurality of gate output enable signal pulses so as to correspond to the pulses of the one source output enable signal when the driving mode signal corresponds to the conversion mode signal, And outputs the converted data to the data driver.

The method according to claim 1,
Wherein the timing control unit comprises:
A control signal generator for generating a gate control signal and a data control signal;
And a data conversion unit for sorting, converting, and arranging the image data signals.
3. The method of claim 2,
Wherein the control signal generator comprises:
And generates a gate output enable signal and a pulse of the source output enable signal in a one-to-one correspondence when the drive mode signal corresponds to a normal mode signal.

3. The method of claim 2,
Wherein the data conversion unit comprises:
And aligns the image data signal and outputs the image data signal to the data driver when the drive mode signal corresponds to the normal mode signal.

A method of driving a liquid crystal display including a liquid crystal panel including a plurality of pixels arranged in a matrix form along a row line and a column line, and a timing controller operating in a normal mode or a conversion mode,
Comparing the inputted image data signal with the resolution of the liquid crystal panel and operating in the normal mode or the conversion mode in the timing control unit,
Wherein the normal mode is a mode in which the liquid crystal panel is operated when the resolution of the image data signal is the same,
Wherein the conversion mode is a mode that operates when the liquid crystal panel and the image data signal have different resolutions,
Wherein the timing controller generates the plurality of gate output enable signal pulses and the one source output enable signal pulse so that the plurality of gate output enable signal pulses correspond to each other, And outputs the converted data to the data driver.

6. The method of claim 5,
Wherein the timing control unit generates the gate output enable signal and the source output enable signal in a one-to-one correspondence when operating in the normal mode.

6. The method of claim 5,
Wherein the timing control unit aligns the image data signal and outputs the image data signal to the data driver when the normal mode is operated.

Images