KR100927012B1 - LCD and its driving method - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof capable of differently adjusting average luminance for each partial region.

The present invention provides a liquid crystal panel in which a liquid crystal cell is formed at an intersection of gate lines and data lines; An identification signal generator for generating an identification signal for specifying the luminance of the display image for each region in response to a user command; A gamma voltage generator for generating at least two gamma voltage sets having different voltage ranges; A data driver selecting one of the gamma voltage sets in response to an identification signal from the identification signal generator and converting digital data into analog data using the selected gamma voltage set to supply the data lines; A gate driver for driving the gate lines; And a timing controller for controlling the gate driver and the data driver.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND METHOD OF DRIVING THE SAME}             

1 is a view showing a conventional liquid crystal display device.

2 is a detailed block diagram of a conventional data drive integrated circuit.

3 is a graph showing a relationship between a pixel signal and a light transmittance in a conventional liquid crystal display.

4 is a view showing an image of a word mode and a high quality image mode displayed simultaneously on the liquid crystal panel;

5 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 6 is a detailed block diagram of a data drive integrated circuit included in the data driver shown in FIG.

7 is a detailed block diagram of the second multiplexer array and decoder array shown in FIG.

8 is a detailed block diagram of another form of the second multiplexer array and decoder array shown in FIG.

9 is a block diagram illustrating an identification signal line shown in FIG. 6;                 

FIG. 10 is a graph illustrating a comparison between a pixel signal and a light transmittance of a word mode and a high quality image mode in a liquid crystal display according to an exemplary embodiment of the present invention. FIG.

<Description of Symbols for Main Parts of Drawings>

2, 42: liquid crystal panel 4, 44: gate driver

6, 46: data driver 8, 48: timing controller

10, 50, 52: reference gamma voltage section 12, 62: data drive IC

14, 64: signal control unit 16, 66, 67: gamma voltage unit

18, 68: shift register array 20, 70: latch array

22, 72: DAC array 24, 74: P decoder array

26, 76: N decoder array 28: MUX array
78: first MUX array 82: second MUX array

30, 80: output buffer array 54: system body

84,184: Second MUXs 86,186: P Decoder

88, 188: N decoder

89, 189: Shift register for storing identification signals

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof, in which the average luminance is differently adjusted for each partial region.

Conventional liquid crystal displays (hereinafter referred to as LCDs) display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the LCD includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In fact, as shown in FIG. 1, the LCD includes a liquid crystal panel 2 in which liquid crystal cells Clc are arranged in a matrix, and a gate driver for driving gate lines GL0 to GLn of the liquid crystal panel 2. (4), a data driver 6 for driving the data lines DL1 to DLm of the liquid crystal panel 2, and a timing controller 8 for controlling the gate driver 4 and the data driver 6 And a reference gamma voltage unit 10 for generating a reference gamma voltage and supplying the data to the data driver 6.

The timing controller 8 generates gate control signals GSP, GSC, and GOE to control the gate driver 4, and generates data control signals SSP, SSC, SOE, and POL to generate the data driver 6. Will be controlled. In addition, the timing controller 8 aligns the pixel data R, G, and B and supplies them to the data driver 6.

The liquid crystal panel 2 includes thin film transistors TFT and liquid crystal cells Clc formed at regions defined by intersections of the gate lines GL1 to GLn and the data lines DL1 to DLm.

The thin film transistor TFT is turned on when the scan signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data line DL to the liquid crystal cell Clc. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell Clc.

The liquid crystal cell Clc is equivalently represented by a capacitor and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell Clc further includes a storage capacitor Cst so that the charged pixel signal is stably maintained until the next pixel signal is charged. The storage capacitor Cst is formed between the previous gate line and the pixel electrode. The liquid crystal cell Clc realizes gray by adjusting light transmittance by varying an arrangement state of liquid crystals having dielectric anisotropy according to pixel signals charged through the thin film transistor TFT.

The gate driver 4 sequentially supplies the gate high voltage VGH to the gate lines GL1 to GLn in response to the gate control signals GSP, GSC, and GOE from the timing controller 8. Accordingly, the gate driver 4 causes the thin film transistor TFT connected to the gate lines GL1 to GLn to be driven in units of the gate line GL. The gate driver 4 supplies the gate low voltage VGL in the remaining periods in which the gate high voltage VGH is not supplied to the gate lines GL1 through GLn. In addition, the gate driver 4 supplies the gate low voltage VGL to the gate line GL0 formed at the uppermost side for the storage capacitor Cst of the first scan line.

The data driver 6 outputs a pixel signal of one line for each horizontal period H1, H2, ... in response to the data control signals SSP, SSC, SOE, and POL from the timing controller 8. To DL1 to DLm. In particular, the data driver 6 converts and supplies the digital pixel data R, G, and B from the timing controller 8 into an analog pixel signal by using the reference gamma voltage from the gamma voltage generator 10. This data driver 6 is composed of a plurality of data drive ICs for separately driving the data lines DL1 to DLm.

The reference gamma voltage unit 10 generates and supplies reference gamma voltages that are reference to gamma voltages of grays used for analog conversion of the data driver 6. In particular, the reference gamma voltage unit 10 generates and supplies a positive reference gamma voltage set having positive polarity and a negative reference gamma voltage set having negative polarity based on a common voltage.

2 is a block diagram showing the detailed configuration of a conventional data drive IC 12. As shown in FIG.

The data drive IC 12 shown in FIG. 2 includes a shift register array 18 for supplying a sequential sampling signal, a latch array 20 for sequentially latching and simultaneously outputting pixel data in response to the sampling signal, and a latch array. Digital-to-analog conversion (hereinafter referred to as DAC) array 22 for converting pixel data from 20 into an analog pixel signal, and an output buffer array 30 for buffering and outputting pixel signals from DAC array 22. ). In addition, the data drive IC 12 subdivides the DAC by subdividing the reference gamma voltage set from the signal control unit 14 relaying the data control signals supplied from the timing control unit 8 and the pixel data, and the reference gamma voltage unit 10. A gamma voltage part 16 for supplying the array 22 is further provided. The data drive IC 12 having such a configuration drives k data lines DL1 to DLk among the n data lines DL1 to DLn.

The signal controller 14 controls various data control signals (SSP, SSC, SOE, REV, POL, etc.) and pixel data from the timing controller 8 to be output to the corresponding components.

The gamma voltage unit 16 divides each of the positive reference gamma voltage set and the negative reference gamma voltage set input from the reference gamma voltage unit 10 by gray to output a positive gamma voltage set and a negative gamma voltage set. .

The shift registers included in the shift register array 18 sequentially shift the source start pulse SSP from the signal controller 14 according to the source sampling clock signal SSC and output the sampling signal.

The latch array 20 sequentially samples and latches pixel data from the signal controller 14 in a predetermined unit in response to a sampling signal from the shift register array 18. To this end, the latch array 20 is composed of k latches for latching k pixel data, each of which has a size corresponding to the number of bits (8 bits) of the pixel data. In particular, in order to reduce the transmission frequency, the timing controller 8 divides the pixel data into even pixel data and odd pixel data and outputs the same through the respective transmission lines. Here, each of the even pixel data and the odd pixel data includes red (R), green (G), and blue (B) pixel data. Accordingly, the latch array 20 simultaneously latches even pixel data and odd pixel data, that is, six pixel data, supplied through the signal controller 14 for each sampling signal. Subsequently, the latch array 20 simultaneously outputs k pixel data latched in response to the source output enable signal SOE from the signal controller 14. In this case, the latch array 20 restores and outputs the pixel data modulated to reduce the number of transition bits in response to the data inversion selection signal REV. This is because the timing controller 8 modulates and supplies the pixel data whose number of transitioned bits exceeds a reference value in order to minimize electromagnetic interference (EMI) during data transmission so that the number of transition bits is reduced.

The DAC array 22 converts the pixel data from the latch array 20 into positive and negative pixel signals at the same time and outputs the same. To this end, the DAC array 22 includes a positive (P) decoder array 24 and a negative (N) decoder array 26 connected to the latch array 20, and a P decoder array 24 and an N decoder array ( A multiplexer array (hereinafter referred to as MUX) array 28 for selecting the output signal of the circuit 26).

The P decoders included in the P decoder array 24 convert the pixel data simultaneously input from the latch array 20 into the positive pixel signal using the positive gamma voltage set from the gamma voltage unit 16.

The k N decoders included in the N decoder array 26 convert the k pixel data simultaneously input from the latch array 20 into the negative pixel signal using the negative gamma voltage set from the gamma voltage unit 16. Done.

The MUXs included in the MUX array 28 select and output the positive polarity pixel signal from the P decoder or the negative polarity pixel signal from the N decoder in response to the polarity control signal POL from the signal controller 14.

The output buffers included in the output buffer array 30 are configured with a voltage follower connected to the k data lines DL1 through DLk in series. These output buffers signal buffer the pixel signals from the DAC array 22 and supply them to the data lines DL1 to DLk.

As such, the LCD selects a gamma voltage of a gamma voltage set divided by gray according to pixel data and supplies the gamma voltage to the liquid crystal panel 2 as a pixel signal. The liquid crystal cells display passive images by controlling the transmittance of light supplied from the same backlight unit according to the pixel signal. When the liquid crystal panel 2 is in the normal white mode, the light transmittance of the liquid crystal cells has an inverse relationship that decreases as the size of the pixel signal, that is, the liquid crystal driving voltage, increases, as shown in FIG. 3.

Such LCDs are intensively developed for improving brightness. As a result, the average brightness of LCDs used for monitors has actually exceeded 100 nits, which is actually the average brightness of CRT (Cathode Ray Tube) monitors. This causes the LCD monitor to be so bright that the user may feel fatigued by glare. This is because the LCD monitor is unilaterally displaying brightly in order to respond to high resolution images, TV images, and moving pictures requiring a bright image of 300 nits or more. In other words, as the average brightness is increased in accordance with an image requiring a bright image, the LCD is too bright even when a bright image is not required, such as a word mode of a computer, to give a user fatigue.

For example, as shown in FIG. 4, the average brightness of the word mode area A of the computer is 100 to 150 nit, which is suitable for the user, and the high quality image mode area B such as a TV picture, a video, or a high quality picture. ), The average brightness of 300 ~ 400nit class is required. However, the brightness of LCDs used for monitors is set around 200-300nits on average. For this reason, LCD monitors are too bright when used in the word mode of a computer, and are too dark for TV images, movies, or high quality pictures.

On the other hand, the LCD can adjust the brightness by adjusting the gamma voltage value or the lamp driving frequency through the OSD. However, as the LCD receives light from the same backlight unit, it is impossible to adjust luminance by region. In other words, it is impossible for the LCD to adjust the average luminance of the word mode region A to 100 to 150 nits in FIG. 4 and to adjust the average luminance of the word mode region A to 300 to 400 nits with the average luminance of the high quality image mode region B.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of adjusting average luminance for each partial region.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention comprises a liquid crystal panel in which a liquid crystal cell is formed at the intersection of the gate line and the data line; An identification signal generator for generating an identification signal for specifying the luminance of the display image for each region in response to a user command; A gamma voltage generator for generating at least two gamma voltage sets having different voltage ranges; A data driver selecting one of the gamma voltage sets in response to an identification signal from the identification signal generator and converting digital data into analog data using the selected gamma voltage set to supply the data lines; A gate driver for driving the gate lines; And a timing controller for controlling the gate driver and the data driver.
The identification signal generator is built in the timing controller.
The data driver includes a shift register array for generating a sampling signal, a latch array for temporarily storing and outputting the digital data in response to the sampling signal, an identification signal shift register for receiving and storing the identification signal, and the identification signal for The analog data is converted into the analog data using a multiplexer array for selecting and outputting any one of the at least two gamma voltage sets according to an identification signal from a shift register, and a gamma voltage set from the multiplexer array. And an output buffer array for outputting the analog data from the digital-analog converter array.
Each multiplexer of the multiplexer array supplies the selected gamma voltage set to a digital-analog converter, but supplies the digital-analog converter in one or three units.
The gamma voltage generator generates a first gamma voltage set and a second gamma voltage set having a gamma voltage range smaller than the gamma voltage range of the first gamma voltage set.
The gamma voltage generator includes at least two reference gamma voltage units for generating at least two reference gamma voltage sets of different voltage ranges, and at least two gamma voltage units for subdividing each of the at least two reference gamma voltage sets for each gray. do.
Each of the at least two reference gamma voltage portions generates a set of positive and negative reference gamma voltages, and each of the at least two gamma voltage portions generates a set of positive and negative gamma voltages.
According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method comprising: generating an identification signal for specifying a luminance of a display image for each region in response to a user command; Generating at least two gamma voltage sets having different voltage ranges; And selecting one of the gamma voltage sets in response to the identification signal, converting digital data into analog data using the selected gamma voltage set, and supplying the digital data to the data line of the liquid crystal panel.
The converting the digital data into the analog data and supplying the analog data to the liquid crystal panel may include: receiving and storing the identification signal; Generating a sampling signal; Temporarily storing the digital data in response to the sampling signal; Selecting and outputting one of the at least two gamma voltage sets according to the identification signal; Converting the digital data into the analog data using the selected gamma voltage set; And supplying the analog data to a data line of the liquid crystal panel.
Generating the gamma voltage set generates a first gamma voltage set and a second gamma voltage set having a gamma voltage range that is less than the gamma voltage range of the first gamma voltage set.
The converting of the digital data into the analog data may include converting the digital data into the analog data with the first gamma voltage set when the identification signal indicating a high quality image mode is input; And converting the digital data into the analog data with the second gamma voltage set when the identification signal indicating the word mode is input.

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Generating an identification signal for specifying the luminance of the display image for each region in response to a user's command, generating at least two gamma voltage sets having different voltage ranges, and identifying from the identification signal generator And selecting one of the gamma voltage sets in response to the signal, converting digital data into analog data using the selected gamma voltage set, and supplying the digital data to the liquid crystal panel.

In the driving method, converting the digital data into analog data and supplying the digital data to the liquid crystal panel may include receiving and storing the identification signal, generating a sampling signal, and temporarily stopping the digital data in response to the sampling signal. Storing and selecting and outputting one of the at least two gamma voltage sets according to the identification signal, and converting the digital data into the analog data using the gamma voltage set. And outputting the analog data and supplying the analog data to the liquid crystal panel.

The generating of the gamma voltage set in the driving method may include generating a first gamma voltage set having a relatively wide gamma voltage range and a second gamma voltage set having a gamma voltage range smaller than the first gamma voltage set. It is done.

In the driving method, converting the digital data into the analog data may include converting the digital data into the analog data using the first gamma voltage set in a high quality video mode having a relatively high average brightness in response to the identification signal. And converting the digital data into the analog data using the second gamma voltage set in a word mode having a relatively low average brightness in response to the identification signal.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 10.

Referring to FIG. 5, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 42 in which liquid crystal cells Clc are arranged in a matrix, and gate lines GL0 to GLn of the liquid crystal panel 42. A gate driver 44 for driving the gate driver, a data driver 46 for driving the data lines DL1 to DLm of the liquid crystal panel 42, and a reference gamma voltage to be supplied to the data driver 46. The first and second reference gamma voltage units 50 and 52 and the identification signal generator 56 and the gate driver 44 which receive a selection signal of the image mode area from the user and supply them to the data driver 46. A timing controller 48 for controlling the driver 46 is provided.

The timing controller 48 controls the gate driver 44 by generating gate control signals GSP, GSC, and GOE using synchronization signals from a graphics card (not shown) of the system main body 54, and the data control signal. The data driver 46 is controlled by generating the fields SSP, SSC, SOE, and POL. In addition, the timing controller 48 aligns the pixel data from the graphics card of the system main body 54 and supplies it to the data driver 46.

The liquid crystal panel 42 includes thin film transistors TFT and liquid crystal cells Clc formed at respective regions defined by intersections of the gate lines GL1 to GLn and the data lines DL1 to DLm.

The thin film transistor TFT is turned on when the scan signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data line DL to the liquid crystal cell Clc. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell Clc.

The liquid crystal cell Clc is equivalently represented by a capacitor and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell Clc further includes a storage capacitor Cst so that the charged pixel signal is stably maintained until the next pixel signal is charged. The storage capacitor Cst is formed between the previous gate line and the pixel electrode. The liquid crystal cell Clc realizes gray by adjusting light transmittance by varying an arrangement state of liquid crystals having dielectric anisotropy according to pixel signals charged through the thin film transistor TFT.

The identification signal generator 56 generates an identification signal for specifying the luminance of the display image for each region in response to a user's command. That is, the identification signal generator 56 receives the position information of the high definition image mode and the word mode of the liquid crystal panel 42 from the user and generates the identification signal RVSS in units of one liquid crystal cell composed of red, green, and blue. Done. On the other hand, the identification signal generator 56 is the position information of the high-definition mode and the word mode of the liquid crystal panel 42 by a mouse operation on an application program of the user or an operation of an operation panel (not shown) provided in the monitor using a liquid crystal display device. In response to the input signal, the identification signal RVSS is generated in one liquid crystal cell unit composed of red, green, and blue. The identification signal generator 56 may be built in the timing controller 48.

The gate driver 44 sequentially supplies the gate high voltage VGH to the gate lines GL1 to GLn in response to the gate control signals GSP, GSC, and GOE from the timing controller 48. Accordingly, the gate driver 44 causes the thin film transistor TFT connected to the gate lines GL1 to GLn to be driven in units of the gate line GL. The gate driver 44 supplies the gate low voltage VGL to the gate lines GL1 through GLn in the remaining periods when the gate high voltage VGH is not supplied. In addition, the gate driver 44 supplies the gate low voltage VGL to the gate line GL0 formed at the uppermost side for the storage capacitor Cst of the first scan line.

The data driver 46 outputs one pixel signal for one line per horizontal period H1, H2, ... in response to the data control signals SSP, SSC, SOE, and POL from the timing controller 48. To DL1 to DLm. In this case, the data driver 46 converts the digital pixel data from the timing controller 48 into an analog pixel using the first and second reference gamma voltage sets from the first and second reference gamma voltage units 50 and 52. Supply it by converting it into a signal. In particular, the data driver 46 selects and uses the first reference gamma voltage set or the second reference gamma voltage set according to the identification signal RVSS from the identification signal generator 56. The data driver 46 is composed of a plurality of data drive ICs for separately driving the data lines DL1 to DLm. The detailed configuration of the data drive IC will be described later.

The first and second reference gamma voltage units 50 and 52 generate and supply the first and second reference gamma voltage sets which are the reference of gamma voltages for gray used in the analog conversion of the data driver 46. In particular, the first and second reference gamma voltage units 50 and 52 generate at least two reference gamma voltages different from the same gray to be selectively used according to the identification signal RVSS. In other words, the first and second reference gamma voltage units 50 and 52 generate at least two gamma voltage sets having different gamma voltage ranges to be selectively used according to the identification signal RVSS. For example, the first reference gamma voltage set generated by the first reference gamma voltage unit 50 is used for the high quality image mode, and the second reference gamma voltage set generated by the second reference gamma voltage unit 52 is used for the word mode. If assumed, the second reference gamma voltage set is set such that the gamma voltage range is smaller than the first reference gamma voltage set. Accordingly, since the average brightness of the word mode using the second reference gamma voltage set is lower than the high quality image mode using the first reference gamma voltage set, the luminance of the liquid crystal panel 42 can be adjusted for each region according to a user's operation. Will be. The first and second reference gamma voltage units 50 and 52 generate a positive reference gamma voltage set having a positive polarity based on a common voltage and a negative reference gamma voltage set having a negative polarity.

FIG. 6 is a block diagram showing a detailed configuration of a data drive IC constituting the data driver shown in FIG.                     

The data drive IC 62 shown in FIG. 6 includes a shift register array 68 for supplying a sequential sampling signal, a latch array 70 for sequentially latching and simultaneously outputting pixel data in response to the sampling signal, and a latch array. A DAC array 72 for converting the pixel data from 70 into an analog pixel signal, and an output buffer array 80 for buffering and outputting the pixel signal from the DAC array 72. In addition, the data drive IC 62 subdivides the data control signals supplied from the timing controller 48 and the signal controller 64 for relaying the pixel data, and each of the first and second reference gamma voltage sets to divide the DAC array ( And first and second gamma voltage portions 66 and 67 to be supplied to 72. The data drive IC 62 having such a configuration drives k data lines DL1 to DLk among the n data lines DL1 to DLn.

The signal controller 64 controls various data control signals (SSP, SSC, SOE, REV, POL, etc.) and pixel data from the timing controller 48 to be output to the corresponding components.

The first and second gamma voltage units 66 and 67 may divide and output the first and second reference gamma voltage sets input from the first and second reference gamma voltage units 50 and 52 for each gray. In particular, the first and second gamma voltage units 66 and 67 generate different gamma voltage sets compared to the same gray to be selectively used according to the identification signal RVSS. For example, when the first gamma voltage set generated by the first gamma voltage unit 66 is assumed to be used in the high-definition image mode and the second gamma voltage set generated by the second gamma voltage unit 67 is used in the word mode, The two gamma voltage set is set such that the gamma voltage range is smaller than the first gamma voltage set. Accordingly, since the average luminance of the word mode using the second gamma voltage set can be lowered than the high quality image mode using the first gamma voltage set, the luminance of the liquid crystal panel 42 can be adjusted for each region according to the user's operation. . In addition, the first and second gamma voltage units 66 and 67 generate a positive gamma voltage set having positive polarity and a negative gamma voltage set having negative polarity based on the common voltage.

The shift registers included in the shift register array 68 sequentially shift the source start pulse SSP from the signal controller 64 according to the source sampling clock signal SSC and output the sampling signal.

The latch array 70 sequentially samples and latches pixel data from the signal controller 64 in predetermined units in response to a sampling signal from the shift register array 68. To this end, the latch array 70 is composed of k latches for latching k pixel data, each of which has a size corresponding to the number of bits (9 bits) of the pixel data. In particular, the timing controller 48 divides the pixel data into even pixel data and odd pixel data so as to reduce the transmission frequency and outputs the same through the respective transmission lines. The even pixel data and the odd pixel data each include red (R), green (G), and blue (B) pixel data. Accordingly, the latch array 70 simultaneously latches even pixel data and odd pixel data, that is, six pixel data, supplied through the signal controller 64 for each sampling signal. Subsequently, the latch array 70 simultaneously outputs k pixel data latched in response to the source output enable signal SOE from the signal controller 64. In this case, the latch array 70 restores and outputs the pixel data modulated to reduce the number of transition bits in response to the data inversion selection signal REV. This is because the timing controller 48 modulates and supplies the pixel data whose number of transitioned bits exceeds a reference value to minimize electromagnetic interference (EMI) during data transmission so that the number of transition bits is reduced.

The DAC array 72 converts the pixel data from the latch array 70 into positive and negative pixel signals at the same time and outputs the same. To this end, the DAC array 72 generates an identification signal via the P (Positive) decoder array 74 and the N (Negative) decoder array 76 commonly connected to the latch array 70 and the signal control unit 64. An identification signal storage shift register 89 for sequentially storing the identification signal RVSS supplied from the unit 56 and supplying the stored identification signal RVSS to the second MUX array 82; Second MUX array 82 for selectively supplying the first or second gamma voltage set to P decoder array 74 and N decoder array 76 in response to an output signal from shift register 89. And a first MUX array 78 for selecting output signals of the P decoder array 74 and the N decoder array 76.

The shift register 89 for storing the identification signal is supplied with the identification signal RVSS supplied from the identification signal generator 56 via the signal controller 64. The identification signal RVSS is stored in a plurality of shift registers in the shift register 89 for storing the identification signal by the shift clock CS, and the stored identification signal RVSS is supplied to the second MUX array 82. do.

The second MUX array 82 is the first gamma voltage set from the first gamma voltage section 66 or the second gamma voltage section 67 in accordance with the identification signal RVSS supplied from the identification signal storage shift register 89. Select a second set of gamma voltages from &lt; RTI ID = 0.0 &gt;) &lt; / RTI &gt; For example, the second MUX array 82 selects a first gamma voltage set when the identification signal RVSS indicates a high definition image mode, and a second gamma voltage set when the identification signal RVSS indicates a high quality image mode. Supply to (74, 76). To this end, the second MUX array 82 is configured to supply a first gamma voltage set or a second gamma voltage set to each of the P decoder array 74 and the N decoder array 76 as shown in FIG. 7. With MUXs 84.

Each of the second MUXs 84 includes three units of the first gamma voltage set or the second gamma voltage set in response to the identification signal RVSS from the identification signal storage shift register 89 as shown in FIG. 7. To the P decoder 86 and the N decoder 88 of the apparatus. Meanwhile, each of the second MUXs 184 may set the first gamma voltage set or the second gamma voltage set in response to the identification signal RVSS from the identification signal storage shift register 189 as shown in FIG. 8. The P decoder 186 and the N decoder 188 are supplied to each unit.

The P decoders 86 included in the P decoder array 74 use the first or second positive gamma voltage set from the second MUX array 82 to receive pixel data simultaneously input from the latch array 70. It is converted into a positive pixel signal.

The N decoders 88 included in the N decoder array 76 may use the first or second negative gamma voltage set from the second MUX array 82 to receive pixel data simultaneously input from the latch array 70. It is converted into a negative pixel signal.

The first MUXs included in the first MUX array 78 select a positive pixel signal from the P decoder or a negative pixel signal from the N decoder in response to the polarity control signal POL from the signal controller 64. Will print.

The output buffers included in the output buffer array 80 are configured as voltage followers connected to the data lines DL1 to DLk in series. These output buffers signal buffer the pixel signals from the DAC array 72 to the data lines DL1 to DLk.

As such, in the LCD according to the embodiment of the present invention, the timing controller 48 is installed on the printed circuit board 90 as shown in FIG. 9. At this time, the identification signal lines 92a for supplying the identification signal RVSS from the identification signal generator 56 embedded in the timing controller 48 to the data driver IC 62 on the printed circuit board 90; 92b, 92c) are formed. At this time, the first identification signal line 92a is formed between the timing controller 48 and the first data driver IC, and the second identification signal line 92b is formed between the first data driver ICD and the second data driver IC. Is formed. The identification signal lines except for the first identification signal line 92a among the identification signal lines 92a, 92b, and 92c are formed on the printed circuit board 90 between the plurality of data driver ICs, thereby leading to the data driver IC. The output of the identification signal storage shift register 89 is transferred to the identification signal storage shift register of the data driver IC of the next stage.

As described above, the LCD according to an embodiment of the present invention converts pixel data into an analog pixel signal by using at least two gamma voltage sets having different voltage ranges, that is, at least two gamma voltages different from the same gray. The supplied pixel signals to each of the liquid crystal cells. In particular, the LCD according to the embodiment of the present invention selects one of at least two different gamma voltages from the same gray color data according to the identification signal RVSS from the identification signal generator 56. 42, the average luminance can be adjusted for each partial region.

For example, as illustrated in FIG. 4, the pixel data supplied to the word mode area A of the computer may include a second gamma voltage set C having a relatively small gamma voltage difference between the grays shown in FIG. 10. It converts to a pixel signal by using. Accordingly, the transmittance range between the brightest 255 gray and the darkest 0 gray due to the pixel signals supplied to the word mode region A shown in FIG. 4 is relatively small. As a result, the LCD according to the embodiment of the present invention can independently adjust the average brightness of the word mode area A to 100 ~ 150nit level suitable for the user.

In the LCD, as shown in FIG. 4, the pixel data supplied to the high-definition image mode area B such as a TV image, a video, or a high-definition photo has a relatively different gamma voltage difference between grays as shown in FIG. 10. The large first gamma voltage set D is used to convert the pixel signal. Accordingly, the transmittance range between the brightest 255 gray and the darkest zero gray due to the pixel signals supplied to the high quality image mode area B becomes relatively large. As a result, the LCD according to the embodiment of the present invention can independently adjust the average brightness of the high definition image mode area B to 300 to 400 nits required by the user.

As described above, the liquid crystal display and the driving method thereof according to the embodiment of the present invention use at least two gamma voltage sets having different voltage ranges so that the luminance of the liquid crystal panel can be adjusted for each region according to a user's command. do. Accordingly, the present invention adjusts the brightness required by the user for each high-definition image mode area requiring high brightness, such as a TV image, a video, or a high quality image, and a word mode area requiring low brightness, such as a text mode of a computer. It becomes possible.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (12)

A liquid crystal panel in which a liquid crystal cell is formed at an intersection of the gate lines and the data lines; An identification signal generator for generating an identification signal for specifying the luminance of the display image for each region in response to a user command; A gamma voltage generator for generating at least two gamma voltage sets having different voltage ranges; A data driver selecting one of the gamma voltage sets in response to an identification signal from the identification signal generator and converting digital data into analog data using the selected gamma voltage set to supply the data lines; A gate driver for driving the gate lines; And A timing controller for controlling the gate driver and the data driver, And the identification signal generator is built in the timing controller. delete delete The method of claim 1, The data driver, A shift register array for generating a sampling signal, A latch array configured to temporarily store and output the digital data in response to the sampling signal; An identification signal shift register for receiving and storing the identification signal; A multiplexer array for selecting and outputting any one gamma voltage set of the at least two gamma voltage sets according to the identification signal from the shift register for identification signal; A digital-analog converter array for converting the digital data into the analog data using a set of gamma voltages from the multiplexer array; And an output buffer array for outputting the analog data from the digital-analog converter array. The method of claim 4, wherein And each of the multiplexers of the multiplexer array supplies the selected gamma voltage set to a digital-analog converter, but supplies the digital-analog converter in units of one or three. The method of claim 1, The gamma voltage generator, And generating a second gamma voltage set having a first gamma voltage set and a gamma voltage range that is smaller than the gamma voltage range of the first gamma voltage set. The method of claim 1, The gamma voltage generator, At least two reference gamma voltage sections for generating at least two reference gamma voltage sets in different voltage ranges, At least two gamma voltage sections for subdividing each of the at least two reference gamma voltage sets for each gray; Each of the at least two reference gamma voltage portions generates a set of positive and negative reference gamma voltages, And each of the at least two gamma voltage units generates a set of positive and negative gamma voltages. delete Generating an identification signal for specifying the luminance of the display image for each region in response to a user command; Generating at least two gamma voltage sets having different voltage ranges; And Selecting one of the gamma voltage sets in response to the identification signal, converting digital data into analog data using the selected gamma voltage set, and supplying the digital data to a data line of a liquid crystal panel; Converting the digital data into the analog data and supplying the digital data to a data line of a liquid crystal panel, Receiving and storing the identification signal; Generating a sampling signal; Temporarily storing the digital data in response to the sampling signal; Selecting and outputting one of the at least two gamma voltage sets according to the identification signal; Converting the digital data into the analog data using the selected gamma voltage set; And And supplying the analog data to a data line of the liquid crystal panel. delete The method of claim 9, Generating the gamma voltage set, And a second gamma voltage set having a first gamma voltage set and a gamma voltage range smaller than the gamma voltage range of the first gamma voltage set. The method of claim 9, Converting the digital data into the analog data, Converting the digital data into the analog data with the first gamma voltage set when the identification signal indicating a high quality image mode is input; And And converting the digital data into the analog data with the second gamma voltage set when the identification signal indicating a word mode is input.

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