KR101622641B1 - Driving circuit for liquid crystal display device and method for driving the same - Google Patents

Abstract

The present invention relates to a driving apparatus for a liquid crystal display device and a driving method thereof that can simplify a driving signal of a liquid crystal display device capable of switching a direction of a display image and a supply configuration of driving power sources, A plurality of gates and a data driver for driving a plurality of gates and data lines provided in the liquid crystal panel and image data input from the outside are supplied to the data driver and a video display direction of the liquid crystal panel is selected And a timing controller for generating a direction selection signal and supplying the generated direction selection signal to the gate and the data driver, wherein the data driver sets a voltage level of a plurality of driving voltages inputted to set the driving direction of the gate driver, Switched to invert It characterized in that to be supplied to the gate driver.

Video display direction switching, direction selection signal, driving voltage switching,

Description

TECHNICAL FIELD [0001] The present invention relates to a driving apparatus for a liquid crystal display device and a driving method thereof. BACKGROUND OF THE INVENTION [0002]

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device which can simplify a driving signal of a liquid crystal display device capable of switching the direction of a display image and a supply configuration of driving power sources, And a driving method thereof.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, a driving circuit for driving the liquid crystal panel, and a backlight unit for irradiating light to the liquid crystal panel.

Generally, a data driver constituting a driving circuit in a liquid crystal display device, for example, a plurality of data integrated circuits are attached to at least one source printed circuit board or a printed circuit film, respectively, and in the case of a gate driver, They may be attached separately or directly on the liquid crystal panel. In the case of a timing controller or a drive system, a separate control printed circuit board is separately provided on the back panel to supply drive control signals necessary for the gate and data integrated circuits.

In recent years, a liquid crystal display device has been developed which can invert the display direction of a video image according to need. Such a liquid crystal display device sequentially drives the gate driver in the forward direction or the backward direction to display the image in the forward direction or the reverse direction .

To this end, a conventional liquid crystal display device generates a direction switching signal and a gate driving signal for switching a display direction of an image and supplies the generated driving signal to a gate driver. In addition, a plurality of driving voltages for driving gate drivers in a forward direction or a backward direction And supplies the gate driver.

However, since the direction switching signal and the gate driving signal can be generated and supplied directly, a plurality of driving voltages are required to be supplied by converting the voltage level or the polarity thereof in accordance with the forward or reverse video display direction The supply configuration becomes complicated. In other words, since each of the driving voltages supplied to the gate driver is switched to a positive or negative voltage level according to the display direction of the image, or to be supplied to the gate high or low voltage level, A device, a switching circuit, and the like.

 Accordingly, in the conventional liquid crystal display devices, the structure of the driving circuits and the transmission line structures of the control signals are complicated, resulting in lower space utilization of the driving circuit, and increased manufacturing cost and size.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to simplify the configuration of supplying driving signals and driving voltages of a liquid crystal display device capable of switching the direction of a display image so as to increase the space utilization of the driving circuit, And an object of the present invention is to provide a driving apparatus for a liquid crystal display apparatus and a driving method thereof.

According to an embodiment of the present invention, there is provided an apparatus for driving a liquid crystal display, including: a plurality of gates provided in a liquid crystal panel; a gate and a data driver for driving data lines; And a timing controller for supplying the data driver with a direction selection signal for selecting a video display direction of the liquid crystal panel, and supplying the direction selection signal to the gate and the data driver, wherein the data driver sets a driving direction of the gate driver The voltage level of the plurality of input driving voltages is switched to be inverted according to the direction selection signal, and then supplied to the gate driver.

Wherein the data driver comprises a plurality of data integrated circuits, and at least one of the plurality of data integrated circuits includes a plurality of data drivers for setting a driving direction of the gate driver according to a high or low logic state of the direction selection signal And a driving voltage switching unit for supplying the driving voltages to the gate driver as they are or for switching the driving voltages to each other so that the voltage levels are inverted with respect to each other and supplied to the gate driver.

The driving voltage switching unit may include a first switching device receiving the driving voltages to which the driving direction of the gate driver is set and outputting only one of the driving voltages according to the high or low logic state of the direction selection signal, And a second switching device receiving a driving voltage to which a driving direction of the driver is set and outputting only a driving voltage different from a driving voltage output through the first switching device according to a high or low logic state of the direction selection signal .

Each of the first and second switching elements is composed of a first and a second multiplexer. The first multiplexer receives driving voltages to which the driving direction of the gate driver is set, Selects and outputs a first driving voltage of a gate high voltage level among the driving voltages depending on a state and selectively outputs a second driving voltage of a gate low voltage level according to a low logic state of the direction selection signal, 2 multiplexer receives the driving voltages to which the driving direction of the gate driver is set, as opposed to the first multiplexer output, and outputs the gate-low voltage level of the driving voltages according to the high logic state of the direction selection signal A second driving voltage is selectively output, and in accordance with the low logic state of the direction selection signal, Selecting the output voltage is characterized.

Wherein the gate driver includes at least one shift register having a plurality of stages connected to each other in a dependent manner, wherein the at least one shift register has the first or second driving voltage And sequentially drives the gate lines in a forward direction or a backward direction according to a level state.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device, comprising: supplying image data input from an external device to a data driver; Generating a direction selection signal for selecting a video display direction of the liquid crystal panel and supplying the generated direction selection signal to the data driver; Switching the voltage levels of the plurality of driving voltages inputted to set the driving direction of the gate driver to be opposite to each other according to the direction selection signal using the data driver, and supplying the switched voltage to the gate driver.

Wherein the step of switching the voltage level of the plurality of driving voltages to supply the gate driver with the voltage level of the plurality of driving voltages is performed by using at least one data integrated circuit constituting the data driver to drive the gate driver in accordance with the high or low logic state of the direction selection signal And supplying the plurality of driving voltages to the gate driver as they are, or by switching the plurality of driving voltages so that the voltage levels are inverted from each other.

Switching each of the plurality of driving voltages includes receiving the driving voltages using a first switching device and outputting only one of the driving voltages according to a high or low logic state of the direction selection signal, And outputting only a driving voltage different from any one of the driving voltages output through the first switching device in accordance with the high or low logic state of the direction selection signal by receiving the driving voltages using the second switching device .

Each of the first and second switching elements is composed of a first multiplexer and a second multiplexer. The first multiplexer receives driving voltages to which the driving direction of the gate driver is set, A first driving voltage having a gate high voltage level among the driving voltages and a second driving voltage having a gate low voltage level according to a logic low state of the direction selection signal, The second multiplexer receives the driving voltages to which the driving direction of the gate driver is set, as opposed to the first multiplexer output, and outputs a gate low voltage level Of the gate high voltage level according to the low logic state of the direction selection signal, And a drive voltage is selectively output.

Wherein the gate driver includes at least one shift register having a plurality of stages connected to each other in a dependent manner, wherein the at least one shift register has the first or second driving voltage And sequentially drives the gate lines in a forward direction or a backward direction according to a level state.

The driving device and the driving method of the liquid crystal display device according to the embodiment of the present invention can simplify the configuration of supplying the driving signals and driving voltages of the liquid crystal display device capable of changing the direction of the display image. Accordingly, the present invention can increase the space utilization of the simplified driving circuit and reduce the manufacturing cost thereof.

Hereinafter, a driving apparatus and a driving method of a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram showing a liquid crystal display device according to an embodiment of the present invention. 2 is a block diagram showing the liquid crystal display device shown in FIG. 1 in more detail.

The liquid crystal display device shown in FIGS. 1 and 2 includes a liquid crystal panel 2 formed with a plurality of pixel regions; A gate driver 6 for driving the plurality of gate lines GL1 to GLn provided in the liquid crystal panel 2; A data driver 4 for driving a plurality of data lines DL1 to DLm; Generates a direction selection signal (Inv) for supplying image data (RGB) inputted from the outside to the data driver (4) and selecting the image display direction of the liquid crystal panel (2) 4); And a power supply unit 11 for generating a plurality of driving voltages VDD, VSS and Vcom using the external input power supply Vin and supplying the generated driving voltages VDD, VSS and Vcom to the liquid crystal panel 2 and the gate and data drivers 6 and 4, respectively do. The data driver 4 generates the driving voltages VDD and VSS to which the driving direction of the gate driver 4 is set among the plurality of driving voltages VDD, VSS, and Vcom input from the power supply unit 11, ) According to the direction selection signal (Inv), and supplies the inverted voltage level to the gate driver (4).

The liquid crystal panel 2 includes a thin film transistor (TFT) formed in each pixel region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, and a liquid crystal capacitor (Clc). The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT, and a common electrode facing the pixel electrode and the liquid crystal. The TFT supplies a video signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the video signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage. The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied. The storage capacitor Cst is formed by overlapping the pixel electrode with the previous gate line and the insulating film interposed therebetween. Alternatively, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line and the insulating film interposed therebetween.

2, the data driver 4 is provided between one side of the liquid crystal panel 2 and at least one of the source printed circuit boards 8a and 8b to drive the data lines DL1 to DLm And includes a plurality of data integrated circuits 4a and 4b. Each of the plurality of data integrated circuits 4a and 4b is mounted on the data circuit films 6a and 6b and connected between the liquid crystal panel 2 and one of the source printed circuit boards 8a and 8b.

The data circuit films 6a and 6b may be formed of a tape carrier package (TCP) film or a chip on flexible printed circuit (COF) film. Particularly, in the case of the data circuit films 6a and 6b each having the data integrated circuits 4a and 4b mounted thereon, at least one source printed circuit board 8a and 8b and a liquid crystal panel (not shown) are formed by a TAB (Tape Automated Bonding) 2).

Each of the data integrated circuits 4a and 4b outputs a data control signal DCS, for example, a source start signal SSP (Source Start Pulse), a source shift clock (SSP), or the like, according to a direction selection signal Inv from the timing controller 18. [ That is, the video data, from the timing controller 8 using a source shift clock (SSC), a source output enable (SOE) signal, or the like. Specifically, the data driver 4 latches the aligned data Data through the timing controller 8 in accordance with the SSC, and then, in response to the SOE signal, supplies the scan pulses to the gate lines GL1 to GLn And supplies video signals for one horizontal line to each of the data lines DL1 to DLm for each horizontal period. At this time, the data driver 4 selects a positive or negative gamma voltage having a predetermined level according to the gradation value of the aligned data Data, and outputs the selected gamma voltage to each of the data lines DL1 to DLm Supply.

At least one of the data integrated circuits 4a and 4b of each of the data integrated circuits 4a and 4b includes at least one switching unit so that a plurality of driving voltages VDD The voltages of the driving voltages VDD and VSS to which the driving direction of the gate driver 4 is set are switched with each other in accordance with the direction selection signal Inv, To be supplied to the gate driver (4). The data integrated circuits 4a and 4b for inverting and outputting the voltage levels of the driving voltages VDD and VSS will be described in more detail with reference to the accompanying drawings.

The gate driving unit 4 may be formed integrally with the liquid crystal panel 2 in the image non-display area of the liquid crystal panel 2 or may be provided in an integrated circuit form separately on one side of the liquid crystal panel 2. The gate driving unit 4 applies the gate selection signals to the gate lines GL1 to GLn according to the direction selection signal Inv from the timing controller 8 and the driving voltages VDD and VSS input through the data driver 4. [ ) In a forward or backward direction.

Specifically, the gate driving unit 4 generates a gate control signal GCS, for example, a gate start signal GSP (VSS), in accordance with the direction selection signal Inv from the timing controller 8 and the respective driving voltages VDD and VSS. A gate pulse is applied to each gate line GL1 to GLn in a forward direction using a gate start pulse, a gate shift clock (GSC), a gate output enable (GOE) signal, Respectively.

For example, the gate driver 4 may be composed of at least one shift register (not shown), which is composed of a plurality of stages connected to each other in a dependent manner so that each of the stages includes gate lines GL1 to GLn The scan pulse is sequentially output. At this time, the stages connected to each other are respectively supplied with a first driving voltage VDD having a gate high voltage level and a second driving voltage VSS having a gate low voltage level at a plurality of driving voltage input terminals.

Each of the stages is sequentially driven in a forward direction or a reverse direction depending on the driving voltage of a certain voltage level input to each of the driving voltage input terminals. For example, the first driving voltage input terminal of each stage has a gate high voltage level When the first driving voltage VDD is input and the second driving voltage VSS of the gate-low voltage level is input to the second driving voltage input terminal, a plurality of stages, which are connected to each other in a dependent manner, are sequentially driven in the forward direction, And sequentially outputs scan pulses to the scan electrodes GL1 to GLn. When the second driving voltage VSS having the gate low voltage level is input to the first driving voltage input terminal and the first driving voltage VDD having the gate high voltage level is input to the second driving voltage input terminal, A plurality of stages are sequentially driven in the reverse direction to sequentially output scan pulses to the gate lines GL1 to GLn in the opposite direction. In addition, a gate low voltage is supplied during a period in which no scan pulse is supplied to each of the gate lines GL1 to GLn.

The timing controller 8 may be provided on a separate control printed circuit board 10 or on at least one of the source printed circuit boards 8a and 8b as shown in Fig. And controls the data driver 4 and the gate driver 6 in accordance with the plurality of synchronization signals DCLK, Hsync, Vsync, and DE.

Specifically, the timing controller 8 arranges image data (RGB) input from an external system, for example, a TV system or a video card, to suit the drive of the liquid crystal panel 2 and supplies the image data RGB to the data driver 4 do. The gate and data control signals GCS and DCS are generated using at least one of a synchronizing signal input from the outside, that is, a dot clock DCLK, a data enable signal DE, and horizontal and vertical synchronizing signals Hsync and Vsync. And controls the gate and data drivers 6 and 4 by supplying them to the gate and data drivers 6 and 4, respectively. The timing controller 8 also generates a direction selection signal Inv for selecting the driving direction of the liquid crystal panel 2, that is, the video display direction of the liquid crystal panel 2, , 4). Since the direction selection signal Inv can be converted according to the use of the liquid crystal display device, the direction selection signal Inv can be determined by supplying a separate direction signal or the like according to the user's selection.

FIG. 3 is a block diagram specifically showing any one of the data integrated circuit and the gate driver shown in FIG. 2. FIG.

The at least one data integration circuit shown in FIG. 3 includes a shift register 21 for outputting a sampling signal (SAM) in response to SSP and SSC from the timing controller 8; A latch unit 22 for sequentially sampling image data Data in accordance with the sampling signal SAM and simultaneously outputting one line of data RData sampled according to the SOE signal, A gamma voltage generator 24 for varying the voltage level of the gamma voltages GV according to the signal POL and outputting the voltage level of the gamma voltages GV as a whole, A digital-to-analog converter (DAC) 23 for converting line data RData into an analog video signal AData and outputting the analog video signal AData from the DAC 23 The output buffers 25 for supplying the data voltages to the data lines DL1 to DLm and the driving voltages for driving the gate driver 4 in accordance with the high or low logic state of the direction selection signal Inv VDD, VSS) to the gate driver Each supplied or provided with the driving voltages (VDD, VSS), respectively, by switching the driving voltage switching unit 30 to be supplied to the gate driver 4 that voltage level to each other turn.

The shift register 21 generates the sampling signal SAM by using the SSC and the SSP from the timing controller 8. [ Specifically, the shift register 21 generates the sampling signal SAM by shifting the source start pulse SSP according to the SSC, and sequentially supplies the sampling signal SAM to the latch unit 22. [

The latch unit 22 sequentially samples the image data Data supplied from the timing controller 8 through the data bus line in accordance with the sampling signal SAM from the shift register 21. The sampled data is stored in units of one horizontal line, and the latched image data (RData) for one horizontal line is simultaneously output to the DAC 25 in response to the SOE signal.

The gamma voltage generator 24 receives the first and second driving voltages VDD and VSS and a plurality of reference gamma voltages RGV from a power supply unit 11 and a reference gamma voltage generator. Here, the first driving voltage VDD may be a positive DC driving voltage, and the second driving voltage VSS may be a negative DC driving voltage. The gamma voltage generator 24 generates the positive (+) and negative (-) gamma voltages (VDD and VSS) in a divided mode between a plurality of resistors serially connected between the first and second driving voltages And supplies a plurality of positive (+) and negative (-) gamma voltages GV to the DAC 23, as shown in FIG.

The DAC 23 is supplied with a plurality of positive (+) or negative (-) gamma voltages supplied with varying voltage levels according to the polarity control signal POL from the timing controller 8 and the selection enable signal En Converts the video data RData into the positive polarity positive or negative polarity analog video signal AData by using the voltage GV and outputs the converted video signal AData of one line to the output buffer 25). Here, the polarity control signal POL can be inverted in at least one horizontal line unit. Specifically, when a plurality of positive (+) gamma voltages GV are supplied from the gamma voltage generator 24 by the polarity control signal POL, the DAC 23 outputs the image data (+) Gamma voltage (GV) corresponding to the reference voltage (RData) to convert it into an analog video signal (AData) and output it. If a plurality of negative (-) gamma voltages GV are supplied from the gamma voltage generator 24, a negative (-) gamma voltage GV corresponding to the image data RData is selected, Signal (AData) and outputs it.

The output buffer 25 outputs the video signal AData using the first driving voltage VDD in order to prevent the video signal AData from the DAC 23 from being distorted according to the RC time constant of the data lines DL1 to DLm. (AData) and supplies the amplified video signal (AData) to the data lines (DL1 to DLm).

When the direction selection signal Inv input from the timing controller 8 is input in a logical state of a high voltage level, the driving voltage switching unit 30 switches the driving voltages of the gate driver 4 The first drive voltage VDD of the gate high voltage level is supplied to the first drive voltage input terminal of the gate driver 6 and the second drive voltage VSS of the gate low voltage level is supplied to the gate driver 6 6 to the second drive voltage input terminal. In this case, the shift register of the gate driver 6 is driven in a forward direction to sequentially output scan pulses to the gate lines GL1 to GLn.

On the other hand, when the direction selection signal Inv inputted from the timing controller 8 is inputted in the logic state of the low voltage level, the driving voltage switching unit 30 outputs the driving voltages Supplies the first driving voltage VDD of the gate high voltage level of the gate driver 6 to the second driving voltage input terminal of the gate driver 6 and the second driving voltage VSS of the gate low voltage level, To the first drive voltage input terminal of the second transistor (6). In this case, the shift register of the gate driver 6 is driven in the reverse direction to sequentially output scan pulses to the gate lines GL1 to GLn.

4 is a block diagram showing the driving voltage switching unit shown in FIG.

The driving voltage switching unit 30 shown in FIG. 4 receives the driving voltages VDD and VSS at which the driving direction of the gate driver 4 is set, And at least one switching element for outputting only one of the driving voltages VDD and VSS according to a logic state.

More specifically, the at least one switching element may be composed of at least one multiplexer (MUX1, MUX2), and the first multiplexer (MUX1) may control the driving voltage of the gate driver (4) The first driving voltage VDD of the gate high voltage level among the driving voltages VDD and VSS is selectively output according to the high logic state of the direction selection signal Inv, And selectively outputs the second driving voltage VSS having the gate-low voltage level according to the low logic state of the selection signal Inv.

On the other hand, the second multiplexer MUX2 receives the driving voltages VDD and VSS to which the driving direction of the gate driver 4 is set, as opposed to the output of the first multiplexer MUX1, Inv according to the logic state of the direction selection signal (Inv), the second driving voltage (VSS) of the gate low voltage level among the driving voltages (VDD, VSS) And selectively outputs the second driving voltage VSS having the high voltage level. To this end, the second multiplexer MUX2 may further include a phase inversion element for inverting the phase of the direction selection signal Inv supplied to the first multiplexer MUX1.

As described above, the driving apparatus and the driving method of the liquid crystal display according to the embodiment of the present invention are capable of switching the driving signals and driving voltages of the liquid crystal display device capable of changing the direction of the display image to a separate switching circuit, It is possible to switch the data through the data driver 4 without using it. Therefore, by simplifying the configuration of supplying the driving signals and the driving voltages of the liquid crystal display, it is possible to increase the space utilization of the driving circuit and reduce the manufacturing cost.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is a circuit diagram showing a liquid crystal display device according to an embodiment of the present invention.

Fig. 2 is a configuration diagram showing the liquid crystal display device shown in Fig. 1 in more detail.

FIG. 3 is a block diagram specifically showing any one of the data integrated circuit and the gate driver shown in FIG. 2. FIG.

Fig. 4 is a configuration diagram showing the drive voltage switching unit shown in Fig. 3. Fig.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

2: liquid crystal panel 4: data driver

6: Gate driver 8: Timing controller

11: Power supply unit 10: Control printed circuit board

21: shift register 22: latch portion

23: DAC 24: gamma voltage generator

30: driving voltage switching unit

Claims (10)

A gate and a data driver for driving a plurality of gates and data lines provided in the liquid crystal panel; And And a timing controller for generating a direction selection signal for selecting a video display direction of the liquid crystal panel and supplying the generated direction selection signal to the gate and the data driver, The data driver A gate driver for inverting the voltage levels of the plurality of input driving voltages according to the direction selection signal and supplying the inverted voltage levels to the gate driver, Wherein the data driver comprises a plurality of data integrated circuits, Wherein at least one of the plurality of data integrated circuits includes: And supplies the plurality of drive voltages to the gate driver as they are, according to a high or low logic state of the direction selection signal, or supplies the gate drivers with the voltage levels inverted by switching the plurality of drive voltages, respectively A driving apparatus for a liquid crystal display device having a driving voltage switching unit. delete The method according to claim 1, The driving voltage switching unit A first switching element receiving the plurality of driving voltages and outputting only one of the driving voltages according to a high or low logic state of the direction selection signal, And a second switching element receiving a plurality of driving voltages and outputting only a driving voltage different from a driving voltage outputted through the first switching element according to a high or low logic state of the direction selection signal, . The method of claim 3, Each of the first and second switching elements Wherein the first multiplexer receives the plurality of driving voltages and selects one of the driving voltages based on a high logic state of the direction selection signal, And selectively outputs a second drive voltage having a gate low voltage level according to a low logic state of the direction selection signal, The second multiplexer receives the plurality of driving voltages in a direction opposite to the first multiplexer output and receives a second driving voltage having a gate low voltage level of the driving voltages, And selectively outputs a second drive voltage having a gate high voltage level in accordance with the low logic state of the direction selection signal. 5. The method of claim 4, The gate driver And at least one shift register having a plurality of stages connected to each other in a dependent manner, Wherein the at least one shift register sequentially drives the gate lines in a forward or backward direction according to the first or second driving voltage level state inputted to the first and second driving voltage input terminals, . Arranging image data inputted from outside and supplying to the data driver; Generating a direction selection signal for selecting a video display direction of the liquid crystal panel and supplying the generated direction selection signal to the data driver; And supplying the gate driver with a voltage level of a plurality of driving voltages to be inverted in accordance with the direction selection signal to set a driving direction of the gate driver using the data driver, The step of switching the voltage level of the plurality of driving voltages to supply the gate driver And supplying the plurality of driving voltages to the gate driver as it is according to a high or low logic state of the direction selection signal using at least one data integration circuit constituting the data driver, And switching the plurality of driving voltages so that their voltage levels are inverted from each other, and supplying the inverted voltages to the gate driver. delete The method according to claim 6, The step of switching each of the plurality of driving voltages Receiving the driving voltages using a first switching device and outputting only one of the driving voltages according to a high or low logic state of the direction selection signal; And outputting only a driving voltage different from any one of the driving voltages output through the first switching device in accordance with the high or low logic state of the direction selection signal by receiving the driving voltages using the second switching device A method of driving a liquid crystal display device. 9. The method of claim 8, Each of the first and second switching elements Each of the first and second multiplexers having a first multiplexer for receiving the plurality of driving voltages and receiving a first logic level of a gate high voltage level of the driving voltages, And selectively outputs a second drive voltage having a gate low voltage level according to a low logic state of the direction selection signal, The second multiplexer receives the plurality of driving voltages in a direction opposite to the first multiplexer output and receives a second driving voltage having a gate low voltage level of the driving voltages, And selectively outputs a second driving voltage having a gate high voltage level in accordance with a low logic state of the direction selection signal. 10. The method of claim 9, The gate driver And at least one shift register having a plurality of stages connected to each other in a dependent manner, Wherein the at least one shift register sequentially drives gate lines in a forward direction or a backward direction according to the first or second driving voltage level state inputted to the first and second driving voltage input terminals, respectively.

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