KR101958654B1 - Dot inversion type liquid crystal display device - Google Patents

Abstract

The present invention discloses a liquid crystal display device. More particularly, the present invention relates to a two-dot inversion type liquid crystal display device which performs polarity inversion driving in order to prevent deterioration of the liquid crystal for each frame, and a vertical crosstalk occurring due to insufficient charging time of the liquid crystal cell ) Phenomenon is minimized.
A dot inversion liquid crystal display according to an embodiment of the present invention includes a liquid crystal panel in which a plurality of gate lines and data lines are formed in a matrix form, A data driving circuit for applying a data voltage having a polarity inverted in a vertical N-dot unit to the data line, and a timing controller for controlling the gate and the data driving circuit, , In particular, the data driving circuit switches the data voltage to the ground level during the delay period.
Accordingly, the present invention provides a reset unit for grounding a data line between two pixels whose polarity is inverted, thereby inserting a reset period for one clock in the polarity inversion charge period of the pixel to secure a charge period for the pixel, So that the phenomenon can be minimized.

Description

[0001] DOT INVERSION TYPE LIQUID CRYSTAL DISPLAY DEVICE [0002]

The present invention relates to a liquid crystal display device, and more particularly, to a two-dot version liquid crystal display device which performs polarity inversion driving to prevent deterioration of liquid crystal for each frame, a vertical crosstalk occurring due to insufficient charging time of the liquid crystal cell and a dot-inversion liquid crystal display device in which cross talk phenomenon is minimized.

As information electronic devices for realizing high-resolution and high-quality images such as potable devices such as mobile phones and notebook computers and HDTVs are developed, a flat panel display device ) Are increasingly in demand. As such flat panel display devices, a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting diode (OLED) have been actively studied. However, And realization of a large area screen, a liquid crystal display (LCD) is in the spotlight at present.

The liquid crystal display implements an image by adjusting the light transmittance of the liquid crystal cell on the liquid crystal panel in accordance with the gray level value of the data signal. However, when the DC voltage is applied to the pixels arranged in the liquid crystal panel for a long time, the light transmission characteristic of the liquid crystal cell deteriorates. This is due to the DC fixing phenomenon and is known to be the main cause of the after-image on the image displayed on the liquid crystal panel.

In order to prevent the above-described DC fixing, an inversion driving technique has been proposed in which the data signal supplied to the pixels of the liquid crystal panel is inverted based on the common voltage Vcom. The inversion method is a technique for inverting the polarity of each pixel for each frame or line. In the currently known methods, a frame inversion, a line inversion, a column inversion, Dot Inversion method.

Particularly, the N-dot inversion method implements an image of good image quality compared to the normal 1-dot inversion method and the line inversion method. FIG. 1 illustrates an example of a vertical two-dot inversion scheme having inverted polarity between neighboring pixels in the horizontal direction and polarity reversed by two dots between neighboring pixels in the vertical direction.

However, when the liquid crystal display device is driven in the N-dot inversion mode, a vertical crosstalk phenomenon may occur depending on the polarity of the data voltage charged in the pixels. This is caused by the fact that the charging period of the pixel is changed between the line having the same polarity and the line having the opposite polarity of the data voltage charged in the pixel for each horizontal line.

2 is a diagram showing an example of a charging signal waveform of each pixel for one vertical line in a 2-dot inversion type liquid crystal display device.

As shown in the figure, the 2-dot inversion type liquid crystal display device is driven sequentially from the uppermost horizontal line, and the first pixel (1 ^st pixel) is charged to a positive polarity (+) for one vertical line, 2 ^nd pixel) is charged in a strong manner. Next, the third pixel (3 ^rd pixel) is charged to negative (-) as the polarity is inverted, and the fourth pixel (4 ^th pixel) is charged to the same polarity. Then, the 6th and 7th pixels (6 ^th , 7 ^th pixel) are also charged in the same pattern.

That is, the charging period of the third pixel (3 ^rd pixel) and the fifth pixel (5 ^th pixel) whose polarities change is shorter than that of the other pixels. Therefore, before each pixel is sufficiently charged, There is a problem in that a vertical crosstalk phenomenon occurs in proportion to the insufficient amount of charge.

In order to solve such a problem, a pre-charging technique of applying a data voltage applied to a pixel at a charging time point of a pixel whose polarity changes is applied, or a charging period of the pixel is delayed from other pixels, A method of securing a charging period has been proposed. However, the above-described method sets a different charging voltage or period for each pixel in one frame, which is difficult to implement and limits the stability of a liquid crystal display device operating at a constant cycle.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an N-dot liquid crystal display device which reversely drives between N adjacent pixels to secure charge time for each pixel, And a liquid crystal display device.

In order to achieve the above object, a dot inversion type liquid crystal display according to a preferred embodiment of the present invention includes: a liquid crystal panel in which a plurality of gate lines and data lines are formed in a matrix form; A gate driving circuit for applying a gate driving signal having a delay interval in units of vertical N-dots (N is a natural number of 2 or more) to the gate line; A data driving circuit for applying a data voltage having a polarity inverted in a vertical N-dot unit to the data line; And a timing controller for controlling the gate and the data driving circuit, and the data driving circuit switches the data voltage to the ground level during the delay period.

And the delay period is equal to or less than one horizontal period (1H).

The voltage level of the data voltage is determined to be at least one of bipolarity, negative polarity and ground level.

Wherein the timing controller extends a high level period of the gate output enable signal GOE for determining the output timing of the gate driving signal in the polarity inversion period of the data voltage by the delay period, And an output delay unit for generating a polarity reversal signal POL to be determined.

The data driving circuit includes: a shift register unit sequentially outputting a sampling signal under the control of the timing controller; A latch unit for sequentially sampling and storing image data from the timing controller corresponding to the sampling signal; A digital-analog converter (DAC) for selecting a reference voltage corresponding to the image data stored in the latch unit and converting the reference voltage into a data voltage; And a buffer unit for collectively providing the data voltages to the data lines.

And the shift register unit generates the sampling signal corresponding to the source sampling pulse SSP and the source start clock SSC output from the timing controller.

The digital-analog converter includes a P-decoder to which a bipolar reference voltage is applied; An N-decoder to which a negative polarity reference voltage is applied; And a multiplexer for selecting at least one of the P-decoder, the N-decoder, and the ground voltage terminal.

And the multiplexer selects an output corresponding to the polarity inversion signal (POL) output from the timing controller.

According to a preferred embodiment of the present invention, there is provided a reset section for grounding a data line between two pixels whose polarities are inverted in an N-dot inversion type liquid crystal display device, so that a reset period So that the vertical crosstalk phenomenon can be minimized by securing the charging period for the pixel.

FIG. 1 is a diagram showing an example of the polarity of a vertical two-dot inversion type liquid crystal display device.
2 is a diagram showing an example of a charging signal waveform of each pixel for one vertical line in a 2-dot inversion type liquid crystal display device.
3 is a view illustrating an N-dot inversion type liquid crystal display device according to a preferred embodiment of the present invention.
FIG. 4A is a block diagram showing the structure of a data driving circuit according to an embodiment of the present invention, and FIG. 4B is a schematic diagram for explaining the operation of the multiplexer included in the DAC of the data driving circuit of FIG. 4A.
FIG. 5 is a diagram illustrating a signal format when driving a liquid crystal display according to an exemplary embodiment of the present invention. Referring to FIG.

Hereinafter, a dot inversion liquid crystal display according to a preferred embodiment of the present invention will be described with reference to the drawings.

3 is a view illustrating an N-dot inversion type liquid crystal display device according to a preferred embodiment of the present invention.

As shown in the figure, the liquid crystal display device to which the vertical N-dot inversion (N is a natural number) driving method according to the embodiment of the present invention is applied includes a liquid crystal panel 100 for displaying an image, And a driving circuit unit 120 for driving the driving circuit.

The liquid crystal panel 100 has a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm crossing in a matrix form on a substrate using a glass and forming a plurality of pixel regions at intersections. A thin film transistor (TFT), a liquid crystal cell Clc, and a liquid crystal capacitor Cst are formed in each pixel region to display an image.

The driving circuit unit 120 includes an interface 121, a timing controller 122, a gate driving circuit 125, and a data driving circuit 126.

The interface 121 connects an external system such as a personal computer to a liquid crystal display device and transmits image related data input from the external system to the driving circuit 120 and a clock signal CLK, a horizontal synchronizing signal Hsync, Timing signals including a vertical synchronization signal Vsync and a data enable signal DE are supplied to the timing controller 122.

As the interface 21, a low voltage differential signal (LVDS) interface and a TTL interface are widely used. In addition, such an interface may be configured in such a form that the functions are integrated in a single chip by mounting the functions in the timing controller 122.

The timing controller 122 controls the timing of the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE and the clock signal CLK input from the external system through the interface 121 And generates a data control signal DCS for driving the gate control signal GCS and the data driving circuit 126 for driving the gate driving circuit 125 and for controlling the output of the data voltage.

The timing controller 122 includes an output delay unit 123 for a gate driving signal and a data driving signal. The output delay unit 123 delays the output timing of the gate driving signal from the gate control signal GSC for one horizontal period (1H) at the polarity inversion time and at the same time modulates the data voltage to the ground voltage (GND) level .

To this end, the timing controller 122 extends the high level period of the gate output enable signal GOE for determining the output timing of the gate driving signal in the polarity inversion period of the data voltage by the delay period, And an output delay unit 123 for generating a polarity inversion signal POL for determining the polarity inversion signal POL.

The timing controller 122 aligns and converts the image related data (RGB DATA) input through the interface 121 and supplies the image data to the data driving circuit 126.

The gate driving circuit 125 is composed of a plurality of shift registers. The gate driving circuit 125 turns on / off the thin film transistors (TFT) arranged on the liquid crystal panel 100 in response to the gate control signals input from the timing controller 122. [ As shown in FIG.

The gate control signals include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). The gate start pulse GSP is applied to a shift register for generating a first gate driving signal to control the shift register so that a first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to all the shift registers, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE is a signal for controlling the output of the shift registers. In particular, the output delay unit 123 of the timing controller 120 adjusts the width of a part of the high-level period of the gate output enable signal GOE among the above-mentioned control signals for delaying the output of the gate driving signal.

The above-described gate driving circuit 125 generates a gate driving signal corresponding to the above-described control signals and supplies the gate driving signals to the gate lines GL1 to GLn to turn on the thin film transistors. Accordingly, when the video signals are supplied from the data driving circuit 126, the data voltages are applied to the liquid crystal cells connected to the TFTs.

In addition, the gate driving circuit 125 of the present invention applies a gate driving signal having a delay period of one horizontal period (1H) in units of vertical N-dots to the gate lines GL1 to GLn, The gate driving signal becomes low level and all the thin film transistors are turned off.

The data driving circuit 126 includes a shift register, a latch, and a digital-analog converter (DAC). The data driving circuit 126 selects the reference voltages in response to the data control signals input from the timing controller 122 and converts the image data of the input digital waveform corresponding to the selected reference voltage into the data voltage of the analog waveform And supplies it to the liquid crystal panel 100.

The data control signals include a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable (SOE) . The source start pulse SSP is a signal for controlling the data sampling circuit start timing of the data driving circuit 126. The source sampling clock SSC corresponds to the rising or falling edge of the data driving circuit 126, And a clock signal for controlling the timing. The polarity control signal POL is a signal for controlling the horizontal polarity inversion timing of the data voltages simultaneously output from each of the plurality of driver ICs constituting the data driver circuit 126. The source output enable signal SOE is a signal for controlling the output timing of the source driver 126.

In particular, the output delay unit 123 of the timing controller 122 controls the switching point of the data voltage to the ground voltage level through the above-described polarity control signal POL.

The data driving circuit 126 samples the input image data RGB DATA corresponding to the data control signal DCS described above and outputs the polarity control signal To the analog bipolar reference voltage or the negative polarity reference voltage according to the reference voltage (POL), or to ground as the data voltage during the delay period. Here, the data voltages applied to the pixels neighboring in the vertical direction have polarities inverted from each other, and the data voltages applied to the neighboring pixels in the horizontal direction have the same polarity, .

According to this structure, when the liquid crystal display device of the present invention is driven by a version method in which N-dot (N is a natural number of 2 or more), the above-described gate driving circuit 125 supplies vertical N-dots A gate driving signal having a delay period of one horizontal period (1H) is applied in units of a horizontal period (1H), and all the thin film transistors turn-off in the delay period. In synchronization with this, the data driving circuit 126 outputs the data voltage of the ground level, so that all the data lines DL1 to DLm are discharged.

That is, at the time when the polarity of the pixel is inverted in the horizontal direction, the data voltage is switched to the ground voltage level during one horizontal period (1H), so that the charging time can be secured at the time of charging the data voltage of the next pixel so that the vertical crosstalk phenomenon is minimized do.

If as an example, referring again to Figure 2 for a two-dots (N = 2) inversion mode liquid crystal display device, the charging time of the pixels in a horizontal direction the third (3 ^rd pixel), and fifth pixels (5 ^th pixel) Is delayed. Accordingly, as soon as the data voltage of the ground level is applied to the data line immediately after the application of the previous data voltage, the data line is completely discharged, so that the charging period of the next pixel can be further secured.

That is, the liquid crystal display according to the embodiment of the present invention includes a liquid crystal panel 100 in which a plurality of gate lines GL1 to GLn and data lines DL1 to DLm are formed in a matrix form, a plurality of gate lines GL1 to GLn, A gate driving circuit 125 for applying a gate driving signal having a delay period in units of vertical N-dots to data lines DL1 to DLm, A driving circuit 126 and a timing controller 122 for controlling the gate and data driving circuits 125 and 126. Particularly when the data driving circuit 126 switches the data voltage to the ground level during the above- .

According to the above-described structure, the liquid crystal display of the present invention is characterized in that the charging period of each pixel is the same as that of the conventional one, but the entire vertical synchronization period is extended for one frame, But does not affect the image quality.

Hereinafter, the structure of a data driving circuit of a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 4A is a block diagram showing the structure of a data driving circuit according to an embodiment of the present invention, and FIG. 4B is a schematic diagram for explaining the operation of the multiplexer included in the DAC of the data driving circuit of FIG. 4A.

4A, the data driving circuit included in the liquid crystal display of the present invention includes a shift register unit 1261, a latch unit 1263, a digital-analog conversion unit (DAC) 145, and a buffer unit 1267 ).

The shift register 1261 serves to sequentially supply a sampling signal to the latch unit 1263 corresponding to the source sampling clock SSC and the source start pulse SSP input from the timing controller.

The latch unit 1263 samples the video data (RGB DATA) of the digital waveform from the timing controller in response to the sampling signals sequentially supplied from the shift register 1261, latches them so as to correspond to the respective data lines, To the digital-analog converter (1265).

In order to collect all the image data for each data driving circuit, the latch unit 1263 includes a first latch for storing the image data sampled from each data driving circuit, And a second latch for temporarily storing the video data for outputting in synchronization with another data driving circuit.

The digital-to-analog converter (DAC) 1265 includes a P-decoder to which a bipolar reference voltage is supplied, an N-decoder to which a negative polarity reference voltage is supplied, and a polarity control signal POL And a multiplexer (MUX) for selecting the output of the P-decoder and the output of the N-decoder.

In particular, the P-decoder decodes the digital image data (RGB DATA) supplied from the latch unit 1263 and outputs a bipolar reference voltage (P-ref) corresponding to the gray level value of the image data, And outputs the negative polarity reference voltage N-ref corresponding to the gray level value of the image data.

The multiplexer MUX also receives at least one of the positive polarity reference voltage P-ref and the negative polarity reference voltage N-ref and the ground voltage GND in response to the polarity control signal POL output from the timing controller And the positive polarity reference voltage P-ref, the negative polarity reference voltage N-ref, or the ground voltage GND, which are selected in accordance with the version driving with the N-dot (N is a natural number of 2 or more) Output.

4B schematically illustrates the structure of the above-described multiplexer. Each of the data lines DL1 to DLm extending from the buffer section includes a P-decoder, a N-decoder, and a ground voltage terminal corresponding to the polarity inversion signal POL , At least one of them is electrically connected.

 Here, the period in which the ground voltage terminal is selected is synchronized with the delay period in which the gate driving signal is delayed to a low level during one horizontal period (1H).

The buffer unit 1267 supplies analog data voltages having the above-described voltage levels to the data lines DL1 to DLm corresponding to the source output enable signal SOE output from the timing controller.

According to the above-described structure, in the N-dot inversion type liquid crystal display of the present invention, when the polarity of the pixel is inverted in the horizontal direction, the data voltage is switched to the ground voltage level for one horizontal period (1H) The charging time can be ensured when the voltage is charged.

FIG. 5 is a diagram illustrating a signal format when driving a liquid crystal display according to an exemplary embodiment of the present invention. Referring to FIG. Hereinafter, a liquid crystal display device of the present invention will be described as an example of a vertical three-dot inversion method in which three pixels are alternately inverted in the vertical direction.

As shown in the figure, in the version-type liquid crystal display device of vertical N-dot (N = 3) according to the embodiment of the present invention, the output delay portion of the timing controller outputs a gate control signal That is, the period in which the polarity of each pixel in the vertical direction is switched, is maintained at a high level for one horizontal period (1H). Accordingly, the period of the gate driving signal VG output from the gate driving circuit is changed, and the transition from the low level to the high level is delayed in the above-described delay period. Thus, all the thin film transistors are turned off.

In synchronization with this, the data voltage VD is switched to the ground level by the polarity inversion signal POL, and the data voltage VD in the delay period becomes 0 V. [

According to the above-described operation, when charging of the third pixel (3 ^rd pixel) in the vertical direction is completed and the charging of the fourth pixel (4 ^th pixel) and the charging of the sixth pixel (6 ^th pixel) (3 ^rd , 5 ^th pixel) has a sufficient charging period by adding a delay section DT between the end of charging of the first pixel (7 ^th pixel) and the charging of the seventh pixel have.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

100: liquid crystal panel 120: driving circuit part
121: Interface 122: Timing controller
123: output delay unit 125: gate drive circuit
126: Data driving circuit

Claims (8)

A liquid crystal panel in which a plurality of gate lines and data lines are formed in a matrix form;
A gate driving circuit for applying a gate driving signal having a delay period that is maintained for one horizontal period in units of vertical N-dots (N is a natural number of 2 or more) to the gate line;
A data driving circuit for applying a data voltage having a polarity inverted in a vertical N-dot unit to the data line; And
And a timing controller for controlling the gate and the data driving circuit,
During the delay period, the gate driving signal is maintained at a low level,
The data driving circuit maintains the data voltage at the ground level during the delay period,
And the charging periods of the data voltages for the respective pixels are equal to each other.
delete The method according to claim 1,
The voltage level of the data voltage
The polarity, the negative polarity, and the ground level of the dot inversion liquid crystal display device. The method according to claim 1,
The timing controller includes:
Level period of a gate output enable signal (GOE) for determining the output time point of the gate driving signal in the polarity inversion period of the data voltage by the delay period, and a polarity inversion signal Further comprising an output delay unit for generating a reference voltage (POL). 5. The method of claim 4,
The data driving circuit
A shift register unit sequentially outputting a sampling signal under the control of the timing controller;
A latch unit for sequentially sampling and storing image data from the timing controller corresponding to the sampling signal;
A digital-analog converter (DAC) for selecting a reference voltage corresponding to the image data stored in the latch unit and converting the reference voltage into a data voltage; And
And a buffer unit for collectively providing the data voltages to the data lines
And a liquid crystal display panel. 6. The method of claim 5,
The shift register unit includes:
And generates the sampling signal corresponding to the source sampling pulse SSP and the source start clock SSC output from the timing controller. 6. The method of claim 5,
The digital-to-
A P-decoder to which a bipolar reference voltage is applied;
An N-decoder to which a negative polarity reference voltage is applied; And
A multiplexer for selecting at least one of the P-decoder, N-decoder,
And a liquid crystal display panel. 8. The method of claim 7,
The multiplexer comprising:
And selects an output corresponding to the polarity inversion signal (POL) output from the timing controller.

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