KR101264703B1 - LCD and drive method thereof - Google Patents

Abstract

According to an exemplary embodiment of the present invention, an N-frame inversion driving method adjusts a high section width of a gate output enable signal used for masking a scan pulse, thereby reducing the data charging amount of a subsequent frame among neighboring frames without inversion. A display device, comprising: a liquid crystal display panel on which a plurality of gate lines are formed; Generates a frame inversion polarity signal indicative of N-frame inversion, generates a gate start pulse instructing the supply of scan pulses, and generates first and second gate output enable signals used for masking the scan pulses. A timing controller; A masking controller converting the frame inversion polarity signal into a masking selection signal in response to the gate start pulse; A multiplexer for selectively outputting the first and second gate output enable signals in accordance with the masking selection signal; And sequentially supplying scan pulses to the gate lines under the control of the timing controller, wherein the scan pulses are constant in response to the first gate output enable signal or the second gate output enable signal output from the multiplexer. And a gate driver for masking the section.

LCD, Gate Output Enable Signal, Masking, Frame, Inversion

Description

Liquid crystal display and driving method thereof

1 is an equivalent circuit diagram of a pixel formed in a general liquid crystal display device.

2 is a block diagram of a conventional liquid crystal display device.

3 is an illustrative example of N-frame inversion.

4 is a signal characteristic diagram of a conventional liquid crystal display device to which an N-frame inversion scheme is applied.

5 is a luminance characteristic diagram of a conventional liquid crystal display device to which an N-frame inversion scheme is applied.

6 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.

7 is a signal characteristic diagram of a liquid crystal display device according to the present invention;

8 is a circuit diagram of the masking control unit shown in FIG. 6.

9 is a signal characteristic diagram of the masking control unit shown in FIG. 6.

Description of the Related Art

100 and 200: liquid crystal display 110: liquid crystal display panel

120, 250: data driver 130, 240: gate driver

140: gamma reference voltage generator 150: backlight assembly

160: inverter 170: common voltage generator

180: gate driving voltage generator 190, 210: timing controller

220: masking control unit 230: multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device. In particular, in the N-frame inversion driving method, data of a later frame among neighboring frames without inversion is adjusted by adjusting a high section width of a gate output enable signal used for masking a scan pulse. The present invention relates to a liquid crystal display device and a driving method thereof capable of reducing the amount of charging.

A liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal, and an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell enables active control of the switching element. This is advantageous for video implementation. As the switching element used in the active matrix liquid crystal display device, a thin film transistor (hereinafter referred to as TFT) is mainly used as shown in FIG. 1.

Referring to FIG. 1, an active matrix type liquid crystal display converts digital input data into an analog data voltage based on a gamma reference voltage and supplies it to the data line DL and simultaneously supplies scan pulses to the gate line GL. The liquid crystal cell Clc is charged.

The gate electrode of the TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and one electrode of the storage capacitor Cst. Connected.

A common voltage Vcom is supplied to the common electrode of the liquid crystal cell Clc.

The storage capacitor Cst serves to charge the data voltage applied from the data line DL when the TFT is turned on to maintain the voltage of the liquid crystal cell Clc constant.

When a scan pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source electrode and the drain electrode to apply a voltage on the data line DL to the pixel electrode of the liquid crystal cell Clc Supply. At this time, the liquid crystal molecules of the liquid crystal cell Clc modulate the incident light by changing the arrangement by the electric field between the pixel electrode and the common electrode.

A configuration of a conventional liquid crystal display device having pixels having such a structure will be described with reference to FIG. 2.

2 is a block diagram of a conventional liquid crystal display device.

Referring to FIG. 2, the liquid crystal display 100 according to the related art includes a thin film for driving the liquid crystal cell Clc at the intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. A liquid crystal display panel 110 including a TFT (TFT: Thin Film Transistor), a data driver 120 for supplying a data voltage Vdata to the data lines DL1 to DLm of the liquid crystal display panel 110, A gate driver 130 for supplying scan pulses to the gate lines GL1 to GLn of the liquid crystal display panel 110, and a gamma reference voltage generator for generating a gamma reference voltage and supplying the gamma reference voltage to the data driver 120. 140, a backlight assembly 150 for irradiating light to the liquid crystal display panel 110, an inverter 160 for applying an alternating voltage and current to the backlight assembly 150, and a common voltage Vcom. To supply the common electrode of the liquid crystal cell Clc of the liquid crystal display panel 110 to The voltage generator 170, the gate driving voltage generator 180 for generating and supplying the gate high voltage VGH and the gate low voltage VGL to the gate driver 130, the data driver 120 and the gate. A timing controller 190 for controlling the driver 130 is provided.

In the liquid crystal display panel 110, liquid crystal is injected between two glass substrates. On the lower glass substrate of the liquid crystal display panel 110, the data lines DL1 to DLm and the gate lines GL1 to GLn are orthogonal. TFTs are formed at intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. The TFT supplies the data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scan pulse. The gate electrodes of the TFTs are connected to the gate lines GL1 to GLn, and the source electrodes of the TFTs are connected to the data lines DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst.

The TFT is turned on in response to the scan pulse supplied to the gate terminal via the gate lines GL1 to GLn. When the TFT is turned on, video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.

The data driver 120 supplies the data voltage Vdata to the data lines DL1 through DLm in response to the data driving control signal DDC supplied from the timing controller 190. Here, the data driver 120 samples and latches the digital video data RGB supplied from the timing controller 190, and then the liquid crystal display panel 110 based on the gamma reference voltage supplied from the gamma reference voltage generator 140. In the liquid crystal cell (Clc) of the () is converted into an analog data voltage (Vdata) that can represent the gray level is supplied to the data lines (DL1 to DLm).

The gate driver 130 sequentially generates scan pulses, that is, gate pulses, in response to the gate driving control signal GDC and the gate shift clock GSC supplied from the timing controller 190, thereby providing the gate lines GL1 to GLn. To feed. The gate driver 130 determines the high level voltage and the low level voltage of the scan pulse in accordance with the gate high voltage VGH and the gate low voltage VGL supplied from the gate drive voltage generator 180, respectively.

The gamma reference voltage generator 140 receives a high potential power supply voltage VDD to generate a positive gamma reference voltage and a negative gamma reference voltage and output the same to the data driver 120.

The backlight assembly 150 is disposed on the rear surface of the liquid crystal display panel 110 and emits light by an AC voltage and a current supplied from the inverter 160 to irradiate light to each pixel of the liquid crystal display panel 110.

The inverter 160 converts the square wave signal generated therein into a triangular wave signal and compares the triangular wave signal with a DC power supply voltage (VCC) supplied from the system to generate a burst dimming signal proportional to the comparison result. . When the burst dimming signal determined according to the square wave signal inside is generated, the driving IC (not shown) for controlling the generation of the AC voltage and the current in the inverter 160 generates the backlight assembly 150 according to the burst dimming signal. Control the generation of alternating voltage and current supplied to the

The common voltage generator 170 receives the high potential power voltage VDD to generate the common voltage Vcom and supplies the common voltage Vcom to the common electrodes of the liquid crystal cells Clc of each pixel of the liquid crystal display panel 110.

The gate driving voltage generator 180 receives the high potential power voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL to supply the gate driver 130 to the gate driver 130. Here, the gate driving voltage generation unit 180 generates a gate high voltage VGH that is greater than or equal to the threshold voltage of the TFTs provided in each pixel of the liquid crystal display panel 110, and the gate low voltage that is less than or equal to the threshold voltage of the TFT. VGL). The gate high voltage VGH and the gate low voltage VGL generated in this way are used to determine the high level voltage and the low level voltage of the scan pulse generated by the gate driver 130, respectively.

The timing controller 190 supplies the digital video data RGB supplied from the system to the data driver 120 and controls the data driving by using the horizontal / vertical synchronization signals H and V according to the clock signal CLK. The signal DDC and the gate driving control signal GDC are generated and supplied to the data driver 120 and the gate driver 130, respectively. The timing controller 190 generates a gate shift clock GSC and supplies it to the gate driver 130. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a source output enable signal SOE, and the like.

Various inversion methods for driving a conventional liquid crystal display device having such a configuration and function have been developed. For example, an N-frame inversion method has been developed to improve interlace afterimages.

Referring to the N-frame inversion driving method, the frames ((N-3) F, (N-2) F, (N-1)) sequentially input to the conventional LCD as shown in FIG. Inversion is performed between neighboring frames among F, (N) F, (N + 1) F, and (N + 2) F, but any two neighboring frames ((N) F, (N-1) There is no inversion between F). That is, the N-frame inversion driving method inverts a plurality of frames which are sequentially input in order, but does not invert adjacently input frames at every specific time by dividing the plurality of input frames into a certain number of frame units. .

Signal characteristics of the conventional liquid crystal display device driven by the N-frame inversion method will be described with reference to FIG. 4 as follows.

As shown in FIG. 4B, the gate high voltage VGH, which determines the high level of the scan pulse, is kept constant in all frames input in the N-frame inversion scheme. In this case, when the gate high voltage VGH is kept constant, the neighboring frames ((N) F, (N + 1) F, and (N + 2) F) inverted as shown in FIG. ), The polarity of the data voltage (Vdata) is inverted based on the common voltage (Vcom), but the polarity of the data voltage (Vdata) between the adjacent frames ((N-1) F, (N) F) without inversion Remains the same.

Then, as shown in Fig. 4A, the data charging amount of the next frame (N) F among the adjacent frames (N-1) F and (N) F without inversion is the previous frame ((N−). Since it is larger than the data charging amount of 1) F), the next frame ((N) F) of the neighboring frames ((N-1) F, (N) F) without inversion as shown in Fig. 4C. The luminance level of? Is significantly higher than the luminance level of the previous frame (N-1) F. Since the luminance variation is non-uniform in the N-frame inversion scheme, the conventional liquid crystal display device to which the N-frame inversion scheme is applied has a high luminance amount in specific frames as shown in FIG. 5. In FIG. 5, a frame having a high luminance level is a frame having the same polarity of the data voltage as the previous frame.

As described above, the conventional liquid crystal display device driven by the N-frame inversion method has a large amount of change in luminance between neighboring frames ((N-1) F and (N) F) without inversion, thereby preventing flicker. Have

The present invention has been made to solve the above problems, an object of the present invention is to adjust the high section width of the gate output enable signal used for masking the scan pulse in the N-frame inversion driving method without inversion The present invention provides a liquid crystal display and a driving method thereof that can reduce the data charging amount of a later frame among neighboring frames.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display and a driving method thereof in which an amount of luminance can be reduced by reducing the data charging amount of a subsequent frame among neighboring frames without inversion in the N-frame inversion driving scheme. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of eliminating flicker by reducing the amount of luminance of a frame having a high luminance level in an N-frame inversion driving scheme.

According to an aspect of the present invention, a liquid crystal display device includes: a liquid crystal display panel having a plurality of gate lines formed therein; Generates a frame inversion polarity signal indicative of N-frame inversion, generates a gate start pulse instructing the supply of scan pulses, and generates first and second gate output enable signals used for masking the scan pulses. A timing controller; A masking controller converting the frame inversion polarity signal into a masking selection signal in response to the gate start pulse; A multiplexer for selectively outputting the first and second gate output enable signals in accordance with the masking selection signal; And sequentially supplying scan pulses to the gate lines under the control of the timing controller, wherein the scan pulses are constant in response to the first gate output enable signal or the second gate output enable signal output from the multiplexer. And a gate driver for masking the section. The high section width of the second gate output enable signal may be twice as wide as the high section width of the first gate output enable signal.

The masking controller may include: a flip-flop for converting a version inversion polarity signal from the timing controller into a version polarity signal in the first modified frame according to a gate start pulse from the timing controller; A delay unit configured to delay the version polarity signal of the first modified frame inputted from the flip-flop and output a version polarity signal of the second modified frame; And an exclusive logic gate configured to generate the masking selection signal by exclusively combining the first and second modified frames, the version polarity signal. The low-level masking selection signal may be generated in a driving period of a later frame among neighboring frames without inversion in the N-frame inversion scheme and supplied to the multiplexer. The masking selection signal having a high level is generated in the driving period of the frames that have been inverted in the N-frame inversion scheme and is supplied to the multiplexer.

The multiplexer may output the second gate output enable signal to the gate driver among the first and second gate output enable signals input when the low level masking selection signal is input.

The gate driver may mask the scan pulse during a high period of the second gate output enable signal.

The multiplexer outputs the first gate output enable signal to the gate driver among the first and second gate output enable signals input when the high level masking selection signal is input.

The gate driver may mask the scan pulse during a high section of the first gate output enable signal.

The driving method of the liquid crystal display according to the present invention includes a frame inversion polarity signal indicating an N-frame inversion, a gate start pulse indicating a supply of scan pulses, and first and second gates used for masking the scan pulses. Generating an output enable signal; Converting the frame inversion polarity signal into a masking selection signal in response to the gate start pulse; Selecting one of the first gate output enable signal and the second gate output enable signal in response to the masking selection signal; And sequentially supplying scan pulses to gate lines of the liquid crystal display panel, and masking a predetermined section of the scan pulses in response to the selected first gate output enable signal or the second gate output enable signal. do.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

6 is a configuration diagram of a liquid crystal display according to an exemplary embodiment of the present invention. However, the liquid crystal display device 200 of the present invention also has the same gamma reference voltage generator 140, backlight assembly 150, inverter 160, and common voltage as the liquid crystal display device 100 shown in FIG. 2. Although the generator 170 is provided, these components are not shown in FIG. 6 for convenience of description.

Referring to FIG. 6, in the liquid crystal display device 200 of the present invention, the data lines DL1 through DLm and the gate lines GL1 through GLn intersect with each other to drive the liquid crystal cell Clc at an intersection thereof. The liquid crystal display panel 110 includes a thin film transistor TFT.

The liquid crystal display device 200 of the present invention supplies a frame inversion polarity signal POL indicating N-frame inversion, a gate start pulse GSP instructing supply of scan pulses, Responding to the timing controller 210 for supplying the first and second gate output enable signals GOE1 and GOE2 used for masking the scan pulses, and the gate start pulse GSP from the timing controller 210. According to the masking control unit 220 for converting the frame inversion polarity signal POL from the timing controller 210 into the masking selection signal POL_MKS and the masking selection signal POL_MKS from the masking control unit 220. The multiplexer 230 selectively outputs the first and second gate output enable signals GOE1 and GOE2 from the timing controller 210, and the scan pulses are sequentially gate line under the control of the timing controller 220. To the grass (GL1 to GLn) The gate driver 240 masks a predetermined section of the scan pulse in response to the first gate output enable signal GOE1 or the second gate output enable signal GOE from the multiplexer 230, and the timing controller 220. A data driver 250 for N-frame inversion of the frames sequentially input according to the control of the control panel) to be implemented in the liquid crystal display panel 110.

The timing controller 210 supplies a frame-inversion polarity signal POL to the masking controller 220 and the data driver 250 to instruct N-frame inversion of frames sequentially input from the system, and also scans. The gate start pulse GSP indicating the pulse supply is supplied to the masking controller 220 and the gate driver 240.

The timing controller 210 supplies the frame supplied from the system and its digital video data RGB to the data driver 250, and uses the horizontal / vertical synchronization signals H and V according to the clock signal CLK. The data driving control signal DDC and the gate driving control signal GDC are generated and supplied to the data driver 250 and the gate driver 240, respectively. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a source output enable signal SOE, and the like.

The timing controller 210 generates a gate shift clock GSC to supply the gate driver 240, and multiplexes the first and second gate output enable signals GOE1 and GOE2 instructing masking of the scan pulse. 230). The high section width of the second gate output enable signal GOE2 may be twice as wide as the high section width of the first gate output enable signal GOE1.

The masking controller 220 converts the frame inversion polarity signal POL from the timing controller 210 into the masking selection signal POL_MKS in response to the gate start pulse GSP from the timing controller 210. The masking selection signal POL_MKS is supplied to the multiplexer 230 and used to selectively output the first and second gate output enable signals GOE1 and GOE2.

The multiplexer 230 may include a first input terminal IN1 receiving the first gate output enable signal GOE1 from the timing controller 210 and a second gate output enable signal GOE2 from the timing controller 210. It has a second input terminal (IN2) receiving the input, the selection terminal (S) and the output terminal to which the masking selection signal (POL_MKS) from the masking control unit 220 is supplied. The multiplexer 230 selectively selects the first and second gate output enable signals GOE1 and GOE2 from the timing controller 210 according to the masking selection signal POL_MKS from the masking controller 220. 240).

The gate driver 240 sequentially generates scan pulses while the frame is driven on the liquid crystal display panel 110 in response to the gate driving control signal GDC and the gate shift clock GSC from the timing controller 210. Supply to lines GL1 to GLn. The gate driver 240 masks a predetermined section of the scan pulse in response to the first gate output enable signal GOE1 or the second gate output enable signal GOE2 from the multiplexer 230. Here, since the high section width of the first gate output enable signal GOE1 is smaller than the high section width of the second gate output enable signal GOE2, the scan made by the first gate output enable signal GOE1 is performed. The masking period of the pulse is smaller than the masking period of the scan pulse formed by the second gate output enable signal GOE2. This will be described with reference to FIG. 7.

As shown in FIG. 7, the high level of the first gate output enable signal GOE1 is maintained for a period T1 of one horizontal period 1H, and the high level of the second gate output enable signal GOE2 is 1. It is held during the T2 section of the horizontal period 1H. Here, the high level of the second gate output enable signal GOE2 is maintained longer than the high level of the first gate output enable signal GOE1 by the period T3.

When the multiplexer 230 supplies the first gate output enable signal GOE1 to the gate driver 240, the gate driver 240 masks the scan pulse SP1 during the T1 period to gate lines GL1 to GLn. ) Sequentially. The scan pulse SP1 includes neighboring frames ((N-3) F, (N-2) F, (N-1) F, (N + 1) F, It is supplied in the driving period of (N + 2) F).

When the multiplexer 230 supplies the second gate output enable signal GOE2 to the gate driver 240, the gate driver 240 masks the scan pulse SP2 during the T2 period to gate lines GL1 to GLn. ) Sequentially. This scan pulse SP2 is supplied to the driving period of the next frame (N) F among the neighboring frames (N-1) F and (N) F without inversion in the N-frame inversion scheme.

Since the masking period T1 of the scan pulse SP1 is smaller than the masting period T2 of the scan pulse SP2, the frames ((N-3) F, (N-2) F, (N-1) The high section width of the scan pulse SP1 supplied in the driving periods of F, (N + 1) F, and (N + 2) F is the scan pulse SP2 supplied in the driving period of the frame (N) F. It is smaller by the T3 section than the high section width of. Accordingly, the amount of data charged in the driving period of the frame (N) F is (N-3) F, (N-2) F, (N-1) F, (N + 1) F, (N +2) F) is reduced than the amount of data charged in the driving period, and according to the present invention, in the N-frame inversion method, among the neighboring frames ((N-1) F, (N) F) without inversion The luminance level of the subsequent frame (N) F is reduced to make the luminance amount of all the frames uniform. In this way, since the luminance amounts of all the frames are uniform in the N-frame inversion scheme, the flicker generated due to the luminance amount unevenness in the N-frame inversion scheme is eliminated.

The data driver 250 N-frames the frames input through the timing controller 210 in response to the frame-inversion polarity signal POL and implements them on the liquid crystal display panel 110. The data driver 250 supplies the data voltage Vdata to the data lines DL1 to DLm of the liquid crystal display panel 110.

More specifically, as shown in FIG. 3, the data driver 250 includes frames ((N-3) F, (N-2) F, (N-1) F, (N) F, The neighboring frames of (N + 1) F and (N + 2) F are inverted, but the two neighboring frames ((N) F and (N-1) F) are not inverted.

When N-frame inversion is performed, the data voltage Vdata between the inverted neighboring frames ((N) F, (N + 1) F and (N + 2) F) is based on the common voltage Vcom. Although the polarity of is reversed, the polarity of the data voltage Vdata remains the same between the adjacent frames (N-1) F and (N) F without inversion.

FIG. 8 is a circuit diagram of the masking control unit shown in FIG. 6.

Referring to FIG. 8, the masking controller 220 may set the frame-inversion polarity signal POL from the timing controller 210 as the first modified frame according to the gate start pulse GSP from the timing controller 210. The flip-flop 221 converts the version polarity signal POL_1 and the version polarity signal POL_1, which is the first modified frame input from the flip-flop 221, to be delayed. A delay unit 222 for outputting (POL_2), a version polarity signal POL_1 that is the first transformed frame from the flip-flop 221, and a version polarity signal POL_2 that is a second transformed frame from the delay unit 222 And an exclusive logic gate 223 for generating a masking selection signal POL_MKS.

The flip-flop 221 includes a clock terminal CLK for receiving the guest start pulse GSP, an input terminal D for receiving the frame inversion polarity signal POL from the timing controller 210, and a first frame inversion polarity. It has an output terminal Q which outputs the signal POL_1. The function of the flip-flop 221 will be described with reference to FIG.

As shown in FIG. 9, the gate start pulse GSP having the same period as one frame driving period is inputted to the clock terminal CLK of the flip-flop 221 and at the same time, the high level and the low level are alternately repeated at a predetermined period. When the frame-inversion polarity signal POL is input to the input terminal D of the flip-flop 221, the flip-flop 221 is a first modified frame having a phase opposite to the input frame-inversion polarity signal POL. The version polarity signal POL_1 is output to the delay unit 222 and the exclusive logic gate 223 through the output terminal Q, and the widths of the specific high periods among the high periods of the version polarity signal POL_1, which is the first transformed frame, are output. Two times larger than the widths of the other high intervals, and among the low intervals of the version polarity signal POL_1, which is the first modified frame, the widths of the specific low intervals are twice as large as the widths of the other low intervals. Here, the large high section and the low section are alternately repeated at regular intervals.

As shown in FIG. 9, the delay unit 222 delays the version polarity signal POL_1 of the first modified frame for a predetermined time and outputs the version polarity signal POL_2 of the second modified frame to the exclusive logic gate 223. do.

The exclusive logic gate 223 performs an exclusive logic on the version polarity signal POL_1, which is the first modified frame input from the flip-flop 221, and the version polarity signal POL_2, which is the second modified frame input from the delay unit 222. The masking selection signal POL_MKS as shown in FIG. 9 is output to the selection terminal S of the multiplexer 230. As shown in FIG. 9, the exclusive logic gate 223 has a high level masking selection signal POL_MKS when the level of the first polarized frame, the version polarity signal POL_1 and the second modified frame, the version polarity signal POL_2 are different. On the contrary, if the level of the first modified frame, the version polarity signal POL_1 and the second modified frame, the version polarity signal POL_2 are the same, a low level masking selection signal POL_MKS is generated. That is, the exclusive logic gate 223 overlaps a section in which the high levels of the first and second modified frames, the version polarity signal POL_1 overlap, or a high level of the first and second modified frames, the version polarity signal POL_1. The low level masking selection signal POL_MKS is generated only in the interval.

The low level masking selection signal POL_MKS is used in the driving period of the next frame ((N) F) among the neighboring frames ((N-1) F, (N) F) without inversion in the N-frame inversion method. It is supplied to the selection terminal (S) of the multiplexer 230. At this time, the multiplexer 230 supplies the second gate output enable signal GOE2 from the timing controller 210 to the gate driver 240 in response to the low level masking selection signal POL_MKS. As shown in FIG. 7, the scan pulse SP2 is masked during the T2 section and sequentially supplied to the gate lines GL1 to GLn.

The masking selection signal POL_MKS of the high level is composed of frames ((N-3) F, (N-2) F, (N-1) F, and (N + 1) F) that have been inverted in the N-frame inversion scheme. , It is supplied to the selection terminal S of the multiplexer 230 in the driving period of (N + 2) F). At this time, the multiplexer 230 supplies the first gate output enable signal GOE1 from the timing controller 210 to the gate driver 240 in response to the high level masking selection signal POL_MKS. As shown in FIG. 7, the scan pulse SP1 is masked and supplied to the gate lines GL1 to GLn sequentially during the T1 section.

Since the masking period T1 of the scan pulse SP1 is smaller than the masting period T2 of the scan pulse SP2, the frames ((N-3) F, (N-2) F, (N-1) The high section width of the scan pulse SP1 supplied in the driving periods of F, (N + 1) F, and (N + 2) F is the scan pulse SP2 supplied in the driving period of the frame (N) F. It is smaller by the T3 section than the high section width of. Accordingly, the amount of data charged in the driving period of the frame (N) F is (N-3) F, (N-2) F, (N-1) F, (N + 1) F, (N +2) F) is reduced than the amount of data charged in the driving period, and according to the present invention, in the N-frame inversion method, among the neighboring frames ((N-1) F, (N) F) without inversion The luminance level of the subsequent frame (N) F is reduced to make the luminance amount of all the frames uniform. In this way, since the luminance amounts of all the frames are uniform in the N-frame inversion scheme, the flicker generated due to the luminance amount unevenness in the N-frame inversion scheme is eliminated.

As described above, the present invention adjusts the high section width of the gate output enable signal used for masking the scan pulse in the N-frame inversion driving method, thereby the data charging amount of the next frame among neighboring frames without inversion. By decreasing, the amount of luminance can be reduced, thereby eliminating flicker.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (18)

A liquid crystal display panel in which a plurality of gate lines are formed; A first signal used to generate a frame inversion polarity signal indicative of an N-frame inversion (N is a natural number greater than or equal to 2), generate a gate start pulse instructing the supply of scan pulses, and mask the scan pulse; And a timing controller for generating a second gate output enable signal. A masking controller converting the frame inversion polarity signal into a masking selection signal in response to the gate start pulse; A multiplexer for selectively outputting the first and second gate output enable signals in accordance with the masking selection signal; And According to the control of the timing controller, scan pulses are sequentially supplied to the gate lines, and a predetermined period of the scan pulses is responded to in response to the first gate output enable signal or the second gate output enable signal output from the multiplexer. A gate driver for masking the; A high section width of the second gate output enable signal is wider than a high section width of the first gate output enable signal; The masking control unit A flip-flop for converting a frame inversion polarity signal from the timing controller into a first polarization frame inversion polarity signal according to a gate start pulse from the timing controller; A delay unit configured to delay the version polarity signal of the first modified frame inputted from the flip-flop and output a version polarity signal of the second modified frame; And And an exclusive logic gate configured to generate the masking selection signal by exclusively combining the first and second modified frames of the version polarity signal. delete delete The method of claim 1, The low level masking selection signal is generated in the driving period of the next frame among the adjacent frames without inversion in the N-frame inversion scheme, and is supplied to the multiplexer. 5. The method of claim 4, And when the low level masking selection signal is input, the multiplexer outputs the second gate output enable signal to the gate driver among the input first and second gate output enable signals. 6. The method of claim 5, And the gate driver masks the scan pulses during a high period of the second gate output enable signal. The method of claim 1, And the masking selection signal having a high level is generated during the driving period of the inverted frames in the N-frame inversion scheme and supplied to the multiplexer. The method of claim 7, wherein And when the high level masking selection signal is input, the multiplexer outputs the first gate output enable signal to the gate driver among the first and second gate output enable signals. 9. The method of claim 8, And the gate driver masks the scan pulse during a high period of the first gate output enable signal. A frame inversion polarity signal indicating N-frame inversion (N is a natural number greater than or equal to 2), a gate start pulse indicating supply of scan pulses, and first and second gate outputs used for masking scan pulses. Generating an enable signal; Converting the frame inversion polarity signal into a masking selection signal in response to the gate start pulse; Selecting one of the first gate output enable signal and the second gate output enable signal in response to the masking selection signal; And Supplying scan pulses sequentially to gate lines of the liquid crystal display panel, and masking a predetermined period of the scan pulses in response to the selected first gate output enable signal or the second gate output enable signal; A high section width of the second gate output enable signal is wider than a high section width of the first gate output enable signal; The signal conversion step Converting the frame inversion polarity signal into a first modified frame inversion polarity signal according to the gate start pulse; Delaying the first modified frame in-version polarity signal to generate a second modified frame in-version polarity signal; And And exclusively combining the first and second modified frames, the version polarity signals, to generate the masking selection signal. delete delete 11. The method of claim 10, The low level masking selection signal is generated in the driving period of the next frame among the neighboring frames without inversion in the N-frame inversion method. The method of claim 13, And in the signal selecting step, selecting the second gate output enable signal from among the first and second gate output enable signals in response to the low level masking selection signal. 15. The method of claim 14, And in the masking step, mask the scan pulse during a high period of the second gate output enable signal. 11. The method of claim 10, And the masking selection signal having a high level is generated in the driving period of the frames which have been inverted by the N-frame inversion method. 17. The method of claim 16, And in the signal selecting step, selecting the first gate output enable signal from among the first and second gate output enable signals in response to the high level masking selection signal. The method of claim 17, And in the masking step, mask the scan pulse during a high period of the first gate output enable signal.

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