KR20160035142A - Liquid Crystal Display Device and Driving Method the same - Google Patents

Abstract

A liquid crystal display device to prevent image quality degradation and a driving method thereof are disclosed. According to an embodiment of the present invention, the liquid crystal display device includes: a display panel (100) which includes data lines (D) and gate lines (G) which intersect with each other, a thin film transistor (T) connected to them, and a liquid crystal cell (CLC); and a gate driving part (200, 210) which outputs a scan pulse which is supplied to each of the gate lines (G) and drives the thin film transistor (T). The gate driving part (200, 210) outputs a scan pulse which has a gate high voltage (VGH) of different level according to each of the gate lines (G).

Description

[0001] The present invention relates to a liquid crystal display device and a method of driving the same,

The present invention relates to a liquid crystal display device and a driving method thereof.

The liquid crystal display displays an image by controlling the light transmittance of the liquid crystal layer through an electric field applied to the liquid crystal layer in accordance with a video signal.

Such a liquid crystal display device is a flat panel display device having advantages of small size, thinness and low power consumption, and is used as a portable computer such as a notebook PC, office automation equipment, audio / video equipment and the like.

Particularly, an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell is capable of actively controlling a switching element, which is advantageous for a moving image.

A thin film transistor (hereinafter referred to as "TFT") is mainly used as a switching element used in an active matrix type liquid crystal display device. An active matrix type liquid crystal display device converts digital video data into an analog data voltage based on a gamma reference voltage and supplies the same to a data line and simultaneously supplies a scan pulse to a gate line to charge the liquid crystal cell with a data voltage. To this end, the gate electrode of the TFT is connected to the gate line, the source electrode is connected to the data line, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell and one electrode of the storage capacitor. A common voltage is supplied to the common electrode of the liquid crystal cell. The storage capacitor charges the data voltage applied from the data line when the TFT is turned on, thereby maintaining the voltage of the liquid crystal cell constant.

When a scan pulse is applied to the gate line, the TFT is turned on to form a channel between the source electrode and the drain electrode to supply the voltage on the data line to the pixel electrode of the liquid crystal cell. At this time, the liquid crystal molecules of the liquid crystal cell are changed in arrangement by the electric field between the pixel electrode and the common electrode, and the incident light is changed.

Thus, the liquid crystal molecules are polarized by the DC voltage supplied between the pixel electrode and the common electrode. However, if the polarization state is maintained, since the characteristics of the liquid crystal can be weakened, the inversion method is applied to exhibit the same effect as that of supplying the AC voltage to the liquid crystal molecules. However, in applying the inversion method, a deviation of the data voltage charged in the liquid crystal cell occurs depending on the arrangement relationship of the liquid crystal cell, the gate and the data line, resulting in an image quality defect.

The embodiment according to the present invention can provide a liquid crystal display device and a driving method thereof that can prevent a power consumption reduction and an image quality deterioration by improving the deviation of the charged amount of the liquid crystal cell.

A liquid crystal display device and a driving method thereof according to an embodiment of the present invention include a plurality of data lines D and a plurality of gate lines G intersecting with each other and a thin film transistor T and a liquid crystal cell CLC connected thereto, A display panel 100 including the display panel 100; A gate driver (200, 210) which is supplied to each of the plurality of gate lines (G) and outputs a scan pulse for driving the thin film transistor (T); The gate driver (200, 210) outputs a scan pulse having a gate high voltage (VGH) of a different level for each of the plurality of gate lines (G), and a driving method thereof.

In the liquid crystal display device and the driving method thereof according to the embodiment of the present invention, the gate voltage of the scan pulse is set to the gate-source voltage of the scan pulse according to the charged amount of the liquid crystal cell (CLC) of the data voltage supplied through the data line Wherein a level of the voltage (VGH) is changed.

In the liquid crystal display device and the driving method thereof according to the embodiment of the present invention, the display panel 100 includes n (d is a positive even number) liquid crystal cells CLC arranged on the same horizontal line, (M is a natural number) and an (m + 1) th gate line among the plurality of shared data lines D and the plurality of gate lines G, The liquid crystal cells are symmetrically connected to the mth and (m + 1) -th gate lines, and in the liquid crystal cells sharing the nth data line among the data lines, the data signals are supplied in the order of the right liquid crystal cell in the left liquid crystal cell, The liquid crystal cells sharing the (n + 1) th and (n + 2) th data lines among the data lines are supplied with the data signals in the order of the left liquid crystal cell in the right liquid crystal cell, A first gate high voltage VGH1 is applied to the gate line Godd, Outputting a scan pulse with a level, and the even-numbered gate lines (Geven) a second gate liquid crystal display device and its driving method for outputting a scan pulse with the level of the high voltage (VGH2) on.

A liquid crystal display device for controlling the display panel (100) in a vertical two-dot version mode in a liquid crystal display device and a driving method thereof according to an embodiment of the present invention and a driving method thereof.

In the liquid crystal display device and the driving method thereof according to the embodiment of the present invention, the liquid crystal cell CLC includes red, green and blue liquid crystal cells, A liquid crystal display connected to the gate line Geven, and a driving method thereof.

The level of the first gate high voltage VGH1 is higher than the level of the second gate high voltage VGH2 in the liquid crystal display device and the driving method thereof according to the embodiment of the present invention.

The embodiment according to the present invention can provide a liquid crystal display device and a driving method thereof that can prevent a power consumption reduction and an image quality deterioration by improving the deviation of the charged amount of the liquid crystal cell.

1 is a view showing a structure of a liquid crystal display device according to an embodiment of the present invention.
2 is a block diagram of a display device having a display panel of the GIP system.
3 is a view showing a connection structure of liquid crystal cells constituting a display panel according to an embodiment of the present invention.
FIG. 4 is a view showing the pixel structure of a display panel according to an embodiment of the present invention, and is a diagram showing degrees of filling of RGB liquid crystal cells and liquid crystal cells.
FIG. 5 shows a charge voltage waveform in each liquid crystal cell when the liquid crystal cells are charged along the direction of the arrow in FIG.
7 is a waveform diagram showing gate high voltages applied to odd gate lines and even gate lines.
FIG. 8 is a view showing a waveform and a structure of a liquid crystal cell according to FIG. 7. FIG.

Hereinafter, a liquid crystal display according to an embodiment of the present invention and a driving method thereof will be described in detail with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of an apparatus may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

<Structure of Display Device>

1 is a view showing a structure of a liquid crystal display device according to an embodiment of the present invention.

1, a liquid crystal display device according to the present invention includes a display panel 100 in which a plurality of gate lines G and data lines D are crossed and pixels are defined at intersections thereof, A gate driver and data drivers 200 and 300 for driving the display panel 100 through a data line D and a data signal line D and a timing signal and image signal from an external system And a timing controller 400 for determining the driving frequency of the display device.

The display panel 100 includes a plurality of gate wirings G on a transparent substrate and a plurality of data wirings D arranged in a matrix in a direction perpendicular to the gate wirings G, A region is defined. In each pixel region, a thin film transistor T is formed, and a liquid crystal cell CLC controlled by the thin film transistor T and a storage capacitor are formed to display a screen.

The thin film transistor T described above is turned on when a scan pulse from the gate line G, that is, a scan pulse of the gate high voltage VGH is applied to turn on the data voltage from the data line D to the liquid crystal cell CLC . The thin film transistor T is turned off when the gate low voltage VGL is applied from the gate line G so that the data voltage charged in the liquid crystal cell CLC is maintained for one frame.

On the other hand, the level of the scan pulse supplied to the odd-numbered gate lines and the even-numbered gate lines, that is, the level of the gate high voltage, may be different from each other.

The liquid crystal cell CLC includes a pixel electrode and a common electrode represented by a capacitor, and includes a common electrode facing the liquid crystal and a pixel electrode connected to the thin film transistor T. The liquid crystal cell CLC is connected to the storage capacitor so that the charged data voltage stably remains until the next data voltage is charged. The arrangement state of the liquid crystal is changed according to the data voltage charged through the thin film transistor T so that the light transmittance of the liquid crystal cell CLC is controlled to realize the gray level.

A gate driver 200 including a plurality of shift registers is provided at one end of the display panel 100 and is electrically connected to the gate wiring G formed on the display panel 100 to sequentially form a gate And outputs the drive signal GCS.

The gate driver 200 turns on the thin film transistor T arranged on the display panel 100 in response to the gate control signal GCS applied from the timing controller 400, The data voltage of the analog waveform supplied from the data driver 300 is applied to the liquid crystal cell CLC connected to each thin film transistor T. [

The gate control signal GCS includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE). Here, the gate start pulse GSP is a signal for controlling the first gate pulse to be generated by being applied to a shift register for generating a first gate pulse among a plurality of shift registers constituting the gate driver 200, (GSC) is a clock signal commonly input to all shift registers, and is a clock signal for shifting the gate start pulse (GSP). The gate output enable (GOE) controls the output of the shift registers to prevent turn-on of the thin film transistors overlapped with each other in the different horizontal sections.

The data driver 300 arranges the digital video signals RGB input corresponding to the data control signals DCS input from the timing controller 400 and selects the reference voltages gamma, Voltage.

The data voltage is latched by one horizontal interval (1H) and input to the display panel 100 simultaneously through all the data lines D. [

A source start pulse (SSP), a source shift clock (SSC), a source output enable (SOE), and a polarity signal (POL) are used as the data control signal DCS have. Here, the source start pulse SSP is a signal for controlling the data sampling start timing of the data driver 300, and the source sampling clock SSC is a signal for driving the driving ICs 300 constituting the data driver 300, Which controls the sampling timing of data. In addition, the source output enable (SOE) serves to control the output timing of the data driver 300.

The timing controller 400 receives the video data DATA applied from an external system (not shown) and the timing signals such as the clock signal CLK, the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync, And generates a gate control signal GCS and a data control signal DCS.

Here, the horizontal synchronization signal Hsync represents the time taken to display one line of the screen, and the vertical synchronization signal Vsync represents the time taken to display the screen of one frame. In addition, the clock signal CLK is a signal in which the gate and data drivers 200 and 300 and the timing controller 400 are synchronized to generate various signals.

Although not shown, the timing controller 400 is connected to an external system (not shown) via a predetermined interface, and receives image related signals and timing signals output from the external system at high speed without error in the timing controller 400 do. As such an interface, a low voltage differential signal (LVDS) method or a transistor-transistor logic (TTL) interface method can be used.

The gamma voltage setting unit 500 of the display device can generate a plurality of gamma voltages and supply the gamma voltages to the data driver 300. The data driver 300 may divide the gamma voltage to generate a plurality of gradation voltages.

The display device further includes a backlight unit (not shown in FIG. 1) for supplying light to the display panel 100, and a backlight driver for driving the backlight unit. The backlight unit uses a fluorescent lamp such as Cold Cathode Fluorescent Lamp (CCFL) or External Electrode Fluorescent Lamp (EEFL) driven by a backlight driver or a direct type or edge type backlight including a light emitting diode (LED) as a light source. The direct-type backlight includes a light source disposed on the entire display area and a plurality of optical sheets disposed on the light source so as to face the back surface of the display panel 100. Light emitted from the light source is transmitted through the plurality of optical sheets to the display panel 100). The edge type backlight includes a light guide plate facing the back surface of the display panel 100, a light source arranged to face at least one edge of the light guide plate, and a plurality of optical sheets arranged on the light guide plate, Converted into a planar light source through a light guide plate, and irradiated onto the display panel 100 through a plurality of optical sheets. The backlight driver drives the backlight unit in response to the duty ratio of the pulse width modulation (PWM) signal from the outside, and controls the luminance.

The gate driver 300 includes at least one gate IC and is mounted on a circuit film such as TCP, COF, FPC or the like to be attached to the display panel 100 in a TAB manner or in a COG manner on the display panel 100 Can be mounted. Alternatively, the gate driver 300 may be formed on the thin film transistor substrate in the same process as the thin film transistor array of the display panel 100 in a GIP (Gate In Panel) manner and incorporated in the display panel 100.

&Lt; Structure of Display Device of GIP System >

2 is a block diagram of a display device having a display panel of the GIP system.

Referring to FIG. 2, a liquid crystal display device having a display panel 100 of the GIP system will be described in detail.

The display device according to the embodiment of the present invention includes a display panel 100, a gate drive control unit 210, a data driver 300, a timing controller 400 driving voltage generation unit 700, and a voltage control unit 800 can do.

The display panel 100 has a pixel region defined by the intersection of m gate lines G1 to Gm and n data lines D1 to Dn and gate lines G1 to Gm and data lines D1 to Dn And a liquid crystal cell Clc formed thereon. In addition, a gate drive control unit 210 is provided on one side of the display panel 100.

The timing controller 400 may output the gate control signal GCS, the ON clock signal ONCLK, and the OFF clock signal OFFCLK to the driving voltage generator 700.

The driving voltage generator 700 generates the gate high voltage VGH and the gate low voltage VGL and generates the gate high voltage VGH and the gate low voltage VGL based on the ON clock signal ONCLK and the OFF clock signal OFFCLK from the timing controller 400 The clock signal GCLK can be generated and output.

The driving clock signal GCLK may include an odd driving clock signal GCLK_O and an even driving clock signal GCLK_E.

The driving clock signal GCLK sequentially rises in response to the rising time of the ON clock signal ONCLK and is sequentially polled in response to the polling time of the OFF clock signal OFFCLK, Some sections may overlap each other.

The driving voltage generator 700 includes a level shifter to level shift the high voltage of the driving clock signal GCLK to the gate high voltage VGH and the low voltage to the gate low voltage VGL, can do.

Also, the driving voltage generator 700 may have a high voltage level of the odd driving clock signal GCLK_O and the even driving clock signal GCLK_E of the driving clock signal GCLK. Therefore, the gate high voltage VGH for determining the high voltage of the odd driving clock signal GCLK_O and the gate high voltage VGH for determining the high voltage of the even driving clock signal GCLK_E may be different from each other.

By varying the level of the gate high voltage (VGH) of the scan pulse applied to the gate line in this way, it is possible to reduce variations in the charged amount of the liquid crystal cells and to reduce power consumption and image quality by setting the appropriate luminance.

As a method of generating the gate high voltage GCLK_O_VGH of the odd driving clock signal and the gate high voltage GCLK_E_VGH of the even driving clock signal of the driving voltage generator 700 as described above, Different voltages may be automatically generated through settings, but the voltage regulator 800 may be used externally.

The voltage regulator 800 receives the gate high voltage VGH generated from the driving voltage generator 700 and generates a gate high voltage GCLK_O_VGH of the odd driving clock signal having a different voltage level, It is possible to generate the gate high voltage GCLK_E_VGH of the driving clock signal. At this time, the voltage regulator 800 is constituted by a resistor and divides the gate high voltage VGH by a voltage division scheme by a resistor to generate a gate high voltage GCLK_O_VGH of the odd driving clock signal and a gate high voltage GCLK_O_VGH of the odd driving clock signal High voltage (GCLK_E_VGH) may be generated, but is not limited thereto. When the gate high voltage (GCLK_O_VGH) of the odd driving clock signal and the gate high voltage (GCLK_E_VGH) of the even driving clock signal are generated through the voltage controller 800, the driving voltage generator 700 generates the driving voltage The gate high voltage GCLK_O_VGH of the odd driving clock signal and the gate high voltage GCLK_E_VGH of the even driving clock signal may be received from the controller 800 and output to the gate driving controller 210. The scan pulse corresponding to the levels of the gate high voltage GCLK_O_VGH of the odd driving clock signal and the gate high voltage GCLK_E_VGH of the even driving clock signal may be output to the gate line by dividing the odd and even gate lines.

&Lt; Connection structure of liquid crystal cells &

3 is a view showing a connection structure of liquid crystal cells constituting a display panel according to an embodiment of the present invention.

3, the display panel 100 according to the exemplary embodiment of the present invention may include gate and data lines G and D and liquid crystal cells Clc according to a DRD (Double Rate Driving) .

In the DRD driving method, the number of gate lines is doubled, but the number of data lines is reduced by a factor of 1/2 to reduce the number of data driving ICs required by half, thereby realizing the same resolution as the conventional one.

The display panel 100 includes n shared data lines and m (m is a natural number) and n (n is an even number) among the plurality of gate lines for driving d (d is a positive even number) liquid crystal cells arranged on the same horizontal line. An (m + 1) -th gate line is allocated, and two neighboring liquid crystal cells sandwiching each of the shared data lines may be symmetrically connected to the m-th and (m + 1) -th gate lines.

The liquid crystal cells Clc may include a plurality of R liquid crystal cells, G liquid crystal cells, and B liquid crystal cells.

The R liquid crystal cell connected to the first gate line G1 in the first horizontal line HL1 is connected to the first data line D1 adjacent to the G liquid crystal cell connected to the second gate line G2, And the liquid crystal cell B connected to the second gate line G2 is commonly connected to the second data line D2 adjacent to the liquid crystal cell R connected to the first gate line G1, The G liquid crystal cell connected to the line G2 is commonly connected to the third data line D3 adjacent to the B liquid crystal cell connected to the first gate line G1, The liquid crystal cell is commonly connected to the fourth data line D4 adjacent to the G liquid crystal cell connected to the second gate line G2 and the B liquid crystal cell connected to the second gate line G2 is commonly connected to the first gate line The G liquid crystal cell connected in common to the fifth data line D5 adjacent to the R liquid crystal cell connected to the first gate line G1 and the G liquid crystal cell connected to the second gate line G2 is commonly connected to the B liquid crystal cell connected to the first gate line G1, And the neighbor may be commonly connected to a sixth data line (D6).

The R liquid crystal cell connected to the third gate line G3 in the second horizontal line HL2 is commonly connected to the first data line D1 in the neighborhood of the G liquid crystal cell connected to the fourth gate line G4 And the liquid crystal cell B connected to the fourth gate line G4 is commonly connected to the second data line D2 adjacent to the liquid crystal cell R connected to the third gate line G3, The G liquid crystal cell connected to the third gate line G3 is commonly connected to the third data line D3 adjacent to the B liquid crystal cell connected to the third gate line G3, The liquid crystal cell B connected in common to the fourth data line D4 adjacent to the G liquid crystal cell connected to the fourth gate line G4 and commonly connected to the fourth gate line G4 is connected to the third gate line G3 And the G liquid crystal cell connected to the fourth gate line G4 is commonly connected to the fifth data line D5 adjacent to the R liquid crystal cell adjacent to the R liquid crystal cell connected to the third gate line G3, 6 And may be commonly connected to the data line D6.

The R liquid crystal cells connected to the fifth gate line G5 from the third horizontal line HL3 are connected in common to the first data line D1 adjacent to the G liquid crystal cell connected to the sixth gate line G6 And the liquid crystal cell B connected to the sixth gate line G6 are commonly connected to the second data line D2 adjacent to the liquid crystal cell R connected to the fifth gate line G5, The G liquid crystal cell connected to the fifth gate line G5 is commonly connected to the third data line D3 adjacent to the B liquid crystal cell connected to the fifth gate line G5, The liquid crystal cell B commonly connected to the fourth data line D4 adjacent to the G liquid crystal cell connected to the sixth gate line G6 and commonly connected to the sixth gate line G6 is connected to the fifth gate line G5 And the G liquid crystal cell connected to the sixth gate line G6 is connected to the fifth data line D5 adjacent to the R liquid crystal cell adjacent to the R liquid crystal cell adjacent to the B liquid crystal cell connected to the fifth gate line G5, 6 And may be commonly connected to the data line D6.

In other words, in the m-th data line, in the right liquid crystal cell, in the right liquid crystal cell, in the m + 1 and m + 2th data lines, in the right liquid crystal cell, Two liquid crystal cells neighboring each other can be driven. For example, in the first data line D1, the left and right liquid crystal cells are arranged in the order of the right liquid crystal cell. In the second and third data lines D2 and D3, Two adjacent liquid crystal cells can be driven with the data lines sandwiched therebetween. Such a scheme is referred to as a ZSS scheme.

&Lt; Degree of filling of the liquid crystal cell according to the version method with vertical 2 dot >

FIG. 4 is a view showing the pixel structure of a display panel according to an embodiment of the present invention, and is a diagram showing degrees of filling of RGB liquid crystal cells and liquid crystal cells. And FIG. 5 shows a charge voltage waveform in each liquid crystal cell when the liquid crystal cells are charged along the arrow direction in FIG.

In FIG. 4, R (L) means that the red liquid crystal cell is charged to a low level, G (H) means that the green liquid crystal cell is charged to a high level, It is the charge amount.

Referring to FIG. 4, a liquid crystal display according to an embodiment of the present invention in a DRD scheme includes d (d is a positive even number) liquid crystal cells arranged on one horizontal line to two gate lines and d / 2 Data lines.

The Vertical 2 dot inversion method has the effect of minimizing flicker and reducing power consumption.

The reason for using the inversion is that the liquid crystal becomes polarized when a DC voltage is applied to both ends of the liquid crystal (common electrode and pixel electrode). If this state continues, the ionic impurities in the liquid crystal are fixed by the electric field, and the pre-tilt is changed to weaken the characteristics of the liquid crystal such as a residual image. If the state continues for a longer period of time, the characteristics of the liquid crystal will eventually be lost, and eventually it will not be able to function as a liquid crystal display device. A method for preventing this is to prevent the ionic impurities from sticking by periodically inverting the polarization state, and reversing the polarization state is referred to as inversion. That is, the polarization of the liquid crystal is relatively positive (+) and negative (-) depending on the potential difference between the both ends, and is polarized accordingly. Therefore, by reversing the relative value periodically using the DC power supplied from the system, A polarization inversion effect similar to that of an AC power supply can be seen.

The vertical two-dot version inverts the polarity of each of two neighboring gate lines and inverts the polarity of each data line one line at a time.

The two liquid crystal cells adjacent to each other with the data line sandwiched therebetween are connected to the two gate lines so that the data voltages of the same polarity supplied through the data lines .

For example, in a specific frame, the R liquid crystal cell and the G liquid crystal cell shared by the first data line D1 among the liquid crystal cells arranged in the first horizontal line HL1 are supplied with scan pulses from the gate lines G1 and G2 The R liquid crystal cells and the B liquid crystal cells shared in the second data line D2 are charged in the positive polarity in synchronization with the supply timing of the scan pulses from the gate lines G1 and G2 And the B liquid crystal cell and the G liquid crystal cell shared in the third data line D3 are sequentially charged in the positive polarity in synchronization with the supply timing of the scan pulses from the gate lines G1 and G2. The arrow direction shown in Fig. 6 represents the filling order of the liquid crystal cells connected to the respective data lines.

4 to 6, R liquid crystal cells connected to the first or third gate lines G1 and G3 are supplied with a positive voltage (or a positive voltage) rising (or falling) from a negative voltage And a positive voltage (or a negative voltage) varying from a positive voltage (or a negative voltage) is applied to the G liquid crystal cells connected to the gate lines G1 to G9.

A positive voltage (or a negative voltage) rising (or falling) from a negative voltage (or a positive voltage) is applied to the B liquid crystal cells connected to the gate lines G1 to G9, (Or a positive polarity voltage) which varies at a positive polarity (or positive polarity voltage).

In this case, the charged amount of the liquid crystal cells to which the positive voltage (or the negative voltage) rising (or falling) from the negative voltage (or the positive voltage) is applied is the positive The voltage (or the negative voltage) is lower than the charged amount of the liquid crystal cells to which the voltage is applied.

This is because a rising time (or a falling time) of a positive voltage (or a negative voltage) rising (or falling) from a negative voltage (or a positive voltage) is long while a positive voltage (Or the polarity voltage) of the positive polarity voltage (or the negative polarity voltage) varying from the negative polarity voltage (or the negative polarity voltage) is relatively short.

Accordingly, all of the G liquid crystal cells can be charged with a strong current. In the G liquid crystal cell, since the G color tends to account for 60% or more of the luminance, the G liquid crystal cell may be connected to the even gate line to contribute to the luminance increase. Thus, the increase in luminance due to the filling of the G liquid crystal cell results in a reduction in material cost and power consumption, and a consumption power saving effect according to the vertical two-dot version method can save power consumption by more than 30%. Thus, the R liquid crystal cell and the B liquid crystal cell connected to the even gate line are strongly charged but the R liquid crystal cell connected to the odd gate line is substantially charged. Particularly, since the R liquid crystal cell is connected to odd-numbered gate lines, there is a phenomenon that the liquid crystal cell is totally charged. Further, in the case of the liquid crystal cell B, approximately charge and strong charge alternately appear for each vertical line. Thus, in the case of a blue pattern or a blue color dominant image, in the case of the B liquid crystal cell, a blue line dim phenomenon may occur due to the alternation of the strong charging and the weak charging in each line.

FIG. 7 is a waveform diagram showing a gate high voltage applied to the odd gate lines and the even gate lines, and FIG. 8 is a diagram showing the waveform and the structure of the liquid crystal cell according to FIG.

Referring to FIG. 7, the scan pulses applied to the odd gate lines Godd and the even gate lines Geven may be pulse waveforms that last for two frame periods, and the odd gate lines Godd and the even gate lines Geven may be pulse waveforms. The scan pulses applied to each scan pulse may be overlapped during one frame period. The sustain time and the overlap time of the scan pulse are not limited as shown in the drawing. If the duration of the scan pulse is excessively increased, there is a problem of visibility. If the duration is too short, there is a reliability problem. And the overlap period between the scan pulses.

The odd scan pulse SP_O applied to the odd gate line Godd may have a level higher than the even scan voltage SP_E applied to the even gate line Geven. That is, the odd scan pulse SP_O may have a level of a first gate high voltage VGH1 and the even scan pulse SP_E may have a level of a second gate high voltage VGH2. The level of the first gate high voltage VGH1 and the level of the second gate high voltage VGH2 may be different from each other.

Since the gate high voltage VGH can determine the rising time of the charging voltage of the liquid crystal cell, when the level of the gate high voltage VGH increases, the rising time of the charging voltage of the liquid crystal cell becomes faster, The amount of charge can be increased.

With respect to the first data line D1 and the first and second gate lines G1 and G2, the R liquid crystal cell connected to the first data line D1 and the first gate line G1 has a negative polarity A data voltage which varies in a positive polarity is applied and is approximately charged and a data voltage which varies in a positive polarity from a positive polarity is applied to the G liquid crystal cell connected to the first data line D1 and the second gate line G2, . In this case, the odd scan pulse SP_O with the increased level of the first gate high voltage VGH1 is applied to the first gate line G1, so that the charged amount of the R liquid crystal cell can be increased. Accordingly, the amount of charge of the R liquid crystal cell can be increased to about the charge amount of the G liquid crystal cell, thereby reducing the variation according to the amount of charge between the R and G liquid crystal cells. In this way, the charged amount of the liquid crystal cell on the odd-numbered gate line Godd and the charged amount of the liquid crystal cell on the even-numbered gate line Geven are controlled in a balanced manner, so that the image quality defective according to the deviation of the charging amount of the liquid crystal cells, The dim phenomenon can be improved.

Further, by connecting the G liquid crystal cell, which can contribute to 60% or more of the total luminance, to the even-numbered gate line, the power consumption is reduced by increasing the charging power and the charging amount of the R and B liquid crystal cells is increased, It is possible to prevent degradation.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100 liquid crystal display panel
200 gate driver
210 gate drive control section
300 data driver
400 timing controller
500 gamma voltage setting unit
700 driving voltage generating unit
800 voltage regulator

Claims (6)

A display panel including a plurality of data lines and a plurality of gate lines crossing each other and thin film transistors and liquid crystal cells connected to the plurality of data lines;
A gate driver which is supplied to each of the plurality of gate lines and outputs a scan pulse for driving the thin film transistor;
Wherein the gate driver comprises:
And outputs a scan pulse having a gate high voltage of a different level for each of the plurality of gate lines. The method according to claim 1,
Wherein a level of the gate high voltage of the scan pulse is varied according to a charged amount of the liquid crystal cell of the data voltage supplied through the data line in synchronization with the scan pulse. 3. The method of claim 2,
In the display panel,
(M is a natural number) and m + 1 gate lines among the n shared data lines and the plurality of gate lines for driving d (d is a positive even number) liquid crystal cells arranged on the same horizontal line And two neighboring liquid crystal cells sandwiching each of the shared data lines are symmetrically connected to the mth and (m + 1) -th gate lines,
A data signal is supplied from the left liquid crystal cell to the right liquid crystal cell in the liquid crystal cells sharing the nth data line among the data lines,
A data signal is supplied from the right liquid crystal cell to the left liquid crystal cell in the liquid crystal cells sharing the (n + 1) th and (n + 2)
A scan pulse having a level of a first gate high voltage is applied to an odd gate line among the plurality of gate lines and a scan pulse having a level of a second gate high voltage is applied to the even gate line, . The method of claim 3,
Wherein the display panel is controlled by a vertical two-dot version system.
The vertical two-dot version inverts the polarity of each of two neighboring gate lines and inverts the polarity of the data line one line at a time. 5. The method of claim 4,
The liquid crystal cell includes red, green, and blue liquid crystal cells,
And the green liquid crystal cell is connected to the even-numbered gate lines. 6. The method of claim 5,
And the level of the first gate high voltage is higher than the level of the second gate high voltage.

Images