KR102250951B1 - Liquid Crystal Display Device and Driving Method the same - Google Patents

Abstract

In an exemplary embodiment of the present invention, a liquid crystal display device and a driving method thereof include a plurality of data lines (D) and a plurality of gate lines (G) crossing each other, and a thin film transistor (T) and a liquid crystal cell (CLC) connected thereto. A display panel 100 including; Gate driving units 200 and 210 that are supplied to each of the plurality of gate lines G and output scan pulses that drive the thin film transistor T; The gate driving units 200 and 210 output scan pulses having gate high voltages VGH of different levels for each of the plurality of gate lines G, and a driving method thereof.

Description

Liquid Crystal Display Device and Driving Method the same}

The present invention relates to a liquid crystal display device and a driving method thereof.

The liquid crystal display device displays an image by controlling the light transmittance of the liquid crystal layer through an electric field applied to the liquid crystal layer in response to a video signal.

Such a liquid crystal display device is a flat panel display device having advantages of small size, thinness, and low power consumption, and is used as a portable computer such as a notebook PC, an office automation device, and an audio/video device.

In particular, an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell is advantageous for realizing a moving picture because it enables active control of the switching element.

As a switching element used in an active matrix type liquid crystal display device, a thin film transistor (hereinafter referred to as "TFT") is mainly used. An active matrix type liquid crystal display device converts digital video data into an analog data voltage based on a gamma reference voltage and supplies it to a data line and simultaneously supplies a scan pulse to a gate line to charge the data voltage to a liquid crystal cell. To this end, the gate electrode of the TFT is connected to the gate line, the source electrode is connected to the data line, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell and one electrode of the storage capacitor. A common voltage is supplied to the common electrode of the liquid crystal cell. The storage capacitor serves to maintain a constant voltage of the liquid crystal cell by charging the data voltage applied from the data line when the TFT is turned on.

When the scan pulse is applied to the gate line, the TFT is turned on to form a channel between the source electrode and the drain electrode to supply a voltage on the data line to the pixel electrode of the liquid crystal cell. At this time, the liquid crystal molecules of the liquid crystal cell change the arrangement of the liquid crystal molecules by the electric field between the pixel electrode and the common electrode, thereby changing the incident light.

In this way, the liquid crystal molecules are polarized by the DC voltage supplied between the pixel electrode and the common electrode. However, if the polarization state persists, since the characteristics of the liquid crystal may be weakened, an inversion method is applied in order to exhibit the same effect as supplying an AC voltage to the liquid crystal molecules. However, in applying such an inversion method, a variation in the data voltage charged in the liquid crystal cell occurs according to the arrangement relationship between the liquid crystal cell, the gate, and the data line, resulting in poor image quality.

An embodiment of the present invention can provide a liquid crystal display device and a driving method thereof capable of reducing power consumption and preventing deterioration in image quality by improving a variation in the amount of charge of a liquid crystal cell.

In an exemplary embodiment of the present invention, a liquid crystal display device and a driving method thereof include a plurality of data lines (D) and a plurality of gate lines (G) crossing each other, and a thin film transistor (T) and a liquid crystal cell (CLC) connected thereto. A display panel 100 including; Gate driving units 200 and 210 that are supplied to each of the plurality of gate lines G and output scan pulses that drive the thin film transistor T; The gate driving units 200 and 210 output scan pulses having gate high voltages VGH of different levels for each of the plurality of gate lines G, and a driving method thereof.

In the liquid crystal display device and its driving method according to an exemplary embodiment of the present invention, the gate high of the scan pulse is generated according to the amount of charge of the liquid crystal cell CLC of the data voltage supplied through the data line D in synchronization with the scan pulse. A liquid crystal display device in which the voltage VGH level is different and a driving method thereof.

In the liquid crystal display device and its driving method according to an exemplary embodiment of the present invention, the display panel 100 includes n to drive d (d is a positive even number) liquid crystal cells (CLC) arranged on the same horizontal line. Of the shared data lines D and the plurality of gate lines G, an m-th (m is a natural number) and an m+1-th gate line are allocated, and two adjacent two shared data lines are interposed therebetween. The liquid crystal cells are symmetrically connected to the m-th and m+1-th gate lines, and data signals are supplied in the order of the left liquid crystal cell to the right liquid crystal cell in liquid crystal cells that share an n-th data line among the data lines, In liquid crystal cells sharing the n+1 and n+2 data lines among the data lines, data signals are supplied in the order from the right liquid crystal cell to the left liquid crystal cell, and an odd number of the plurality of gate lines G A scan pulse having a level of a first gate high voltage VGH1 is output to the gate line Godd, and a scan pulse having a level of a second gate high voltage VGH2 is output to the even gate line Geven. Liquid crystal display device and its driving method.

In the liquid crystal display device and its driving method according to an embodiment of the present invention, a liquid crystal display device and a driving method thereof for controlling the display panel 100 in a vertical 2-dot inversion method.

In the liquid crystal display device and its driving method according to an embodiment of the present invention, the liquid crystal cell CLC includes red, green, and blue liquid crystal cells, and the green liquid crystal cell is the even-numbered liquid crystal cell. A liquid crystal display connected to a gate line (Geven) and a driving method thereof.

In the liquid crystal display according to an embodiment of the present invention and a driving method thereof, the level of the first gate high voltage VGH1 is higher than the level of the second gate high voltage VGH2, and a driving method thereof.

An embodiment of the present invention can provide a liquid crystal display device and a driving method thereof capable of reducing power consumption and preventing deterioration in image quality by improving a variation in the amount of charge of a liquid crystal cell.

1 is a diagram illustrating a structure of a liquid crystal display device according to an exemplary embodiment of the present invention.
2 is a block diagram of a display device including a GIP type display panel.
3 is a diagram illustrating a connection structure of liquid crystal cells constituting a display panel according to an exemplary embodiment of the present invention.
4 is a diagram illustrating a pixel structure of a display panel according to an exemplary embodiment of the present invention, and is a diagram illustrating RGB liquid crystal cells and a degree of charging of each liquid crystal cell.
5 shows a charging voltage waveform in each liquid crystal cell when the liquid crystal cells are charged in the direction of the arrow of FIG. 6.
7 is a waveform diagram showing a gate high voltage applied to an odd gate line and an even gate line.
8 is a diagram illustrating a waveform diagram and a structure of a liquid crystal cell according to FIG. 7.

Hereinafter, a liquid crystal display device and a driving method thereof according to an embodiment of the present invention will be described in detail with reference to the drawings. The following embodiments are provided as examples in order to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In addition, in the drawings, the size and thickness of the device may be exaggerated for convenience. The same reference numerals represent the same elements throughout the specification.

<Structure of display device>

1 is a diagram illustrating a structure of a liquid crystal display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, in the liquid crystal display device of the present invention, a plurality of gate lines (G) and data lines (D) are intersected, and a display panel 100 in which a pixel is defined at the intersection point, and a gate line Gate driver and data driver 200 and 300 driving the display panel 100 through (G) and data wiring (D), and control the driver by receiving timing signals and image signals from an external system (not shown) And a timing controller 400 that determines the driving frequency of the display device.

In the display panel 100, a plurality of gate wirings (G) and a plurality of data wirings (D) are intersected in a matrix form in a direction perpendicular to the gate wiring (G) on a transparent substrate, and a plurality of pixels are arranged at the intersection points. The area is defined. A thin film transistor (T) is formed in each pixel area, and a liquid crystal cell (CLC) and a storage capacitor controlled by the thin film transistor (T) are configured to display a screen through this.

The above-described thin film transistor T is turned on when a scan pulse from the gate line G, that is, a scan pulse of the gate high voltage VGH, is applied, so that the data voltage from the data line D is converted into a liquid crystal cell (CLC). ). In addition, when the gate low voltage VGL is applied from the gate wiring G, the thin film transistor T is turned off so that the data voltage charged in the liquid crystal cell CLC is maintained for one frame.

Meanwhile, the scan pulse may have different levels of scan pulses supplied to the odd-numbered gate lines and the even-numbered gate lines, that is, the level of the gate high voltage.

The liquid crystal cell CLC is a pixel electrode and a common electrode represented by a capacitor, and includes a common electrode facing each other with a liquid crystal interposed therebetween, and a pixel electrode connected to the thin film transistor T. In addition, the liquid crystal cell CLC is connected to the storage capacitor in order to stably maintain the charged data voltage until it is charged to the next data voltage. In the pixel, the arrangement of liquid crystals is changed according to the data voltage charged through the thin film transistor T, and the light transmittance of the liquid crystal cell CLC is adjusted, thereby implementing gray scale.

In addition, a gate driver 200 including a plurality of shift registers is provided at one end of the display panel 100, and is electrically connected to the gate wiring G formed on the display panel 100 to sequentially gate one horizontal line. Outputs the driving signal GCS.

The gate driver 200 turns on the thin film transistors T arranged on the display panel 100 in response to the gate control signal GCS applied from the timing controller 400, thereby The data voltage of the analog waveform supplied from the data driver 300 is applied to the liquid crystal cell CLC connected to each thin film transistor T.

The gate control signal GCS includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE). Here, the gate start pulse (GSP) is a signal applied to a shift register that generates a first gate pulse among a plurality of shift registers constituting the gate driver 200 to control the first gate pulse to be generated, and a gate shift clock (GSC) is a clock signal commonly input to all shift registers and is a clock signal for shifting the gate start pulse (GSP). In addition, the gate output enable GOE controls the outputs of the shift registers to prevent the thin film transistors corresponding to different horizontal sections from being overlapped and turned on.

The data driver 300 arranges digital image signals RGB input in response to data control signals DCS input from the timing controller 400, selects reference voltages gamma, and selects analog data. Convert to voltage.

The data voltage is latched by one horizontal section (1H) and is simultaneously input to the display panel 100 through all data lines (D).

The data control signal (DCS) includes a source start pulse (SSP), a source shift clock (SSC), a source output enable (SOE), and a polarity (POL) signal. have. Here, the source start pulse SSP is a signal that controls the data sampling start timing of the data driver 300, and the source sampling clock SSC is each driving IC constituting the data driver 300 in response to a rising or falling edge. It is a clock signal that controls the sampling timing of the data at. In addition, the source output enable (SOE) serves to control the output timing of the data driver 300.

The timing controller 400 receives video data (DATA) applied from an external system (not shown) and timing signals such as a clock signal (CLK), a horizontal synchronization signal (Hsync), and a vertical synchronization signal (Vsync). One gate control signal GCS and a data control signal DCS are generated.

Here, the horizontal synchronization signal Hsync represents the time it takes to display one line of the screen, and the vertical synchronization signal Vsync represents the time it takes to display the screen of one frame. In addition, the clock signal CLK is a signal used as a reference for generating various signals in synchronization with the gate and data drivers 200 and 300 and the timing controller 400.

In addition, although not shown, the timing controller 400 is connected to an external system (not shown) through a predetermined interface so that the timing controller 400 receives an image-related signal and a timing signal output from the external system at high speed without error. do. As such an interface, a Low Voltage Differential Signal (LVDS) method or a Transistor-Transistor Logic (TTL) interface method may be used.

The gamma voltage setting unit 500 of the display device may generate a plurality of gamma voltages and supply them to the data driver 300. The data driver 300 may generate a plurality of gray voltages by dividing the gamma voltage.

Although not shown in FIG. 1, the display device further includes a backlight unit that supplies light to the display panel 100 and a backlight driver that drives the backlight unit. The backlight unit uses a fluorescent lamp such as a Cold Cathode Fluorescent Lamp (CCFL) or an External Electrode Fluoresecent Lamp (EEFL) driven by a backlight driver, or a direct-type or edge-type backlight including a Light Emitting Diode (LED) as a light source. The direct type backlight includes a light source disposed in the entire display area so as to face the rear surface of the display panel 100 and a plurality of optical sheets disposed on the light source, and light emitted from the light source is transmitted through the plurality of optical sheets. 100). The edge type backlight includes a light guide plate facing the rear surface of the display panel 100, a light source disposed to face at least one edge of the light guide plate, and a plurality of optical sheets disposed on the light guide plate, and light emitted from the light source is It is converted into a surface light source through a light guide plate and irradiated to the display panel 100 through a plurality of optical sheets. The backlight driver drives the backlight unit and controls luminance in response to a duty ratio of a pulse width modulation (PWM) signal from the outside.

Meanwhile, the gate driver 300 is composed of at least one gate IC, mounted on a circuit film such as TCP, COF, FPC, etc., and attached to the display panel 100 in a TAB method, or on the display panel 100 in a COG method. Can be implemented. In contrast, the gate driver 300 may be formed on the thin film transistor substrate by the same process with the thin film transistor array of the display panel 100 in a GIP (Gate In Panel) method and embedded in the display panel 100.

<Structure of GIP type display device>

2 is a block diagram of a display device having a GIP type display panel.

The liquid crystal display device including the GIP display panel 100 will be described in detail with reference to FIG. 2.

A display device according to an exemplary embodiment of the present invention includes a display panel 100, a gate driving control unit 210, a data driver 300, a timing controller 400, a driving voltage generation unit 700, and a voltage control unit 800. can do.

The display panel 100 is in a pixel region defined by the intersection of m gate lines G1 to Gm, n data lines D1 to Dn, and gate lines G1 to Gm and data lines D1 to Dn. It includes a liquid crystal cell (Clc) to be formed. In addition, a gate driving control unit 210 is provided on one side of the display panel 100.

The timing controller 400 may output a gate control signal GCS, an on-clock signal ONCLK, and an off-clock signal OFFCLK to the driving voltage generator 700.

The driving voltage generator 700 generates a gate high voltage VGH and a gate low voltage VGL, and is driven based on an on-clock signal ONCLK and an off-clock signal OFFCLK from the timing controller 400. A clock signal GCLK may be generated and output.

The driving clock signal GCLK may include an odd driving clock signal GCLK_O and an even driving clock signal GCLK_E.

The driving clock signal GCLK is sequentially rising in response to the rising time of the on-clock signal ONCLK, and sequentially polled in response to the falling time of the off-clock signal OFFCLK, and the adjacent driving clock signal GCLK and Some sections may overlap each other.

In addition, the driving voltage generation unit 700 includes a level shifter therein, and outputs the high voltage of the driving clock signal GCLK by level shifting the high voltage to the gate high voltage VGH and the low voltage to the gate low voltage VGL. can do.

In addition, the driving voltage generator 700 may have different high voltage levels of the odd driving clock signal GCLK_O and the even driving clock signal GCLK_E among the driving clock signals GCLK. Accordingly, the gate high voltage VGH for determining the high voltage of the odd driving clock signal GCLK_O and the gate high voltage VGH for determining the high voltage of the even driving clock signal GCLK_E may be different from each other.

As described above, by varying the level of the gate high voltage VGH of the scan pulse applied to the gate line, variation in the charging amount of the liquid crystal cell can be reduced, thereby reducing power consumption and improving quality of image quality by setting an appropriate luminance.

In this way, the gate high voltage (GCLK_O_VGH) of the odd driving clock signal of the driving voltage generation unit 700 and the gate high voltage (GCLK_E_VGH) of the even driving clock signal are generated by the internal driving voltage generation unit 700. Different voltages may be automatically generated through setting, but unlike this, the voltage controller 800 may be used externally.

The voltage control unit 800 receives and uses the gate high voltage VGH generated from the driving voltage generator 700 and uses the gate high voltage GCLK_O_VGH and even of the odd driving clock signals having different voltage levels. A gate high voltage GCLK_E_VGH of the driving clock signal may be generated. At this time, the voltage control unit 800 is composed of a resistor and divides the gate high voltage VGH in a voltage dividing method by a resistance to generate the gate high voltage (GCLK_O_VGH) of the odd driving clock signal and the gate of the even driving clock signal. The high voltage GCLK_E_VGH may be generated, but is not limited thereto. When generating the gate high voltage (GCLK_O_VGH) of the odd driving clock signal and the gate high voltage (GCLK_E_VGH) of the even driving clock signal through the voltage adjusting unit 800 as described above, the driving voltage generator 700 controls the voltage. The gate high voltage GCLK_O_VGH of the odd driving clock signal and the gate high voltage GCLK_E_VGH of the even driving clock signal may be applied from the unit 800 and output to the gate driving control unit 210. In addition, scan pulses corresponding to the respective levels of the gate high voltage GCLK_O_VGH of the odd driving clock signal and the gate high voltage GCLK_E_VGH of the even driving clock signal may be output to the gate line by dividing the odd and even gate lines.

<Connection structure of liquid crystal cells>

3 is a diagram illustrating a connection structure of liquid crystal cells constituting a display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 3, in the display panel 100 according to an exemplary embodiment of the present invention, gates, data lines G and D, and liquid crystal cells Clc may be formed according to a double rate driving (DRD) driving method. .

The DRD driving method is a driving method that implements the same resolution as before by halving the number of data drive ICs required by halving the number of data lines by halving the number of data lines instead of doubling the number of gate lines compared to the conventional one.

In order to drive d (d is a positive even number) liquid crystal cells arranged on the same horizontal line, the display panel 100 includes n shared data lines and an m-th (m is a natural number) among a plurality of gate lines. An m+1th gate line is allocated, and two adjacent liquid crystal cells with each of the shared data lines interposed therebetween may be symmetrically connected to the mth and m+1th gate lines.

The liquid crystal cells Clc may include a plurality of R liquid crystal cells, G liquid crystal cells, and B liquid crystal cells.

Looking at the connection structure, the R liquid crystal cell connected to the first gate line G1 from the first horizontal line HL1 is adjacent to the G liquid crystal cell connected to the second gate line G2, and the first data line D1 The B liquid crystal cell is commonly connected to the second gate line G2 and is adjacent to the R liquid crystal cell connected to the first gate line G1 and is commonly connected to the second data line D2, and is connected to the second gate line G1. The G liquid crystal cell connected to the line G2 is adjacent to the B liquid crystal cell connected to the first gate line G1 and is commonly connected to the third data line D3, and R connected to the first gate line G1. The liquid crystal cell is adjacent to the G liquid crystal cell connected to the second gate line G2 and is commonly connected to the fourth data line D4, and the B liquid crystal cell connected to the second gate line G2 is a first gate line ( The G liquid crystal cell is connected to the fifth data line D5 and is adjacent to the R liquid crystal cell connected to G1), and the G liquid crystal cell connected to the second gate line G2 is a B liquid crystal cell connected to the first gate line G1. It may be adjacent to and commonly connected to the sixth data line D6.

In addition, the R liquid crystal cell connected to the third gate line G3 from the second horizontal line HL2 is adjacent to the G liquid crystal cell connected to the fourth gate line G4 and is commonly connected to the first data line D1. , The B liquid crystal cell connected to the fourth gate line G4 is adjacent to the R liquid crystal cell connected to the third gate line G3 and is commonly connected to the second data line D2, and the fourth gate line G4 The G liquid crystal cell connected to is adjacent to the B liquid crystal cell connected to the third gate line G3 and is commonly connected to the third data line D3, and the R liquid crystal cell connected to the third gate line G3 is 4 Adjacent to the G liquid crystal cell connected to the gate line G4 and commonly connected to the fourth data line D4, and the B liquid crystal cell connected to the fourth gate line G4 connected to the third gate line G3 The G liquid crystal cell is connected to the fifth data line D5 and is adjacent to the R liquid crystal cell, and the G liquid crystal cell connected to the fourth gate line G4 is adjacent to the B liquid crystal cell connected to the third gate line G3. 6 It may be commonly connected to the data line D6.

In addition, the R liquid crystal cell connected to the fifth gate line G5 from the third horizontal line HL3 is adjacent to the G liquid crystal cell connected to the sixth gate line G6 and is commonly connected to the first data line D1. , The B liquid crystal cell connected to the sixth gate line G6 is adjacent to the R liquid crystal cell connected to the fifth gate line G5 and is commonly connected to the second data line D2, and the sixth gate line G6 The G liquid crystal cell connected to is adjacent to the B liquid crystal cell connected to the fifth gate line G5 and is commonly connected to the third data line D3, and the R liquid crystal cell connected to the fifth gate line G5 is 6 Adjacent to the G liquid crystal cell connected to the gate line G6 and commonly connected to the fourth data line D4, and the B liquid crystal cell connected to the sixth gate line G6 connected to the fifth gate line G5. The G liquid crystal cell connected to the fifth data line D5 and connected to the sixth gate line G6 is adjacent to and adjacent to the B liquid crystal cell connected to the fifth gate line G5. 6 It may be commonly connected to the data line D6.

In sum, the shared data lines are arranged on the same vertical line in the order of the left liquid crystal cell to the right liquid crystal cell in the m-th data line, and the right liquid crystal cell to the left liquid crystal cell in the m+1 and m+2 data lines. Two adjacent liquid crystal cells may be driven with each interposed therebetween. For example, the sharing is arranged on the same vertical line in the order from the left liquid crystal cell to the right liquid crystal cell in the first data line (D1), and from the right liquid crystal cell to the left liquid crystal cell in the second and third data lines (D2, D3). Two adjacent liquid crystal cells may be driven with each of the data lines interposed therebetween. This method is referred to as the ZSS method.

<The degree of charging of the liquid crystal cell according to the vertical 2-dot inversion method>

4 is a diagram illustrating a pixel structure of a display panel according to an exemplary embodiment of the present invention, and is a diagram illustrating RGB liquid crystal cells and a degree of charging of each liquid crystal cell. And FIG. 5 shows the charging voltage waveform in each liquid crystal cell when the liquid crystal cells are charged along the direction of the arrow of FIG. 6.

In Figure 4, R(L) means that the red liquid crystal cell is charged low, G(H) means that the green liquid crystal cell is charged high, and the above-described low charge and high charge are relative. It is the amount of filling.

Referring to FIG. 4, in a liquid crystal display according to an exemplary embodiment of the present invention in a DRD method, d (d is a positive even number) liquid crystal cells arranged on one horizontal line are divided into two gate lines and d/2. It is driven using data lines.

The vertical 2 dot inversion method has an effect of minimizing flicker and reducing power consumption.

The reason for using the inversion is that when a DC voltage is applied to both ends of the liquid crystal (common electrode and pixel electrode), the liquid crystal becomes polarized. When this state persists, ionic impurities in the liquid crystal are fixed by the electric field, and the characteristics of the liquid crystal such as generation of afterimages are weakened by changing the pre-tilt. If the state persists for a longer period of time, the properties as a liquid crystal are eventually lost, and eventually, the liquid crystal display device cannot function as a liquid crystal display device. The method for preventing this is to prevent ionic impurities from sticking by periodically inverting the polarization state, and inverting the polarization state in this way is called inversion. In other words, the polarization of the liquid crystal has a relatively positive (+) value and a negative (-) value due to the potential difference between both ends, and is polarized accordingly. The same polarization reversal effect as supplied with AC power can be seen.

In the vertical 2-dot inversion, the polarity is reversed by two neighboring gate lines and at the same time, the polarity is reversed by one data line, and the state is inverted for each frame.

As the liquid crystal display panel 100 is driven by the first inversion method, two liquid crystal cells adjacent to each other with a data line interposed therebetween are connected to the two gate lines, respectively, and a data voltage of the same polarity supplied through the data line To charge.

For example, in a specific frame, among the liquid crystal cells arranged on the first horizontal line HL1, the R liquid crystal cell and the G liquid crystal cell shared by the first data line D1 are scan pulses from the gate lines G1 and G2. In synchronization with the supply time, the R liquid crystal cells and B liquid crystal cells, which are sequentially charged with positive polarity, are synchronized with the supply time of the scan pulses from the gate lines G1 and G2 to become negative polarity. The B liquid crystal cells and the G liquid crystal cells, which are sequentially charged, and shared with the third data line D3 are sequentially charged in a positive polarity in synchronization with the time when the scan pulses are supplied from the gate lines G1 and G2. The arrow direction shown in FIG. 6 indicates the charging order of the liquid crystal cells connected to each of the data lines.

4 to 6, the R liquid crystal cells connected to the first or third gate lines G1 and G3 have a positive voltage (or a positive voltage) rising (or falling) from a negative voltage (or a positive voltage). A negative polarity voltage) is applied, and a positive polarity voltage (or a negative polarity voltage) that varies from a positive polarity voltage (or a negative polarity voltage) is applied to the G liquid crystal cells connected to each of the gate lines G1 to G9.

In addition, a positive voltage (or negative voltage) rising (or falling) from a negative voltage (or a positive voltage) is applied to the B liquid crystal cells connected to each gate line (G1 to G9), or a negative voltage A negative polarity voltage (or a positive polarity voltage) that varies from (or a positive polarity voltage) is applied.

In this case, the amount of charge of the liquid crystal cells to which the positive voltage (or negative voltage) rising (or falling) from the negative polarity voltage (or the positive polarity voltage) is applied is the positive polarity that changes from the positive polarity voltage (or negative polarity voltage). The voltage (or negative voltage) is lower than the amount of charge of the applied liquid crystal cells.

This is because the rising time (or falling time) of the positive voltage (or negative voltage) rising (or falling) from the negative voltage (or positive voltage) is long, whereas the positive voltage ( Alternatively, the rising time (or falling time) of the positive voltage (or negative voltage) that changes from the negative voltage) is relatively short.

Accordingly, all G liquid crystal cells can be strongly charged. In the G liquid crystal cell, since the G color is involved in more than 60% of the luminance, the G liquid crystal cell may be connected to an even gate line to contribute to an increase in luminance. Thus, the increase in luminance due to strong charging of the G liquid crystal cell can reduce material cost and power consumption, and power consumption can be reduced by 30% or more through the power consumption reduction effect of the vertical 2-dot inversion method. As described above, the G liquid crystal cell connected to the even gate line is strongly charged, but the R liquid crystal cell and the B liquid crystal cell connected to the odd gate line are weakly charged. In particular, since the R liquid crystal cell is connected to an odd-numbered gate line, there is a phenomenon in which weak charging occurs as a whole. In addition, in the case of the B liquid crystal cell, weak charging and strong charging alternately appear for each vertical line. Thus, in the case of the B liquid crystal cell in an image dominated by a blue pattern or blue color, a strong charge and a weak charge alternately appear for each line, resulting in a blue line dim phenomenon.

7 is a waveform diagram illustrating a gate high voltage applied to an odd gate line and an even gate line, and FIG. 8 is a diagram illustrating a waveform diagram and a structure of a liquid crystal cell according to FIG. 7.

Referring to FIG. 7, scan pulses applied to odd gate lines Godd and even gate lines Geven may be pulse waveforms lasting for two frame periods, and odd gate lines Godd and even gate lines Geven. The scan pulses applied to each may overlap during one frame period. The duration and overlapping time of the scan pulses are not limited as shown in the drawing, and if the duration of the scan pulse is too long, there is a problem of visibility, and if the duration is too short, there is a reliability problem. It is possible to determine the duration of and an overlapping period between scan pulses.

The odd scan pulse SP_O applied to the odd gate line Godd may have a level higher than that of the even scan pulse SP_E applied to the even gate line Geven. That is, the odd scan pulse SP_O may have a level of a first gate high voltage VGH1, and the even scan pulse SP_E may have a level of a second gate high voltage VGH2. In addition, a level of the first gate high voltage VGH1 and a level of the second gate high voltage VGH2 may be different from each other.

Since the gate high voltage VGH can determine the rising time of the charging voltage of the liquid crystal cell, when the level of the gate high voltage VGH increases, the rising time of the charging voltage of the liquid crystal cell increases. The filling amount can be increased.

Based on the first data line D1 and the first and second gate lines G1 and G2, the R liquid crystal cell connected to the first data line D1 and the first gate line G1 has a negative polarity. A data voltage that changes to positive polarity is applied to weakly charge, and a data voltage that changes from positive polarity to positive polarity is applied to the G liquid crystal cell connected to the first data line D1 and the second gate line G2, resulting in strong charging. . In this case, an odd scan pulse SP_O with an increased level of the first gate high voltage VGH1 is applied to the first gate line G1, thereby increasing the amount of charge of the R liquid crystal cell. Accordingly, the amount of charge of the R liquid crystal cell is increased to the level of the charge amount of the G liquid crystal cell, thereby reducing a deviation according to the amount of charge between the R and G liquid crystal cells. In this way, the amount of charge of the liquid crystal cells on the odd gate line (Godd) and the liquid crystal cells on the even gate line (Geven) are controlled in a balanced manner. Dim phenomenon can be improved.

In addition, by connecting the G liquid crystal cell, which can participate in more than 60% of the total luminance, to the even-numbered gate line, the power consumption is reduced and the charging amount of the R and B liquid crystal cells is increased, and the image quality according to the non-uniform charge amount. It can prevent deterioration.

In the detailed description of the present invention described above, it has been described with reference to preferred embodiments of the present invention, but those skilled in the art or those of ordinary skill in the relevant technical field of the present invention described in the claims to be described later It will be appreciated that various modifications and changes can be made to the present invention without departing from the spirit and technical scope. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

100 LCD panel
200 gate driver
210 gate drive control
300 data driver
400 timing controller
500 gamma voltage setting unit
700 driving voltage generator
800 voltage regulator

Claims (6)

A display panel including a plurality of data lines and a plurality of gate lines crossing each other, and a thin film transistor and a liquid crystal cell connected thereto;
A gate driver that is supplied to each of the plurality of gate lines and outputs a scan pulse for driving the thin film transistor;
The gate driver,
Each of the plurality of gate lines outputs scan pulses having different levels of gate high voltages, and a first gate high voltage of a level higher than the level of a second gate high voltage is applied to an odd-numbered gate line among the plurality of gate lines. The branch is a liquid crystal display that outputs scan pulses. The method of claim 1,
A liquid crystal display device in which a level of a gate high voltage of the scan pulse is changed according to a charge amount of the liquid crystal cell of the data voltage supplied through the data line in synchronization with the scan pulse. The method of claim 2,
The display panel,
In order to drive d (d is a positive even number) liquid crystal cells arranged on the same horizontal line, the mth (m is a natural number) and the m+1th gate line among n shared data lines and a plurality of gate lines are Two liquid crystal cells that are allocated and adjacent to each other with each of the shared data lines interposed therebetween are symmetrically connected to the mth and m+1th gate lines,
In the liquid crystal cells sharing the n-th data line among the data lines, data signals are supplied in the order from the left liquid crystal cell to the right liquid crystal cell,
In the liquid crystal cells sharing the n+1 and n+2 data lines among the data lines, data signals are supplied in the order from the right liquid crystal cell to the left liquid crystal cell,
A liquid crystal display device configured to output a scan pulse having a level of a first gate high voltage to an odd-numbered gate line among the plurality of gate lines, and outputting a scan pulse having a level of a second gate high voltage to an even-numbered gate line. The method of claim 3,
A liquid crystal display device for controlling the polarity of the display panel in a vertical 2-dot inversion method in which the polarity of the display panel is reversed by 2 adjacent gate lines, and the polarity is reversed by 1 data line, and the state of the display panel is reversed and driven for each frame. The method of claim 4,
The liquid crystal cell includes red, green, and blue liquid crystal cells,
The green liquid crystal cell is a liquid crystal display connected to the even gate line. delete

Images