KR102562943B1 - Display Device - Google Patents

Abstract

A display device according to the present invention includes a gate driver driving a plurality of gate lines, a data driver driving a plurality of data lines, and a timing controller applying a control signal to control the gate driver and the data driver, Intersecting gate lines and data lines are connected to a plurality of subpixels having one color among R, G, B, and W disposed in each pixel row through thin film transistors, and the plurality of gate lines are connected to the subpixels. upper and lower ends are alternately arranged in a zigzag pattern, the plurality of data lines are formed to cross the gate line, and one data line and four gate lines among the plurality of gate lines and data lines form four sub-pixels. It is a display device including a display panel that drives.

Description

Display Device {Display Device}

The present invention relates to a display device, and more particularly, to a display device using a quad rate driving (QRD) method capable of improving an aperture ratio and driving with low power consumption.

Flat Panel Displays (FPDs) are used in various types of electronic products, including mobile phones, tablet PCs, and laptop computers. Flat panel display devices include a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display device (OLED), and the like, and recently, an electrophoretic display device. (EPD: ELECTROPHORETIC DISPLAY) is also widely used.

Among flat panel displays (hereinafter simply referred to as 'display devices'), a liquid crystal display (LCD) is a device that displays an image by using the optical anisotropy of liquid crystal, and has advantages such as thin, small size, low power consumption, and high image quality. Because of this, it is widely used.

In general, liquid crystal displays display images using electrical and optical properties of liquid crystals. Liquid crystals have different anisotropic properties such as refractive index and permittivity depending on the direction of the long axis and the direction of the short axis of the molecule, and the molecular arrangement and optical properties can be easily controlled. A liquid crystal display using this displays an image by adjusting the light transmittance passing through the polarizing plate by changing the arrangement direction of the liquid crystal molecules according to the magnitude of the electric field.

A liquid crystal display device includes a liquid crystal panel in which a plurality of pixels are arranged in a matrix form, a gate driver driving gate lines of the liquid crystal panel, and a data driver driving data lines of the liquid crystal panel.

In order to reduce a direct current (DC) offset component and reduce deterioration of a liquid crystal, an inversion driving method in which polarities are inverted between adjacent liquid crystal cells and polarities are inverted on a frame basis is applied to the liquid crystal display.

In addition, in order to reduce the number of data drivers or the number of data lines DL of the display device, a double rate driving (hereinafter simply referred to as 'DRD') method is used.

In a display device using the DRD method, the number of horizontal gate lines is doubled compared to the conventional one, but the number of data lines is reduced by half. That is, the DRD method is a method capable of realizing the same resolution while reducing the number of required data drives or data lines by half.

A display device using a conventional DRD method uses a 2-dot inversion method. However, in a display device using a 2-dot inversion method, high power consumption is required and vertical line dimming may occur.

To overcome this, various types of Z-inversion schemes and structures using the DRD scheme are being developed.

Recently, in order to further reduce the number of D-ICs or the number of data lines DL in the data driver of the display device, a Quad Rate Driving (hereinafter simply referred to as 'QRD') method has been developed. there is. The QRD-type display device has an advantage of reducing the number of data lines by 1/4 compared to the conventional display device, but a QRD-type rendering structure that implements performance equivalent to that of the DRD-type display device has not been proposed.

The present invention is proposed to implement performance equivalent to that of a display device using the conventional DRD method while performing Horizontal 2 dot Inversion in the above-described QRD method rendering structure. Its purpose is to provide a QRD display device having a novel rendering structure to implement performance.

In order to achieve the above object, a display device according to the present invention is provided with a plurality of sub-pixels disposed in pixel rows and each having one color of R, G, B, and W, and upper and lower ends of the sub-pixels. , a plurality of gate lines alternately arranged in a zigzag pattern, a plurality of data lines formed to cross the gate lines, and one data line and four gate lines among the plurality of gate lines and data lines to drive four sub-pixels. It is a display device that

The display device according to the present invention having the above characteristics has the following effects.

First, since four sub-pixels can be operated with one data line, the number of data lines can be reduced and the aperture ratio can be improved. As a result, the number of required data channels can be reduced. has the effect of lowering

Second, since the present invention applies an oxide thin film transistor (Oxide TFT) with excellent mobility compared to an amorphous-silicon thin film transistor (a-Si TFT), even if the charging time is reduced to ¼, the same image quality as the prior art is obtained without lowering the resolution. can be implemented.

Third, even if the polarity of the data signal is driven in the column inversion method, it can be displayed in the horizontal 2-dot inversion method, so power consumption can be reduced.

1 is a block diagram of a QRD Z-inversion type display device according to an embodiment of the present invention.
FIG. 2 is a layout in which some of the pixels shown in FIG. 1 are enlarged and displayed.
3A is a comparison example of data signal and gate signal waveforms of a display device to which a general normal driving method is applied.
3B is a comparison example of data signal and gate signal waveforms of a display device to which a general DRD driving method is applied.
3C is a simplified embodiment of data signal and gate signal waveforms of the display device of the QRD driving method according to the present invention.
4 is a waveform diagram showing outputs of a data driver ( ) and a gate driver ( ) according to an embodiment of the present invention.
FIG. 5 is a diagram for explaining a method of generating each of the gate signals G1 to G8 in FIG. 4 .
6 is a block diagram of a QRD Z-inversion type display device according to another embodiment of the present invention.
7 is a configuration diagram of a QRD Normal type display device according to another embodiment of the present invention.

A display device according to the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

1 is a block diagram of a QRD Z-inversion type display device according to an embodiment of the present invention.

FIG. 2 is a layout in which some of the pixels shown in FIG. 1 are enlarged and displayed.

1 and 2, a display panel 400 having a pixel matrix by a plurality of gate lines GL1 to GLn and data lines DL0, DL2m-1 to DL2m crossing each other; The data driver 200 charges the data lines DL1 to DLm of the display panel 400 with image signals, and the gate driver 300 drives the gate lines GL1 to GLn of the display panel 400 ), and external image data (RGB) are arranged and supplied to the data driver 200, and a timing controller 100 controls the data driver 200 by generating a data control signal DCS.

The driving circuit unit 1000 may include a timing controller 100 , a data driver 200 , a gate driver 300 , a gamma voltage supply unit 500 , and a power generator 600 .

Here, the timing controller 100 receives control signals (TCS) such as video data (RGB), vertical sync signal, horizontal sync signal, main clock signal, and data enable signal from an external system such as a TV system or video card. do. Meanwhile, although not shown, these signals may be input through an interface configured in the timing controller 100 .

The timing controller 100 generates a data control signal DCS for controlling the data driver 200 using the input control signal TCS.

The data control signal (DCS) includes a source start signal (SSS), a source sampling clock (SSC), a source output enable signal (SOE), a polarity signal (POL), etc. can include

In addition, the timing controller 100 receives image data RGB from an external system, arranges them, and transfers them to the data driver 200 .

In addition, the timing controller 100 generates a gate control signal GCS for controlling the gate driver 300 in response to the input control signal TCS, and the gate control signal GCS includes a gate start signal VST, It includes an on-clock pulse (on-CLK), an off-clock pulse (off-CLK), gate signals (G1 to Gn), and the like.

The data driver 200 supplies data voltages to the plurality of data lines DL1 to DLm in response to the data control signal DCS and the image data RGB supplied from the timing controller 100 . That is, a data voltage corresponding to the image data RGB is generated using the gamma voltage Vgamma, and the generated data voltage is supplied to the corresponding data lines DL1 to DLm.

The power generator 600 generates various driving voltages required for driving the display device. For example, the power supply voltage supplied to the timing controller 100, the data driver 200, and the gate driver 300, the gate high voltage (Vgh) and the gate low voltage (Vgl) supplied to the gate driver 300, etc. will create

The gate driver 300 sequentially selects a plurality of gate lines GL1 to GLn in response to the gate control signal GCS supplied from the timing controller 100, and turns on the selected gate lines GL1 to GLn. -on) voltage, for example, the gate high voltage (Vgh) is output. The thin film transistors TFT connected to the corresponding gate lines GL1 to GLn are turned on by the gate high voltage Vgh.

Meanwhile, a turn-off voltage, for example, a gate low voltage Vgl is supplied to the gate lines GL1 to GLn until the next frame is selected, so that the thin film transistor TFT maintains a turned-off state.

The display panel 400 includes a plurality of gate lines GL1 to GLn and data lines DL1 to DLm that cross each other, a plurality of sub-pixels R, G, and B, gate lines GL1 to GLn, and data and thin film transistors TFTs connected to the lines DL1 to DLm, respectively.

More specifically, it is as follows.

A display panel according to an embodiment of the present invention includes a 4n-3 gate line GL4n-3, a 4n-2 gate line GL4n-2, a 4n-1 gate line GL4n-1, and a 4n gate. The lines GL4n are arranged in pairs so that they are parallel to each other.

The 4n−3 gate line GL4n−3 and the 4n−2 gate line GL4n−2 pass through the tops of the leftmost three subpixels, that is, the first subpixel to the third subpixel to form the third subpixel. It is formed by bending to pass between the sub-pixel and the 4th sub-pixel, and is formed by passing through the lower ends of the 2 sub-pixels, that is, the 4th to 5th sub-pixels, and passing between the 5th and 6th sub-pixels. and is formed to pass through the upper ends of six sub-pixels, that is, the 6th sub-pixel to the 11th sub-pixel. After that, it is repeatedly formed to pass through the lower part of the two sub-pixels and the upper part of the six sub-pixels until the last sub-pixel.

The 4n−1 gate line GL4n−1 and the 4n gate line GL4n pass through the top of one leftmost subpixel, that is, the first subpixel, and pass between the first subpixel and the second subpixel. It is formed by bending to pass through six sub-pixels, that is, through lower ends of the second to seventh sub-pixels, and by bending to pass between the seventh sub-pixel and the eighth sub-pixel, and through two sub-pixels, that is, It is formed to pass through the upper ends of the eighth sub-pixel to the ninth sub-pixel. After that, it is repeatedly formed to pass through the lower part of six sub-pixels and the upper part of two sub-pixels until the last sub-pixel.

In other words, the plurality of gate lines include a 4n−3 th gate line GL4n−3, a 4n−2 th gate line GL4n−2, a 4n−1 th gate line GL4n−1 and a 4n th gate line GL4n. ) are arranged in pairs so as to be parallel to each other, and after passing the upper end of one or three sub-pixels located at the leftmost side, respectively, the upper and lower ends of two or six consecutive sub-pixels are alternately arranged in a zigzag pattern.

Also, the 4n−3 gate line GL4n−3 is connected to the 4j th subpixel and the 4j+1 th subpixel, and the 4n−2 th gate line GL4n−2 is connected to the 4j−1th subpixel and the 4jth subpixel. +2 sub-pixel, the 4n-1 gate line GL4n-1 is connected to the 4j-2 sub-pixel and the 4j+3 sub-pixel, and the 4n-th gate line GL4n is connected to the 4j-3 sub-pixel. pixel and the 4j+4th sub-pixel.

The 4n−3 gate lines GL4n−3 to 4n gate lines GL4n are repeatedly formed in the same form in the k−1 th pixel row and the k th pixel row in the display panel 400 .

However, it is not limited thereto, and a QRD method implementing horizontal 2 dot inversion within a range that does not deviate from the technical idea of the present invention by a person skilled in the art to which the present invention belongs. Various modifications to the gate line structure may be possible.

A plurality of data lines DL0 and DL2m-1 to DL2m are formed in a direction perpendicular to the plurality of gate lines GL1 to GLn to pass between the sub-pixels.

Except for the first data line DL0, the 2m−1 th data line DL2m−1 and the 2m th data line DL2m are arranged in pairs.

In this case, the 2m−1 data line DL2m−1 and the 2m data line DL2m are formed to be spaced apart by 6 sub-pixels, and then the 2m−1 data line DL2m−1 and the 2m−1 data line DL2m−1 are formed until the last subpixel. A pair of 2m data lines DL2m is repeatedly formed while being spaced apart by 2 sub-pixels.

Specifically, the first data line DL0 is formed adjacent to the leftmost sub-pixel and positioned at the end of the display panel 400 .

The first data line DL1 is spaced apart from the first data line DL0 by two subpixels and disposed between the second subpixel and the third subpixel, and the second data line DL2 is disposed between the first data line DL1. ) and is spaced apart by 6 sub-pixels and disposed between the 8th sub-pixel and the 9th sub-pixel.

Again, the third data line DL3 is spaced apart from the second data line DL2 by two subpixels and disposed between the tenth subpixel and the eleventh subpixel, and the fourth data line DL4 receives the first data line DL4. It is spaced apart from the line DL3 by 6 sub-pixels and disposed between the 16th sub-pixel and the 17th sub-pixel.

In other words, the first data line DL0 is not connected to the subpixel of the k−1 th pixel row, but is connected to the 4j−3 and 4j−2 th subpixels of the k th pixel row.

The 2m-1th data line DL2m-1 is connected to the 4j-3rd and 4j-2th sub-pixels, the 4j+1th sub-pixel and the 4j+2th sub-pixel of the k-1th pixel row, It is connected to the 4j−1 th and 4j th subpixels, and the 4j+3 th subpixel and 4j+4th subpixels of the kth pixel row.

The 2mth data line DL2m is connected to the 4j−1th and 4jth subpixels, the 4j+3th subpixel and the 4j+4th subpixel of the k−1th pixel row, and is connected to the kth subpixel of the kth pixel row. The 4j+1 sub-pixel, the 4j+2 sub-pixel, the 4(j+1)-3 sub-pixel and the 4(j+1)-2 sub-pixel are connected.

where j is an odd number, k is an even number, and n and m are natural numbers. In addition, R, G, and B sub-pixels (R, G, and B) displaying red, green, and blue may be used as the sub-pixels, and R, G, and B adjacent to each other in the horizontal direction, The G and B sub-pixels R, G, and B constitute a pixel P, which is a unit of image display.

The 4n-3 to 4n gate lines are repeatedly formed identically in all pixel rows;

It is connected to the R, G, and B sub-pixels (R, G, B) sequentially and repeatedly arranged in all pixel rows.

Also, the plurality of gate lines and the plurality of data lines are connected to each sub-pixel through thin film transistors.

However, it is not limited thereto, and a QRD method implementing horizontal 2 dot inversion within a range that does not deviate from the technical idea of the present invention by a person skilled in the art to which the present invention belongs. Various modifications to the data line structure will be possible.

FIG. 2 is an enlarged layout of the area indicated by the dotted line in FIG. 1, and further subdividing the data line DL with reference to FIG. (DSL) and data connection line (DCL).

The data line DL is connected to the data driver and is formed to pass between sub-pixels.

The data supply line DSL is a line branching from the data line DL toward a sub-pixel to which data is applied, and may branch from the data line DL in one direction or both directions.

The data connection line DCL receives a data signal from the data supply line DSL and applies it to the sub-pixel, has a U shape, and is connected to the thin film transistor TFT.

The thin film transistor TFT includes a gate electrode made of a first metal and source and drain electrodes made of a first metal.

The first metal and the second metal may be the same material.

The data supply line DSL and data connection line DCL do not overlap each other and are connected with a bend A, which is to make the area of each sub-pixel equal.

In addition, when the data connection line (DCL) is connected to the subpixel through the thin film transistor (TFT), it is connected at the top or bottom of the subpixel. Depending on the connection position, the shape of the subpixel may be reversed, and the inverted shape It is most preferable that the number of sub-pixels of the shape match the number of sub-pixels of the non-inverted shape.

When the plurality of gate lines GL1 to GLn and the plurality of data lines DL0 and DL2m-1 to DL2m are formed as described above, any gate line (GL) is provided between the 2a th subpixel and the 2a+1 th subpixel. ) is not formed, and no data line DL is formed between the b-7th sub-pixel and the b-6th sub-pixel and between the b-5th sub-pixel to the b-th sub-pixel. Therefore, no gate line GL or data line DL is formed between the c-4th subpixel and the c-3th subpixel and between the c-2th subpixel and the c-1th subpixel. , an effect of improving the aperture ratio can be obtained compared to a conventional structure in which data lines are formed between all sub-pixels. where a is a natural number, and b and c are multiples of 8. In addition, since the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm are formed on different layers, a common voltage is supplied using a region between sub-pixels where the data lines DL are not formed. A more improved image quality can be obtained by additionally forming a voltage line (not shown), and in the case of a display device including a touch function, performance can be improved by forming an auxiliary touch line (not shown).

In the case of a display device having a touch function as described above, a touch electrode (not shown) may be formed on the sub-pixel. The touch electrode is connected through the touch line, and the touch line may be formed in an area between subpixels where the data line DL is not formed.

Also, the touch line may be formed of a third metal different from the first metal of the gate electrode and the second metal of the source/drain electrodes of the thin film transistor TFT. The touch line formed of the third metal may operate as a touch sensing line during touch driving and as a common voltage line during display.

In addition, a separate touch panel may be configured in addition to the method of forming the touch line inside the panel as described above.

However, it is not limited thereto, and a QRD method implementing horizontal 2 dot inversion within a range that does not deviate from the technical idea of the present invention by a person skilled in the art to which the present invention belongs. Various modifications to the pixel structure will be possible.

3A is a comparison example of data signal and gate signal waveforms of a display device to which a general normal driving method is applied.

3B is a comparison example of data signal and gate signal waveforms of a display device to which a general DRD driving method is applied.

3C is a simplified embodiment of data signal and gate signal waveforms of the display device of the QRD driving method according to the present invention.

Referring to FIGS. 3A to 3C , compared to the general normal driving method, the DRD driving method takes 1/2 the pixel charging time, and the QRD driving method takes 1/4 the pixel charging time. In conventional display panels using a-Si TFT, the DRD driving method takes half the charging time compared to the normal driving method, so although the charging time is somewhat reduced, normal operation is possible.

However, in a display panel to which an a-Si TFT is applied, when the QRD driving method is applied by maintaining the same resolution as before without changing the resolution, normal operation is impossible because the charging time of the pixel is insufficient.

In the case of the present invention, by applying an oxide thin film transistor (Oxide TFT) instead of a-Si TFT, normal operation is possible while maintaining the same resolution as before despite a short charging time reduced to 1/4.

In addition, since the oxide thin film transistor (Oxide TFT) is applied, since the mobility is improved compared to that applied with the a-Si TFT, the width of the gate line can be reduced compared to the prior art. Accordingly, even if the number of gate lines is increased compared to when the conventional normal driving method or the DRD driving method is applied, the distance between upper and lower subpixels due to the gate lines does not excessively increase, and the same level as the conventional method can be maintained. Therefore, in the present invention to which the QRD driving method is applied, the number of gate lines is doubled or quadrupled compared to the normal driving method or the DRD driving method, but the number of data lines is reduced to 1/2 or 1/4 times, Since the width of the gate line is also reduced, an effect of improving the aperture ratio can be obtained.

4 is a waveform diagram showing outputs of the data driver 200 and the gate driver 300 according to an embodiment of the present invention.

Referring to FIG. 4 , data signals DO, D2m-1, and D2m output from each of the data drivers 200 during the Nth (N is a natural number) and N+1th frame periods are shown, and the gate driver ( 300) is applied to each of the gate lines G1, G2, G3, ... G4n-1, G4n.

D0 is the first data signals supplied to the first data line DL0, D1 is the first data signals supplied to the first data line DL1, and D2 is the second data signal supplied to the second data line DL2. , D2m−1 denotes 2m−1 th data signals supplied to the 2m−1 th data line DL2m−1, and D2m denotes 2m th data signals supplied to the m th data line DL2m.

G1 is the first gate signal supplied to the first gate line GL1, G2 is the second gate signal supplied to the second gate line GL2, and G3 is the third gate signal supplied to the third gate line GL3. , Gn−1 denotes an n−1 th gate signal supplied to the n−1 th gate line GLn−1, and Gn denotes an n th gate signal supplied to the n−th gate line GLn.

The data driver 200 supplies data voltages to the data lines in a column inversion method. The column inversion method refers to a method of supplying data voltages having opposite polarities to adjacent data lines and maintaining the same polarity of data signals supplied to each of the data lines for one frame period. For example, as shown in FIG. 4 , the data driver 200 supplies first data signals D0 with a first polarity and supplies first data signals D1 with a second polarity during the Nth frame period. The second data signals D2 are supplied with the first polarity, the 2m−1 data signals D2m−1 are supplied with the second polarity, and the 2m data signals D2m are supplied with the first polarity. do.

In addition, the data driver 200 supplies the first data signals D0 with the second polarity and the first data signals D1 with the first polarity during the N+1th frame period as shown in FIG. The second data signals D2 are supplied with the second polarity, the 2m−1 data signals D2m−1 are supplied with the first polarity, and the 2m data signals D2m are supplied with the second polarity. do. In FIG. 4 , the first polarity is positive and the second polarity is negative, but it should be noted that it is not limited thereto. That is, the first polarity may be implemented as negative polarity, and the second polarity may be implemented as positive polarity.

The gate driver 300 sequentially outputs gate signals to gate lines. For example, as shown in FIG. 4 , the gate driver 300 outputs the first gate signal G1 to the first gate line G1 in the Nth and N+1th frame periods, respectively, and outputs the first gate signal G1 to the second gate line G2. ), outputs the third gate signal G3 to the third gate line G3, and outputs the n−1 th gate to the n−1 th gate line G n−1. The signal Gn−1 is output, and the nth gate signal Gn is outputted to the nth gate line Gn. Each of the gate signals is generated as a gate high voltage (VGH) for a predetermined period. The predetermined period may be implemented as 3 to 7 horizontal periods. One horizontal period (1H) means one-line scanning time in which digital video data is written to pixels of one horizontal line in the display panel 400 .

Hereinafter, with reference to FIGS. 1 to 4 , a method of charging the data voltage to the sub-pixels during the first to eighth periods (t1 to t8) of the Nth frame period will be described in detail.

The first period t1 is a period in which the 4n−3 th gate signal G4n−3 is supplied to the 4n−3 th gate line GL4n−3 of the k−1 th pixel row, and the second period t2 is The 4n−2 th gate signal G4n−2 is supplied to the 4n−2 th gate line GL4n−2 of the k−1 th pixel row, and the third period t3 is the 4n−1 th gate signal ( G4n−1) is a period in which the 4n−1 gate line GL4n−1 of the k−1 th pixel row is supplied, and in the fourth period t4, the 4n gate signal G4n is supplied to the k−1 th pixel row. During the fifth period t5, the 4n-3 gate signal G4n-3 is applied to the 4n-3 gate line GL4n-3 of the k-th pixel row. The sixth period t6 is a period in which the 4n−2 gate signal G4n−2 is supplied to the 4n−2 gate line GL4n−2 of the k th pixel row, and the seventh period ( t7) is a period in which the 4n−1 th gate signal G4n−1 is supplied to the 4n−1 th gate line GL4n−1 of the k th pixel row, and the eighth period t8 is a period in which the 4n th gate signal G4n ) is supplied to the 4n th gate line GL4n of the k th pixel row.

During the first period t1, the 4j th sub-pixel and the 4j+1 th sub-pixel connected to the 4n-3 gate line GL4n-3 of the k-1 th pixel row receive the 4n-3 gate signal G4n-3 ) to charge the data voltage. The 4j+1th sub-pixel of the k-1th pixel row connected to the 2m-1th data line DL2m-1 is charged according to the 2m-1th data signal D2m-1 of the second polarity, and The 4j subpixel of the k−1th pixel row connected to the data line DL2m is charged according to the 2m data Dm+1 of the first polarity.

During the second period t2, the 4j−1 th subpixel and the 4j+2 th subpixel connected to the 4n−2 th gate line GL4n−2 of the k−1 th pixel row receive the 4n−2 th gate signal G4n. In response to -2), the data voltage is charged. The 4j+2 sub-pixel of the k-1 th pixel row connected to the 2m-1 th data line DL2m-1 is charged according to the 2m-1 th data signal D2m-1 of the second polarity, and The 4j-1 th sub-pixel of the k-1 th pixel row connected to the data line DL2m is charged according to the 2m data D2m of the first polarity.

During the third period t3, the 4j-2 subpixel and the 4j+3 subpixel connected to the 4n−1 gate line GL4n−1 of the k−1 th pixel row receive the 4n−1 gate signal G4n. In response to -1), the data voltage is charged. The 4j-2 sub-pixel of the k-1 th pixel row connected to the 2m-1 data line DL2m-1 is charged according to the 2m-1 data signal D2m-1 of the second polarity, and The 4j+3 subpixels of the k−1th pixel row connected to the data line DL2m are charged according to the 2m data D2m of the first polarity.

During the fourth period t4, the 4j−3 subpixel and the 4j+4th subpixel connected to the 4n gate line GL4n of the k−1 th pixel row receive a data voltage in response to the 4n gate signal G4n. to charge The 4j-3 sub-pixel of the k-1 th pixel row connected to the 2m-1 data line DL2m-1 is charged according to the 2m-1 data signal D2m-1 of the second polarity, and The 4j+4 subpixels of the k−1th pixel row connected to the data line DL2m are charged according to the 2m data D2m of the first polarity.

During the fifth period t5, the 4j th subpixel and the 4j+1 th subpixel connected to the 4n−3 th gate line GL4n−3 of the k th pixel row respond to the 4n−3 th gate signal G4n−3. In response, the data voltage is charged. The 4j+1th subpixel of the kth pixel row connected to the 2m−1th data line DL2m−1 is charged according to the 2m−1 th data signal D2m−1 of the second polarity, and the 2mth data line The 4j subpixel of the kth pixel row connected to (DL2m) is charged according to the 2m data D2m of the first polarity.

During the sixth period t6, the 4j−1 th subpixel and the 4j+2 th subpixel connected to the 4n−2 th gate line GL4n−2 of the k th pixel row receive the 4n−2 gate signal G4n−2. ) to charge the data voltage. The 4j-1 th subpixel of the k th pixel row connected to the 2m-1 th data line DL2m-1 is charged according to the 2m-1 th data signal D2m-1 of the second polarity, and the 2m th data line The 4j+2th subpixel of the kth pixel row connected to (DL2m) is charged according to the 2mth data D2m of the first polarity.

During the seventh period t7, the 4j-2th subpixel and the 4j+3th subpixel connected to the 4n−1th gate line GL4n−1 of the kth pixel row receive the 4n−1th gate signal G4n−1. ) to charge the data voltage. The second subpixel of the kth pixel row connected to the first data line DL0 is charged according to the first data signal D0 of the first polarity and connected to the 2m data line DL2m excluding the second subpixel. The 4j-2 sub-pixels of the k-th pixel row are charged according to the 2m data D2m of the first polarity, and the 4j+ sub-pixels of the k-th pixel row connected to the 2m-1 data line DL2m-1. The third sub-pixel is charged according to the 2m-1 data D2m-1 of the second polarity.

During the eighth period t8, the 4j−3 and 4j+4 subpixels connected to the 4n gate line GL4n of the k th pixel row are charged with data voltages in response to the 4n gate signal G4n. do. The first subpixel of the kth pixel row connected to the first data line DL0 is charged according to the first data signal D0 of the first polarity, and is connected to the 2m data line DL2m excluding the first subpixel. The 4j-3 sub-pixels of the k-th pixel row are charged according to the 2m data D2m of the first polarity, and the 4j+ sub-pixels of the k-th pixel row connected to the 2m-1 data line DL2m-1. The 4 sub-pixels are charged according to the 2m-1 data D2m-1 of the second polarity.

FIG. 5 is a diagram for explaining a method of generating each of the gate signals G1 to G8 in FIG. 4 .

The active time and inactive time of each gate signal (G1 to G8) are determined by the corresponding impulse of the on-clock pulse (on-CLK) and the corresponding impulse of the off-clock pulse (off-CLK) corresponding thereto, A specific example will be described with reference to FIG. 5 .

Both the on-clock pulse (on-CLK) and the off-clock pulse (off-CLK) provided from the timing controller (TC) are clock pulses composed of a plurality of periodically output impulses. In this case, the off-clock pulse (off-CLK) is output later than the on-clock pulse (on-CLK).

For example, as shown in FIG. 5, immediately after the fourth impulse (④) of the on-clock pulse (on-CLK) is generated, the first impulse (ⓐ) of the off-clock pulse (off-CLK) starts to occur That is, the output point (ⓐ) of the first impulse of the off-clock pulse (off-CLK) is located between the fourth impulse (④) and the fifth impulse (⑤) of the on-clock pulse (on-CLK). do.

Gate signals G1 to G8 are generated by the on-clock pulse (on-CLK) and the off-clock pulse (off-CLK). That is, the active time and inactive time of each gate signal (G1 to G8) is determined by a pair of corresponding on-clock pulses (on-CLK) and off-clock pulses (off-CLK). Here, the active time of a signal means a time when the signal transitions from an inactive voltage to an active voltage, and an inactive time of a signal means a time when the signal transitions from an active voltage to an inactive voltage. At this time, if the active voltage corresponds to a high logic voltage and the inactive voltage corresponds to a low logic voltage, the active time is the rising edge of the signal and the inactive time is the falling edge of the signal ) becomes the point in time. On the other hand, when the active voltage corresponds to the low logic voltage and the inactive voltage corresponds to the high logic voltage, the active time point becomes the falling edge time point of the signal and the inactive time point becomes the rising edge time point of the signal. Also, the active period of a signal means a period in which the signal is maintained in an active voltage state.

As shown in FIG. 5, the first gate signal G1 (the first impulse output) is the first impulse (①) of the on-clock pulse (on-CLK) and the corresponding off-clock pulse ( The active time and inactive time are determined by the first impulse (ⓐ) of off-CLK. Specifically, the first gate signal (G1) starts to transition to a high logic voltage (active voltage) in time with the rising edge of the first impulse (①) of the on-clock pulse (on-CLK), and the impulse The transition to the low logic voltage (inactive voltage) starts at the time of the falling edge of the first impulse (ⓐ) of the off-clock pulse (off-CLK) corresponding to (①).

In other words, the gate driver rises to a high logic voltage in line with the rising edge of the first impulse (①) of the on-clock pulse (on-CLK) described above, and the off-clock pulse (off-CLK) A first gate signal G1 transitioning to a low voltage according to the time of the falling edge of the first impulse ⓐ is generated.

In this way, the second gate signal G2 generates the second impulse (②) of the on-clock pulse (on-CLK) and the second impulse (ⓑ) of the off-clock pulse (off-CLK) corresponding thereto. The active time and the inactive time are determined by , and the third gate signal (G3) is the third impulse (③) of the on-clock pulse (on-CLK) and the off-clock pulse (off-clock pulse) corresponding thereto. The active time and inactive time are determined by the third impulse (ⓒ) of CLK), and in this way, the eighth impulse of on-clock pulse (on-CLK) and its corresponding The active time and inactive time are determined by the eighth impulse of the off-clock pulse (off-CLK).

Each of the first to eighth gate signals (G1 to G8) may have a signal width section corresponding to 3 horizontal periods to 7 horizontal periods for pre-charging to increase the charging time. Signal width sections of two adjacent gate signals may overlap for more than one horizontal period. Meanwhile, the signal width section of the gate start signal Vst may correspond to two horizontal periods.

However, it is not limited thereto, and various modifications are possible without departing from the technical spirit of the present invention.

6 is a configuration diagram of a display device to which a QRD Z-inversion method according to another embodiment of the present invention is applied.

6, R, G, B, and W sub-pixels (R, G, B, and W) displaying red, green, blue, and white are used. In addition, R, G, B, and W sub-pixels (R, G, B, and W) adjacent to each other in the horizontal direction constitute a pixel P, which is a unit of image display.

In the QRD structure according to the present invention, the gate line GL and the data line DL are repeatedly formed for eight sub-pixels, and R, G, B, and W sub-pixels (R, G, B, and W) are applied. In this case, since four sub-pixels form one pixel and the same color is repeatedly formed in the same form, three sub-pixels consist of R, G, and B sub-pixels (R, G, B) constituting one pixel. In contrast, the uniformity of the entire display panel can be improved by controlling for each color.

7 is a configuration diagram of a display device to which a QRD normal inversion method according to another embodiment of the present invention is applied.

7A is a structure for normal inversion as another embodiment of the present invention, in which R, G, and B sub-pixels (R, G, and B) displaying red, green, and blue are used. R, G, and B) adjacent to each other in the horizontal direction constitute a pixel P, which is a unit of image display.

7B is a structure for normal inversion as another embodiment of the present invention, and R, G, B, and W sub-pixels (R) displaying red, green, blue, and white , G, B, W) can be used, and the R, G, B, and W sub-pixels (R, G, B, and W) adjacent to each other in the horizontal direction constitute a pixel (P), which is a unit of image display. .

The above description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed by the claims below, and all techniques within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: timing control unit
200: data driving unit
300: gate driving unit
400: display panel
GL: gate line
DL: data line
TFT: thin film transistor

Claims (15)

A plurality of sub-pixels disposed in a pixel row, each having one color of R, G, B, and W, and rendering the R, G, B, and W colors;
a plurality of gate lines alternately disposed between upper and lower ends of the sub-pixels in a zigzag pattern;
A plurality of data lines formed to cross the gate line, and
a thin film transistor connecting the plurality of gate lines and data lines to each sub-pixel;
Four sub-pixels among the plurality of sub-pixels are activated through one data line and four gate lines among the plurality of gate lines and data lines.
According to claim 1,
The data line includes a data line connected to a data driver and passing between sub-pixels;
a data supply line branching from the data line toward a sub-pixel to which data is applied;
A display device that can be divided into data connection lines that receive data signals from the data supply lines and apply them to sub-pixels
According to claim 2,
A display device having a bend in the data supply line so that the sub-pixels are formed in the same area as each other
According to claim 3,
The thin film transistor is a display device composed of an oxide thin film transistor (Oxide TFT)
According to claim 4,
The data connection line has a U-shape and is connected to the thin film transistor, and the display device applies data to the sub-pixel through the thin film transistor.
According to claim 5,
A display device in which three R, G, and B sub-pixels are arranged one by one, or four R, G, B, and W sub-pixels are arranged one by one, in the sub-pixels adjacent to each other.
According to claim 1,
A display device in which no gate line is formed between the 2a subpixel (a is a natural number) and the 2a+1 subpixel
According to claim 1,
A display device in which no data lines are formed between the b-7th sub-pixel (b is a multiple of 8) and the b-6th sub-pixel and between the b-5th sub-pixel to the b-th sub-pixel
According to claim 1,
Indicates that no gate line or data line is formed between the c-4th subpixel (c is a multiple of 8) and the c-3th subpixel and between the c-2th subpixel and the c-1th subpixel Device
A display panel having a pixel matrix by a plurality of gate lines and data lines crossing each other;
a data driver for charging image signals to each data line of the display panel;
a gate driver driving gate lines of the display panel;
A timing controller for aligning image data from the outside and supplying the data to the data driver and generating a data control signal to control the data driver;
The display panel,
A plurality of sub-pixels disposed in a pixel row, each having one color of R, G, B, and W, and rendering the R, G, B, and W colors;
the plurality of gate lines arranged in a zigzag pattern by alternating between upper and lower ends of the sub-pixels;
The plurality of data lines formed to cross the gate line, and
a thin film transistor connecting the plurality of gate lines and data lines to each sub-pixel;
Four sub-pixels among the plurality of sub-pixels are activated through one data line and four gate lines among the plurality of gate lines and data lines.
display device.
According to claim 10,
A data voltage of a first polarity is applied to odd-numbered data lines in an N (N is a natural number) frame among the data lines, and a data voltage of a second polarity opposite to the first polarity is applied to even-numbered data lines. And a display device further comprising a data driver for applying opposite polarities in the N+1 frame.
According to claim 11,
Supplying a power voltage to the timing controller, data driver, and gate driver;
and a power generator generating a gate high voltage and a gate low voltage supplied to the gate driver.
According to claim 12,
A display device in which a gate signal applied to the gate line overlaps an adjacent gate signal with a high logic voltage period by more than one horizontal period.
According to claim 13,
The gate signal is activated with a high logic voltage at the rising edge of the on-clock pulse and inactive with a low logic voltage at the falling edge of the off-clock pulse.
According to claim 14,
A display device in which the width of the gate line is narrower than the width of the data line

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