KR101201333B1 - LCD and drive method thereof - Google Patents

Abstract

The present invention provides a liquid crystal display device in which subpixels of each pixel are arranged in a column stripe type and can drive subpixels of one pixel using only two data lines. The liquid crystal display is formed by crossing data lines and gate lines. And a plurality of pixels formed of first to third subpixels arranged in a column stripe type, and a first data line is commonly connected to first and third subpixels of an odd numbered pixel among the pixels. The second data line of the stage is connected to the second subpixel, the first gate line is commonly connected to the first and second subpixels, and the second gate line of the next stage is connected to the third subpixel. First and third subpixels of the even-numbered pixel adjacent to the odd-numbered pixel are commonly connected to the second data line and the even-numbered pick The second subpixel of is connected to the first data line, the first subpixel of the even-numbered pixel is connected to the second gate line, and the third gate line of the next stage is connected to the second and second pixels of the even-numbered pixel. And a liquid crystal display panel commonly connected to the third subpixel.

LCD, subpixel, stripe, row, reorder, data

Description

Liquid crystal display and driving method thereof

1 is an equivalent circuit diagram of a pixel formed in a general liquid crystal display device.

2 is a block diagram of a conventional liquid crystal display device.

FIG. 3 is a circuit diagram illustrating an arrangement structure of subpixels formed in the liquid crystal display panel illustrated in FIG. 2.

4 is a block diagram of a liquid crystal display device according to an exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating an arrangement structure of subpixels formed in the liquid crystal display panel illustrated in FIG. 4.

FIG. 6 is a structural diagram illustrating an arrangement structure of subpixels formed in a liquid crystal display panel shown in FIG. 4; FIG.

FIG. 7 is an equivalent circuit diagram of two neighboring pixels shown in FIG. 5. FIG.

8 is a structural diagram illustrating an arrangement structure of another embodiment of subpixels formed in the liquid crystal display panel illustrated in FIG. 4.

FIG. 9 is a configuration diagram of the timing controller shown in FIG. 4. FIG.

Description of the Related Art

100, 200: liquid crystal display device 110, 210: liquid crystal display panel

120, 230: data driver 130, 240: gate driver

140: gamma reference voltage generator 150: backlight assembly

160: inverter 170: common voltage generator

180: gate driving voltage generation unit 190, 220: timing controller

221: first line memory 222: second line memory

223: data alignment control unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and in particular, a liquid crystal display capable of arranging subpixels of each pixel in a column stripe type and driving subpixels of one pixel using only two data lines. And a driving method thereof.

A liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal, and an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell enables active control of the switching element. This is advantageous for video implementation. As the switching element used in the active matrix liquid crystal display device, a thin film transistor (hereinafter referred to as TFT) is mainly used as shown in FIG. 1.

Referring to FIG. 1, an active matrix type liquid crystal display converts digital input data into an analog data voltage based on a gamma reference voltage and supplies it to the data line DL and simultaneously supplies scan pulses to the gate line GL. The liquid crystal cell Clc is charged.

The gate electrode of the TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and one electrode of the storage capacitor Cst. Connected.

A common voltage Vcom is supplied to the common electrode of the liquid crystal cell Clc.

The storage capacitor Cst serves to charge the data voltage applied from the data line DL when the TFT is turned on to maintain the voltage of the liquid crystal cell Clc constant.

When a scan pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source electrode and the drain electrode to apply a voltage on the data line DL to the pixel electrode of the liquid crystal cell Clc Supply. At this time, the liquid crystal molecules of the liquid crystal cell Clc modulate the incident light by changing the arrangement by the electric field between the pixel electrode and the common electrode.

A configuration of a conventional liquid crystal display device having pixels having such a structure will be described with reference to FIG. 2.

2 is a block diagram of a conventional liquid crystal display device.

Referring to FIG. 2, in the conventional LCD 100, the data lines DL1 to DLm and the gate lines GL1 to GLn cross each other, and a thin film for driving the liquid crystal cell Clc at an intersection thereof. A liquid crystal display panel 110 having a TFT (TFT: Thin Film Transistor) formed thereon, a data driver 120 for supplying data to the data lines DL1 to DLm of the liquid crystal display panel 110, and a liquid crystal display panel ( A gate driver 130 for supplying scan pulses to the gate lines GL1 to GLn of the 110, a gamma reference voltage generator 140 for generating a gamma reference voltage and supplying the gamma reference voltage to the data driver 120; The backlight assembly 150 for irradiating light to the liquid crystal display panel 110, the inverter 160 for applying an alternating voltage and current to the backlight assembly 150, and a common voltage Vcom are generated to generate the liquid crystal display panel. Common voltage generation for supplying the common electrode of the liquid crystal cell Clc of (110) The gate 170 and the gate driving voltage generator 180 for generating and supplying the gate high voltage VGH and the gate low voltage VGL to the gate driver 130, the data driver 120 and the gate driver A timing controller 190 for controlling 130.

In the liquid crystal display panel 110, liquid crystal is injected between two glass substrates. On the lower glass substrate of the liquid crystal display panel 110, the data lines DL1 to DLm and the gate lines GL1 to GLn are orthogonal. TFTs are formed at intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. The TFT supplies the data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scan pulse. The gate electrodes of the TFTs are connected to the gate lines GL1 to GLn, and the source electrodes of the TFTs are connected to the data lines DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst.

The TFT is turned on in response to the scan pulse supplied to the gate terminal via the gate lines GL1 to GLn. When the TFT is turned on, video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.

The data driver 120 supplies data to the data lines DL1 to DLm in response to the data driving control signal DDC supplied from the timing controller 190. Here, the data driver 120 samples and latches the digital video data RGB supplied from the timing controller 190, and then the liquid crystal display panel 110 based on the gamma reference voltage supplied from the gamma reference voltage generator 140. In the liquid crystal cell Clc of FIG. 1, the grayscale is converted into an analog data voltage that can express gray levels, and is supplied to the data lines DL1 to DLm.

The gate driver 130 sequentially generates scan pulses, that is, gate pulses, in response to the gate driving control signal GDC and the gate shift clock GSC supplied from the timing controller 190, thereby providing the gate lines GL1 to GLn. To feed. The gate driver 130 determines the high level voltage and the low level voltage of the scan pulse in accordance with the gate high voltage VGH and the gate low voltage VGL supplied from the gate drive voltage generator 180, respectively.

The gamma reference voltage generator 140 receives a high potential power supply voltage VDD to generate a positive gamma reference voltage and a negative gamma reference voltage and output the same to the data driver 120.

The backlight assembly 150 is disposed on the rear surface of the liquid crystal display panel 110 and emits light by an AC voltage and a current supplied from the inverter 160 to irradiate light to each pixel of the liquid crystal display panel 110.

The inverter 160 converts the square wave signal generated therein into a triangular wave signal and compares the triangular wave signal with a DC power supply voltage (VCC) supplied from the system to generate a burst dimming signal proportional to the comparison result. . When a burst dimming signal determined according to an internal square wave signal is generated, a driving IC (not shown) for controlling the generation of AC voltage and current in the inverter 160 is supplied to the backlight assembly 150 according to the burst dimming signal. Control the generation of alternating voltage and current.

The common voltage generator 170 receives the high potential power voltage VDD to generate the common voltage Vcom and supplies the common voltage Vcom to the common electrodes of the liquid crystal cells Clc of each pixel of the liquid crystal display panel 110.

The gate driving voltage generator 180 receives the high potential power voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL to supply the gate driver 130 to the gate driver 130. Here, the gate driving voltage generation unit 180 generates a gate high voltage VGH that is greater than or equal to the threshold voltage of the TFTs provided in each pixel of the liquid crystal display panel 110, and the gate low voltage that is less than or equal to the threshold voltage of the TFT. VGL). The gate high voltage VGH and the gate low voltage VGL generated in this way are used to determine the high level voltage and the low level voltage of the scan pulse generated by the gate driver 130, respectively.

The timing controller 190 supplies the digital video data RGB supplied from the system to the data driver 120 and controls the data driving by using the horizontal / vertical synchronization signals H and V according to the clock signal CLK. The signal DDC and the gate driving control signal GDC are generated and supplied to the data driver 120 and the gate driver 130, respectively. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and a gate driving control signal GDC. ) Includes a gate start pulse (GSP) and a gate output enable (GOE).

In the conventional LCD having such a configuration and function, as illustrated in FIG. 3, R, G, and B subpixels of each pixel are arranged in the liquid crystal display panel 110 in a low stripe structure.

As shown in FIG. 3, a conventional liquid crystal display having a row stripe type has pixels consisting of three subpixels arranged in a row stripe type. Here, one gate line is commonly connected to subpixels arranged in each horizontal line, and one data line is commonly connected to subpixels arranged in each vertical line. That is, the number of data lines is the same as the number of subpixels arranged in one horizontal line, and the number of gate lines is the same as the number of subpixels arranged in one vertical line.

In the conventional liquid crystal display having the low stripe type, relatively one data line is formed on the liquid crystal display panel 110 because one data line is correspondingly connected to each subpixel disposed on one horizontal line. Accordingly, the liquid crystal display of the related art increases the number of circuit components of the data driver 120 in proportion to the relatively large number of data lines. As a result, the manufacturing cost of the product increases and power consumption of the data driver 120 increases. Rather, the heat generation temperature in the data driver 120 increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to arrange subpixels of each pixel in a column stripe type and to drive the subpixels of one pixel using only two data lines. A display device and a driving method thereof are provided.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of reducing the number of circuit components used to drive a data line by driving subpixels of one pixel arranged in a column stripe using only two data lines. There is.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a method of driving the same, which can reduce the manufacturing cost of a product by arranging subpixels of each pixel in a column stripe type and reducing the number of circuit components used to drive a data line. There is.

In the liquid crystal display of the present invention for achieving the above object, the data lines and the gate lines are formed to cross, a plurality of pixels consisting of the first to third sub-pixels arranged in a column stripe type is formed, A first data line is commonly connected to the first and third subpixels of the odd pixel of the pixels, and a second data line of the next stage is connected to the second subpixel, and is connected to the first and second subpixels. A first gate line is commonly connected and a second gate line of a next stage is connected to the third subpixel, and the first and third subpixels of even-numbered pixels adjacent to the odd-numbered pixel are the second data line. A second subpixel of the even pixel is connected to the first data line, and a first subpixel of the even pixel is connected to the second gate line. A liquid crystal display panel connected to the third gate line of the next stage and commonly connected to the second and third subpixels of the even pixel; A timing controller for rearranging data of the odd and even horizontal lines inputted from the system into subpixels arranged in a column stripe type; A data driver supplying the rearranged data to the liquid crystal display panel; And a gate driver sequentially supplying scan pulses to the gate lines. The first to third subpixels may be R, G, and B subpixels, respectively.

The timing controller may include a first line memory configured to store R1, G1, and B1 data of an odd-numbered horizontal line inputted from the system; A second line memory for storing R2, G2 and B2 data of even-numbered horizontal lines inputted from the system; And a data alignment control unit for controlling the storage and rearrangement of R1, G1, and B1 data of the inputted odd horizontal line and R2, G2, and B2 data of the inputted even horizontal line in synchronization with a clock from the system. do.

The data sorting control unit rearranges the R1, B1, and G2 data as data to be supplied to an odd horizontal line, and rearranges the G1, R2 and B2 data as data to be supplied to an even horizontal line.

The data driver supplies the rearranged R1, B1 and G2 data to the first data line in the order of G2 → B1 → R1 data and supplies the rearranged G1, R2 and B2 data in the order of B2 → R2 → G1 data. It is characterized by supplying to two data lines.

While the scan pulse is supplied to the first gate line, the R1 data is supplied to the R subpixel of the odd pixel through the first data line, and the G1 data is transmitted through the second data line. And a G subpixel of the pixel.

While the scan pulse is supplied to the second gate line after the first gate line, the B1 data is supplied to the B subpixel of the odd pixel through the first data line, and the R2 data is supplied to the second gate line. And the R subpixel of the even-th pixel through a data line.

While the scan pulse is supplied to the third gate line after the second gate line, the G2 data is supplied to the G subpixel of the even pixel through the first data line, and the B2 data is supplied to the second gate line. And supplied to the B subpixel of the even-th pixel through a data line.

According to an embodiment of the present invention, a plurality of pixels formed by crossing data lines and gate lines and formed of first to third subpixels arranged in a column stripe type are formed, and the first and the first pixels of the odd pixel of the pixels are formed. A first data line is commonly connected to three subpixels, a second data line of a next stage is connected to the second subpixel, and a first gate line is commonly connected to the first and second subpixels. A second gate line of is connected to the third subpixel, and the first and third subpixels of even-numbered pixels neighboring the odd-numbered pixel are commonly connected to the second data line, Two subpixels are connected to the first data line, a first subpixel of the even-numbered pixel is connected to the second gate line, and a third gate line of the next stage is connected. A method of driving a liquid crystal display device having a liquid crystal display panel commonly connected to second and third subpixels of even-numbered pixels, the method comprising arranging data of odd and even horizontal lines input from a system into the column stripe type Reordering the formed first to third subpixels; And sequentially supplying scan pulses to the gate lines and supplying the rearranged data to the data lines. The first to third subpixels may be R, G, and B subpixels, respectively.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the odd-numbered pixels, even-numbered pixels, and neighboring pixels to be described below are named based on vertical lines.

4 is a configuration diagram of a liquid crystal display according to an exemplary embodiment of the present invention. However, in the liquid crystal display device 200 of the present invention, the gamma reference voltage generator 140, the backlight assembly 150, the inverter 160, and the common voltage are the same as the liquid crystal display device 100 shown in FIG. 2. Although the generator 170 and the gate driving voltage generator 180 are provided, these components are not shown in FIG. 4 for convenience of description.

Referring to FIG. 4, the liquid crystal display 200 of the present invention is formed by crossing data lines DL1 through DLi and gate lines GL1 through GLp, and arranged in a column stripe type, R, G, and the like. A plurality of pixels consisting of B subpixels are formed, one data line is commonly connected to two of the R, G, and B subpixels of one pixel, and the data line formed next to the data line is the other one. A gate line is commonly connected to the first and second subpixels of the R, G, and B subpixels, and a gate line formed next to the gate line is perpendicular to the other subpixel. A liquid crystal display panel 110 commonly connected to the first subpixel of a neighboring pixel, R1, G1, and B1 data of an odd horizontal line inputted from the system in synchronization with a clock CLK input from the system; A timing controller 220 that temporarily stores R2, G2, and B2 data of the even-th horizontal line, and then controls driving timing of the rearranged and rearranged data in the form of R, G, and B subpixels arranged in a column stripe type; The data driver 230 supplying the rearranged data by the timing controller 220 to the liquid crystal display panel 110 under the control of the controller 220, and the scan pulses according to the control of the timing controller 220. A gate driver 240 that sequentially supplies GL1 to GLp is provided.

In the liquid crystal display panel 110, the data lines DL1 to DLi and the gate lines GL1 to GLp cross each other, and a plurality of pixels are formed adjacent to the intersection area, and R, G and B subpixels are arranged in a column stripe type. I is less than m, and p is more than n.

Here, one data line is commonly connected to the R and B subpixels among the R, G, and B subpixels of one pixel arranged in the column stripe type, and the data line formed next to the data line is connected to the G subpixel. And one gate line is commonly connected to the R and G subpixels among the R, G, and B subpixels, and the gate line formed next to the gate line is the first subpixel of the neighboring pixel in the vertical direction with the B subpixel. Common connection to the R subpixel.

The timing controller 220 temporarily stores the R1, G1, and B1 data of the odd-numbered horizontal line and the R2, G2, and B2 data of the even-numbered horizontal line in synchronization with the clock CLK input from the system. The R, G, and B subpixels arranged in a stripe type are rearranged and output to the data driver 230. Here, the timing controller 220 sequentially outputs the temporarily stored R1, G1, and B1 data and the R1, B1, and G2 data among the R2, G2, and B2 data, and then sequentially outputs the G1, R2, and B2 data.

In addition, the timing controller 220 generates a data driving control signal DDC and a gate driving control signal GDC using the horizontal / vertical synchronization signals H and V according to the clock signal CLK, respectively. 230 and the gate driver 240. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and a gate driving control signal GDC. ) Includes a gate start pulse (GSP) and a gate output enable (GOE).

The data driver 230 sequentially supplies the rearranged R1, B1, and G2 data by the timing controller 220 to the liquid crystal display panel 110, and sequentially arranges the rearranged G1, R2, and B2 data. 110). That is, the data is supplied in the order of G2 → B1 → R1 data, and then the data is supplied in the order of B2 → R2 → G1 data.

The gate driver 240 sequentially supplies scan pulses to the gate lines GL1 to GLp under the control of the timing controller 220.

FIG. 5 is a circuit diagram illustrating an arrangement structure of subpixels formed in the liquid crystal display panel illustrated in FIG. 4.

6 is a structural diagram illustrating an arrangement structure of subpixels formed in the liquid crystal display panel illustrated in FIG. 4.

5 and 6, the R, G, and B subpixels arranged in the column stripe type include a thin film transistor TFT, a storage capacitor Cst, a liquid crystal cell Clc, and the like.

The thin film transistor TFT has a gate connected to a gate line, a drain connected to a data line, and a source commonly connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst. The common voltage Vcom is applied to the common electrode of the liquid crystal cell Clc.

Meanwhile, the data line and gate line connection structures of the R, G, and B subpixels forming the even-numbered pixels adjacent to the odd-numbered pixels will be described in more detail with reference to FIG. 7.

FIG. 7 is an equivalent circuit diagram of two neighboring pixels illustrated in FIG. 5, and illustrates an equivalent circuit of a first pixel among a plurality of pixels and a neighboring pixel thereof.

As shown in FIG. 7, the R and B subpixels of the first pixel, the odd pixel, are commonly connected to the first data line DL1, and the G subpixel of the odd pixel is connected to the second data line DL2. . R subpixels and G subpixels of the odd pixel are commonly connected to the first gate line GL1 and B subpixels of the odd pixel are connected to the second gate line GL2. More specifically, the drains of the thin film transistors provided in the R subpixel and the B subpixel are commonly connected to the first data line DL1, and the drain of the thin film transistors provided in the G subpixel of the odd pixel is the second data line DL2. ) Is connected. The gates of the thin film transistors provided in the R subpixel and the G subpixel of the odd pixel are commonly connected to the first gate line GL1, and the gate of the thin film transistor provided in the B subpixel of the odd pixel is the second gate line. It is connected to GL2.

The R subpixels and the B subpixels of the even-numbered pixel adjacent to the first pixel are commonly connected to the second data line DL2, and the G subpixel of the even-numbered pixel is connected to the first data line DL1. The G subpixel and B subpixel of the even-numbered pixel are commonly connected to the third gate line GL3, and the R subpixel of the even-numbered pixel is commonly connected to the B subpixel and the second gate line GL2 of the odd pixel. do. More specifically, the drains of the thin film transistors provided in the R subpixels and the B subpixels of the even pixel are commonly connected to the second data line DL2, and the drain of the thin film transistors provided in the G subpixel of the even pixel is first. It is connected to the data line DL1. The gates of the thin film transistors provided in the G and B subpixels of the even pixel are commonly connected to the third gate line GL3, and the gate of the thin film transistors provided in the R subpixel of the even pixel is the odd pixel. Commonly connected to the gate and the second gate line (GL2) of the thin film transistor provided in the B subpixel of.

This connection structure is commonly applied to all pixels of the liquid crystal display panel 110. That is, neighboring odd-numbered pixels and even-numbered pixels have a connection structure as shown in FIG.

FIG. 8 is a structural diagram illustrating an arrangement structure of another embodiment of subpixels formed in the liquid crystal display panel of FIG. 4.

In FIG. 8, all of the subpixels formed in the same vertical line are arranged in a zigzag form, so that the data lines DL1 to DLi maintain the same interval. In contrast, in FIG. 6, all of the subpixels formed in the same vertical line are vertically arranged in a row so that the data lines DL1 to DLi do not maintain equal intervals.

9 is a configuration diagram of the timing controller shown in FIG. 4.

Referring to FIG. 9, the timing controller 220 may include a first line memory 221 for storing odd-numbered horizontal line data input from the system, and a second second memory for storing even-numbered horizontal line data input from the system. A data alignment control unit 223 for storing input data synchronized with the line memory 222 and the clock CLK from the system in the first and second line memories 221 and 222 and then rearranging and outputting the stored data. It is provided.

The first line memory 221 temporarily stores the odd-numbered horizontal lines R1, G1, and B1 data input from the system according to the writing control signal from the data alignment control unit 223, and then reads from the data alignment control unit 223. Outputs the temporarily stored R1, G1 and B1 data according to the control signal.

The second line memory 222 temporarily stores the even-numbered horizontal lines R2, G2, and B2 data input from the system according to the writing control signal from the data alignment control unit 223, and then reads from the data alignment control unit 223. Outputs the temporarily stored R2, G2 and B2 data according to the control signal.

The data alignment control unit 223 selectively supplies the writing control signal and the reading control signal to the first and second line memories 221 and 222 in synchronization with the clock CLK from the system. R1, G1, and B1 data stored in 222 and R2, G2, and B2 data stored in second line memory 222 are rearranged in the form of R, G, and B subpixels arranged in a column stripe type to the data driver 230. Output

Here, the data sorting control unit 223 rearranges the R1, B1 and G2 data as the data to be supplied to the odd horizontal line, and rearranges the G1, R2 and B2 data as the data to be supplied to the even horizontal line. When the data are rearranged in this way, the data sorting control unit 223 outputs the data to the data driver 230 in the order of G2 → B1 → R1 data in the odd horizontal line, and then in the order of B2 → R2 → G1 data in the even horizontal line. The data is output to the data driver 230.

A case where the rearranged data is supplied to the first pixel, which is the odd pixel shown in FIG.

R1, B1, and G2 data of the rearranged odd horizontal line are supplied to the first data line DL1, and G1, R2, and B2 data of the even-order even horizontal line are supplied to the second data line DL2.

First, while scan pulses are supplied to the first gate line GL1, R1 data is supplied to the R subpixel of the odd pixel through the first data line DL1, and G1 data is radiated through the second data line DL2. It is supplied to the G subpixel of the first pixel.

While the scan pulse is supplied to the second gate line GL2 after the first gate line GL1, the B1 data is supplied to the B subpixel of the odd pixel through the first data line DL1, and the R2 data is supplied to the second data line. Through DL2, the R subpixel of the even pixel is supplied.

While the scan pulse is supplied to the third gate line GL3 after the second gate line GL2, the G2 data is supplied to the G subpixel of the even pixel through the first data line DL1, and the B2 data is supplied to the second data line. It is supplied to the B subpixel of the even-th pixel through DL2.

As described above, the present invention reduces the number of circuit components used to drive data lines by driving subpixels of one pixel arranged in a column stripe using only two data lines, thereby reducing the manufacturing cost of the product. It can reduce the heat generation temperature by driving the data line.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (16)

Data lines and gate lines are formed to cross each other, and a plurality of pixels including first to third subpixels arranged in a column stripe type are formed, and first and third subpixels of an odd pixel among the pixels are formed. A first data line is commonly connected to the second data line, and a second data line of the next stage is connected to the second subpixel, and a first gate line is commonly connected to the first and second subpixels. A line is connected to the third subpixel, the first and third subpixels of the even pixel neighboring the odd pixel are commonly connected to the second data line, and the second subpixel of the even pixel is A first subpixel of the even-th pixel is connected to the second gate line, and a third gate line of a next stage is connected to the first-th data line. The commonly connected to the second and third sub-pixels of the cell the liquid crystal display panel; A timing controller for rearranging data of the odd and even horizontal lines inputted from the system into subpixels arranged in a column stripe type; A data driver supplying the rearranged data to the liquid crystal display panel; And A gate driver sequentially supplying scan pulses to the gate lines Liquid crystal display comprising a. The method of claim 1, And the first to third subpixels are R, G, and B subpixels, respectively. The method of claim 2, The timing controller,  A first line memory for storing R1, G1, and B1 data of the odd horizontal line inputted from the system; A second line memory for storing R2, G2 and B2 data of even-numbered horizontal lines inputted from the system; And A data alignment control unit for controlling the storage and reordering of R1, G1, and B1 data of the inputted odd horizontal line and R2, G2, and B2 data of the inputted even horizontal line in synchronization with a clock from the system; Liquid crystal display comprising a. The method of claim 3, wherein The data sorting control unit rearranges the R1, B1 and G2 data as data to be supplied to an odd horizontal line and rearranges the G1, R2 and B2 data as data to be supplied to an even horizontal line. Display. 5. The method of claim 4, The data driver supplies the rearranged R1, B1 and G2 data to the first data line in the order of G2 → B1 → R1 data and supplies the rearranged G1, R2 and B2 data in the order of B2 → R2 → G1 data. 2. A liquid crystal display device, characterized by supplying two data lines. 6. The method of claim 5, While the scan pulse is supplied to the first gate line, the R1 data is supplied to the R subpixel of the odd pixel through the first data line, and the G1 data is transmitted through the second data line. And a G subpixel of the pixel. The method of claim 6, While the scan pulse is supplied to the second gate line after the first gate line, the B1 data is supplied to the B subpixel of the odd pixel through the first data line, and the R2 data is supplied to the second gate line. And an R subpixel of the even-th pixel through a data line. The method of claim 7, wherein While the scan pulse is supplied to the third gate line after the second gate line, the G2 data is supplied to the G subpixel of the even-numbered pixel through the first data line, and the B2 data is stored in the third gate line. And a second subpixel of the even-th pixel through a second data line. Data lines and gate lines are formed to cross each other, and a plurality of pixels including first to third subpixels arranged in a column stripe type are formed, and first and third subpixels of an odd pixel among the pixels are formed. A first data line is commonly connected to the second data line, and a second data line of the next stage is connected to the second subpixel, and a first gate line is commonly connected to the first and second subpixels. A line is connected to the third subpixel, the first and third subpixels of the even pixel neighboring the odd pixel are commonly connected to the second data line, and the second subpixel of the even pixel is A first subpixel of the even-th pixel is connected to the second gate line, and a third gate line of a next stage is connected to the first-th data line. A method for driving a liquid crystal display device having a common liquid crystal display panel connected to the second and third sub-pixels of the cell, Rearranging the data of the odd and even horizontal lines inputted from the system into the first to third subpixels arranged in the column stripe type; And Sequentially supplying scan pulses to the gate lines and supplying the rearranged data to the data lines Method of driving a liquid crystal display comprising a. The method of claim 9, And the first to third subpixels are R, G, and B subpixels, respectively. 11. The method of claim 10, The reordering step,  Temporarily storing R1, G1, and B1 data of the odd horizontal line input from the system, and temporarily storing R2, G2, and B2 data of the even horizontal line inputted from the system; And Realigning R1, G1, and B1 data of the inputted odd horizontal line and R2, G2, and B2 data of the inputted even horizontal line in synchronization with a clock from the system. Method of driving a liquid crystal display comprising a. The method of claim 11, Realigning the R1, B1, and G2 data as data to be supplied to the odd horizontal line, and rearranging the G1, R2, and B2 data as data to be supplied to the even horizontal line. Driving method. 13. The method of claim 12, The rearranged R1, B1, and G2 data are supplied to the first data line in the order of G2 → B1 → R1 data, and the rearranged G1, R2, and B2 data are supplied to the second data line in the order of B2 → R2 → G1 data. The liquid crystal display device driving method characterized in that the supply. The method of claim 13, While the scan pulse is supplied to the first gate line, the R1 data is supplied to the R subpixel of the odd pixel through the first data line, and the G1 data is transmitted through the second data line. A method of driving a liquid crystal display device, characterized in that it is supplied to a G subpixel of a pixel. 15. The method of claim 14, While the scan pulse is supplied to the second gate line after the first gate line, the B1 data is supplied to the B subpixel of the odd pixel through the first data line, and the R2 data is supplied to the second gate line. And a R subpixel of the even-th pixel through a data line. 16. The method of claim 15, While the scan pulse is supplied to the third gate line after the second gate line, the G2 data is supplied to the G subpixel of the even pixel through the first data line, and the B2 data is supplied to the second gate line. And a B subpixel of the even-th pixel through a data line.

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