CN115236908B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN115236908B CN115236908B CN202210917985.9A CN202210917985A CN115236908B CN 115236908 B CN115236908 B CN 115236908B CN 202210917985 A CN202210917985 A CN 202210917985A CN 115236908 B CN115236908 B CN 115236908B
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- 239000000758 substrate Substances 0.000 title claims abstract description 44
- 239000003086 colorant Substances 0.000 claims abstract description 6
- 125000004122 cyclic group Chemical group 0.000 claims description 3
- 238000000034 method Methods 0.000 description 13
- 230000007547 defect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000007306 turnover Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136222—Colour filters incorporated in the active matrix substrate
Abstract
The embodiment of the application provides an array substrate, a display panel and a display device. The array substrate includes: a plurality of data lines, a plurality of gate lines and a plurality of sub-pixel units, wherein two sides of each row of sub-pixel units are respectively provided with one gate line, and the plurality of sub-pixel units comprise sub-pixel units with a plurality of luminous colors; in any row of sub-pixel units, the sub-pixel units of the first luminous color are all connected with a first gate line, and the sub-pixel units of the second luminous color are all connected with a second gate line; the first gate line and the second gate line are located at both sides of the row of sub-pixel units. The array substrate provided by the embodiment of the application can solve the problem that vertical lines appear on pictures in the prior art.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
For a display panel with a conventional single-gate structure, each column of sub-pixels needs one Data (Data) line to drive, and with the continuous improvement of the requirements of the market on high resolution and narrow frames, a dual-gate (dual gate) pixel design mode appears. The display panel with the double-gate structure adopts one data line to drive two rows of sub-pixels, so that the wiring of a fan-out area of the lower frame of the display panel is changed into half of the original wiring, the lower frame of the display panel is greatly reduced, and meanwhile, the whole length of an integrated circuit chip is shortened due to the corresponding reduction of pins of the integrated circuit chip, and the display panel can be further applied to LCD (Liquid Crystal Display ) products with small size and high resolution.
However, in the currently commonly used dual-gate pixel design mode, there is a situation that vertical lines appear on the picture.
Disclosure of Invention
The application provides an array substrate, a display panel and a display device aiming at the defects of the prior art, and is used for solving the technical problem that vertical lines appear on pictures in the prior art.
In a first aspect, an embodiment of the present application provides an array substrate, including: the display device comprises a plurality of data lines, a plurality of gate lines and a plurality of sub-pixel units, wherein two sides of each row of sub-pixel units are respectively provided with one gate line, and the plurality of sub-pixel units comprise sub-pixel units with a plurality of luminous colors;
among the sub-pixel units in any row, the sub-pixel unit in the first luminous color is connected with a first gate line, and the sub-pixel unit in the second luminous color is connected with a second gate line;
the first gate line and the second gate line are located at both sides of the row of sub-pixel units.
Optionally, the plurality of sub-pixel units include a plurality of red sub-pixel units, a plurality of green sub-pixel units, and a plurality of blue sub-pixel units;
in any row of the sub-pixel units, the red sub-pixel units are all connected with the first gate line, and the green sub-pixel units are all connected with the second gate line;
the blue sub-pixel unit is alternately connected with the first gate line and the second gate line.
Optionally, in any row of the sub-pixel units, the red sub-pixel unit, the green sub-pixel unit and the blue sub-pixel unit are arranged in a cyclic manner;
in any column of the sub-pixel units, the luminous colors of the sub-pixel units are the same.
Optionally, the sub-pixel units in any row include a plurality of pixel unit groups, where each pixel unit group includes the red sub-pixel unit, the green sub-pixel unit, the blue sub-pixel unit, the red sub-pixel unit, the green sub-pixel unit, and the blue sub-pixel unit that are sequentially set;
each pixel unit group is correspondingly connected with the first gate line and the second gate line, and is correspondingly connected with three data lines which are sequentially arranged.
Optionally, in the pixel unit group, a first red sub-pixel unit and a second red sub-pixel unit are both connected to the first gate line, the first red sub-pixel unit is connected to a first data line, and the second red sub-pixel unit is connected to a second data line;
the first green sub-pixel unit and the second green sub-pixel unit are both connected with the second gate line, the first green sub-pixel unit is connected with the first data line, and the second green sub-pixel unit is connected with the third data line;
the first blue sub-pixel unit is connected with the second gate line, the second blue sub-pixel unit is connected with the first gate line, the first blue sub-pixel unit is connected with the second data line, and the second blue sub-pixel unit is connected with the third data line.
Optionally, the array substrate further comprises a GOA circuit, wherein the GOA circuit is positioned at two sides of the display area of the array substrate;
each gate line is connected with the GOA circuit.
Optionally, the array substrate further includes a plurality of touch leads, the touch leads are disposed between two adjacent data lines, and the distances between the touch leads and the data lines adjacent to the touch leads are equal.
Optionally, the touch lead and the data line are arranged on the same layer.
In a second aspect, an embodiment of the present application provides a display panel, including the above array substrate.
In a third aspect, an embodiment of the present application provides a display device including the display panel described above.
The beneficial technical effects that technical scheme that this application embodiment provided brought include:
when the array substrate provided by the embodiment of the application is turned over in a 1+2 point turning over mode or in a 2 point turning over mode, the sub-pixel units of the first luminescent color are all connected with the first gate line, and the sub-pixel units of the second luminescent color are all connected with the second gate line in any row of sub-pixel units; the design mode has no difference of brightness and darkness of the light emission of the sub-pixel units with the first light emission color connected with the data lines with different columns, and the light emission of the sub-pixel units with the second light emission color connected with the data lines with different columns has no difference of brightness and darkness, so that the macro cannot display as vertical streak defects.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic structural diagram of an array substrate of a related patent;
FIG. 2a is a schematic diagram showing the polarity of each sub-pixel unit when the display panel is turned 1+2 dots;
FIG. 2b is a schematic diagram showing the polarity of each sub-pixel unit when the display panel is turned 2-point;
FIG. 3 is a schematic diagram of a display panel according to the related patent when 1+2 dot inversion occurs;
FIG. 4 is a schematic diagram of a display panel according to the related patent when 2-point flip occurs;
fig. 5 is a schematic structural diagram of an array substrate according to an embodiment of the present application;
FIG. 6 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure when 1+2 dot inversion occurs;
fig. 7 is a schematic structural diagram of an array substrate according to an embodiment of the present application when 2-point flip occurs.
Reference numerals illustrate:
11-red subpixel units; a 12-green subpixel unit; 13-blue sub-pixel units; 14-touch leads.
Detailed Description
Embodiments of the present application are described below with reference to the drawings in the present application. It should be understood that the embodiments described below with reference to the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and the technical solutions of the embodiments of the present application are not limited.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of other features, information, data, steps, operations, elements, components, and/or groups thereof, etc. that may be implemented as desired in the art. The term "and/or" as used herein refers to at least one of the items defined by the term, e.g., "a and/or B" may be implemented as "a", or as "B", or as "a and B".
The currently used dual-gate pixel design is shown in fig. 1, where odd-numbered rows of gate lines (e.g., G1, G3, G5, etc.) control odd-numbered columns of sub-pixels, even-numbered rows of gate lines (e.g., G2, G4, G6, etc.) control even-numbered columns of sub-pixels, i.e., in the same row of sub-pixels, each R (red) sub-pixel (red sub-pixel unit 11) is connected to a different gate line, each G (green) sub-pixel (green sub-pixel unit 12) is connected to a different gate line, and each B (blue) sub-pixel (blue sub-pixel unit 13) is connected to a different gate line. In the display panel with the double-gate design, when the display panel is matched with a 1+2 point turnover (shown in fig. 2 a) or a 2 point turnover (shown in fig. 2 b) and other turnover modes, the adjacent sub-pixels on one data line have different charging amplitudes (Margin) of the sub-pixels in odd columns and the sub-pixels in even columns due to the difference of the pre-charging polarities, the low temperature (-20 ℃) is reduced by 60% due to the starting voltage (Ion) of the thin film transistor, the dielectric constant of the liquid crystal is increased by 30%, and the charging rate is reduced, so that the display panel has vertical lines.
Specifically, as shown in fig. 1, 2a, 2B and 3, the display panel is turned over by 1+2 dots, in the process of displaying a picture, the turn-on sequence of the gate lines G1, G2, G3 is turned on row by row, in the TN (Twist Nematic) display mode, when the first column of data lines S1 is turned on, the G sub-pixel and the B sub-pixel are not bright, i.e., the G sub-pixel and the B sub-pixel are L0 gray scale, and the R sub-pixel is L127 gray scale, when the first column of data lines S1 is turned on to display a monochrome picture red (R); the first row and first column R sub-pixels are turned on by the first row gate line G1, the second row and first column R sub-pixels are turned on by the third row gate line G3, the third row and first column R sub-pixels are turned on by the fifth row gate line G5, the polarity of the first column data line S1 is inverted to + - ++, when the second row and first column R sub-pixels are bright, the polarity inversion of the second row and first column R sub-pixels is from-to-i.e. the charging of the R sub-pixels turned on by the third row gate line G3 is changed from the negative polarity-L0 of the G sub-pixels controlled by the second row gate line G2 to the negative polarity-L127 of the R sub-pixels, the voltage difference is small, the charging of the pixels is relatively sufficient, and the pixels are dark.
With continued reference to fig. 1, 2a, 2B and 3, when the second column data line S2 is turned on, the first row and fourth column R sub-pixels are turned on by the second row gate line G2, the second row and fourth column R sub-pixels are turned on by the fourth row gate line G4, the third row and fourth column R sub-pixels are turned on by the sixth row gate line G6, the polarity of the second column data line S2 is inverted to "+ - -, when the second row and fourth column R sub-pixels are on, the polarity of the second column data line S2 is inverted from +to-, that is, the positive polarity +l0 charge of the B sub-pixels controlled by the third row gate line G3 is changed to the negative polarity-L127 of the R sub-pixels, the voltage difference is large, the charge of the pixels is relatively insufficient, and the pixels are on; for the seventh column R sub-pixel, there is also a case where the pixel is darkened.
When the display mode of the display panel is the display mode of the advanced super-dimensional field switching (Advanced Super Dimension Switch, ADS), similar to the display mode of the display panel being the TN type display mode, there are also cases where the brightness of the pixels is different, which will not be described here again.
In addition, as shown in fig. 4, the display panel is turned over by 2 points, in the process of displaying the picture, the turn-on sequence of the gate lines G1, G2, G3, etc. is turned on row by row, in the TN display mode, when the first column of data line S1 is turned on, the G sub-pixel and the B sub-pixel are not bright, i.e., the G sub-pixel and the B sub-pixel are L0 gray scale, and the R sub-pixel is L127 gray scale, when the monochrome picture is displayed in red (R); the first row and first column R sub-pixels are turned on by the first row gate line G1, the second row and first column R sub-pixels are turned on by the third row gate line G3, the third row and first column R sub-pixels are turned on by the fifth row gate line G5, the polarity of the first column data line S1 is inverted to +- - ++, when the second row and first column R sub-pixels are bright, the polarity inversion of the second row and first column R sub-pixels is from +to-, that is, the charging of the R sub-pixels turned on by the third row gate line G3 is changed from the positive polarity +L0 of the G sub-pixels controlled by the second row gate line G2 to the negative polarity-L127 of the R sub-pixels, the voltage difference is large, the charging of the pixels is relatively insufficient, and the pixels are bright.
With continued reference to fig. 4, when the second column data line S2 is turned on, the first row and fourth column R sub-pixels are turned on by the second row gate line G2, the second row and fourth column R sub-pixels are turned on by the fourth row gate line G4, the third row and fourth column R sub-pixels are turned on by the sixth row gate line G6, the polarity of the second column data line S2 is inverted to "+ - -, and when the second row and fourth column R sub-pixels are bright, the polarity of the second column data line S2 is inverted from +to +i.e., the charging of the R sub-pixels turned on by the fourth row gate line G4 is changed from the positive polarity +l0 of the B sub-pixels controlled by the third row gate line G3 to the positive polarity +l127 of the R sub-pixels, the voltage difference is small, the charging of the pixels is relatively sufficient, and the pixels are darkened.
As can be seen from the above description, the display panel adopts either the 1+2 dot inversion mode or the 2 dot inversion mode, and the R sub-pixel connected to the first column data line S1 and the R sub-pixel connected to the second column data line S2 have a difference in brightness, so that the display panel macroscopically displays as a vertical stripe; similarly, vertical streak defects occur in the G-monochrome screen and the B-monochrome screen.
In order to solve the technical problem that vertical lines appear on a picture in the prior art, the embodiment of the application provides a new design mode of the array substrate.
The following describes in detail the array substrate provided in the embodiments of the present application with reference to the accompanying drawings.
The embodiment of the application provides an array substrate, which comprises: a plurality of data lines, a plurality of gate lines and a plurality of sub-pixel units, wherein two sides of each row of sub-pixel units are respectively provided with one gate line, and the plurality of sub-pixel units comprise sub-pixel units with a plurality of luminous colors; in any row of sub-pixel units, the sub-pixel units of the first luminous color are all connected with a first gate line, and the sub-pixel units of the second luminous color are all connected with a second gate line; the first gate line and the second gate line are located at both sides of the row of sub-pixel units.
Specifically, the array substrate in the embodiment of the present application is in a dual-gate design manner, one data line may be used to drive two rows of sub-pixel units, the specific arrangement manner of the data line and the gate line is the same as that of the prior art, and specifically, as shown in fig. 1, two sides of each row of sub-pixel units are respectively provided with a gate line, for example: the first row of sub-pixel units are respectively provided with a first gate line G1 and a second gate line G2 at both sides, and the second row of sub-pixel units are respectively provided with a third gate line G3 and a fourth gate line G4 at both sides.
When the array substrate provided by the embodiment of the application is turned over in a 1+2 point turning over mode or in a 2 point turning over mode, the sub-pixel units of the first luminescent color are all connected with the first gate line, and the sub-pixel units of the second luminescent color are all connected with the second gate line in any row of sub-pixel units; the design mode has no difference of brightness and darkness of the light emission of the sub-pixel units with the first light emission color connected with the data lines with different columns, and the light emission of the sub-pixel units with the second light emission color connected with the data lines with different columns has no difference of brightness and darkness, so that the macro cannot display as vertical streak defects.
When the array substrate provided by the embodiment of the application is turned over in a 1+2 dot turning manner or in a 2 dot turning manner, the luminance of the sub-pixel units of the first light emitting color connected with the different column data lines is not different, and the specific reason why the luminance of the sub-pixel units of the second light emitting color connected with the different column data lines is not different will be described in detail below with reference to the accompanying drawings.
In a specific embodiment, as shown in fig. 5, the plurality of sub-pixel units in the embodiment of the present application includes a plurality of red sub-pixel units 11, a plurality of green sub-pixel units 12, and a plurality of blue sub-pixel units 13; in any row of sub-pixel units, the red sub-pixel unit 11 is connected with a first gate line, and the green sub-pixel unit 12 is connected with a second gate line; the blue subpixel unit 13 alternately connects the first gate line and the second gate line.
It should be noted that, in the embodiment of the present application, the first gate line refers to a gate line located above a row of sub-pixel units and connected to a portion of the sub-pixel units in the row of sub-pixel units, and the second gate line refers to a gate line located below the row of sub-pixel units and connected to the rest of the sub-pixel units in the row of sub-pixel units, for example: for the first row of sub-pixel units, the first gate line refers to the first gate line G1, the second gate line refers to the second gate line G2, and for the second row of sub-pixel units, the first gate line refers to the third gate line G3, and the second gate line refers to the fourth gate line G4.
It should be noted that, in practical design, the design method is not limited to the above, and for any row of sub-pixel units, it is also possible to design that the green sub-pixel units 12 are all connected to the first gate line, and the blue sub-pixel units 13 are all connected to the second gate line; the red subpixel unit 13 alternately connects the first gate line and the second gate line.
Specifically, in the first row of sub-pixel units, the red sub-pixel units 11 are all connected to the first gate line G1, the green sub-pixel units 12 are all connected to the second gate line G2, and the blue sub-pixel units 13 are alternately connected to the second gate line G2 and the first gate line G1; in the second row of sub-pixel units, the red sub-pixel units 11 are all connected with the third gate line G3, the green sub-pixel units 12 are all connected with the fourth gate line G4, the blue sub-pixel units 13 are alternately connected with the fourth gate line G4 and the third gate line G3, and the connection modes of the red sub-pixel units 11, the green sub-pixel units 12 and the blue sub-pixel units 13 in other rows are similar, and are not repeated here.
Specifically, as shown in fig. 5, in the embodiment of the present application, in any row of sub-pixel units, the sub-pixel units are arranged in a cyclic manner of a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit; in any row of sub-pixel units, the luminous colors of the sub-pixel units are the same. For example: each row of sub-pixel units comprises a red sub-pixel unit 11, a green sub-pixel unit 12, a blue sub-pixel unit 13, a red sub-pixel unit 11, a green sub-pixel unit 12, a blue sub-pixel unit 13 and the like which are sequentially arranged, and a plurality of sub-pixel units are repeatedly arranged according to the arrangement mode of the red sub-pixel unit 11, the green sub-pixel unit 12 and the blue sub-pixel unit 13.
In an alternative embodiment, as shown in fig. 5, in any row of sub-pixel units, a plurality of pixel unit groups are included, and each pixel unit group includes a red sub-pixel unit 11, a green sub-pixel unit 12, a blue sub-pixel unit 13, a red sub-pixel unit 11, a green sub-pixel unit 12, and a blue sub-pixel unit 13, which are sequentially disposed; each pixel unit group is correspondingly connected with the first gate line and the second gate line and is correspondingly connected with three data lines which are sequentially arranged; specifically, in any row of sub-pixel units, only two pixel unit groups are shown in fig. 5, each pixel unit group includes two red sub-pixel units 11, two green sub-pixel units 12 and two blue sub-pixel units 13, the two red sub-pixel units 11 are connected to the same gate line and different data lines, the two green sub-pixel units 12 are connected to the same gate line and different data lines, and the two blue sub-pixel units 13 are connected to different gate lines and different data lines.
Specifically, in any pixel unit group in the embodiment of the present application, a first red sub-pixel unit 11 and a second red sub-pixel unit 11 are both connected to a first gate line, the first red sub-pixel unit 11 is connected to a first data line, and the second red sub-pixel unit 11 is connected to a second data line; the first green sub-pixel unit 12 and the second green sub-pixel unit 12 are both connected with the second gate line, the first green sub-pixel unit 12 is connected with the first data line, and the second green sub-pixel unit 12 is connected with the third data line; the first blue sub-pixel unit 13 is connected with the second gate line, the second blue sub-pixel unit 13 is connected with the first gate line, the first blue sub-pixel unit 13 is connected with the second data line, and the second blue sub-pixel unit 13 is connected with the third data line.
For example: in a first pixel unit group (i.e., a pixel unit group in the upper left corner in the figure) included in the first row of sub-pixel units, a first red sub-pixel unit 11 and a second red sub-pixel unit 11 are both connected to a first gate line G1, the first red sub-pixel unit 11 is connected to a first data line S1, and the second red sub-pixel unit 11 is connected to a second data line S2; the first green sub-pixel unit 12 and the second green sub-pixel unit 12 are both connected with the second gate line G2, the first green sub-pixel unit 12 is connected with the first data line S1, and the second green sub-pixel unit 12 is connected with the third data line S3; the first blue subpixel unit 13 is connected to the second gate line G2, the second blue subpixel unit 13 is connected to the first gate line G1, the first blue subpixel unit 13 is connected to the second data line S2, and the second blue subpixel unit 13 is connected to the third data line S3.
Specifically, as shown in fig. 6, the display panel is turned over by 1+2 dots, in the process of displaying the picture, the gate lines G1, G2, G3, etc. are turned on row by row, and in the TN display mode, when the first column data line S1 is turned on, the G sub-pixel and the B sub-pixel are not bright, i.e., the G sub-pixel and the B sub-pixel are L0 gray scale, and the R sub-pixel is L127 gray scale, when the monochrome picture is displayed in red (R); the first row and first column R sub-pixels are turned on by the first row gate line G1, the second row and first column R sub-pixels are turned on by the third row gate line G3, the third row and first column R sub-pixels are turned on by the fifth row gate line G5, the polarity of the first column data line S1 is inverted to + - ++, when the second row and first column R sub-pixels are bright, the polarity inversion of the second row and first column R sub-pixels is from-to-i.e. the charging of the R sub-pixels turned on by the third row gate line G3 is changed from the negative polarity-L0 of the G sub-pixels controlled by the second row gate line G2 to the negative polarity-L127 of the R sub-pixels, the voltage difference is small, the charging of the pixels is relatively sufficient, and the pixels are dark.
With continued reference to fig. 6, when the second column data line S2 is turned on, the first row and fourth column R sub-pixels are turned on by the first row gate line G1, the second row and fourth column R sub-pixels are turned on by the third row gate line G3, the third row and fourth column R sub-pixels are turned on by the fifth row gate line G5, the polarity of the second column data line S2 is inverted to "+ -, and when the second row and fourth column R sub-pixels are bright, the polarity of the second column data line S2 is inverted from-to-i.e., the charging of the R sub-pixels turned on by the third row gate line G3 is changed from the negative polarity-L0 of the B sub-pixels controlled by the second row gate line G2 to the negative polarity-L127 of the R sub-pixels, the voltage difference is small, the charge of the pixels is relatively sufficient, and the pixels are darkened.
Therefore, when the display panel is turned over by 1+2 dots, the R sub-pixel connected to the first column data line S1 and the R sub-pixel connected to the second column data line S2 are not different in light and dark (are dark at the same time), so that they are not macroscopically displayed as vertical streaks; similarly, the G monochrome screen does not suffer from moire defects.
Further, as shown in fig. 7, the display panel is turned over by 2 points, in the process of displaying the picture, the turn-on sequence of the gate lines G1, G2, G3, etc. is turned on row by row, in the TN display mode, when the first column of the data line S1 is turned on, the G sub-pixel and the B sub-pixel are not bright, i.e., the G sub-pixel and the B sub-pixel are L0 gray scale, and the R sub-pixel is L127 gray scale, when the monochrome picture is displayed in red (R); the first row and first column R sub-pixels are turned on by the first row gate line G1, the second row and first column R sub-pixels are turned on by the third row gate line G3, the third row and first column R sub-pixels are turned on by the fifth row gate line G5, the polarity of the first column data line S1 is inverted to +- - ++, when the second row and first column R sub-pixels are bright, the polarity inversion of the second row and first column R sub-pixels is from +to-, that is, the charging of the R sub-pixels turned on by the third row gate line G3 is changed from the positive polarity +L0 of the G sub-pixels controlled by the second row gate line G2 to the negative polarity-L127 of the R sub-pixels, the voltage difference is large, the charging of the pixels is relatively insufficient, and the pixels are bright.
With continued reference to fig. 7, when the second column data line S2 is turned on, the first row and fourth column R sub-pixels are turned on by the first row gate line G1, the second row and fourth column R sub-pixels are turned on by the third row gate line G3, the third row and fourth column R sub-pixels are turned on by the fifth row gate line G5, the polarity of the second column data line S2 is inverted to "+ - - -, and when the second row and fourth column R sub-pixels are bright, the polarity of the second column data line S2 is inverted from-to +, i.e., the charging of the R sub-pixels turned on by the third row gate line G3 is changed from the positive polarity of the B sub-pixels controlled by the second row gate line G2 to the positive polarity of the R sub-pixels +l127, the voltage difference is large, the charging of the pixels is relatively insufficient, and the pixels are bright.
Therefore, when the display panel is turned over at 2 points, the R sub-pixel connected to the first column data line S1 and the R sub-pixel connected to the second column data line S2 are not different in light and dark (are simultaneously lit), so that they are not macroscopically displayed as vertical streaks; similarly, the G monochrome screen does not suffer from moire defects. Namely, under the condition that the existing process and specification design are unchanged, the pixel structure design mode provided by the embodiment of the application can solve the problem that the picture of the conventional double-gate pixel structure appears vertical lines under the low-temperature condition.
In addition, the applicant finds through experiments that no matter the array substrate provided by the embodiment of the application adopts a 1+2 point overturning mode or a 2 point overturning mode, no vertical stripe defect can occur, and further confirms the feasibility of the design mode of the embodiment of the application.
In a specific embodiment, the array substrate provided in the embodiment of the present application further includes a GOA circuit, where the GOA circuit is located at two sides of the display area of the array substrate; each gate line is connected to the GOA circuit. The GOA circuit, i.e. Gate On Glass (GOA), or the array substrate row driving circuit (Gate Driver On Array, GOA) is similar to the prior art, and the detailed arrangement is not repeated here.
In a specific embodiment, as shown in fig. 6 and fig. 7, the array substrate provided in the embodiment of the present application further includes a plurality of touch leads 14, the touch leads 14 are disposed between two adjacent data lines, and the intervals between the touch leads 14 and the data lines adjacent to the touch leads are equal; for example: the distance between the first touch lead 14 and the first data line S1 is a first distance, the distance between the first touch lead 14 and the second data line S2 is a second distance, and the value of the first distance is equal to the value of the second distance.
Specifically, the touch lead and the data line in the embodiment of the application are arranged on the same layer, so that the touch lead and the data line can be manufactured simultaneously through a one-time composition process, the production cost can be reduced, the process time is saved, and the competitiveness of the product is improved. The array substrate provided by the embodiment of the application comprises the touch lead, so that the array substrate has a touch function, and the requirements of customers are better met.
Based on the same inventive concept, the embodiment of the application provides a display panel, which comprises the array substrate. Since the display panel includes the array substrate, the display panel has the same beneficial effects as the array substrate, and the description thereof is omitted.
Based on the same inventive concept, embodiments of the present application provide a display device including the above display panel. Since the display device includes the above-mentioned display panel, the display device has the same advantageous effects as the above-mentioned display panel, and will not be described again here.
In summary, by applying the embodiment of the present application, at least the following beneficial effects can be achieved:
when the array substrate provided by the embodiment of the application is turned over in a 1+2 point turning over mode or in a 2 point turning over mode, the sub-pixel units of the first luminescent color are all connected with the first gate line, and the sub-pixel units of the second luminescent color are all connected with the second gate line in any row of sub-pixel units; the design mode has no difference of brightness and darkness of the light emission of the sub-pixel units with the first light emission color connected with the data lines with different columns, and the light emission of the sub-pixel units with the second light emission color connected with the data lines with different columns has no difference of brightness and darkness, so that the macro cannot display as vertical streak defects.
Those of skill in the art will appreciate that the various operations, methods, steps in the flow, actions, schemes, and alternatives discussed in the present application may be alternated, altered, combined, or eliminated. Further, other steps, means, or steps in a process having various operations, methods, or procedures discussed in this application may be alternated, altered, rearranged, split, combined, or eliminated. Further, steps, measures, schemes in the prior art with various operations, methods, flows disclosed in the present application may also be alternated, altered, rearranged, decomposed, combined, or deleted.
In the description of the present application, the directions or positional relationships indicated by the words "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., are based on the exemplary directions or positional relationships shown in the drawings, are for convenience of description or simplifying the description of the embodiments of the present application, and do not indicate or imply that the apparatus or components referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.
The foregoing is only a part of the embodiments of the present application, and it should be noted that, for those skilled in the art, other similar implementation means based on the technical ideas of the present application are adopted without departing from the technical ideas of the solutions of the present application, and also belong to the protection scope of the embodiments of the present application.
Claims (10)
1. An array substrate, comprising: the display device comprises a plurality of data lines, a plurality of gate lines and a plurality of sub-pixel units, wherein two sides of each row of sub-pixel units are respectively provided with one gate line; one data line drives two rows of sub-pixel units;
among the sub-pixel units in any row, the sub-pixel unit in the first luminous color is connected with a first gate line, and the sub-pixel unit in the second luminous color is connected with a second gate line;
the first gate line and the second gate line are positioned at two sides of the row of sub-pixel units;
the same row of the sub-pixel units comprises a plurality of sub-pixel unit groups except the sub-pixel units in the first column, each sub-pixel unit group comprises two sub-pixel units, the turning polarities of two sub-pixel units in the same sub-pixel unit group are the same, the turning polarities of adjacent sub-pixel unit groups are different, and the turning polarity of a first sub-pixel unit group is different from the turning polarity of the sub-pixel units in the first column;
or the same row of the sub-pixel units comprises a plurality of sub-pixel unit groups, each sub-pixel unit group comprises two sub-pixel units, the turning polarities of two sub-pixel units in the same sub-pixel unit group are the same, and the turning polarities of adjacent sub-pixel unit groups are different.
2. The array substrate of claim 1, wherein the plurality of sub-pixel units comprises a plurality of red sub-pixel units, a plurality of green sub-pixel units, and a plurality of blue sub-pixel units;
in any row of the sub-pixel units, the red sub-pixel units are all connected with the first gate line, and the green sub-pixel units are all connected with the second gate line;
the blue sub-pixel unit is alternately connected with the first gate line and the second gate line.
3. The array substrate according to claim 2, wherein the red sub-pixel units, the green sub-pixel units, and the blue sub-pixel units are arranged in a cyclic manner in any row of the sub-pixel units;
in any column of the sub-pixel units, the luminous colors of the sub-pixel units are the same.
4. The array substrate of claim 3, wherein each row of the sub-pixel units comprises a plurality of pixel unit groups, each pixel unit group comprising the red sub-pixel unit, the green sub-pixel unit, the blue sub-pixel unit, the red sub-pixel unit, the green sub-pixel unit and the blue sub-pixel unit, which are sequentially arranged;
each pixel unit group is correspondingly connected with the first gate line and the second gate line, and is correspondingly connected with three data lines which are sequentially arranged.
5. The array substrate of claim 4, wherein in the pixel cell group, a first one of the red sub-pixel cells and a second one of the red sub-pixel cells are connected to the first gate line, the first one of the red sub-pixel cells is connected to a first data line, and the second one of the red sub-pixel cells is connected to a second data line;
the first green sub-pixel unit and the second green sub-pixel unit are both connected with the second gate line, the first green sub-pixel unit is connected with the first data line, and the second green sub-pixel unit is connected with the third data line;
the first blue sub-pixel unit is connected with the second gate line, the second blue sub-pixel unit is connected with the first gate line, the first blue sub-pixel unit is connected with the second data line, and the second blue sub-pixel unit is connected with the third data line.
6. The array substrate of claim 1, further comprising GOA circuitry located on both sides of a display area of the array substrate;
each gate line is connected with the GOA circuit.
7. The array substrate of any one of claims 1-5, further comprising a plurality of touch leads, wherein the touch leads are disposed between two adjacent data lines, and the distance between the touch leads and the data lines adjacent to the touch leads is equal.
8. The array substrate of claim 7, wherein the touch lead is disposed on the same layer as the data line.
9. A display panel comprising an array substrate according to any one of claims 1-8.
10. A display device comprising the display panel according to claim 9.
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