CN111123598A - Array substrate and display device - Google Patents
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- 239000003086 colorant Substances 0.000 claims description 34
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- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
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Abstract
The invention discloses an array substrate and a display device.A data line which is correspondingly and electrically connected with at least two rows of sub-pixels with the same polarity is electrically connected with the same bonding pad which is positioned in a non-display area, so that the bridging positions of the sub-pixels in different rows are arranged in the non-display area, on one hand, the aperture opening ratio of the pixels can be improved, the display brightness is improved, and on the other hand, the problem that the display picture is poor due to the coupling of the bridging of the data line and the pixels in the display area in the prior art can be avoided; in addition, when the array substrate provided by the invention displays a pure color picture, the same data line can output constant output voltage, and the power consumption when the pure color picture is displayed is effectively reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a display device.
Background
Liquid Crystal Display (LCD) devices are widely used in modern information devices, such as displays, televisions, mobile phones, and digital products, because of their advantages, such as light weight, low power consumption, low radiation, and portability. The main structure of the liquid crystal display device consists of an array substrate, a color film substrate and a liquid crystal layer filled between the two substrates.
With the development of high-resolution display, not only the power consumption of the display device is gradually increased, but also the cost of the driving IC is continuously increased. In order to reduce the cost of the driver IC, the related art proposes an array substrate driven by a Dual Gate (Dual Gate), which can reduce not only the number of data lines, thereby reducing the cost of the driver IC, but also the fan-out (Fanout) wiring space, thereby reducing the bezel width.
Practical use shows that the conventional double-gate driving display device has the problems of large power consumption, low aperture ratio and poor display picture.
Disclosure of Invention
The embodiment of the invention provides an array substrate and a device, which are used for solving the problems of high power consumption, low aperture ratio and poor display picture of the conventional double-gate driving display device.
The embodiment of the invention provides an array substrate, which comprises a display area and a non-display area surrounding the display area; the display area includes: the pixel structure comprises a plurality of grid lines and a plurality of data lines, wherein the grid lines and the data lines are vertically crossed to define a plurality of pixel units distributed in an array; the pixel unit comprises a plurality of sub-pixels with different colors, and the colors of the sub-pixels in the same column are the same; the sub-pixels in the same row are correspondingly and electrically connected with the two grid lines, and the two grid lines correspondingly and electrically connected with the sub-pixels in the same row are positioned at two sides of the sub-pixels; each row of the sub-pixels is electrically connected with the same data line, and two adjacent rows of the sub-pixels are correspondingly electrically connected with different data lines;
the polarities of the sub-pixels in the same column are the same, and the polarities of the sub-pixels in the same row are not completely the same;
the non-display area comprises a driving chip, the driving chip is provided with a plurality of bonding pads, and at least two rows of data lines which are electrically connected with the same sub-pixels in the same polarity correspondingly are electrically connected with the same bonding pad.
Optionally, in a specific implementation, in the array substrate provided in an embodiment of the present invention, the non-display area further includes a plurality of cross-over wires, and at least two rows of data lines electrically connected to the sub-pixels with the same polarity are electrically connected to the same pad through the same cross-over wire.
Optionally, in a specific implementation, in the array substrate provided in the embodiment of the present invention, the data lines, which are electrically connected to the sub-pixels with the same polarity in two columns, are electrically connected to the same pad through the same jumper wire.
Optionally, in a specific implementation, in the array substrate provided in an embodiment of the present invention, the pixel unit includes sub-pixels with different three colors, and each of the sub-pixels in the same row is periodically arranged according to the three colors.
Optionally, in a specific implementation, in the array substrate provided in the embodiment of the present invention, two columns of the subpixels, corresponding to two data lines electrically connected to a same pad, are different in color, polarities of the subpixels, corresponding to data lines electrically connected to adjacent pads, are opposite, and the subpixels, corresponding to the two data lines electrically connected to the same pad, in a same row are electrically connected to different gate lines.
Optionally, in a specific implementation, in the array substrate provided in the embodiment of the present invention, two columns of the sub-pixels corresponding to two data lines electrically connected to the same pad have one column of the sub-pixels with different colors therebetween.
Optionally, in a specific implementation, in the array substrate provided in the embodiment of the present invention, two columns of the subpixels, corresponding to two data lines electrically connected to a same pad, are the same in color, and the subpixels, corresponding to the two data lines electrically connected to the same pad, in a same row are electrically connected to different gate lines.
Optionally, in a specific implementation, in the array substrate provided in the embodiment of the present invention, two columns of the sub-pixels with different colors are disposed between two columns of the sub-pixels corresponding to two data lines electrically connected to the same pad.
Optionally, in a specific implementation, in the array substrate provided in the embodiment of the present invention, five rows of the sub-pixels with different colors are disposed between two rows of the sub-pixels corresponding to two data lines electrically connected to the same pad.
Correspondingly, the embodiment of the invention also provides a display device, which comprises the array substrate provided by the embodiment of the invention.
The invention has the following beneficial effects:
according to the array substrate and the display device provided by the embodiment of the invention, at least two rows of data lines which are correspondingly and electrically connected with the same polarity of the sub-pixels are electrically connected with the same bonding pad positioned in the non-display area, so that the bridging positions of the sub-pixels in different rows are arranged in the non-display area, on one hand, the aperture opening ratio of the pixels can be improved, the display brightness is improved, and on the other hand, the problem that the display picture is poor due to the coupling of the bridging of the data lines and the pixels to the pixels in the display area in the prior art can be avoided; in addition, when the array substrate provided by the invention displays a pure color picture, the same data line can output constant output voltage, and the power consumption when the pure color picture is displayed is effectively reduced.
Drawings
Fig. 1 is a schematic structural view of an array substrate provided in the related art;
fig. 2 is a timing diagram of the array substrate shown in fig. 1;
fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the invention;
fig. 4 is a second schematic structural diagram of an array substrate according to an embodiment of the invention;
fig. 5 is a third schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 6 is a timing diagram of an array substrate according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the array substrate and the display device according to the embodiments of the present invention will be described in further detail with reference to the accompanying drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The shapes and sizes of the various elements in the drawings are not intended to reflect the true scale of the array substrate, but are merely illustrative of the present invention.
The inventor of the present application has found that, in the dual-gate driving lcd device in the related art, the pixels that are turned on during the period when the scan Clock (Clock, CK) of the 2N +1(N includes 0) th row is at the high level are always in the state of storing electric energy, and the scan Clock signal of the 2N (N does not include 0) th row is pulled down and coupled to the pixels that are driven by the 2N +1(N includes 0) th row, so that the phenomenon of the weakened state of storing electric energy of the 2N +1 th row of pixels is caused, and the charge driving of the 2N +1 th row of pixels is insufficient, which causes the inconsistent charging effect of the positive and negative polarities and the difference between the bright and dark of the pixels. Meanwhile, two columns of sub-pixels with the same polarity are adjacent, so that thicker vertical stripes are caused after the phenomenon of brightness difference of positive and negative polarities is superposed. Most of the existing solutions to solve the above problems adopt a Zigzag driving (Zigzag) driving manner, that is, the data lines drive different pixels in different rows through left or right bridging pixels, so that the positions of the coupled pixels are scattered when displaying the same color, and what is brought about is that the pixel connecting lines cross and surround the pixel routing lines for many times, the coupling capacitance between the pixel connecting lines and the pixels is very large, and when displaying a pure color picture, the potential on each data line repeatedly changes 0V → +5V, +5V → 0V for many times, and the expressive force in terms of heavy-load driving power consumption is very poor. In addition, since a plurality of pixel lines need to be provided in the display region for pixel bridging, the aperture ratio is decreased, and the luminance is lowered.
Taking a double-gate driving liquid crystal display device in the related art as an example, as shown in fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of a double-gate array substrate in the related art, fig. 2 is a timing diagram shown in fig. 1, fig. 2 takes 16CLK as an example, and scanning signals are output row by row, the double-gate array substrate includes a plurality of sub-pixels arranged in an array, in each pixel row, a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B are periodically arranged, colors of the sub-pixels in the same pixel column are the same, one data line connects two rows of sub-pixels with different colors, and two rows of sub-pixels connected by one data line are arranged at intervals, so that the data line and the sub-pixels need to be bridged, and the bridged line and the sub-pixels are coupled with each other, thereby causing a phenomenon of poor display picture; the bridging occupies the space of the pixel area, so that the aperture opening ratio is reduced, and the display brightness is reduced; in addition, in the structure of fig. 1, when displaying a pure color image, taking the data line S1 as an example, in each row of pixels, the data line S1 connects the red sub-pixel R on the left side and the blue sub-pixel B spaced by one column on the right side, so that the output voltage of the data line S1 needs to change constantly when displaying the pure color image. For example, assuming that the data voltage is +5V and the common voltage is 0V, when the first row gate line G1 is turned on, the data line S1 needs to output +5V to the left red subpixel R; when the second row gate line G2 is turned on, the data line S1 needs to output 0V to the blue subpixels B spaced by one column on the right side because a red picture is displayed; when the third row gate line G1 is turned on, the data line S1 needs to output +5V to the red subpixel R on the left side; when the fourth row gate line G2 is turned on, the data line S1 needs to output 0V to the blue sub-pixel B spaced by one column on the right side because a red picture is displayed; and so on. Therefore, the output voltage of the data line S1 needs to be changed repeatedly from 0V → +5V and from +5V → 0V, and similarly, the output voltage is changed repeatedly for the other data lines. Therefore, when the conventional double-gate array substrate displays a pure-color picture, the output of the data line is actually the same as that of the data line of the heavy-load picture, and the power consumption is greatly increased due to repeated change of the output voltage.
In summary, the dual-gate display device in the related art has the problems of large power consumption, low aperture ratio and poor display quality.
In view of the above, to solve the above problems, embodiments of the present invention provide an array substrate, as shown in fig. 3 to 5, including a display area and a non-display area surrounding the display area; the display area includes: the pixel structure comprises a plurality of gate lines (G1, G2, G3 … …) and a plurality of data lines (S1, S2, S3 … …), wherein the gate lines and the data lines are vertically crossed to define a plurality of pixel units distributed in an array; the pixel unit comprises a plurality of sub-pixels with different colors (for example, each pixel unit comprises a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B), and the colors of the sub-pixels in the same column are the same (for example, the colors of the sub-pixels in the first column are red, the colors of the sub-pixels in the second class are green, and the colors of the sub-pixels in the third column are blue … …); the same row of sub-pixels are correspondingly and electrically connected with two gate lines (for example, the first row of sub-pixels are respectively and electrically connected with a first gate line G1 and a second gate line G2, the second row of sub-pixels are respectively and electrically connected with a third gate line G3 and a fourth gate line G4, the third row of sub-pixels are respectively and electrically connected with a fifth gate line G5 and a sixth gate line G6 … …), and the two gate lines correspondingly and electrically connected with the same row of sub-pixels are located at two sides of the sub-pixels (for example, the first gate line G1 and the second gate line G2 correspondingly and electrically connected with the first row of sub-pixels are located at the upper and lower sides of the first row of sub-pixels, the third gate line G3 and the fourth gate line G4 correspondingly and electrically connected with the second row of sub-pixels are located at the upper and lower sides of the second row of the sub-pixels, and the third row of sub-pixels correspondingly and electrically connected fifth gate line; each column of sub-pixels is electrically connected with the same data line (for example, a first column of sub-pixels is electrically connected with the data line S1, a second column of sub-pixels is electrically connected with the data line S2, a third column of sub-pixels is electrically connected with the data line S3, … …), and two adjacent columns of sub-pixels are correspondingly electrically connected with different data lines (for example, the adjacent first and second columns of sub-pixels are electrically connected with the data line S1 and the data line S2 respectively, the adjacent second and third columns of sub-pixels are electrically connected with the data line S2 and the data line S3 respectively, and the adjacent third and fourth columns of sub-pixels are electrically connected with the data line S3 and the data line S4 … … respectively);
the polarities of the sub-pixels in the same column are the same (e.g., the polarities of the sub-pixels in the first column are positive, and the polarities of the sub-pixels in the second column are negative … …), and the polarities of the sub-pixels in the same row are not completely the same (e.g., the polarities of the sub-pixels in the first row include positive and negative polarities, and the polarities of the sub-pixels in the second row include positive and negative polarities … …);
the non-display area comprises a driving chip, the driving chip is provided with a plurality of bonding pads (Pad1, Pad2 and Pad3 … …), at least two columns of data lines electrically connected with the same polarity correspondingly are electrically connected with the same bonding Pad (for example, a data line S1 electrically connected with a first column of sub-pixels and a data line S3 electrically connected with a third column of sub-pixels are electrically connected with a bonding Pad1 in fig. 3, a data line S1 electrically connected with a first column of sub-pixels and a data line S4 electrically connected with a fourth column of sub-pixels are electrically connected with the bonding Pad1 in fig. 4, and a data line S1 electrically connected with a first column of sub-pixels and a data line S7 electrically connected with a seventh column of sub-pixels are electrically connected with the bonding Pad1 and … … in fig. 5).
According to the array substrate provided by the embodiment of the invention, at least two rows of data lines which are correspondingly and electrically connected with the same polarity of the sub-pixels are electrically connected with the same bonding pad positioned in the non-display area, so that the bridging positions of the sub-pixels in different rows are arranged in the non-display area, on one hand, the aperture opening ratio of the pixels can be improved, the display brightness can be improved, and on the other hand, the problem that the display picture is poor due to the coupling of the bridging of the data lines and the pixels to the pixels in the display area in the prior art can be avoided; in addition, when the array substrate provided by the invention displays a pure color picture, the same data line can output constant output voltage, and the power consumption when the pure color picture is displayed is effectively reduced.
It should be noted that, in the array substrate shown in fig. 3 to 5 provided in the embodiment of the present invention, only a part of the pixel units is taken as an example for description, and in the specific implementation, the number of the pixel units in the array substrate is designed according to the actual situation, and the present invention is only for schematic description.
In a specific implementation, as shown in fig. 3 to 5, the non-display area further includes a plurality of cross-over wires 01, and at least two rows of data lines electrically connected to the sub-pixels with the same polarity are electrically connected to the same pad through the same cross-over wire 01. Specifically, the data lines which are correspondingly and electrically connected with at least two rows of sub-pixels with the same polarity are electrically connected with the same bonding pad which is positioned in the non-display area through the same bridging conductor 01, the bridging conductor 01 is arranged in the non-display area, the space of the pixel area is not occupied, the aperture opening ratio of the pixels can be improved, the display brightness is improved, the coupling phenomenon between the bridging conductor 01 and the sub-pixels does not exist in the pixel area, and therefore the problem of poor display pictures cannot occur.
In a specific implementation, in the array substrate provided in the embodiment of the present invention, as shown in fig. 3 to fig. 5, the data lines electrically connected to the two rows of sub-pixels with the same polarity are electrically connected to the same pad through the same jumper wire 01. Specifically, as shown in fig. 3, the data line S1 electrically connected to the sub-pixel of the first column and the data line S3 electrically connected to the sub-pixel of the third column are electrically connected to the Pad1 through the same jumper wire 01, and the data line S2 electrically connected to the sub-pixel of the second column and the data line S4 electrically connected to the sub-pixel of the fourth column are electrically connected to the Pad2 through the same jumper wire 01 … …; as shown in fig. 4, the data line S1 electrically connected to the sub-pixel in the first column and the data line S4 electrically connected to the sub-pixel in the fourth column are electrically connected to the Pad1 through the same jumper wire 01, and the data line S2 electrically connected to the sub-pixel in the second column and the data line S5 electrically connected to the sub-pixel in the fifth column are electrically connected to the Pad2 through the same jumper wire 01 … …; as shown in fig. 5, the data line S1 electrically connected to the sub-pixel in the first column and the data line S7 electrically connected to the sub-pixel in the seventh column are electrically connected to the Pad1 through the same jumper wire 01, and the data line S2 electrically connected to the sub-pixel in the second column and the data line S8 electrically connected to the sub-pixel in the eighth column are electrically connected to the Pad2 through the same jumper wire 01 … ….
In specific implementation, as shown in fig. 3 to 5, the pixel unit includes three sub-pixels (a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B) with different colors, and the sub-pixels in the same row are periodically arranged according to the three colors, for example, the sub-pixels in the same row are periodically arranged according to the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B. Of course, in a specific implementation, the pixel unit may also include more than three sub-pixels with different colors, for example, a white sub-pixel or a yellow sub-pixel, and the like, which is not limited herein.
In specific implementation, as shown in fig. 3, in the array substrate provided in the embodiment of the present invention, the two columns of sub-pixels corresponding to the two data lines electrically connected to the same Pad are different in color, for example, the two columns of sub-pixels corresponding to the two data lines S1 and S3 electrically connected to the Pad1 are respectively red and blue in color, the two columns of sub-pixels corresponding to the two data lines S2 and S4 electrically connected to the Pad2 are respectively green and red in color, the two columns of sub-pixels corresponding to the two data lines S5 and S7 electrically connected to the Pad3 are respectively green and red in color, and the two columns of sub-pixels corresponding to the two data lines S6 and S8 electrically connected to the Pad4 are respectively blue and green … … in color; the polarities of the sub-pixels corresponding to the data lines electrically connected with the adjacent pads are opposite, for example, the polarity of the sub-pixel corresponding to the data lines S1 and S3 electrically connected with the Pad1 is positive, the polarity of the sub-pixel corresponding to the data lines S2 and S4 electrically connected with the Pad2 is negative, the polarity of the sub-pixel corresponding to the data lines S5 and S7 electrically connected with the Pad3 is positive, and the polarity of the sub-pixel corresponding to the data lines S6 and S8 electrically connected with the Pad4 is negative … …; for example, two subpixels in a first row corresponding to two data lines S1 and S3 electrically connected to a Pad1 are electrically connected to a first gate line G1 and a second gate line G2, respectively, and two subpixels in a first row corresponding to two data lines S2 and S4 electrically connected to a Pad2 are electrically connected to a second gate line G2 and a first gate line G1, respectively, and … …. The same Pad of the driving chip is connected to the sub-pixels in different columns for driving after crossing two columns, and because the polarity of the sub-pixels under the driving of the same data line (such as the data line S1) is unchanged (the sub-pixels in the first column are positive), the polarity distribution of the sub-pixels is the result that the same polarity appears once every two columns of the sub-pixels, namely, each sub-pixel column is alternately arranged according to the positive polarity and the negative polarity, which is the same as the panel design of single gate in realization, and no cross-connection wires among the pixels are coupled to the pixel potential in the display area, so that the charging difference caused by the coupling is avoided.
In specific implementation, as shown in fig. 3, in the array substrate provided in the embodiment of the present invention, two columns of sub-pixels corresponding to two data lines electrically connected to the same Pad have one column of sub-pixels with different colors, for example, a column of green sub-pixels G with different colors is provided between two columns of sub-pixels (a first column of red sub-pixels R and a third column of blue sub-pixels B) corresponding to two data lines S1 and S3 electrically connected to the Pad1, and a column of blue sub-pixels B … … with different colors is provided between two columns of sub-pixels (a second column of green sub-pixels G and a fourth column of red sub-pixels R) corresponding to two data lines S2 and S4 electrically connected to the Pad 2.
In a specific implementation, in the array substrate provided in the embodiment of the present invention, as shown in fig. 4 and fig. 5, two columns of sub-pixels corresponding to two data lines electrically connected to a same Pad have the same color, specifically, as shown in fig. 4, a first column of sub-pixels and a fourth column of sub-pixels corresponding to two data lines S1 and S4 electrically connected to a Pad1 are both red sub-pixels R, a second column of sub-pixels and a fifth column of sub-pixels corresponding to two data lines S2 and S5 electrically connected to a Pad2 are both green sub-pixels G, and a third column of sub-pixels and a sixth column of sub-pixels corresponding to two data lines S3 and S6 electrically connected to a Pad3 are both blue sub-pixels B … …; as shown in fig. 5, the sub-pixels in the first column and the sub-pixels in the seventh column corresponding to the two data lines S1 and S7 electrically connected to the Pad1 are all red sub-pixels R, the sub-pixels in the second column and the sub-pixels in the eighth column corresponding to the two data lines S2 and S8 electrically connected to the Pad2 are all green sub-pixels G, and the sub-pixels in the third column and the sub-pixels in the ninth column corresponding to the two data lines S3 and S9 electrically connected to the Pad3 are all blue sub-pixels B … …. And the same row of sub-pixels corresponding to the two data lines electrically connected to the same Pad are electrically connected to different gate lines, specifically, as shown in fig. 4, two sub-pixels R in the first row corresponding to the two data lines S1 and S4 electrically connected to the Pad1 are electrically connected to the first gate line G1 and the second gate line G2, two sub-pixels G in the first row corresponding to the two data lines S2 and S5 electrically connected to the Pad2 are electrically connected to the second gate line G2 and the first gate line G1, and two sub-pixels B in the first row corresponding to the two data lines S3 and S6 electrically connected to the Pad3 are electrically connected to the first gate line G1 and the second gate line G2, … …, respectively; as shown in fig. 5, two subpixels R in the first row corresponding to two data lines S1 and S7 to which a Pad1 is electrically connected are electrically connected to a first gate line G1 and a second gate line G2, respectively, two subpixels G in the first row corresponding to two data lines S2 and S8 to which a Pad2 is electrically connected are electrically connected to a second gate line G2 and a first gate line G1, respectively, and two subpixels B in the first row corresponding to two data lines S3 and S9 to which a Pad3 is electrically connected are electrically connected to a first gate line G1 and a second gate line G2, respectively, and … ….
In practical implementation, in the array substrate provided by the embodiment of the invention, as shown in fig. 4, two columns of sub-pixels with different colors are arranged between two columns of sub-pixels corresponding to two data lines electrically connected to the same pad, for example, two columns of sub-pixels (a first column of red sub-pixels R and a fourth column of red sub-pixels R) corresponding to two data lines S1 and S4 electrically connected by a Pad1 have a green sub-pixel G column and a blue sub-pixel B column with different colors therebetween, two columns of sub-pixels (a second column of green sub-pixels G and a fifth column of green sub-pixels G) corresponding to two data lines S2 and S5 electrically connected by a Pad2 have a blue sub-pixel B column and a red sub-pixel R column with different colors therebetween, and two columns of sub-pixels (a third column of blue sub-pixels B and a sixth column of blue sub-pixels B) corresponding to two data lines S3 and S6 electrically connected by a Pad3 have a red sub-pixel R column and a green sub-pixel G column … … with different colors therebetween. Therefore, the same Pad of the driving chip is connected to the sub-pixels of different columns for driving after crossing three columns of sub-pixels, two data lines electrically connected to each Pad are respectively electrically connected to the sub-pixels of the same color, and because the polarities of the sub-pixels of the same color are the same, the polarities of the output on the panel are "+, -" during displaying, that is, the data mapping in the mode that the output polarity of the driving chip of the liquid crystal display panel is 4dot can save power consumption.
In specific implementation, in the array substrate provided in the embodiment of the present invention, as shown in fig. 5, five rows of sub-pixels with different colors are located between two rows of sub-pixels corresponding to two data lines electrically connected to a same Pad, for example, a green sub-pixel G row, a blue sub-pixel B row, a red sub-pixel R row, a green sub-pixel G row, and a blue sub-pixel B row are located between two rows of sub-pixels (a first row of red sub-pixels R and a seventh row of red sub-pixels R) corresponding to two data lines S1 and S7 electrically connected to a Pad1, a blue sub-pixel B row, a red sub-pixel R row, a green sub-pixel G row, a blue sub-pixel B row, a Pad R row, and a blue sub-pixel B row (a second row of green sub-pixels G and an eighth row of green sub-pixels G) corresponding to two data lines S6725 and S8678 electrically connected to a Pad sad 2 electrically connected to a Pad 3663 are located between two rows of blue sub-pixels (a second row and a third row of blue sub Nine columns of blue subpixels B) have red R and green G, blue B, red R and green G subpixel columns … … of different colors between them. Therefore, the same Pad of the driving chip spans six columns of sub-pixels and then is connected to sub-pixels of different columns for driving, two data lines electrically connected with each Pad are respectively and electrically connected with the sub-pixels of the same color, the polarity of the sub-pixels under the driving of the same data line is unchanged, and the polarities of the two columns of sub-pixels corresponding to the two data lines electrically connected with the same Pad are also the same, so that the polarity distribution of the sub-pixels is the result that the same polarity appears once for every other column of sub-pixels, namely, each sub-pixel column is alternately arranged according to positive polarity and negative polarity, the design is the same as that of a single gate panel, no crossover lead among pixels is arranged in a display area for coupling pixel potential, and the charging difference caused by the coupling is avoided. In the scheme shown in fig. 5, because neither the polarity nor the data mapping of the driver chip needs to be changed (changed), the workload for the driver chip is lower than that of the schemes shown in fig. 3 and 4, which is more convenient to implement.
The following describes a principle of saving power consumption of a display panel on which the array substrate (fig. 3) according to an embodiment of the present invention is disposed, compared with the array substrate (fig. 1) in the related art, with reference to a timing diagram.
As shown in fig. 1 and fig. 2, taking the array substrate including 1080 data lines as an example, of course, fig. 1 only illustrates a part of the 1080 data lines, when the array substrate shown in fig. 1 is used to display a pure color image, a corresponding timing diagram is shown in fig. 2 (partial timing sequence), a Dummy phase of a clock signal in fig. 2 is a pre-start phase, CLK signals are turned on one by one, corresponding gate lines are turned on line by line, taking an example of displaying a red image, assuming that a data voltage is +5V, a common voltage on a common electrode line 02 is 0V, and when a first row of gate lines G1 is turned on, a data line S1 needs to output +5V to a left red subpixel R; when the second row gate line G2 is turned on, the data line S1 needs to output 0V to the blue subpixels B spaced by one column on the right side because a red picture is displayed; when the third row gate line G1 is turned on, the data line S1 needs to output +5V to the red subpixel R on the left side; when the fourth row gate line G2 is turned on, the data line S1 needs to output 0V to the blue sub-pixel B spaced by one column on the right side because a red picture is displayed; and so on. Therefore, the output voltage of the data line S1 needs to be changed repeatedly from 0V → +5V, and from +5V → 0V, and through the research and statistics of the inventor of the present invention, the conventional driving (as shown in fig. 2) is adopted on the conventional Z-shaped panel (as shown in fig. 1), the driving process is as follows, and all power consumption occurs during the switching process of the voltage on the data line, for example: taking three data lines of Sn-1, Sn and Sn +1 as an example:
sn-1: r → B → R → G → R → B → R → G, the number of times of switching of the voltage polarity is: red sub-pixel: 16 times, 8 times for the blue sub-pixel, and 8 times for the green sub-pixel;
sn: r → G → B → G → R → G → B → G → R → G → B → G, the number of times of switching of the voltage polarity is: red sub-pixel 8 times, blue sub-pixel 8 times and green sub-pixel 16 times;
sn + 1: b → G → R → B → B → G → R → B, the number of times of switching the voltage polarity is: the red sub-pixel 8 times, the blue sub-pixel 8 times, and the green sub-pixel 8 times.
As shown in fig. 3 and fig. 6, taking the array substrate including 1080 data lines as an example, of course, fig. 3 only illustrates a part of the 1080 data lines, when the array substrate shown in fig. 3 is used to display a pure color image, the corresponding timing diagram is as shown in fig. 6 (partial timing sequence), the Dummy phase of the clock signal in fig. 6 is a pre-start phase, the CLK signals are turned on one by one, the corresponding gate lines are turned on alternately, taking the example of displaying a red image, assuming that the data voltage is +5V, the common voltage on the common electrode line 02 is 0V, and when the CLK1 is turned on, the gate line G1 in the first row is turned on, and the data line S1 needs to output +5V to the red subpixel R on the left side; when CLK2 is turned on, the third row gate line G3 is turned on, and the data line S1 needs to output +5V to the left red subpixel R; when CLK3 is turned on, the gate line G5 in the fifth row is turned on, and the data line S1 needs to output +5V to the red subpixel R on the left side; and so on. Therefore, the data line S1 continuously outputs a constant voltage of +5V for one frame time, thereby preventing the output voltage from changing repeatedly, reducing the power consumption of the data driving circuit, and effectively reducing the overall power consumption. Through the research and statistics of the inventor of the present invention, when the timing sequence of fig. 6 is used for driving fig. 3, that is, after new driving is used, the following driving effect is formed, wherein the number of voltage switching times on one data line is reduced to 1/4 or 1/2 of the number of voltage switching times on the data line shown in fig. 1:
sn-1: 1R → 3R → 5R → 7R → 2B → 4B → 6B → 8B → 9R → 11R → 13R → 15R → 10B → 12B → 14B → 16B, the number of voltage polarity switching times is: red sub-pixel 4 times, blue sub-pixel 4 times, green sub-pixel 0 times;
sn: 1R → 3R → 5R → 7R → 2G → 4G → 6G → 8G → 9R → 11R → 13R → 15R → 10G → 12G → 14G → 16G, the number of times of switching of the voltage polarity is: red sub-pixel 4 times, blue sub-pixel 0 times, green sub-pixel 4 times;
sn + 1: 1B → 3B → 5B → 7B → 2G → 4G → 6G → 8G → 9B → 11B → 13B → 15B → 10G → 12G → 14G → 16G, the number of times of switching of the voltage polarity is: the red sub-pixel 0 times, the blue sub-pixel 4 times, and the green sub-pixel 4 times.
In summary, it is found by comparing fig. 1 and fig. 3 that the power consumption of the array substrate provided by the embodiment of the invention is significantly improved when the array substrate is driven to display a pure color picture, wherein the power consumption of the red sub-pixel is reduced to 1/4, the power consumption of the blue sub-pixel is reduced to 1/3, and the power consumption of the green sub-pixel is reduced to 1/4.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the array substrate provided by the embodiment of the invention. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The principle of the display device to solve the problem is similar to the array substrate, so the implementation of the display device can be referred to the implementation of the array substrate, and repeated details are not repeated herein.
According to the array substrate and the display device provided by the embodiment of the invention, at least two rows of data lines which are correspondingly and electrically connected with the same polarity of the sub-pixels are electrically connected with the same bonding pad positioned in the non-display area, so that the bridging positions of the sub-pixels in different rows are arranged in the non-display area, on one hand, the aperture opening ratio of the pixels can be improved, the display brightness is improved, and on the other hand, the problem that the display picture is poor due to the coupling of the bridging of the data lines and the pixels to the pixels in the display area in the prior art can be avoided; in addition, when the array substrate provided by the invention displays a pure color picture, the same data line can output constant output voltage, and the power consumption when the pure color picture is displayed is effectively reduced.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. The array substrate is characterized by comprising a display area and a non-display area surrounding the display area; the display area includes: the pixel structure comprises a plurality of grid lines and a plurality of data lines, wherein the grid lines and the data lines are vertically crossed to define a plurality of pixel units distributed in an array; the pixel unit comprises a plurality of sub-pixels with different colors, and the colors of the sub-pixels in the same column are the same; the sub-pixels in the same row are correspondingly and electrically connected with the two grid lines, and the two grid lines correspondingly and electrically connected with the sub-pixels in the same row are positioned at two sides of the sub-pixels; each row of the sub-pixels is electrically connected with the same data line, and two adjacent rows of the sub-pixels are correspondingly electrically connected with different data lines;
the polarities of the sub-pixels in the same column are the same, and the polarities of the sub-pixels in the same row are not completely the same;
the non-display area comprises a driving chip, the driving chip is provided with a plurality of bonding pads, and at least two rows of data lines which are electrically connected with the same sub-pixels in the same polarity correspondingly are electrically connected with the same bonding pad.
2. The array substrate of claim 1, wherein the non-display area further comprises a plurality of cross-over wires, and the data lines correspondingly and electrically connected with the sub-pixels with the same polarity in at least two columns are electrically connected with the same bonding pad through the same cross-over wire.
3. The array substrate of claim 2, wherein two columns of data lines electrically connected with the same polarity of the sub-pixels are electrically connected with the same bonding pad through the same jumper wire.
4. The array substrate of claim 3, wherein the pixel unit comprises sub-pixels with three different colors, and each sub-pixel in a same row is periodically arranged according to the three colors.
5. The array substrate of claim 4, wherein two columns of the subpixels corresponding to two of the data lines electrically connected to the same pad have different colors, the subpixels corresponding to the data lines electrically connected to adjacent pads have opposite polarities, and the subpixels in the same row corresponding to the two data lines electrically connected to the same pad are electrically connected to different gate lines.
6. The array substrate of claim 5, wherein a column of the sub-pixels with different colors is arranged between two columns of the sub-pixels corresponding to two data lines electrically connected with the same bonding pad.
7. The array substrate of claim 4, wherein two columns of the sub-pixels corresponding to two data lines electrically connected with the same bonding pad have the same color, and two rows of the sub-pixels corresponding to two data lines electrically connected with the same bonding pad are electrically connected with different gate lines.
8. The array substrate of claim 7, wherein two columns of the sub-pixels with different colors are arranged between two columns of the sub-pixels corresponding to two data lines electrically connected with the same bonding pad.
9. The array substrate of claim 7, wherein five rows of the sub-pixels with different colors are arranged between two rows of the sub-pixels corresponding to two data lines electrically connected with the same bonding pad.
10. A display device comprising the array substrate according to any one of claims 1 to 9.
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