KR102076839B1 - Liquid crystal display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, wherein vertical lines and horizontal lines intersecting each other, pixels arranged in a matrix and including thin film transistors, a common electrode commonly connected to the pixels, and a center of the display panel. It includes a display panel including a horizontal common line formed across. The horizontal lines include horizontal gate lines supplied with a gate voltage. The vertical lines include vertical data lines to which a data voltage is supplied. The horizontal gate lines have a vertically symmetrical structure that is divided into both sides and merges under the vertical data lines with a pixel contact hole connecting the pixel electrode of the pixel and the thin film transistor interposed therebetween.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a liquid crystal display device.

Flat display devices include Liquid Crystal Display Devices (LCDs), Plasma Display Panels (PDPs), Organic Light Emitting Display Devices (OLEDs), Electrophoretic Display Devices: EPD) and the like. The liquid crystal display displays an image by controlling an electric field applied to liquid crystal molecules according to the data voltage. Active matrix type liquid crystal display devices are widely used in almost all display devices, from small mobile devices to large televisions, due to the low price and high performance due to the development of process technology and driving technology.

Manufacturers of flat panel displays have made various attempts to implement narrow bezels. Narrow bezel technology can reduce the size of the bezel in which an image is not displayed at the edge of the display panel to increase the size of an effective screen on which an image is displayed on the same sized display panel. In general, gate drive integrated circuits (ICs) are disposed at left and right edges of the display panel. Accordingly, the left and right edges of the display panel should have a region to which the gate drive IC is bonded and a gate link region connecting the gate drive IC to the horizontal gate lines of the pixel array. Due to the structural problem of such a flat panel display device, it is difficult to implement a narrow bezel.

The flat panel display may include a transparent electrode which is connected to the pixels of the display screen in common to form a wide film. Indium Tin Oxide (ITO) is the most widely used transparent electrode. A pair of sustain electrodes to which a sustain voltage is alternately applied in a common electrode and a pixel electrode supplied with a common voltage Vcom in an LCD, an OLED, and a plasma display panel in an LCD. And the like are formed of transparent electrodes. The common electrode of the liquid crystal display (LCD) or the sustain electrode pair of the plasma display panel (PDP) are connected to a plurality of pixels in common, thereby increasing the area thereof.

Since the transparent electrode material has a relatively high resistivity, when the screen of the display panel is enlarged, a voltage drop may occur, which may cause luminance uniformity between pixels. Since the resistance of the transparent electrode increases in proportion to the area of the transparent electrode, the larger the display panel, the larger the resistance.

As the display panel grows, a method of compensating for the high specific resistance of the transparent electrode material by using a highly conductive metal to contact the transparent electrode is used. However, since most of the highly conductive metal is an opaque metal, the aperture ratio of the pixels is reduced. The highly conductive metal may be connected to the transparent electrode material at every display line of the pixel array. As the pixels per inch (PPI) of the display panel increase, the pixel size decreases. Therefore, when the opaque metal is contacted with the transparent electrode on every display line of the pixel array, the aperture ratio of the pixel becomes smaller.

The present invention provides a liquid crystal display device capable of minimizing bezel width, widening aperture ratio of pixels, and wide viewing angle.

According to an exemplary embodiment of the present invention, a liquid crystal display includes vertical lines and horizontal lines intersecting with each other, pixels arranged in a matrix and including thin film transistors, a common electrode commonly connected to the pixels, and formed across a center of the display panel. And a display panel including horizontal common lines.

The horizontal lines include horizontal gate lines supplied with a gate voltage. The vertical lines include vertical data lines to which a data voltage is supplied.

The horizontal gate lines have a vertically symmetrical structure that is divided into both sides and merges under the vertical data lines with a pixel contact hole connecting the pixel electrode of the pixel and the thin film transistor interposed therebetween.

According to the present invention, data lines and gate lines may be vertically formed to minimize the width of the left and right bezels of the display panel, and horizontal common lines may be formed at the center of the display panel to increase the aperture ratio of the pixels in the LCD. Further, the present invention can widen the viewing angle of the liquid crystal display by forming horizontal gate lines in a vertically symmetrical structure in each of the upper half and the lower half of the pixel array separated by the horizontal common line.

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.
2 is a diagram illustrating a first embodiment of a display panel driving circuit.
FIG. 3 is an enlarged view of the COF shown in FIG. 2.
4 illustrates a second embodiment of a display panel driver circuit.
FIG. 5 is an equivalent circuit diagram showing a portion of the pixel array shown in FIG. 1.
6 is a waveform diagram illustrating an example of a data voltage and a gate pulse applied to the pixel array of FIG. 5.
FIG. 7 is an equivalent circuit diagram illustrating pixels formed in a center of a display panel and a part of a horizontal common line.
FIG. 8 is a plan view illustrating two pixels vertically neighboring the center of the display panel and a horizontal common line across the pixels.
9 illustrates an example of viewing the display panel at an upper viewing angle and a lower viewing angle.
FIG. 10 is a cross-sectional view illustrating a cross-sectional structure of horizontal gate lines separated along a line "I-I '" and a line "II-II'" in FIG. 8 with a horizontal common line interposed therebetween.
FIG. 11 is a cross-sectional view illustrating a cross-sectional structure of a central portion of a display panel in which horizontal common lines are cut along lines "III-III '" and "IV-IV'" in FIG. 12.
12 is a plan view illustrating horizontal gate lines according to an exemplary embodiment of the present invention.
FIG. 13 is a cross-sectional view illustrating a cross-sectional structure of horizontal gate lines taken along a line "V-V '" and a line "VI-VI'" in FIG. 12.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The names of the components used in the following description are selected in consideration of the ease of preparation of the specification, and may be different from the names of the actual products.

1 to 4, the liquid crystal display of the present invention includes a display panel PNL, a display panel driving circuit 10, a timing controller TCON 12, and the like.

The display panel PNL may be implemented in a liquid crystal mode having any known structure, such as twisted nematic (TN) mode, vertical alignment (VA) mode, in plane switching (IPS) mode, and fringe field switching (FFS).

The display panel PNL includes an upper substrate and a lower substrate facing each other with the liquid crystal layer interposed therebetween. In the display panel PNL, image data is displayed on the pixel array PIXR in which pixels are arranged in a matrix form. The pixel array includes a thin film transistor (TFT) array formed on the lower substrate and a color filter array formed on the upper substrate. The bezel BZ outside the pixel array PIXR is a non-display area.

The TFT array includes vertical lines and horizontal lines. The vertical lines are formed along the vertical direction (y-axis direction) of the display panel PNL. The horizontal lines are formed along the horizontal direction (x-axis direction) of the display panel PNL to be perpendicular to the vertical lines. The vertical lines and the horizontal lines may be formed of an opaque metal having high conductivity. The vertical lines include vertical data lines VD, vertical gate lines VG, and vertical common lines VC. Data voltages are supplied to the vertical data lines VD, and gate pulses synchronized with the data voltages are supplied to the vertical gate lines VG. The common voltage Vcom is supplied to the vertical common lines VC from a power supply circuit (not shown).

The horizontal lines include horizontal gate lines HG that receive gate pulses through the vertical gate lines VG, and a horizontal common line HC. The horizontal gate lines HG are connected to the vertical gate lines VG to receive gate pulses through the vertical gate lines VG. The horizontal gate lines HG may be connected to the vertical gate lines VG at the bezel BZ on the left or right side of the display panel PNL as shown in FIG. 2.

The common voltage Vcom is supplied to the horizontal common line HC from a power supply circuit (not shown). The horizontal common line HC may not be formed at every line of the display panel PNL, but may be formed to cross horizontally between pixels in the central horizontal line of the display panel PNL. The horizontal gate lines HG are not formed at the position of the horizontal common line, and the upper half of the pixel array and the lower half of the pixel array divided with the horizontal common line HC interposed therebetween as shown in FIGS. 7, 8, and 12. Is formed.

In the TFT array, TFTs are formed at the intersections of the vertical data lines VD and the horizontal gate lines HG. The TFT supplies the data voltage from the vertical data line VD to the pixel electrode 1 of the liquid crystal cell Clc in response to the gate pulse from the horizontal gate line HG. Each of the liquid crystal cells Clc is driven by the voltage difference between the pixel electrode 1 charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied. The common voltage Vcom is applied to the common electrode 2 of all the pixels through the vertical common lines VC. The common electrode 2 of the pixels is connected to the vertical common lines VC. In addition, the common electrode 2 of the pixels is connected to the horizontal common line HC to receive the common voltage Vcom through the horizontal common line HC. The common electrode 2 and the pixel electrode 1 are formed of a transparent electrode material such as ITO. The storage capacitor Cst is connected to the pixel electrode 1 of the liquid crystal cell Clc to maintain the voltage of the liquid crystal cell Clc for one frame period. The color filter array includes a color filter and a black matrix. Polarizing plates are attached to each of the upper and lower glass substrates of the display panel PNL, and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

The display panel driver circuit 10 writes data input from the timing controller 12 to pixels of the display panel. The display panel driver circuit 10 includes a source drive IC (SIC) for outputting a data voltage and a gate drive IC (GIC) for outputting a gate pulse.

The source drive IC (SIC) and the gate drive IC (GIC) may be mounted together on a flexible circuit board such as a chip on film (COF) as shown in FIG. 3. The input terminal of the COF is bonded to a printed circuit board (PCB), and the output terminal of the COF is bonded to a TFT array substrate of the display panel PNL. In the COF, an insulating layer is provided between the wires connected to the source drive IC (SIC) (FIG. 3, dotted line) and the wires connected to the gate drive IC (GIC) (FIG. 3, solid line) so as to be electrically separated. Is formed. The source drive IC SIC and the gate drive IC GIC may be separately disposed on the upper bezel and the lower bezel of the display panel PNL as shown in FIG. 4. The source drive IC (SIC) and the gate drive IC (GIC) may be directly bonded on the substrate of the display panel PNL by a chip on glass (COG) process. In this case, the source drive IC SIC may be bonded to the substrate in the lower bezel outside the lower side of the pixel array region PIXR as shown in FIG. 4. The gate drive IC GIC may be bonded to the substrate in an upper bezel region disposed outside the pixel array region PIXR.

The source drive IC (SIC) samples the digital video data of the input image under the control of the timing controller 12 and then latches and converts the digital video data into data of a parallel data system. The source drive IC (SIC) generates a data voltage by converting the digital video data into an analog gamma compensation voltage using a digital to analog converter (ADC) under the control of the timing controller 12. Supply to vertical data lines VD. The gate drive IC GIC sequentially supplies a gate pulse (or scan pulse) synchronized with the data voltage from the first vertical gate line to the nth vertical gate line under the control of the timing controller 12.

The source drive IC SIC and the gate drive IC GIC are disposed above or below the display panel PNL. As a result, the gate drive IC GIC does not need to be bonded or embedded in the left and right bezel regions of the display panel PNL, and the gate link line connects the horizontal gate lines HG and the gate drive IC GIC. There is no need. Therefore, the widths of the display panel PNL of the present invention are reduced by removing the junction region and the gate link region of the gate drive IC GIC from the left and right bezels BZ.

Gate contact portions GC connected to the vertical gate lines VG and the horizontal gate lines HG are connected to the left bezel BZ or the right bezel BZ of the display panel PNL of the present invention. Is formed. Even though the left bezel BS or the right bezel BZ of the display panel PNL includes the gate contact parts, the width of the left bezel BS or the right bezel BZ is 1.5 mm or less and is equal to or greater than the horizontal length of the gate contact part GC. Accordingly, the present invention can minimize the left bezel BZ and the right bezel BZ of the display panel.

The timing controller 12 transmits digital video data of the input image received from the host system 14 to the source drive ICs SIC. The timing controller 12 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable (DE), and a main clock CLK from the host system 14. These timing signals are synchronized with the digital video data of the input image. The timing controller 12 uses a timing signal Vsync, Hsync, DE, and CLK to control a source timing control signal for controlling the operation timing of the source drive ICs SIC, and an operation timing of the gate drive ICs GIC. Generates a gate timing control signal for controlling the signal.

The host system 14 may be implemented as one of a television system, a set top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. have. The host system 14 converts the digital video data RGB of the input image into a format suitable for the display panel PNL. The host system 14 transmits timing signals Vsync, Hsync, DE, and MCLK together with the digital video data of the input image to the timing controller 12.

The pixel array may be implemented in various structures. For example, the pixel array may be implemented as shown in FIG. 5.

Referring to FIG. 5, the pixels may include an R (red) sub pixel, a G (green) sub pixel, and a B (blue) sub pixel.

The pixels arranged on the odd horizontal lines include the TFT T1 disposed between the left vertical data lines VD1 to VD5 and the horizontal gate lines HG1 to HG4, and the pixel electrode PIX1 connected to the TFT T1. It includes. The pixels arranged on the even-numbered horizontal line include the TFT T2 disposed between the right vertical data lines VD2 to VD6 and the horizontal gate lines HG1 to HG4, and the pixel electrode PIX2 connected to the TFT T2. It includes.

The vertical gate lines VG1 to VG3 are connected to the horizontal gate lines HG1 to HG3 through gate contact portions GC formed in the left or right bezel BZ of the display panel PNL. The vertical gate lines VG1 to VG3 are patterned in an L shape along the vertical data lines VD2, VD4 and VD5 and the horizontal gate lines HG1 to HG3 to form horizontal gate lines through the gate contact parts GC. To HG1 to HG3 1: 1. For example, the first vertical gate lines VG1 are patterned in an L shape bent along the second vertical data line VD2 and the first horizontal gate line HG1 to form a gate contact portion GC in the bezel BZ. ) Is connected to the first horizontal gate line HG1. The second vertical gate lines VG2 are patterned in an L shape bent along the fourth vertical data line VD4 and the second horizontal gate line HG2 to be formed through the gate contact part GC in the bezel BZ. 2 is connected to the horizontal gate line HG2. The third vertical gate line VG3 is patterned in an L shape bent along the sixth data line D4 and the third horizontal gate line HG3 to form a third horizontal gate line through the gate contact portion GC in the bezel BZ. It is connected to the gate line HG1. The gate pulse is sequentially applied to the vertical gate lines VG1 to VG3 in the order of the first vertical gate line VG1, the second vertical gate line VG2, and the third vertical gate line VG3.

The present invention overlaps the vertical gate lines VG1 to VG3 and the vertical common lines VC with the vertical data lines VD1 to VD6 and the horizontal gate lines HG1 to HG4 with an insulating layer therebetween. Therefore, in the present invention, the aperture ratio of the pixels does not decrease due to the vertical gate lines VG1 to VG3 and the vertical common lines VC. In FIG. 5, the vertical common lines VC, the common electrode, the storage capacitor, and the like are omitted.

The vertical gate lines VG1 to VG3 and the vertical common lines VC should not be short circuited with the vertical data lines VD1 to VD6 and the horizontal gate lines HG1 to HG4. To this end, the vertical gate lines VG1 to VG3 and the vertical common lines VC are formed in a separate metal pattern separated from the vertical data lines VD1 to VD6 and the horizontal gate lines HG1 to HG4. Can be. For example, the horizontal gate lines HG1 to HG4 are formed in the first metal pattern. The vertical data lines VD1 to VD6 are formed in a second metal pattern separated from the first metal pattern with the first insulating layer interposed therebetween. The vertical gate lines VG1 to VG3 and the vertical common lines VC are formed of a third metal pattern separated from the second metal pattern with the second insulating layer interposed therebetween.

The pixel array having the structure as shown in FIG. 5 allows the data voltages having the same polarity to be output to the vertical data lines VD for one frame period, thereby reducing power consumption and heat generation of the source drive IC SIC and improving dot inversion in the pixel array. The picture quality can be improved. For example, the positive data voltage is supplied to the odd vertical data lines VD1 and VD3 as shown in FIG. 6 during the Nth (N is a positive integer) frame period, and the negative data voltage is supplied during the Nth frame period. It is supplied to even-numbered vertical data lines VD2 and VD4. In the pixel array structure of FIG. 5, data voltages having different polarities are charged to upper and lower neighboring pixels, and data voltages of different polarities are charged to neighboring pixels to the left and right. Therefore, the source drive IC (SIC) is driven in the form of column inversion that outputs the data voltage of the same polarity for one frame period, and the pixel array charges the data voltage whose polarity is inverted by the dot inversion.

The pixel array structure is not limited to FIG. For example, the pixel array PIXR is disclosed in Korean Patent Application No. 10-2012-0138187 (Nov. 30, 2012), Korean Patent Application No. 10-2012-0155172 (Dec. 27, 2012), and Korean Patent Application No. 10-2012-0138918 ( 2012. 12. 03.) and the like can be applied to the pixel array proposed.

In order to increase the aperture ratio of the pixels, the horizontal common line HC is not formed at every display line in the display panel PNL, but only at boundaries between pixels formed at the center of the display panel PNL. The horizontal gate line HC is not formed at a boundary between the nth display line and the n + 1th display line where the horizontal common line HC is formed. Therefore, as shown in FIG. 7, the upper half of the pixel array disposed above the horizontal common line HC on the horizontal common line HC and the lower half of the pixel array disposed below the horizontal common line HC are arranged in the pixel structure. Can be different. For example, as illustrated in FIGS. 7 and 8, pixels disposed in the upper half of the pixel array are selected according to gate pulses from a horizontal gate line disposed above the pixels. On the other hand, the pixels disposed in the lower half of the pixel array are selected according to the gate pulses from the horizontal gate line disposed below the pixels.

7 and 8, an nth (n is a positive integer of 2 or more) display line #n and an n + 1th display line # n + 1 are formed at the center of the display panel PNL. When present, the horizontal common line HC is formed along the horizontal direction x at the boundary between the nth display line and the n + 1th display line. The horizontal gate line HG is not formed at a boundary between the nth display line and the n + 1th display line.

The upper half pixel structure of the pixel array is formed in the same structure as the pixels of the n-th and n-th display lines # n-1 and #n. The lower half pixel structure of the pixel array is formed in the same structure as the pixels of the n + 1 and n + 2th display lines # n + 1 and # n + 2. The lower half pixel structure is formed in a vertically symmetrical structure with respect to the pixel structure in which the upper half pixel structure is inverted by 180 ° in the horizontal direction (x).

An upper half structure of the pixel array will be described using n−1 and n-th display lines as examples. The pixels arranged on the n-th display line # n-1 include vertical data lines VD1 to VD5 formed on the left side of the pixels and an n-1 horizontal gate line HGn-1 formed on the pixels. TFTs (Tn-1) formed at intersections between them, and pixel electrodes (PIXn-1) connected to the TFTs (Tn-1). The TFT Tn-1 supplies the data voltage from the vertical data lines VD1 to VD5 to the pixel electrode PIXn-1 in response to the gate pulse from the n-1th horizontal gate line HGn-1. The pixels arranged on the nth display line #n are formed in the intersection portion between the vertical data lines VD2 to VD6 formed on the right side of the pixels and the nth horizontal gate line HGn formed on the pixels. Tn and the pixel electrode PIXn connected to the TFT Tn. The TFT Tn supplies the data voltage from the vertical data lines VD2 to VD6 to the pixel electrode PIXn in response to the gate pulse from the nth horizontal gate line HGn.

The pixels of the nth and nth + 1th display lines #n and # n + 1 are separated up and down with the horizontal common line HC interposed therebetween. The nth-1th display line #n is disposed above the nthth display line #n. The n + 2th display line # n + 2 is disposed below the n + 1th display line # n + 1.

The lower half structure of the pixel array is formed of a pixel structure in which the upper half pixels are inverted by 180 ° in the horizontal direction (x) and then inverted in a vertically symmetrical structure. The lower half structure of the pixel array will be described using n + 1 and n + 2 display lines as an example.

The pixels arranged on the n + 1th display line # n + 1 are vertical data lines VD1 to VD5 formed on the left side of the pixels and the n + 1 horizontal gate line HGn + 1 formed below the pixels. TFTs (Tn + 1) formed at intersections therebetween and pixel electrodes (PIXn + 1) connected to the TFTs (Tn + 1). The TFT Tn + 1 supplies the data voltage from the vertical data lines VD1 to VD5 to the pixel electrode PIXn + 1 in response to the gate pulse from the n + 1th horizontal gate line HGn + 1. The pixels arranged on the n + 2th display line # n + 2 are vertical data lines VD2 to VD6 formed on the right side of the pixels and an n + 2 horizontal gate line HGn + 2 formed below the pixels. TFTs (Tn + 2) formed at intersections between them, and pixel electrodes (PIXn + 2) connected to the TFTs (Tn + 2). The TFT (Tn + 2) supplies the data voltage from the vertical data lines VD2 to VD6 to the pixel electrode PIXn + 2 in response to the gate pulse from the n + 2th horizontal gate line HGn + 2.

Horizontal gate lines may be formed in different shapes in the upper half and the lower half of the pixel array as shown in FIG. 8. In this case, as shown in FIG. 9, when the display panel PNL is viewed from the upper viewing angle higher than the front or lower viewing angle lower than the front, the luminance difference may be seen in the upper half and the lower half of the pixel array. Can be. This is because the horizontal gate lines HGn and HGn + 1 are formed in the vertically asymmetrical structure with the pixel contact hole C1 interposed therebetween as shown in FIGS. 8 and 10.

FIG. 10 is a cross-sectional view illustrating a cross-sectional structure of horizontal gate lines separated along a line "I-I '" and a line "II-II'" in FIG. 8 with a horizontal common line interposed therebetween. FIG. 11 is a cross-sectional view illustrating a cross-sectional structure of a central portion of a display panel in which horizontal common lines are cut along lines "III-III '" and "IV-IV'" in FIG. 12.

10 to 11, the TFTs Tn and Tn + 1 are formed on the gate electrode GE on the substrate SUBS, the gate insulating film GI covering the gate electrode GE, and the gate insulating film GI. An active layer ACT, a source electrode SE formed on the active layer ACT, and a drain electrode DE are included. The active layer ACT is formed of a semiconductor. The first passivation layer Pas1 and the organic passivation layer PAC cover the TFTs. Second and third passivation layers Pas2 and Pas3 are stacked on the organic passivation layer PAC. The source electrode SE of the TFT is connected to the pixel electrodes PIXn and PIXn + 1 through the pixel contact hole C1 penetrating the insulating layers PAC, Pas2 and Pas3. The drain electrode DE is connected to the vertical data lines VD1 to VD4. The gate electrode GE and the horizontal gate lines HGn and HGn + 1 are formed of the first metal. The vertical data lines VD1 to VD4, the source electrode SE, and the drain electrode DE are formed of a second metal. The pixel electrodes PIXn and PIXn + 1 and the common electrode COM are formed of transparent electrodes. The common electrode COM is formed between the second passivation layer Pas2 and the third passivation layer Pas3. The vertical common line VC and the horizontal common line HC may be formed of a third metal formed on the organic passivation layer. The horizontal common line HC may be formed on the substrate SUBS with the first metal at the same time as the horizontal gate lines HGn and HGn + 1.

The horizontal gate line HG is not formed at the boundary between pixels in which the horizontal gate line HC is formed, as shown in FIG. 11. The transparent electrode pattern ITO1 contacts the horizontal common line HC through the contact hole C2 and contacts the common electrode COM through the other contact hole C3 to form the horizontal common line HC as the common electrode ( COM).

The n-th horizontal gate line HGn includes an opening 81a from which metal is removed below the pixel contact hole C1 as shown in FIGS. 8 and 10. On the contrary, the n + 1th horizontal gate line HGn + 1 includes an opening 81b from which metal is removed from the pixel contact hole C1. The nth horizontal gate line HGn and the n + 1th horizontal gate line HGn + 1 have a vertically asymmetric structure. The opening 81a of the nth horizontal gate line HGn is formed below the pixel contact hole C1, while the opening 81b of the n + 1th horizontal gate line HGn + 1 is the pixel contact hole C1. Is formed on top of). When the display panel PNL is viewed from the lower viewing angle due to the horizontal gate lines HGn and HGn + 1 as shown in FIGS. 8 and 10, the upper half of the pixel array displays the same gray level data in the entire pixel array. Looks brighter than the bottom half of the array. This is because when the viewing panel PNL is viewed from the lower viewing angle, the opening of the pixel appears wide due to the opening 81a of the horizontal gate line HGn in the upper half of the pixel array, while the horizontal gate line HGn in the lower half of the pixel array. This is because the opening of the pixel appears small due to the metal of +1).

When the display panel PNL is viewed at an image viewing angle due to the horizontal gate lines HGn and HGn + 1 as shown in FIG. 8, when the same gray level data is displayed on the entire pixel array, the lower half of the pixel array is the upper half of the pixel array. Looks brighter than This is because when the display panel PNL is viewed from the image viewing angle, the opening of the pixel appears wide due to the opening 81b of the horizontal gate line HGn + 1 in the lower half of the pixel array, while the horizontal gate line is located in the upper half of the pixel array. This is because the opening of the pixel appears small due to the metal of (HGn). Accordingly, when the horizontal gate lines having the vertically asymmetric structure as shown in FIGS. 8 and 10 are formed in opposite shapes to the upper half and the lower half of the pixel array, the viewing angle of the display panel may be narrowed near the front viewing angle.

According to the present invention, when the pixel structure is different in the upper half and the lower half of the pixel array with the horizontal common line HC interposed therebetween, all horizontal gate lines in the pixel array are moved up and down around the pixel contact hole C1 as shown in FIG. 7. It is formed into a symmetrical structure.

12 is a plan view illustrating horizontal gate lines according to an exemplary embodiment of the present invention. FIG. 13 is a cross-sectional view illustrating the cross-sectional structure of horizontal gate lines taken along the line "V-V '" and the line "VI-VI'" in FIG. 12.

7, 12, and 13, the pixel array is divided into an upper half and a lower half with a horizontal common line HC interposed therebetween. In the pixel array of FIGS. 12 and 13, the TFT cross-sectional structure of the pixel and the cross-sectional structure of the horizontal common line HC are the same as those of FIG.

The horizontal gate lines HGn and HGn + 1 have a vertically symmetrical structure with the pixel contact hole C1 interposed so that the luminance of the entire pixel array is uniform at the vertical viewing angle of the display panel PNL. For example, the n-th horizontal gate lines HGn formed at the upper half of the pixel array are separated on both sides with the pixel contact hole C1 interposed therebetween, and are merged into one under the vertical data lines VD1 to VD4. Is patterned. Similarly, the n + 1th horizontal gate lines HGn + 1 formed in the upper half of the pixel array are separated on both sides with the pixel contact hole C1 interposed therebetween, and merged into one under the vertical data lines VD1 to VD4. Loss is patterned.

As shown in FIGS. 12 and 13, the horizontal gate lines HGn and HGn + 1 having a vertically symmetrical structure have pixels in the upper half and the lower half of the pixel array when the viewer views the display panel PNL at an upper viewing angle or a lower viewing angle. These aperture ratios are made the same. As a result, the present invention can increase the aperture ratio of the pixels by forming a horizontal common line HC only at the center of the display panel PNL and widen the viewing angle by minimizing the luminance difference between the upper half and the lower half of the pixel array in the upper and lower viewing angles.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the present invention should not be limited to the details described in the detailed description but should be defined by the claims.

PNL: Display panel 10: Display panel drive circuit
12: timing controller 14: host system
VD: vertical data line VG: vertical gate line
VC: vertical common line HG: horizontal gate line
HC: horizontal common line

Claims (4)

A display panel including vertical wirings and horizontal wirings crossing each other, pixels including thin film transistors arranged in a matrix form, a common electrode connected to the pixels in common, and a horizontal common line formed across the center thereof; and,
The horizontal lines include horizontal gate lines supplied with a gate voltage,
The vertical wires include vertical data lines to which a data voltage is supplied;
Each of the horizontal gate lines may be divided in both sides with respect to a vertical direction through which the vertical wiring runs, with the pixel contact hole connecting the pixel electrode of the pixel and the thin film transistor interposed therebetween and be joined under the vertical data lines. Liquid crystal display device characterized in that. The method of claim 1,
The vertical lines further include vertical gate lines supplied with a gate pulse, and vertical common lines supplied with a common voltage,
And the vertical gate lines and the horizontal gate lines are connected to each other. The method according to claim 1 or 2,
The pixel array of the display panel is divided into an upper half and a lower half divided by the horizontal common line.
And the horizontal gate lines formed on the upper half of the pixel array and the horizontal gate lines formed on the lower half of the pixel array each have a vertically symmetrical structure with the pixel contact hole therebetween. The method of claim 3, wherein
The horizontal gate lines,
An upper half of the pixel array and a lower half of the pixel array;
And not formed at the position of the horizontal common line.

Images