KR102107408B1 - Liquid crystal display device - Google Patents

Abstract

In the liquid crystal display of the present invention, vertical borders are formed between neighboring pixels in a horizontal direction, two data lines and one vertical gate line are alternately arranged on the vertical borders, and each of the vertical gate lines is A display panel connected to a horizontal gate line extending in a horizontal direction; A driving circuit that supplies a data voltage to the pixels through the data lines and a gate pulse to the pixels through the vertical gate lines; Each of the pixels arranged in the odd horizontal pixel line of the display panel is connected to the data line arranged closest to itself; Each of the pixels arranged on the superior horizontal pixel line of the display panel jumps to one data line or one vertical gate line disposed closest to itself in one direction, thereby neighboring the one data line or one vertical gate line. Is connected to another data line adjacent to.

Description

Liquid crystal display device {LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a liquid crystal display device having a reduced bezel width.

The display field has rapidly changed to a thin, light and large-area flat panel display device (FPD), which replaces a bulky cathode ray tube (CRT). The flat panel display includes a liquid crystal display device (LCD), a plasma display panel (PDP), an organic light emitting display device (OLED), and an electrophoretic display device. : EPD). Among them, the liquid crystal display device controls the electric field applied to the liquid crystal molecules according to the data voltage to display an image. 2. Description of the Related Art Active matrix type liquid crystal display (LCD) devices are most widely used as they are applied to almost all display devices, from small mobile devices to large TVs, due to the lower price and higher performance thanks to the development of process technology and driving technology.

Manufacturers of liquid crystal display devices are making various attempts to implement a narrow bezel. The narrow bezel technology is a technique of minimizing a bezel in which an image is not displayed at the edge of the display panel in order to relatively increase the size of an effective screen on which an image is displayed on the display panel of the same size. The narrow bezel technology has a limitation in reducing the bezel width due to the limitation of the fine processing technology. Therefore, it is necessary to develop a narrow bezel technology that can overcome the process technology.

Accordingly, an object of the present invention is to provide a liquid crystal display device to minimize the bezel width.

In order to achieve the above object, in the liquid crystal display device of the present invention, vertical borders are formed between adjacent pixels in a horizontal direction, and two data lines and one vertical gate line are alternately arranged on the vertical borders. Each of the vertical gate lines includes a display panel connected to a horizontal gate line extending in a horizontal direction; A driving circuit that supplies a data voltage to the pixels through the data lines and a gate pulse to the pixels through the vertical gate lines; Each of the pixels arranged in the odd horizontal pixel line of the display panel is connected to the data line arranged closest to itself; Each of the pixels arranged on the superior horizontal pixel line of the display panel jumps to one data line or one vertical gate line disposed closest to itself in one direction, thereby neighboring the one data line or one vertical gate line. Is connected to another data line adjacent to.

In the odd horizontal pixel line of the display panel, a first pixel and a second pixel are disposed between the first data line and the second data line included in the data line pairs, and included in the data line pairs. A third pixel and a fourth pixel are disposed with the third data line and the fourth data line interposed therebetween, and in the even-th horizontal pixel line of the display panel, the first and second data lines are interposed. A fifth pixel and a sixth pixel are disposed, a seventh pixel and an eighth pixel are disposed with the third data line and the fourth data line interposed therebetween, and the second pixel and the third pixel are disposed. When the vertical gate line is disposed between the sixth pixel and the seventh pixel, the first pixel is connected to the first data line through a first TFT, and the second pixel is connected to the first through a second TFT. 2 connected to the data line, Three pixels are connected to the third data line through a third TFT, the fifth pixel is connected to the second data line through a fifth TFT, and the sixth pixel is the third data through a sixth TFT. Line, and the seventh pixel is connected to the fourth data line through a seventh TFT.

The pixel electrode of the fifth pixel is connected to the fifth TFT across the first data line through a first jumping wiring formed on the first data line with an insulating film interposed therebetween; The pixel electrode of the sixth pixel is connected to the sixth TFT across the vertical gate line through a second jumping wire formed on the vertical gate line with an insulating film interposed therebetween; The pixel electrode of the seventh pixel is connected to the seventh TFT across the third data line through a third jumping wire formed on the third data line with an insulating film interposed therebetween.

The driving circuit supplies data voltages of a first polarity to the first and third data lines during an Nth frame (where N is a positive integer), and a data voltage of a second polarity opposite to the first polarity. To the second and fourth data lines; During the N + 1 frame, data voltages of the second polarity are supplied to the first and third data lines, and data voltages of the first polarity are supplied to the second and fourth data lines.

The first jumping wiring is integrated with the pixel electrode of the fifth pixel on the same layer as the pixel electrode of the fifth pixel, and the second jumping wiring is of the sixth pixel on the same layer as the pixel electrode of the sixth pixel. It is integrated with the pixel electrode, and the third jumping wiring is integrated with the pixel electrode of the seventh pixel on the same layer as the pixel electrode of the seventh pixel.

The width of each of the data lines is smaller than the width of each of the vertical gate lines.

In the liquid crystal display device of the present invention, it is possible to narrow the bezel width of the display panel to a minimum by arranging two data lines at the first vertical boundary and one vertical gate line at the second vertical boundary. Since the separation distance between the data line and the vertical gate line can be widened by the width occupied by the pixel electrode of 1 pixel, the signal interference problem due to parasitic capacitance between the vertical gate line and the data line can be solved. In addition, the present invention not only improves the aperture ratio by narrowing the width of the data lines to that of the vertical gate line, but also reduces the gate load, thereby minimizing the signal deviation of the gate pulse for each display position.

Furthermore, the present invention connects the pixels in different forms in the odd horizontal pixel line and the even horizontal pixel line, so that the polarity change of the display panel is changed to dot inversion using a source drive IC driven by a column inversion method. By controlling, it is possible not only to improve the charging characteristics of the panel, but also to reduce power consumption and heat generation of the source drive IC.

1 and 2 are views showing a liquid crystal display device according to an embodiment of the present invention.
FIG. 3 is an enlarged view of the COF shown in FIG. 2.
4 is an equivalent circuit diagram showing a portion of a pixel array according to an embodiment of the present invention.
FIG. 5 is a view showing a polarity change of data voltages supplied to the data lines of FIG. 4.
6 is an equivalent circuit diagram showing a portion of a pixel array contrasted with FIG. 4 for a comparative example.
7 is a plan view showing a part of FIG. 6 in detail.
8 is a cross-sectional view of FIG. 7 taken along line A-A '.
9 is a view showing a luminance difference between pixels due to signal interference caused by parasitic capacitance between a vertical gate line and a data line.
10A and 10B are equivalent circuit diagrams and pixel array plan views for further explaining a connection configuration between a data line and a pixel.
11A-11C are cross-sectional views of portions of FIG. 10B.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Throughout the specification, the same reference numerals refer to substantially the same components. In the following description, when it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description is omitted.

The names of the components used in the following description are selected in consideration of the ease of writing the specification, and may be different from the names of actual products.

1 to 3, the liquid crystal display of the present invention includes a display panel (PNL), a drive IC (Integrated Circuit, DIC) 10, a timing controller (Timing Controller, TCON) 12, and the like.

The liquid crystal display device of the present invention can be implemented in all known liquid crystal modes such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, and FFS (Fringe Field Switching). In addition, the liquid crystal display device of the present invention can be implemented in any form, such as a transmissive liquid crystal display device, a transflective liquid crystal display device, a reflective liquid crystal display device.

The display panel PNL includes an upper substrate and a lower substrate facing each other with the liquid crystal cell Clc interposed therebetween. In the display panel PNL, image data is displayed in a pixel array area in which pixels are arranged in a matrix form. The pixel array includes a TFT array formed on the lower substrate and a color filter array formed on the upper substrate. Using a color filter on TFT (COT) process, a color filter can be formed on the TFT array of the lower substrate.

The TFT array includes vertical wirings and horizontal wirings. The vertical wires are formed along the vertical direction (FIG. 1, y-axis direction) of the display panel PNL. The horizontal wires are formed along the horizontal direction (FIG. 1, x-axis direction) of the display panel PNL and are orthogonal to the vertical wires. The vertical wires include data lines DL and vertical gate lines VGL. The horizontal lines include horizontal gate lines HGL receiving a gate pulse through the vertical gate lines VGL. The horizontal gate lines HGL are connected 1: 1 with the vertical gate lines VGL through contact holes CONT1 as shown in FIG. 4 to receive a gate pulse through the vertical gate lines VGL.

In the TFT array, TFTs (Thin Film Transistors) are formed at each intersection of the data lines DL and the horizontal gate lines HGL. The TFT supplies the data voltage from the vertical data line DL to the pixel electrode 1 of the liquid crystal cell Clc in response to the gate pulse from the horizontal gate line HGL. Each of the liquid crystal cells Clc, that is, the pixels is driven by a voltage difference between the pixel electrode 1 charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied. The common voltage Vcom is supplied to the common electrode 2 formed in the pixels through the common voltage supply line. A storage capacitor Cst that maintains the voltage of the liquid crystal cell for one frame period is connected to the liquid crystal cell Clc. The color filter array includes a color filter and a black matrix. A polarizing plate is attached to each of the upper and lower glass substrates of the display panel PNL, and an alignment layer is formed to set a pre-tilt angle of the liquid crystal.

The drive IC 10 is a driving circuit of a display panel including a source drive IC (SIC) and a gate drive IC (GIC). The source drive IC (SIC) and the gate drive IC (GIC) may be mounted together on a flexible circuit board such as a chip on film (COF) as shown in FIG. 3. The input terminal of the COF is bonded to the printed circuit board (PCB), and the output terminal of the COF is bonded to the lower substrate of the display panel PNL. In COF, an insulating layer is provided between the wirings connected to the source drive IC (SIC) (FIG. 3, dashed line) and the wirings connected to the gate drive IC (GIC) (FIG. 3, solid line) to be electrically separated. It is formed.

The source drive IC (SIC) samples the digital video data of the input image under the control of the timing controller 12 and then latches it to convert it into data of a parallel data system. The source drive IC (SIC) converts digital video data into an analog gamma compensation voltage using a digital to analog converter (ADC) under the control of the timing controller 12 to generate a data voltage and generates the data voltage. It is supplied to the data lines DL. The gate drive IC (GIC) sequentially supplies a gate pulse (or scan pulse) synchronized with the data voltage from the first vertical gate line to the nth vertical gate line under the control of the timing controller 12.

All drive ICs DIC are formed on the COF connected to the top of the display panel PNL, and a gate pulse is applied to the horizontal gate lines HGL through the vertical gate lines HGL. Accordingly, the gate drive IC need not be bonded or embedded at the left edge and the right edge of the display panel PNL, and the horizontal gate lines HGL and the gate drive IC are disposed at the left and right edges of the display panel PNL. Connecting routing wires are not formed. As a result, the width of the bezels BZ on the left and right edges of the display panel and the bezels on the bottom edge can be minimized.

The timing controller 12 transmits digital video data of the input image received from the host system 14 to the source drive ICs SIC. The timing controller 12 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), and a main clock (CLK) from the host system 14. These timing signals are synchronized with the digital video data of the input image. The timing controller 12 uses the timing signals Vsync, Hsync, DE, and CLK to control the operation timing of the source drive ICs SIC and the operation timing of the gate drive ICs GIC. Generates a gate timing control signal to control.

The host system 14 may be implemented as any one of a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. have. The host system 14 converts digital video data (RGB) of the input image into a format suitable for the display panel PNL. The host system 14 transmits timing signals Vsync, Hsync, DE, and MCLK together with digital video data of the input image to the timing controller 12.

4 is an equivalent circuit diagram showing a portion of a pixel array according to an embodiment of the present invention. 5 is a view showing a change in polarity of the data voltage supplied to the data lines of FIG. 4. 4 and 5, 'D1 to D6' denote data lines, 'VG1 to VG4' denote vertical gate lines, and 'HG1 to HG4' denote horizontal gate lines.

Referring to FIG. 4, one vertical gate line VG1 to VG4 is formed or two data lines D1 to D6 are formed between neighboring pixels in a horizontal direction. Vertical boundaries CB1 and CB2 are formed between pixels neighboring in the horizontal direction, and two data lines D1 / D2, D3 / D4 extending in the vertical direction are formed in the vertical boundaries CB1 and CB2. D5 / D6) and one vertical gate line VG1 to VG4 are alternately arranged. For example, when four pixels are arranged side by side in each horizontal pixel line, the first between the first pixel P1 and the second pixel P2 and between the fifth pixel P5 and the sixth pixel P6. Two data lines D1 and D2 are formed on the vertical boundary CB1. On the other hand, one vertical gate line (CB2) between the left and right neighboring second pixels P2 and the third pixel P3 and the sixth pixel P6 and the seventh pixel P7 has a vertical gate line ( VG2) is formed. In order to increase the aperture ratio of the pixels, the width of each of the data lines D1 to D6 is preferably set smaller than the width of the vertical gate lines VG1 to VG4. The vertical gate lines VG1 to VG4 are connected 1: 1 to the horizontal gate lines HG1 to HG4 through the first contact holes CONT1. TFTs are not connected to the vertical gate lines VG1 to VG4.

Meanwhile, in the present invention, each of the pixels P1 to P4 arranged in the odd horizontal pixel line HL_O is connected to the data line disposed closest to itself among the data lines D1 to D6. On the other hand, each of the pixels P5 to P8 arranged in the even-th horizontal pixel line HL_E jumps one data line or one vertical gate line disposed closest to itself in one direction, thereby neighboring the one data line. Or another data line adjacent to the one vertical gate line.

In this way, the present invention uses a source drive IC (SIC) driven by a column inversion method as shown in FIG. 5 by connecting pixels in different forms in the odd horizontal pixel line HL_O and the superior horizontal pixel line HL_E. By doing so, the polarity change of the display panel can be controlled in the form of dot inversion. Referring to FIG. 5, the source drive IC SIC supplies the data voltage of the first polarity (+) to the odd-numbered data lines D1, D3, and D5 during the Nth frame (N is a positive integer). In addition, the data voltage of the second polarity (-) opposite thereto may be supplied to the superior data lines D2, D4, and D6. In addition, the source drive IC SIC supplies the data voltage of the second polarity (-) to the odd-numbered data lines D1, D3, and D5 during the N + 1 frame, and the first polarity (+ ) Can supply the data voltage to the even-numbered data lines D2, D4, and D6. To control the polarity of the display panel with dot inversion, the polarity of the data voltage output from each output channel of the source drive IC (SIC) is changed once per frame. If the pixel connection configuration as shown in FIG. 4 is not employed, the polarity of the data voltage output from each output channel of the source drive IC (SIC) in order to control the polarity of the display panel with dot inversion is 1 horizontal period (1 Frame period / vertical resolution). According to the present invention, since the number of data transitions for each output channel of the source drive IC (SIC) can be set once per frame, the power consumption of the source drive IC (SIC) is reduced accordingly.

Referring to Figure 4, the pixel connection configuration of the present invention will be described in detail as follows.

For example, in the odd horizontal pixel line HL_O of the display panel, the first pixel P1 and the second pixel P2 are disposed with the first data line D1 and the second data line D2 interposed therebetween. The third pixel P3 and the fourth pixel P4 may be disposed with the third data line D3 and the fourth data line D4 interposed therebetween. In addition, in the fifth horizontal pixel line HL_E of the display panel, the fifth pixel P5 and the sixth pixel P6 are disposed with the first data line D1 and the second data line D2 interposed therebetween. The seventh pixel P7 and the eighth pixel P8 may be disposed with the third data line D3 and the fourth data line D4 interposed therebetween. In addition, a vertical gate line VG2 may be disposed between the second pixel P2 and the third pixel P3 and between the sixth pixel P6 and the seventh pixel P7.

At this time, the first pixel P1 is connected to the first data line D1 through the first TFT T1, and the second pixel P2 is the second data line D2 through the second TFT T2. The third pixel P3 is connected to the third data line D3 through the third TFT T3.

In particular, the fifth pixel P5 is connected to the second data line D2 through the fifth TFT T5, and the sixth pixel P6 is the third data line D3 through the sixth TFT T6. And the seventh pixel P7 is connected to the fourth data line D4 through the seventh TFT T7. To this end, the pixel electrode of the fifth pixel P5 is connected to the fifth TFT T5 across the first data line D1 through the first jumping wiring formed on the first data line with the insulating film interposed therebetween. The pixel electrode of the sixth pixel P6 is connected to the sixth TFT (T6) across the vertical gate line (VG2) through a second jumping wiring formed on the vertical gate line (VG2) with an insulating film therebetween, The pixel electrode of the seventh pixel P7 is connected to the seventh TFT (T7) across the third data line (D3) through a third jumping wire formed on the third data line (D3) with an insulating film therebetween. There are features.

Here, the first to third jumping wires may be formed on the same layer as the pixel electrode of the pixels to prevent shorting between the data line and the vertical gate line. The detailed cross-sectional structure will be described later in detail through FIGS. 11A to 11C.

FIG. 6 is a view showing a part of the pixel array compared to FIG. 4 for a comparative example, and FIG. 7 is a plan view showing a part of FIG. 6 in detail. And, FIG. 8 is a cross-sectional view of FIG. 7 taken along line A-A, and FIG. 9 shows that luminance differences between pixels are generated due to signal interference due to parasitic capacitance between the vertical gate line and the data line. 6 to 8, 'D1 to D6' are data lines, 'VG1 to VG3' are vertical gate lines, 'HG1 to HG3' are horizontal gate lines, 'VomV' is a vertical common voltage supply line, ' VcomH 'means each horizontal common voltage supply line.

Referring to FIG. 6, two vertical wires are disposed between neighboring pixels in a horizontal direction. Here, the two vertical wires include one data line and one vertical gate line, or one data line and one vertical common voltage supply line. As shown in FIG. 7, each of the vertical gate lines 13 is connected to the horizontal gate lines HGL through the first contact hole CONT1, and the vertical common voltage supply line VcomV connects the second contact hole CONT2. It is connected to the horizontal common voltage supply line (VcomH). 8, the vertical gate line 13, the data line DL, and the vertical common voltage supply line VcomV are formed on the same layer on the gate insulating layer 12. In addition, the horizontal gate lines HGL and the horizontal common voltage supply line VcomH are formed on the same layer as the Vcom blocking unit 11 under the gate insulating layer 12.

Under this structure, since the vertical gate line 13 and the data line 14 are disposed adjacent to each other as in FIGS. 7 to 9, parasitic capacitance Cgd between the vertical gate line 13 and the data line 14 Due to the influence of the signal interference occurs in the data voltage (Vdata) applied to the data line (14). Signal interference due to parasitic capacitance (Cgd) appears in the form of data ripple.

The data ripple is mixed with the data voltage Vdata at the rising and falling edges of the gate pulse SCAN. The data ripple is relatively larger in pixels in which the first contact hole CONT1 is disposed close. As illustrated in FIG. 9, the first pixel voltage Vp1 charged in a pixel having a relatively large data ripple has an effect of kick-back compared to the second pixel voltage Vp2 charged in a pixel having a relatively small data ripple. The more the voltage level is lowered. This pixel voltage difference appears as a luminance difference, and as a result, unwanted line dim is seen along the first contact holes CONT1 in the display panel.

To minimize signal interference, 1) widen the separation distance W1 between the vertical gate line 13 and the data line 14 as much as possible, and 2) block the Vcom between the vertical gate line 13 and the data line 14 It is possible to consider a method of further forming (11). However, according to the above methods, there is a problem in that the aperture ratio is lowered because the region where the pixel electrodes 19 are to be formed is relatively narrow. In FIG. 8, reference numeral '10', which is not described, denotes a lower substrate, '15', '16', and '18' denote insulating films, and '17' denotes a common electrode.

In order to solve the problem in the comparative example as in FIGS. 6 to 9, the present invention arranges two data lines in the first vertical boundary CB1 and the second vertical boundary CB2 as described in FIG. 4. By arranging one vertical gate line, the separation distance between the data line and the vertical gate line can be widened by a width occupied by a pixel electrode of 1 pixel, thereby causing signal interference due to parasitic capacitance (Cgd) between the vertical gate line and the data line. Can solve it. In addition, the present invention can improve the aperture ratio by narrowing the width of the data lines (WD2 in FIG. 10B) to that of the vertical gate line (WD1 in FIG. 10B). In addition, according to the present invention, the width of the vertical gate line (WD1 in FIG. 10B) is relatively wide due to the independent arrangement structure, thereby reducing the gate load amount and minimizing the signal deviation of the gate pulse for each display position.

10A and 10B are equivalent circuit diagrams and pixel array plan views for further explaining a connection configuration between a data line and a pixel. And, FIGS. 11A to 11C are cross-sectional views of parts of FIG. 10B.

The first and second pixels PIXa and PIXb connected to the data lines Dj and Dj + 1 in the first horizontal pixel line and the data lines Dj and Dj + 1 in the second horizontal pixel line. The connection relationship between the third and fourth pixels PIXc and PIXd to be connected will be described below.

Data lines Dj and Dj + 1 are disposed between the first pixel PIXa and the second pixel PIXb in the first horizontal pixel line.

The first TFT Ta of the first pixel PIXa and the first pixel electrode 30a are disposed on the left side of the data line Dj. The first TFT (Ta) supplies the data voltage of the first polarity (+) from the data line Dj to the first pixel electrode 30a in response to the first gate pulse from the first horizontal gate line HG1. do. The first TFT (Ta) includes a gate electrode 22 integrated with the first horizontal gate line HG1, a drain electrode integrated with the data line Dj, and a first pixel electrode 30a through a contact hole CONT3a. It includes a source electrode 26 connected to.

The second TFT Tb and the second pixel electrode 30b of the second pixel PIXb are disposed on the right side of the data line Dj + 1. The second TFT Tb sets the data voltage of the second polarity (-) from the data line Dj + 1 to the second pixel electrode 30b in response to the first gate pulse from the first horizontal gate line HG1. To supply. The second TFT Tb includes a gate electrode 22 integrated with the first horizontal gate line HG1, a drain electrode integrated with the data line Dj + 1, and a second pixel electrode through the contact hole CONT3b. 30b).

The third pixel PIXc is not disposed vertically below the first pixel PIXa, but is disposed diagonally to the left below the first pixel PIXa. The fourth pixel PIXd is vertically disposed under the first pixel PIXa. The vertical gate line VG4 is disposed between the third pixel PIXc and the fourth pixel PIXd.

The third TFT Tc and the third pixel electrode 30c of the third pixel PIXc are disposed on the left side of the data line Dj. The third TFT Tc supplies the data voltage of the first polarity (+) from the data line Dj to the third pixel electrode 30c in response to the second gate pulse from the second horizontal gate line HG2. do. The third TFT (Tc) is the third pixel electrode 30c through the gate electrode 22 'integrated with the second horizontal gate line HG2, the drain electrode integrated with the data line Dj, and the contact hole CONT3c. ).

The source electrode 26 'of the third TFT (Tc) passes through the insulating films 28 and 29 through the first jumping wiring formed on the vertical gate lines VG4 and 25, and the vertical gate lines VG4 and 25 are formed. It is connected to the third pixel electrode 30c of the third pixel PIXc across. The first jumping wiring is integrated with the third pixel electrode 30c on the same layer as the third pixel electrode 30c.

The fourth TFT Td and the fourth pixel electrode 30d of the fourth pixel PIXd are disposed on the right side of the data line Dj + 1. The fourth TFT Td sets the data voltage of the second polarity (-) from the data line Dj + 1 to the fourth pixel electrode 30d in response to the second gate pulse from the second horizontal gate line HG2. To supply. The fourth TFT (Td) includes a gate electrode 22 'integrated with the second horizontal gate line HG2, a drain electrode integrated with the data line Dj + 1, and a fourth pixel electrode through a contact hole CONT3d. And a source electrode 27 'connected to 30d.

The source electrode 27 'of the fourth TFT Td crosses the data line Dj through the second jumping wiring formed on the data line Dj with the insulating films 28 and 29 interposed therebetween. PIXd) is connected to the fourth pixel electrode 30d. The second jumping wiring is integrated with the fourth pixel electrode 30d on the same layer as the fourth pixel electrode 30d.

11A to 11C, reference numeral '21' denotes a lower substrate, '23' denotes a gate insulating film, '24' denotes a semiconductor layer, and '28' and '29' denote first and second insulating films, respectively. do. The gate insulating layer 23 covers gate metal patterns such as horizontal gate lines HG1 to HG5 and a horizontal common voltage supply line (not shown). A semiconductor pattern 24 and a source-drain metal pattern are stacked on the gate insulating layer 23. The patterns in which the semiconductor pattern 24 and the source-drain metal pattern are stacked are formed of data lines and vertical gate lines VG1 to VG5 and a vertical common voltage supply line (not shown). The first insulating layer 28 and the second insulating layer 29 sequentially cover the source-drain metal patterns. On the second insulating film 29, pixel electrodes 30a to 30d and jumping wirings integrated therewith are formed. The common electrode may be formed on the same layer as the pixel electrodes 30a to 30d to implement the IPS mode, or may be formed under the pixel electrode with a separate insulating layer as shown in FIG. 8 to implement the FFS mode.

Through the above description, those skilled in the art will appreciate that various changes and modifications are possible without departing from the spirit of the present invention. Therefore, the present invention should not be limited to the contents described in the detailed description, but should be defined by the claims.

10: drive IC 12: timing controller
PNL: Display panel SIC: Source drive IC
GIC: Gate drive IC

Claims (6)

Vertical boundaries are formed between adjacent pixels in the horizontal direction, two data lines and one vertical gate line are alternately arranged in the vertical boundaries, and each of the vertical gate lines is a horizontal gate extending in a horizontal direction. A display panel connected to the line and having one horizontal gate line disposed between adjacent pixels in a vertical direction;
A driving circuit that supplies a data voltage to the pixels through the data lines and a gate pulse to the pixels through the vertical gate lines;
Each of the pixels arranged in the odd horizontal pixel line of the display panel is connected to the data line arranged closest to itself;
Each of the pixels arranged on the superior horizontal pixel line of the display panel jumps to one data line or one vertical gate line disposed closest to itself in one direction, thereby neighboring the one data line or one vertical gate line. A liquid crystal display device, characterized in that it is connected to another data line adjacent to. According to claim 1,
In the odd horizontal pixel line of the display panel, a first pixel and a second pixel are disposed between the first data line and the second data line included in the data line pairs, and included in the data line pairs. A third pixel and a fourth pixel are disposed with the third data line and the fourth data line interposed therebetween,
In the superior horizontal pixel line of the display panel, a fifth pixel and a sixth pixel are disposed with the first data line and the second data line interposed therebetween, and the third data line and the fourth data line are interposed therebetween. The seventh and eighth pixels are arranged,
When the one vertical gate line is disposed between the second pixel and the third pixel, and between the sixth pixel and the seventh pixel,
The first pixel is connected to the first data line through a first TFT, the second pixel is connected to the second data line through a second TFT, and the third pixel is connected to the first data line through a third TFT. 3 connected to the data line,
The fifth pixel is connected to the second data line through a fifth TFT, the sixth pixel is connected to the third data line through a sixth TFT, and the seventh pixel is connected to the second data line through a seventh TFT. 4 A liquid crystal display device characterized in that it is connected to the data line. According to claim 2,
The pixel electrode of the fifth pixel is connected to the fifth TFT across the first data line through a first jumping wiring formed on the first data line with an insulating film interposed therebetween;
The pixel electrode of the sixth pixel is connected to the sixth TFT across the vertical gate line through a second jumping wire formed on the vertical gate line with an insulating film interposed therebetween;
The pixel electrode of the seventh pixel is connected to the seventh TFT across the third data line through a third jumping wire formed on the third data line with an insulating film interposed therebetween. According to claim 2,
The driving circuit,
During the Nth frame (where N is a positive integer), data voltages of a first polarity are supplied to the first and third data lines, and data voltages of a second polarity opposite to the first polarity are applied to the second and Supply to a fourth data line;
During the N + 1 frame, the data voltage of the second polarity is supplied to the first and third data lines, and the data voltage of the first polarity is supplied to the second and fourth data lines. Liquid crystal display device. The method of claim 3,
The first jumping wiring is integrated with the pixel electrode of the fifth pixel on the same layer as the pixel electrode of the fifth pixel,
The second jumping wiring is integrated with the pixel electrode of the sixth pixel on the same layer as the pixel electrode of the sixth pixel,
The third jumping wiring is integrated with the pixel electrode of the seventh pixel on the same layer as the pixel electrode of the seventh pixel. According to claim 1,
The width of each of the data lines is smaller than the width of each of the vertical gate lines.

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