KR102636688B1 - Display Device Having Narrow Bezel - Google Patents

Abstract

A display device according to an embodiment of the present specification includes a plurality of data lines extending in a first direction driven by a data voltage, driven by a gate pulse synchronized with the data voltage, and extending in a second direction orthogonal to the first direction. a display panel having a plurality of extended horizontal gate lines, a plurality of vertical gate lines that overlap the data lines and are connected one-to-one to the horizontal gate lines through a plurality of contact holes at different positions; a source driver IC that generates the data voltage and supplies it to the data line; a gate driver IC that generates the gate pulse and supplies it to the vertical gate line; and a flexible circuit board bonded to one side of the display panel and on which the source driver IC and the gate driver IC are mounted together, wherein the length of the vertical gate line extending from the gate driver IC to the contact hole is the contact hole. Regardless of the location of the hole, all positions of the display panel are identical.

Description

Display device having a narrow bezel

This specification relates to a display device having a narrow bezel.

Thanks to the development of process technology and driving technology, the active matrix type liquid crystal display device has lowered its price and increased its performance, and is being applied to almost all display devices, from small mobile devices to large televisions.

Manufacturers of liquid crystal display devices are making various attempts to implement a narrow bezel. Narrow bezel technology is a technology that minimizes the bezel at the edge of the display panel where images are not displayed in order to relatively increase the size of the effective screen on which images are displayed in a display panel of the same size. Narrow bezel technology has limitations in reducing the bezel width due to limitations in microprocessing technology. Therefore, there is a need to develop narrow bezel technology that can overcome process technology.

This specification provides a display device that can minimize the bezel width by changing the mounting position of the gate driver through a vertical gate line.

This specification provides a display device that can minimize the line load difference between vertical gate lines.

This specification provides a display device that minimizes the impact of data coupling on vertical gate lines.

A display device according to an embodiment of the present specification includes a plurality of data lines extending in a first direction driven by a data voltage, driven by a gate pulse synchronized with the data voltage, and extending in a second direction orthogonal to the first direction. a display panel having a plurality of extended horizontal gate lines, a plurality of vertical gate lines that overlap the data lines and are connected one-to-one to the horizontal gate lines through a plurality of contact holes at different positions; a source driver IC that generates the data voltage and supplies it to the data line; a gate driver IC that generates the gate pulse and supplies it to the vertical gate line; and a flexible circuit board bonded to one side of the display panel and on which the source driver IC and the gate driver IC are mounted together, wherein the length of the vertical gate line extending from the gate driver IC to the contact hole is the contact hole. Regardless of the location of the hole, all positions of the display panel are identical.

This embodiment has the following effects.

In this embodiment, the source driver IC and gate driver IC are mounted together on a flexible circuit board bonded to one side of the display panel, and the gate driver IC is connected to the horizontal gate line through a vertical gate line. Through this, this embodiment can minimize the bezel width at the left and right sides of the display panel.

In this embodiment, the length of the vertical gate line extending from the gate driver IC to the contact hole is designed to be the same at all positions of the display panel, regardless of the position of the contact hole, by appropriately bending the vertical gate lines, Line load differences can be minimized.

In this embodiment, a decrease in the aperture ratio of the display panel can be minimized by overlapping the bent parts constituting the vertical gate lines with the data line and the horizontal gate line.

In this embodiment, in each vertical gate line, the first total overlap area due to overlap with the data line of the first polarity pattern and the second total overlap area due to overlap with the data line of the second polarity pattern are equal to each other. Thus, the data coupling influence on the vertical gate line can be minimized.

The effects according to the present specification are not limited to the contents exemplified above, and further various effects are included in the present specification.

1 and 2 are diagrams showing a display device according to an embodiment of the present specification.
FIG. 3 is an enlarged view of the COF shown in FIG. 2.
Figure 4 is a diagram schematically showing a pixel array according to an embodiment of the present specification.
5 to 8 are diagrams showing a vertical gate line design method according to an embodiment of the present specification.
9 and 10 are diagrams showing a vertical gate line design method according to another embodiment of the present specification.
11 to 13 are diagrams showing that the length of a 180-degree bent portion varies depending on the position of a vertical gate line on the display panel.
Figures 14 to 16 are diagrams showing various shapes of the 180-degree bend and 90-degree bend of the vertical gate line according to the data polarity pattern.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present specification is complete, and that common knowledge in the technical field to which this specification pertains is provided. It is provided to fully inform those who have the scope of the invention, and this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative, and the present specification is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two parts is described as 'on top', 'on top', 'at the bottom', 'next to ~', 'right next to' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

First, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical idea of the present specification.

Like reference numerals refer to substantially like elements throughout the specification.

In the following description, if it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the gist of the present specification, the detailed description will be omitted.

Hereinafter, embodiments of the present specification will be described in detail with reference to the attached drawings.

1 and 2 are diagrams showing a display device according to an embodiment of the present specification. And FIG. 3 is an enlarged view of the COF shown in FIG. 2.

Referring to Figures 1 to 3, the display device of this specification may be implemented as a liquid crystal display device. The liquid crystal display device includes a display panel (PNL), a drive IC (Integrated Circuit, DIC) (10), and a timing controller (Timing Controller, TCON) (12).

The liquid crystal display device of this specification can be implemented in all known liquid crystal modes, such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, and FFS (Fringe Field Switching) mode. Additionally, the liquid crystal display device of this specification may be implemented in any form, such as a transmissive liquid crystal display device, a transflective liquid crystal display device, or a reflective liquid crystal display device.

The display panel (PNL) includes an upper substrate and a lower substrate that face each other with a liquid crystal cell (Clc) in between. In the display panel (PNL), image data is displayed in a pixel array area where pixels are arranged in a matrix form. The pixel array includes a TFT array formed on a lower substrate and a color filter array formed on an upper substrate. Using a color filter on TFT (COT) process, a color filter can be formed on the TFT array of the lower substrate.

The TFT array includes vertical interconnections and horizontal interconnections. Vertical wires are formed along the vertical direction (y-axis direction in FIG. 1) of the display panel PNL. The horizontal wires are formed along the horizontal direction of the display panel (PNL) (Figure 1, x-axis direction) and are perpendicular to the vertical wires. Vertical interconnections include data lines (DL) and vertical gate lines (VGL). The horizontal interconnections include horizontal gate lines (HGL) that receive gate pulses through vertical gate lines (VGL). As shown in FIG. 4, the horizontal gate lines (HGL) are connected 1:1 to the vertical gate lines (VGL) through contact holes (CNT) and receive gate pulses through the vertical gate lines (VGL).

In the TFT array, thin film transistors (TFTs) are formed at each intersection of data lines DL and horizontal gate lines HGL. The TFT supplies the data voltage from the data line (DL) to the pixel electrode (1) of the liquid crystal cell (Clc) in response to the gate pulse from the horizontal gate line (HGL). Each of the liquid crystal cells Clc, that is, the pixels, is driven by the voltage difference between the pixel electrode 1, which charges the data voltage through the TFT, and the common electrode 2, to which the common voltage Vcom is applied. The common voltage Vcom is supplied to the common electrode 2 formed in the pixels through the common voltage supply line. A storage capacitor (Cst) that maintains the voltage of the liquid crystal cell for one frame period is connected to the liquid crystal cell (Clc). The color filter array includes a color filter and a black matrix. A polarizer is attached to each of the upper and lower glass substrates of the display panel (PNL), and an alignment film is formed to set the pre-tilt angle of the liquid crystal.

The drive IC (DIC, 10) is a driving circuit for the display panel and can be mounted on a flexible circuit board such as COF (Chip on film), as shown in FIG. 2.

The drive IC (DIC, 10) may include a source drive IC (SIC) and a gate drive IC (GIC). The source drive IC (SIC) and gate drive IC (GIC) may be mounted together on the COF as shown in FIG. 3. The input terminal of the COF is bonded to the PCB (Printed Circuit Board), and the output terminal of the COF is bonded to the lower substrate of the display panel (PNL). In the COF, an insulating film is placed between the wires connected to the source drive IC (SIC) (Figure 3, dotted line) and the wires connected to the gate drive IC (GIC) (Figure 3, solid line) so that the wires can be electrically separated. can be formed.

The source drive IC (SIC) samples digital video data of the input image under the control of the timing controller 12, latches it, and converts it into data in a parallel data system. The source drive IC (SIC) generates a data voltage by converting digital video data into an analog gamma compensation voltage using a digital to analog converter (ADC) under the control of the timing controller 12. It can be supplied to data lines (DL).

The gate drive IC (GIC) can generate gate pulses (or scan pulses) synchronized to the data voltage under the control of the timing controller 12 and sequentially supply them to the vertical gate lines (VGL). Then, the gate pulse supplied to the vertical gate lines (VGL) may be applied to the horizontal gate lines (HGL) through the contact holes (CNT).

In this way, both the source drive IC (SIC) and the gate drive IC (GIC) are formed in the COF connected to the top of the display panel (PNL), and the gate pulse is transmitted to the horizontal gate lines (HGL) through the vertical gate lines (VGL). is approved. Therefore, there is no need to bond or embed a gate drive IC at the left and right edges of the display panel (PNL), and horizontal gate lines (HGL) and a gate drive IC are installed at the left and right edges of the display panel (PNL). Connecting routing wires are not formed. As a result, the width of the bezel (BZ) at the left and right edges of the display panel and the bezel at the bottom edge can be minimized.

The timing controller 12 transmits digital video data of the input image received from the host system 14 to source drive ICs (SICs). The timing controller 12 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), and a main clock (CLK) from the host system 14. These timing signals are synchronized with the digital video data of the input image. The timing controller 12 uses timing signals (Vsync, Hsync, DE, CLK) to control the operation timing of the source drive ICs (SIC) and the operation of the gate drive ICs (GIC). Generates a gate timing control signal to control timing.

The Host System (SYSTEM) 14 can be implemented as any one of a television system, set-top box, navigation system, DVD player, Blu-ray player, personal computer (PC), home theater system, and phone system. there is. The host system 14 converts digital video data of the input image into a format suitable for the display panel (PNL). The host system 14 transmits timing signals (Vsync, Hsync, DE, MCLK) along with digital video data of the input image to the timing controller 12.

Figure 4 is a diagram schematically showing a pixel array according to an embodiment of the present specification. In FIG. 4, 'D1 to D4' refer to data lines, 'VG1 to VG4' refer to vertical gate lines, and 'HG1 to HG4' refer to horizontal gate lines.

Referring to FIG. 4, the data lines (D1 to D4) and the horizontal gate lines (HG1 to HG4) intersect each other, and a pixel (P) is disposed in each intersection area. Each pixel (P) is connected to one horizontal gate line and one data line.

At least one insulating film is positioned between the data lines (D1 to D4) and the horizontal gate lines (HG1 to HG4) to electrically separate the data lines (D1 to D4) from the horizontal gate lines (HG1 to HG4). I order it.

At least one insulating film may also be positioned between the vertical gate lines (VG1 to VG4) and the horizontal gate lines (HG1 to HG4). The vertical gate lines (VG1 to VG4) may be connected one-to-one to the horizontal gate lines (HG1 to HG4) through one of the contact holes (CNT1 to CNT4) penetrating the insulating film. The contact holes (CNT1 to CNT4) may be located diagonally as shown in FIG. 4, but this is only an example. The positions of the contact holes (CNT1 to CNT4) can be modified in various ways.

Meanwhile, to prevent a decrease in the aperture ratio of the display panel due to the vertical gate lines (VG1 to VG4), the vertical gate lines (VG1 to VG4) are formed on the display panel by overlapping with the data lines (D1 to D4). You can. At this time, at least one insulating film is positioned between the vertical gate lines (VG1 to VG4) and the data lines (D1 to D4) to electrically connect the vertical gate lines (VG1 to VG4) and the data lines (D1 to D4). Separate it into

5 to 8 are diagrams showing a vertical gate line design method according to an embodiment of the present specification.

The vertical gate line design method of FIGS. 5 to 8 is intended to equalize the line load applied to the vertical gate lines at all positions of the display panel.

Referring to FIG. 5 , first, second, and third horizontal gate lines (HGa, HGb, and HGc) may be disposed on the display panel. On the display panel, a second horizontal gate line (HGb) may be located between the first horizontal gate line (HGa) and the third horizontal gate line (HGc). For example, as shown in FIG. 5, the gap between the first horizontal gate line (HGa) and the second horizontal gate line (HGb) may be “D”, and the distance between the third horizontal gate line (HGc and the second horizontal gate line) may be “D”. The spacing between (HGb) may also be “D”.

At this time, the first vertical gate line (VGa) may be connected to the first gate driver IC (GIC1) and may be connected to the first horizontal gate line (HGa) through the first contact hole (CNTa). The second vertical gate line (VGb) may be connected to the second gate driver IC (GIC2) and may be connected to the second horizontal gate line (HGb) through the second contact hole (CNTb). Additionally, the third vertical gate line (VGc) may be connected to the third gate driver IC (GIC3) and may be connected to the third horizontal gate line (HGc) through the third contact hole (CNTc).

However, the straight line distance between the gate driver IC and the contact hole, which are connected to each other through the vertical gate line, varies depending on the location of the display panel. If all vertical gate lines are designed to be straight and straight, the line load on the vertical gate lines is bound to be different for all vertical gate lines. This is because the length of the vertical gate line varies depending on the location of the contact hole. The line load increases in proportion to the length of the vertical gate line, and this difference in line load can cause a difference in kickback voltage for each position on the display panel, deteriorating display quality. In order to minimize the side effects caused by differences in kickback voltage, the capacity of the storage capacitor must be increased, but in the case of high-resolution models, it is difficult to increase the capacity of the storage capacitor to secure the aperture ratio.

Therefore, this specification proposes a method to ensure that the line load applied to the vertical gate line is equalized at all positions of the display panel by changing the shape of the vertical gate line. That is, in this specification, regardless of the location of the contact hole, the length of the vertical gate line extending from the gate driver IC to the contact hole is made the same at all locations of the display panel. If the line load applied to the vertical gate line is equalized at all positions of the display panel, the above-mentioned problems due to differences in kickback voltage can be prevented in advance.

To this end, the first vertical gate line connected to the contact hole with the longest straight line distance from the gate driver IC and the remaining second vertical gate lines may be formed in different shapes. Specifically, as shown in FIGS. 5 and 6, the first vertical gate line (VGa) connected to the contact hole with the longest straight line distance from the gate driver IC is formed to include only one extension extending in the vertical direction without a 180-degree bend. And the remaining second vertical gate lines (VGb, VGc) correspond to each other and extend in the vertical direction, first extension portions LA and second extension portions LC, and first and second extension portions LC along the horizontal direction. It may be formed to include a connection portion (LB) connecting the extension portions LA and LC. Here, the first extension part LA may be longer than the second extension part LC. In the second vertical gate lines (VGb, VGc), the opposing portions of the first extension portion (LA) and the second extension portion (LC) and the connection portion (LB) have a “ㄷ” shape or similar shape. It forms a first bending area (TWA). That is, the first bending area TWA constitutes a 180-degree bending portion.

In the second vertical gate lines VGb and VGc, the first bending area TWA is a 'line load compensation area' that ensures that the line load is equalized at all positions of the display panel. The line load compensation length of the second vertical gate line constituting the first bent area (TWA) (i.e., the length of the 180-degree bent portion of the second vertical gate line) increases as the straight line distance between the gate driver IC and the contact hole becomes shorter. It can be. For example, in the example of FIG. 5, the line load compensation length of the second vertical gate line VGb constituting the first bent area TWA may be approximately 'D', and the line load compensation length of the second vertical gate line VGb constituting the first bent area TWA may be approximately 'D'. The line load compensation length of the second vertical gate line VGc may be approximately '2D'. Meanwhile, in the example of FIG. 5, the first vertical gate line (VGa) connected to the contact hole (CNTa) with the longest straight line distance from the gate driver IC (GIC1) does not have the first bent area (TWA). Accordingly, in the example of FIG. 5, the line load applied to the vertical gate line can be equalized at all positions of the display panel.

In the example of FIG. 6 , the first extension portion LA and the second extension portion LC included in the second vertical gate lines VGb and VGc may overlap different data lines. If the line width of the second vertical gate lines (VGb, VGc) is designed to be less than 1/2 that of the data line, the first extension portion (LA) and the second extension portion (LC) may overlap the same data line. However, considering the RC delay of the second vertical gate lines (VGb and VGc), this is not desirable. In order to minimize distortion of the gate pulse due to RC delay, the line width of the second vertical gate line should be designed to be similar to the line width of the data line. Therefore, as shown in FIG. 7, the first extension part LA and the second extension part LC included in the second vertical gate lines VGb and VGc are different from each other with at least one first insulating film INS1 therebetween. It is preferable that it overlaps the data line (DL).

Meanwhile, in order to secure the aperture ratio, as shown in FIG. 8, the connection portion LB included in the second vertical gate lines VGb and VGc is located among the horizontal gate lines HG with at least one second insulating film INS2 interposed therebetween. Can be nested in either one. In the example of FIG. 5, the connection part belonging to the second vertical gate line (VGb) may overlap any horizontal gate line located between the first horizontal gate line (HGa) and the second horizontal gate line (HGb), The connection part belonging to the second vertical gate line (VGc) may overlap the second horizontal gate line (HGb).

9 and 10 are diagrams showing a vertical gate line design method according to another embodiment of the present specification.

FIGS. 9 and 10 are based on the vertical gate line design method described in FIGS. 5 to 8. The vertical gate line design method of FIGS. 9 and 10 not only ensures that the line load applied to the vertical gate line is equalized at all positions of the display panel, but furthermore, the coupling effect applied to the vertical gate line at all positions of the display panel is This is to ensure that they are offset through polarity balance.

Referring to FIGS. 9 and 10 , the second vertical gate line (VGk4) having the first bent area (TWA) has the first extension portion (LA) and the second extension portion (LC) parallel to each other and along the horizontal direction. It may be formed to include a connection portion LB connecting the first and second extension portions LA and LC. To cancel out the coupling effect, the first extension portion LA and the second extension portion LC may each be formed in a step shape.

Specifically, the first extension LA extends in the horizontal direction between a plurality of first branch extensions LA1 to LA5 extending in the vertical direction and neighboring first branch extensions LA1 to LA5. It may include first branch connection parts (LD1 to LD4) that connect to each other. Two adjacent first branch extension parts and one first branch connection part connected between them form a step-shaped second bent area (TWB). That is, the second bent area TWB constitutes a 90-degree bend.

In addition, the second extension portion LC is a second extension portion LC that connects the plurality of second branch extension portions LC1 to LC3 extending in the vertical direction and the adjacent second branch extension portions LC1 to LC3 along the horizontal direction. It may include two branch connections (LD5, LD6). Two adjacent second branch extension parts and one second branch connection part connected between them form a step-shaped second bent area (TWB). That is, the second bent area TWB constitutes a 90-degree bend.

The first branch extensions LA1 to LA5 may overlap each of the plurality of first data lines, and the second branch connection parts LD5 and LD6 may overlap each of the plurality of second data lines. Here, the first and second data lines may be independent from each other as shown in FIGS. 14 to 16, or may have at least part of them in common as shown in FIGS. 9 and 10.

The first branch connectors LD1 to LD4 may overlap each of the plurality of first horizontal gate lines, and the second branch connectors LD5 and LD6 may overlap each of the plurality of second horizontal gate lines. there is. Here, the first and second horizontal gate lines may be independent from each other, as shown in FIGS. 14 to 16, or may have at least some parts in common, as shown in FIGS. 9 and 10.

Adjacent first data lines are charged with data voltages of different polarity patterns, and neighboring second data lines are also charged with data voltages of different polarity patterns. The first and second branch extensions (LA1 to LA5, LC1 to LC3) overlapping the first and second data lines may be affected by coupling depending on the data polarity, and this coupling effect is biased toward a specific polarity. The overlapping positions of the first and second branch extensions (LA1 to LA5 and LC1 to LC3) may be set so that they offset each other without hitting. That is, in the second vertical gate line VGk4, the first total overlap area due to overlapping with the data lines of the first polarity pattern and the second total overlapping area due to overlapping with the data lines of the second polarity pattern are each other. The overlapping positions of the first and second branch extensions LA1 to LA5 and LC1 to LC3 may be set to be the same. When the first and second total overlap areas of the second vertical gate line VGk4 are equal to each other, the coupling effect due to polarity bias, that is, the distortion of the gate pulse, can be suppressed. In other words, as shown in FIG. 10, when the first and second total overlap areas in the second vertical gate line VGk4 are equal to each other, the (+) coupling and the (-) coupling cancel each other, causing a ripple in the gate pulse. ) The gate pulse can be stabilized by suppressing the generation. In the example of FIG. 10, 'Dj1 to Dj6' refer to data lines, and 'HGk1 to HGk5' refer to horizontal gate lines. Data voltages of opposite polarities (+, -) are applied to the data lines (Dj1 to Dj6) on a column-by-column basis. The second vertical gate line (VGk4) partially overlaps the data lines (Dj1 to Dj6), so that the number of (+) couplings and (-) couplings are equal to 4 each, so that (+) couplings and (-) ) Couplings can cancel each other out.

11 to 13 are diagrams showing that the length of a 180-degree bent portion varies depending on the position of a vertical gate line on the display panel. 11 to 13, the gate driver IC is omitted. However, the gate driver IC can be located below the lowest horizontal gate line (HG 1800).

In FIG. 11, VG1 is the above-described first vertical gate line, and does not have a 180-degree bend, but only has a plurality of 90-degree bends. Additionally, in FIG. 11, VG1800 and VG900 are the above-described second vertical gate lines and have a 180-degree bend and a plurality of 90-degree bends. The length of the 180-degree bend is longer in VG1800 than in VG900. This is because the straight line distance between the VG1800's contact hole (CNT1800) and the gate driver IC is closer than the straight line distance between the VG900's contact hole (CNT900) and the gate driver IC. Accordingly, the lengths of the first and second vertical gate lines become the same, and the line loads applied to the first and second vertical gate lines become the same.

Meanwhile, as shown in FIG. 11, in each of VG1, VG900, and VG1800, the plurality of branch extensions forming the 90-degree bends are 1/2 of the 90-degree bends of the first polar pattern to prevent bias in polar coupling. The data voltage may overlap the charged data lines, and the remaining 1/2 of the 90 degree bends may overlap the data lines charged with the data voltage of the second polarity pattern.

Figure 12 shows the application of the vertical gate line design method according to the above-described embodiment of the present specification to a landscape type display panel. In Figure 12, 'AR1, AR2' represents a 180 degree bend. In the case of a landscape type display panel, the horizontal gate line is long, so it is necessary to further consider the line load in the horizontal direction. Therefore, in the case of a landscape type display panel, two vertical gate lines (e.g., CNT1A, CNT1B) are formed at different positions of the same horizontal gate line (e.g., HG1). For example, it can be connected to VG1A, VG1B). Since gate pulses of the same phase are applied to the two vertical gate lines, distortion of the gate pulse due to RC delay in the horizontal direction can be minimized. This method is called the double feeding scheme. The double feeding method refers to supplying one gate pulse to two different positions on the same horizontal gate line.

Figure 13 shows the application of the vertical gate line design method according to the embodiment of the present specification described above to a portrait type display panel. In Figure 13, 'AR' represents a 180 degree bend. In the case of a portrait type display panel, since the length of the horizontal gate line is relatively short, the gate pulse may be applied using the single feeding scheme shown. The single feeding method refers to supplying one gate pulse to a specific 1 position of the same horizontal gate line.

Figures 14 to 16 are diagrams showing various shapes of the 180-degree bend and 90-degree bend of the vertical gate line according to the data polarity pattern. 14 to 16 are just examples of vertical gate lines, and various modifications are possible.

Referring to FIG. 14, the source driver may supply a data voltage whose polarity is inverted in a horizontal direction by 1 dot and in a vertical direction by a column to the data lines (D1 to D12). VG1 extends along a first path and then connects to HG1 through CNT1, VG9 extends along a second path and connects to HG9 through CNT9, and VG17 extends along a third path and then connects to HG17 through CNT17. connected to

In this case, VG1 partially overlaps with D9 to D12 along the first path so that the (+) coupling and (-) coupling cancel each other out. VG9 partially overlaps with D5 to D8 along the second path, thereby causing (+) coupling and (-) coupling to cancel each other out. Additionally, VG17 partially overlaps with D1 to D4 along the third path, thereby causing (+) coupling and (-) coupling to cancel each other out.

Referring to FIG. 15 , the source driver may supply a data voltage whose polarity is inverted in 1-dot increments in the horizontal direction and in increments of 2 dots in the vertical direction to the data lines (D1 to D12). VG1 extends along a first path and then connects to HG1 through CNT1, VG9 extends along a second path and connects to HG9 through CNT9, and VG17 extends along a third path and then connects to HG17 through CNT17. connected to

In this case, VG1 partially overlaps with D9 to D12 along the first path so that the (+) coupling and (-) coupling cancel each other out. VG9 partially overlaps with D5 to D7 and D9 along the second path, thereby causing (+) coupling and (-) coupling to cancel each other out. Additionally, VG17 partially overlaps with D1 to D4 along the third path, thereby causing (+) coupling and (-) coupling to cancel each other out.

Referring to FIG. 16, the source driver can supply data voltages whose polarity is inverted in 1-dot increments in the horizontal and vertical directions, respectively, to the data lines D1 to D12. VG1 extends along a first path and then connects to HG1 through CNT1, VG9 extends along a second path and connects to HG9 through CNT9, and VG17 extends along a third path and then connects to HG17 through CNT17. connected to

In this case, VG1 partially overlaps with D9 to D12 along the first path so that the (+) coupling and (-) coupling cancel each other out. VG9 partially overlaps with D5 to D7 and D9 along the second path, thereby causing (+) coupling and (-) coupling to cancel each other out. Additionally, VG17 partially overlaps with D1 to D4 along the third path, thereby causing (+) coupling and (-) coupling to cancel each other out.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present specification. Therefore, the technical scope of the present specification is not limited to the content described in the detailed description of the specification, but should be determined by the scope of the patent claims.

PNL: Display panel SIC: Source driver IC
GIC: Gate driver IC COF: Flexible circuit board
HG: Horizontal gate line VG: Vertical gate line
CNT: Contact hole

Claims (15)

A plurality of data lines extending in a first direction driven by a data voltage, a plurality of horizontal gate lines driven by a gate pulse synchronized to the data voltage and extending in a second direction orthogonal to the first direction, the data a display panel having a plurality of vertical gate lines that overlap the lines and are connected one-to-one to the horizontal gate lines through a plurality of contact holes at different positions;
a source driver IC that generates the data voltage and supplies it to the data line;
a gate driver IC that generates the gate pulse and supplies it to the vertical gate line; and
It is bonded to one side of the display panel and includes a flexible circuit board on which the source driver IC and the gate driver IC are mounted together,
The length of the vertical gate line extending from the gate driver IC to the contact hole is the same at all positions of the display panel regardless of the position of the contact hole. According to claim 1,
The plurality of vertical gate lines are,
It includes a first vertical gate line connected to a contact hole with the greatest straight line distance from the gate driver IC, and a plurality of second vertical gate lines excluding the first vertical gate line,
The second vertical gate line is a display device including a 180 degree bend. According to claim 2,
A display device in which the length of the 180-degree bent portion varies depending on the position of the second vertical gate line on the display panel. According to claim 3,
A display device in which the length of the 180-degree bent portion increases as the straight-line distance between the gate driver IC and the contact hole becomes shorter. According to claim 2,
The second vertical gate line is,
a first extension part and a second extension part corresponding to each other and extending in the first direction; and
A display device including a connecting portion connecting the first and second extension portions to each other along the second direction. delete According to claim 5,
A display device wherein the connection portion overlaps one of the horizontal gate lines with at least one second insulating film interposed therebetween. According to claim 5,
The first extension portion and the second extension portion each include at least one 90-degree bent portion and are implemented in a staircase shape. According to claim 8,
The first extension part,
a plurality of first branch extensions extending in the first direction; and
It includes a plurality of first branch connection parts connecting adjacent first branch extension parts along the second direction,
A display device wherein the two first branch extensions connected through the first branch connector overlap a first data line and a second data line respectively charged with data voltages of different polarity patterns. According to clause 9,
The second extension part,
a plurality of second branch extensions extending in the first direction; and
It includes a plurality of second branch connection parts connecting adjacent second branch extension parts along the second direction,
The two second branch extensions connected through the second branch connector overlap a third data line and a fourth data line respectively charged with data voltages of different polarity patterns. According to claim 10,
In the second vertical gate line,
A display device in which a first total overlap area resulting from overlapping with a data line of a first polar pattern and a second total overlapping area resulting from overlapping with a data line of a second polar pattern are equal to each other. delete According to claim 10,
The first vertical gate line is,
a plurality of third branch extensions extending in the first direction; and
A plurality of third branch connection parts connecting adjacent third branch extension parts along the second direction,
A display device in which two third branch extensions connected through the third branch connection portion overlap a fifth data line and a sixth data line respectively charged with data voltages of different polarity patterns. According to claim 13,
In the first vertical gate line,
A display device in which a first total overlap area resulting from overlapping with a data line of a first polar pattern and a second total overlapping area resulting from overlapping with a data line of a second polar pattern are equal to each other. According to claim 13,
The first branch connection part, the second branch connection part, and the third branch connection part are each overlapped with one of the horizontal gate lines.