KR20150015638A - Display device having narrow bezel and fabricating method thereof - Google Patents

Abstract

The present invention relates to a display device which is capable of minimizing a bezel and includes: vertical data lines; vertical gate lines; horizontal gate lines which are connected to the vertical gate lines; a display panel which includes pixel arrays on which pixels are arranged in a matrix; a data driving circuit which supplies a data voltage to the vertical data lines; and a gate driving circuit which is directly formed on a substrate of the display panel and supplies a gate pulse to the vertical gate lines.

Description

TECHNICAL FIELD [0001] The present invention relates to a display device having a narrow bezel,

The present invention relates to a display device having a narrow bezel.

The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display device EPD). A liquid crystal display device displays an image by controlling an electric field applied to liquid crystal molecules in accordance with a data voltage. Active matrix type liquid crystal display devices are being applied to almost all display devices from small mobile devices to large televisions due to their low price and high performance due to the development of process technology and driving technology.

Manufacturers of flat panel display devices have made various attempts to implement Narrow bezels. Narrow-bezel technology can reduce the amount of bezels that do not display images at the edges of the display panel, thereby increasing the size of the effective screen displayed on the same size display panel. Generally, a gate drive IC (Integrated Circuit) is disposed on the left and right edges of the display panel. Therefore, an area where the gate drive IC is joined in the left and right bezels of the display panel, a gate link area connecting the gate drive IC and the horizontal gate lines of the active area, etc. must be ensured. Due to the structural problems of such a flat panel display device, it is difficult to realize a narrow bezel.

The present invention provides a display device capable of minimizing a bezel.

A display panel of the present invention includes a pixel array including vertical data lines, vertical gate lines, and horizontal gate lines connected to the vertical gate lines, the pixel array including pixels arranged in a matrix form; A data driving circuit for supplying a data voltage to the vertical data lines; And a gate driving circuit formed directly on the substrate of the display panel to supply gate pulses to the vertical gate lines.

The present invention can minimize the right and left bezels of the display panel by directly forming a gate drive circuit for supplying gate pulses to the vertical gate lines on the substrate of the display panel. Further, the present invention can prevent the distortion of the data voltage due to the clock signal by separating the clock signal lines input to the gate driving circuit from the data pads and the data links.

1 is a block diagram showing a display device according to an embodiment of the present invention.
2 is a plan view showing the connection of the display panel with the COF in which the source drive IC is mounted.
FIGS. 3 and 4 are plan views showing the clock wiring region, the data pad and the link region, and the gate shift resist region by enlarging the A portion of the display panel in FIG.
5 is a cross-sectional view showing a longitudinal sectional structure of part A of the display panel shown in Figs. 3 and 4. Fig.
6 is a circuit diagram showing an example of a gate shift register.
7 is a circuit diagram showing the N stage in detail in FIG.
8 is a waveform diagram showing the operation of the N stage shown in FIG.
9 to 13 are plan views showing various connection methods of the vertical gate lines and the horizontal gate lines.
14 is a view illustrating an example of a pixel array according to an embodiment of the present invention.
FIG. 15 is a waveform diagram showing an example of a data pulse and a gate pulse applied to the pixel array shown in FIG.
16 is a cross-sectional view showing a cross-sectional structure of a pixel array.
17 is a cross-sectional view showing a cross-sectional structure of the clock wiring region taken along the line "I-I" in Fig.
Figs. 18 and 19 are plan views showing another embodiment of the A portion of the display panel in Fig.
20 is a cross-sectional view showing a longitudinal sectional structure of portion A shown in Figs. 18 and 19. Fig.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

The display device of the present invention can be manufactured on the basis of flat panel display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display (EPD). Hereinafter, a liquid crystal display will be mainly described as an example of the display device, but the present invention is not limited thereto. For example, the display device of the present invention can be fabricated as any flat panel display device in which data voltages and gate voltages (or scan voltages) are applied to the pixels.

1 and 2, the display device of the present invention includes a display panel PNL, a display panel driving circuit, a timing controller (TCON), and the like.

The active area A / A of the display panel PNL displays input image data. The active area A / A includes a pixel array in which pixels are arranged in a matrix form. In the case of a liquid crystal display device, the display panel PNL may be a liquid crystal mode of any known structure such as Twisted Nematic mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS Can be implemented. The display panel PNL includes a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer formed between the substrates. The bezel BZ outside the active area A / A is a non-display area.

The TFT array substrate includes vertical wirings and horizontal wirings. The vertical wirings are formed along the vertical direction (y-axis direction) of the display panel PNL. The horizontal wirings are formed along the horizontal direction (x-axis direction) of the display panel PNL and perpendicular to the vertical wirings. The vertical wirings include vertical data lines (VD), vertical gate lines (VG), and vertical common lines (VC). Data voltages are supplied to the vertical data lines VD, and gate pulses synchronized with the data voltages are supplied to the vertical gate lines VG. A common voltage Vcom is supplied to the vertical common lines VC.

The horizontal wirings include horizontal gate lines (HG) receiving gate pulses through the vertical gate lines (VG). The horizontal gate lines HG are connected to the vertical gate lines VG and are supplied with gate pulses through the vertical gate lines VG.

In the TFT array substrate, TFTs are formed at intersections of vertical data lines (VD) and horizontal gate lines (HG). The TFT supplies the data voltage from the vertical data line VD to the pixel electrode 1 of the liquid crystal cell Clc in response to the gate pulse from the horizontal gate line HG. Each of the liquid crystal cells Clc is driven by the voltage difference between the pixel electrode 1 for charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied. The common electrode 2 of the pixels is connected to the vertical common lines VC. The common voltage Vcom is applied to the common electrode 2 of all the pixels through the vertical common lines VC. The common electrode 2 and the pixel electrode 1 may be formed of a transparent electrode such as ITO (Indium Tin Oxide). The storage capacitor Cst is connected to the pixel electrode 1 of the liquid crystal cell Clc to maintain the voltage of the liquid crystal cell Clc for one frame period. The color filter array substrate includes a color filter and a black matrix. A polarizing plate is attached to each of the color filter array substrate and the TFT array substrate of the display panel (PNL), and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The display panel driving circuit includes a data driving circuit for outputting a data voltage and a gate driving circuit for outputting a gate pulse.

The data driving circuit includes a plurality of source drive ICs (SIC). The source driver IC (SIC) may be mounted on a flexible circuit board such as chip on film (COF), tape carrier packages (TCP), etc., as shown in FIG. Hereinafter, the flexible circuit board will be described as COF, but it is not limited thereto.

The source driver IC (SIC) converts the digital video data to an analog gamma compensation voltage using a digital-to-analog converter (ADC) to generate a data voltage. The input terminals of the COF are connected to the output terminals of the PCB (Printed Circuit Board) through ACF (Anisotropic Conductive Film), and the output terminals of the COF are connected to the TFT array substrate through the ACF at the upper or lower bezel of the display panel The data pad and the link area (12 in Figs. 3 and 18). The output terminals of the COF are connected 1: 1 to data pads formed on the TFT array substrate. The data voltage output from the source drive IC (SIC) is supplied to the vertical data lines (VD) through the output terminal of the COF and the data pad. The common voltage Vcom can be supplied to the vertical common lines VC through the dummy channel of the COF. The dummy channel output terminal of the COF is connected to the output terminal of the DC power supply circuit which is not connected to the source drive IC (SIC) but outputs the common voltage (Vcom). The DC power supply circuit is implemented as a power IC (PIC) including a DC-DC converter (DC-DC converter) and mounted on a PCB. The power IC PIC outputs DC power necessary for driving the display panel PNL such as the common voltage Vcom, the gate high voltage, the gate low voltage, and the gamma reference voltage. The analog gamma compensation voltage is divided from the gamma reference voltage and input to the digital-to-analog converter (DAC) of the source drive IC (SIC).

2 and 3 show an example in which the source drive ICs SIC are connected to the display panel PNL via the COF, a method of connecting the source drive ICs SIC to the display panel PNL is not limited thereto It is not limited. For example, the source drive ICs (SIC) can be directly bonded onto the substrate of the display panel (PNL) by a COG (Chip On Glass) process without COF. In this case, the output terminals of the source drive ICs SIC are directly bonded to the data pad and the link area (12 in Figs. 3 and 18) in the upper or lower bezel of the display panel PNL.

The gate drive circuit includes a level shifter (not shown) and a gate shift register (hereinafter referred to as "GIP S / R").

The level shifter is omitted from the drawing. The level shifter may be implemented with a level shifter disclosed in U.S. Patent Application No. 10-2009-0131289 (Dec. 24, 2009), U.S. Patent No. 8,405,595 (2013/03/26) filed by the applicant of the present invention, but is not limited thereto. The level shifter is provided between the timing controller TCON and the gate shift register GIP S / R and outputs a gate start pulse, a gate shift clock, and n clock signals input from the timing controller TCON as a TTL (Transistor-Transistor- Logic) Level-shifts the logic level voltage to the gate high voltage (Gate High Voltage) and the gate low voltage (Gate High Voltage). The TTL logic level voltage is the voltage swinging between 0V and 3.3V. The gate high voltage and the gate low voltage are set to the operating voltages of the TFTs formed in the shift register (GIP S / R) and the active area (A / A) of the display panel (PNL). For example, the gate high voltage is a voltage of about 15 V or more, and the gate low voltage is a voltage of 0 V or less.

The gate shift register GIR S / R is formed directly on the TFT array substrate of the display panel PNL together with the pixel array of the active area A / A by a gate in panel (GIP) process. The gate shift register (GIP S / R) includes a plurality of stages connected in a dependent manner. The stages of the gate shift register GIP S / R receive the start signal and the clock signal, generate a gate pulse, and sequentially supply the gate pulse to the vertical gate lines VG by shifting the gate pulse in response to the clock signal . The gate shift register (GIP S / R) is formed in the upper or lower bezel of the display panel (PNL) close to the COF in which the source drive IC (SIC) is located, as shown in FIG. Therefore, in the display panel (PNL) of the present invention, the left or right bezel BZ does not include the gate drive IC junction region and the gate link region, so that the size thereof can be minimized.

The timing controller TCON transfers the digital video data of the input image received from the host system SYSTEM to the source drive ICs SIC. The timing controller TCON receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock CLK from the host system SYSTEM. These timing signals are synchronized with the digital video data of the input image. The timing controller TCON includes a source timing control signal for controlling the operation timing of the source drive ICs SIC using the timing signals Vsync, Hsync, DE, and CLK, and a timing control signal for controlling the operation timing of the gate drive circuit And generates a gate timing control signal. The gate timing control signal includes a clock signal. The clock signal is level shifted through the level shifter and can be supplied to the gate shift register (GIP S / R) via the clock signal lines formed on the PCB and the COF.

The host system may be implemented in any one of a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. The host system (SYSTEM) converts digital video data (RGB) of the input image into a format suitable for the display panel (PNL). The host system transmits timing signals (Vsync, Hsync, DE, MCLK) to the timing controller (TCON) together with the digital video data of the input video.

A method of mounting the source drive IC and the gate drive IC together in the COF can be considered. The number of gate lines VG, HG in the display panel PNL is much smaller than the number of vertical data lines VD. Therefore, the number of gate drive ICs required for driving the display panel PNL is smaller than that of the source drive IC. For this reason, the method of mounting the source drive IC and the gate drive IC together in the COF can increase the driving circuit cost by using the gate drive IC more than necessary.

The swing width of the clock signal voltage input to the gate shift register (GIP S / R) is larger than the swing width of the data voltage. Therefore, when the clock signal line crosses the data pad (DPAD in FIG. 4) or the data link (DLINK in FIG. 4) connected to the output terminals of the COF, the clock signal line and the vertical data line VD The data voltage may be distorted by the clock signal voltage. The data pad (DPAD) is connected to the vertical data line (VD) via a data link (DLINK). The data pad contacts the output terminal of the source drive IC (SIC) or the output terminal of the COF to supply the data voltage output from the source drive IC (SIC) to the vertical data line (VD). The data links DLINK connect the output terminals of the COF 1: 1 to the data pads formed at the end of the vertical data line VD. The pitch between the data links DLINK is wider as it approaches the data pads to compensate for the spacing between the output terminals of the COF and the spacing between the data pads.

4, the clock signal line is divided into a clock bus line 11a formed along the horizontal direction (x-axis direction in FIG. 1) and a gate shift register GIP S / R branched from the clock bus line 11a. And extended clock link lines 11b.

In order to realize a narrow bezel and to reduce the driving circuit cost, the present invention provides a method of manufacturing a display device using a GIP process in a top or bottom bezel of a display panel (PNL) close to a source drive IC (SIC) Is formed directly on the substrate. Also, in order to prevent distortion of the data voltage, the present invention separates the clock signal wires from the data pad (DPAD) and the data link (DLINK) according to the method shown in Figs. 3 to 19. Therefore, the clock signal lines 11a and 11b do not cross the data pad (DPAD) and the data link (DLINK) connected to the vertical data line (VD). As a result, the data signal supplied to the display panel PNL through the clock signal lines 11a and 11b and the vertical data line VD is not affected by the clock signal of the gate shift register GIP S / R.

FIGS. 3 and 4 are plan views showing the clock wiring region, the data pad and the link region, and the gate shift resist region by enlarging the A portion of the display panel PNL in FIG. 5 is a cross-sectional view showing a longitudinal sectional structure of part A of the display panel shown in Figs. 3 and 4. Fig.

3 and 5, the upper or lower bezel of the display panel PNL includes a clock wiring area (hereinafter referred to as a "GIP CLK wiring area") 10, a data pad and a link area ≪ / LINK region ") 12, and a gate shift register region (hereinafter referred to as" GIP S / R region ") 14.

The GIP CLK wiring region 10 is a region close to the top or end of the display panel PNL. The GIP CLK wiring region 10 is formed with clock bus lines 11a and clock links 11b branched from the clock bus lines 11a. The clock bus lines 11a are supplied with the clock signals CLK1 to CLK6 necessary for the operation of the gate shift register GIR S / R. The clock bus lines 11a are elongated along the horizontal direction (x-axis direction in Fig. 1) at the upper or lower end of the substrate of the display panel PNL. The clock links 11b branch vertically (in the y axis direction in FIG. 1) from the clock bus lines 11a to connect the clock bus lines 11a to the clock input terminals of the gate shift register (GIP S / R) Lt; / RTI >

The DATA PAD & LINK area 12 is located between the GIP CLK wiring area 10 and the GIP S / R area 14. In the DATA PAD & LINK area 12, data pads DPAD are formed and data links DLINK connected between the data pads DPAD and the vertical data lines VD are formed. The clock links 11b are connected across the DATA PAD & LINK region 12 to the clock input terminals of the gate shift register (GIP S / R).

The GIP S / R area 14 is located between the DATA PAD & LINK area 12 and the active area A / A. In the GIP S / R region 14, a gate shift register (GIP S / R) is formed.

In Fig. 4, SB is a shorting bar temporarily used in the inspection process. The shorting bar (SB) connects data pads (DPAD) in common. The shorting bar SB is connected to a probe pin of a test jig in the inspection process and applies a test signal from the test jig to the vertical data lines VD. The TFT array substrate of the display panel (PNL) is cut along a scribing line (SL). Therefore, after the scribing process, the shot bar SB is separated and removed from the TFT array substrate of the display panel PNL. In Fig. 5, the sealant 22 bonds the color filter array substrate 21 and the TFT array substrate 23 together. "BM" is a black matrix formed on the edge of the color filter array substrate 21.

The gate shift register (GIP S / R) of the present invention can be implemented in various forms. 6 to 8 show an example of the gate shift register (GIP S / R) of the present invention, and it should be noted that the present invention is not limited to this. 6 is a circuit diagram showing an example of a gate shift register (GIP S / R). FIG. 7 is a circuit diagram showing the N-th stage STn in detail in FIG. 8 is a waveform diagram showing the operation of the N-th stage STn shown in FIG.

6 to 8, the gate shift register GIP S / R includes a plurality of stages STn-2 to STn + 2, which are connected in a dependent manner, Lt; / RTI > with the pixel array. The gate shift register (GIP S / R) sequentially supplies gate pulses to the vertical gate lines (VG). The gate shift register GIP S / R is formed on the upper or lower substrate of the display panel PNL close to the source drive IC SIC. The gate shift register GIP S / R operates based on the signals (VST, CLK1 to CLK4, VDD, VDDE, VDDO) swinging between the gate high voltage and the gate low voltage from the level shifter. In Fig. 6, VDD may be set to a gate high voltage as a high-potential power supply voltage. The odd gate high voltage VDDH and the even gate high voltage VDDL are applied to the first and second QB nodes QBO, QNO and QNO in stages STn-2 to STn + 2 of the gate shift register GIP S / QBE of the first and second QB nodes QBO and QBE are periodically inverted so that the DC bias stresses of the pull-down transistors T7O and T7E, (DC gate bias stress). The odd gate high voltage VDDH may be generated at the gate high voltage during the odd frame period (Odd Frame) as shown in FIG. 8 and may be generated at the gate low voltage during the even frame period (Even Frame). The even gate high voltage VDDL may be generated at the gate low voltage during the odd frame period and may be generated at the gate high voltage during the even frame period.

An output of the start pulse VST or the output of the (N-2) th stage STN-2 is inputted as a start pulse VST to the start terminal of the N-th (N is a positive integer) stage STN. The output (VNEXT) of the (N + 2) th stage STN + 2 is input to the reset terminal of the N-th stage STN. A power supply voltage such as a gate high voltage VDD, an odd gate high voltage VDDH, an even gate high voltage VDDL and a gate low voltage VSS is supplied to the N-th stage STN. The N-th stage STN includes a pull-up transistor T6 and pull-down transistors T7O and T7E connected to each other through an output terminal, The QB node QB1 controlling the pull-down transistors T7C and T7D connected to the first output terminal for controlling the Q node Q controlling the transistor T6 and the pull-down transistors T7O and T7E QB2 and transistors Q1 to Q5 for switching the voltage of the Q node QB and the QB nodes QBO and QBE.

The first transistor T1 operates as a diode which supplies the start signal VST or the output of the (n-2) th stage STn-1 to the second transistor T2. The gate electrode and the drain electrode of the first transistor T1 are connected to the start terminal. The source electrode of the first transistor T1 is connected to the drain electrode of the second transistor T2. The second transistor T2 charges the Q node by supplying the voltage of the start signal VST to the Q node Q in response to the first clock signal CLK1. The first clock signal CLK1 is input to the gate electrode of the second transistor T2. The drain electrode of the second transistor T2 is connected to the source electrode of the first transistor T1 and the source electrode of the second transistor T2 is connected to the Q node Q.

The pull-up transistor T6 is turned on when the second clock signal CLK2 is input in the state where the Q node Q is charged and charges the output terminal OUTN with the voltage of the second clock signal CLK2 . The second clock signal CLK2 is input to the drain electrode of the pull-up transistor T6. The gate electrode of the pull-up transistor T6 is connected to the Q node Q and the source electrode of the pull-up transistor T6 is connected to the output terminal OUTN. Thus, the Nth stage STN generates a gate pulse in response to the second clock signal CLK2.

The third transistor T1 discharges the Q node Q in response to the fourth clock signal CLK4. The fourth clock signal CLK4 is input to the gate electrode of the third Q transistor T3Q. The drain electrode of the third Q transistor T3Q is connected to the Q node Q, and its source electrode is connected to the low potential voltage source. The low potential voltage source generates the gate low voltage (VSS).

The third ON transistor T3O is turned on in response to the voltage of the first QB node QBO when the first QB node QBO is charged to discharge the Q node Q. The gate electrode of the third transistor T3O is connected to the first QB node QBO and the drain electrode of the third transistor T3O is connected to the Q node Q. The source electrode of the third transistor (T3O) is connected to the low potential voltage source. The third E transistor T3E is turned on in response to the voltage of the second QB node QBE when the second QB node QBE is charged to discharge the Q node Q. The gate electrode of the third E transistor T3E is connected to the second QB node QBE and the drain electrode of the third E transistor T3E is connected to the Q node Q. [ The source electrode of the third E transistor T3E is connected to the low potential voltage source.

The fourth transistor T4O charges the first QB node QBO in response to the fourth clock signal CLK4 and supplies the first pull-down transistor T7O and the third transistor T3O to the odd gate high voltage VDDH Turn on. The fourth clock signal (CLK4) is inputted to the gate electrode of the fourth transistor (T4O), and the odd gate high voltage (VDDH) is inputted to the drain electrode thereof. The source electrode of the fourth transistor T4O is connected to the first QB node QBO. The fourth E transistor T4E charges the second QB node QBE in response to the fourth clock signal CLK4 and supplies the second pull-down transistor T7E and the third E transistor T3E to the even gate high voltage VDDL Turn on. The fourth clock signal (CLK4) is input to the gate electrode of the fourth E-transistor T4E, and the even gate high voltage (VDDL) is input to the drain electrode thereof. The source electrode of the fourth E transistor T4E is connected to the second QB node QBE. Thus, the fourth transistor T4O charges the first QB node QB in response to the fourth clock signal CLK4 in the odd-numbered frame period. The fourth E transistor T4E charges the first QB node QB in response to the fourth clock signal CLK4 in the odd-numbered frame period.

The fifth transistor (T5O) discharges the first QB node (QBO) in response to the start signal (VST) to turn off the first pull-down transistor (T70) and the third transistor (T3O). A start signal (VST) is input to the gate electrode of the fifth transistor (T5O). The drain electrode of the fifth O transistor T50 is connected to the Q node, and the source electrode thereof is connected to the low potential voltage source. The fifth E transistor T5E responds to the start signal VST to discharge the second QB node QBE to turn off the second pull down transistor T7E and the third E transistor T3E. A start signal VST is input to the gate electrode of the fifth E-transistor T5E. The drain electrode of the fifth E transistor T5E is connected to the Q node, and its source electrode is connected to the low potential voltage source.

The first pull-down transistor T70 is turned on when the first QB node QBO is charged during the odd-numbered frame period to discharge the output terminal OUTN. The gate electrode of the first pull-down transistor T70 is connected to the first QB node QBO. The drain electrode of the first pull-down transistor T70 is connected to the output terminal OUTN and the source electrode of the first pull-down transistor T70 is connected to the low potential voltage source. The second pull-down transistor T7E is turned on when the second QB node QBE is charged during the odd-numbered frame period to discharge the output terminal OUTN. The gate electrode of the second pull-down transistor T7E is connected to the second QB node QBE. The drain electrode of the second pull-down transistor T7E is connected to the output terminal OUTN and the source electrode of the second pull-down transistor T7E is connected to the low potential voltage source.

The vertical gate lines VG and the horizontal gate lines HG are formed of separated metal layers with an insulating layer sandwiched therebetween. For example, the horizontal gate lines HG may be formed of a first metal pattern formed on a TFT array substrate, and the first metal pattern may be covered with an insulating layer. The vertical gate lines VG may be formed of a second metal pattern formed on the insulating layer. The Nth vertical gate line may be connected to the Nth horizontal gate line through a contact hole passing through the insulating layer at the Nth horizontal gate line and the gate contact GC intersected at the Nth horizontal gate line. The number of vertical wirings in the display panel (PNL) is larger than that in the horizontal wirings. Therefore, in the display panel PNL, the gate contact portions GC can be formed in a part of the active array A / A as shown in Figs. 9 to 13.

The gate pulse is delayed due to the resistance R and the parasitic capacitance C of the gate lines VG and HG. As the size of the display panel PNL increases, the length of the gate lines VG and HG becomes larger, so that the RC delay of the gate pulse becomes larger. The present invention is characterized in that the delay of the gate pulse is reduced by double feeding simultaneously applying gate pulses to both sides of one horizontal gate line HG through two vertical gate lines VG as shown in FIGS. You can compensate. The present invention is applicable to a case where a display panel PNL is small or a RC delay of gate lines VG and HG is small, A gate pulse may be applied to the gate electrode HG.

9 to 13 are plan views showing various connection methods of the vertical gate lines VG and the horizontal gate lines HG.

9-12, the first and second gate shift registers GIPS / RA, GIPS / SRB are formed in the upper or lower bezel of the display panel PNL so as to be disposed close to the source drive ICs. . There is a non-GIP area (NGIP) in which there is no gate shift register between the first gate shift register (GIP S / R A) and the second gate shift register (GIP S / SR B). The first group of vertical gate lines VG1a to VG4a and the second group of vertical gate lines VG1a to VG4a are arranged in the left region of the display panel PNL in which the first GIP S / R region in which the first gate shift register GIP S / The data lines VD may be formed. The second group of vertical gate lines (VG1b to VG4b) and the second group of vertical gate lines (VG1b to VG4b) are arranged in the right region of the display panel (PNL) in which the second GIP S / R region in which the second gate shift register The data lines VD may be formed. One vertical gate line VG1a to VG4a belonging to the first group and one vertical gate line VG1b to VG4b belonging to the second group are connected to one horizontal gate line HG1 to HG4 through the left and right gate contact portions GC, HG4 to supply gate pulses to the horizontal gate lines HG1 to HG4 at the same time. Thus, a pair of vertical gate lines apply gate pulses to both sides of one horizontal gate line to compensate for the delay of the gate pulse.

A part of the active area A / A included when the non-GIP area NGIP extends vertically in the active area A / A is a vertical data line VD, A common line (VC), and signal wiring that does not affect other pixels can be formed.

The vertical gate lines VG and the horizontal gate lines HG are connected via the gate contact portion GC. The virtual gate contact line GCL connecting the near gate contact portions GC can be trapezoidal (or inverted V) or V-shaped.

The first gate shift register GIP S / R A sequentially supplies gate pulses to the vertical gate lines VG1a to VG4a disposed on the left side of the display panel PNL. At the same time, the second gate shift register GIPS / RB is controlled by the timing controller TCON in synchronization with the first gate shift register GIP S / (VG1a to VG4a). 10, after the gate pulses are simultaneously applied to both sides of the first horizontal gate line HG1 through the first pair of vertical gate lines VG1a and VG1b, the second pair of vertical gate lines VG2a and VG2b A gate pulse is simultaneously applied to the second horizontal gate line HG2. Subsequently, gate pulses are simultaneously applied to both sides of the third horizontal gate line HG3 through the third pair of vertical gate lines VG3a and VG3b, and then the fourth horizontal line pair VG4a and VG4b is applied Gate pulses are simultaneously applied to the gate line HG4.

Referring to FIG. 11, first and second non-GIP regions 44a and 44b are secured at the left and right upper ends (or lower ends) of the display panel PNL. First and second gate shift registers GIP S / R A and GIP S / R B are formed in the GIP S / R region 42 between the first and second non-GIP regions 44a and 44b. The gate contact lines GCL may be formed in an inverted V shape extending from the upper end to the lower end of the display panel PNL. The first and second gate shift registers GIPS / RA and GIPS / RB apply a gate pulse to the horizontal gate line through a pair of vertical gate lines to compensate for the delay of the gate pulse, And is shifted along a predetermined scanning direction. The vertical gate lines are formed in the active region A / A extending vertically without forming the GIP S / R region 42 in the active region A / A extending vertically from the non-GIP regions 44a and 44b. do.

Referring to FIG. 12, first and second non-GIP regions 48a and 48b are secured on the left and right upper ends (or lower ends) of the display panel PNL. First and second gate shift registers GIP S / R A and GIP S / R B are formed in the GIP S / R region 46 between the first and second non-GIP regions 48a and 48b. The gate contact lines GCL may be formed in a V-shape that becomes narrower from the upper end to the lower end of the display panel PNL. The first and second gate shift registers GIPS / RA and GIPS / RB apply a gate pulse to the horizontal gate line through a pair of vertical gate lines to compensate for the delay of the gate pulse, And is shifted along a predetermined scanning direction. The vertical gate lines are formed in the active region A / A extending vertically without forming the GIP S / R region 46 in the active region A / A vertically extending the non-GIP regions 48a and 48b. do.

Referring to FIG. 13, a non-GIP area 54 is secured at the left or right upper end (or lower end) of the display panel PNL. A gate shift register GIP S / R is formed in the GIP S / R area 52 secured at the top of the display panel PNL except for the non-GIP area 54. [ The vertical gate lines and the horizontal gate lines are connected 1: 1 through the gate contact portion (GC). A gate shift register (GIP S / R) sequentially supplies gate pulses to the vertical gate lines. The vertical gate lines are formed in the active region A / A extending vertically from the GIP S / R region 52 without being formed in the active region A / A vertically extending the non-GIP region 54.

The present invention can form an active area A / A in a pixel array as shown in Fig. 14 in order to reduce the number of vertical wirings in the active area A / A and reduce the power consumption of the source driver IC (SIC). It should be noted that the pixel array structure of the present invention is not limited to Fig. 14, PIX1 to PIX16 are pixel electrodes. T1 to T16 are TFTs.

Referring to FIGS. 14 and 15, there is only one vertical wiring between the pixels neighboring in the horizontal direction. For example, only the first vertical gate line VG1 is disposed between the first and second pixel electrodes PIX1 and PIX2, and the second vertical data VIX is provided between the second and third pixel electrodes PIX2 and PIX3. Only the line VD2 is disposed. The method of arranging the vertical wirings can reduce the width of the black matrix formed between neighboring pixels in the horizontal direction.

The present invention minimizes the flicker by inverting the polarity of the data voltage in the form of a dot inversion in the pixel array using the pixel array as shown in FIG. 14, and outputs the data through the output channels of the source drive IC (SIC) Since the polarity of the output voltage is not changed, the power consumption and heat generation of the source drive IC (SIC) can be reduced. The source driver IC SIC outputs a data voltage maintained at a first polarity through odd-numbered output channels during the odd-numbered frame period, and a data voltage maintained at a second polarity through odd-numbered output channels. Then, the source driver IC (SIC) outputs the data voltage maintained at the second polarity through the odd-numbered output channels during the odd-numbered frame period, and the data voltage maintained at the first polarity through the odd- Output. Thus, the source driver IC (SIC) is a column inversion that inverts the polarity of the data voltages output through neighboring output channels without inverting the polarity of the data voltages output through a particular output channel during one frame period. Circuit.

The first and second pixels horizontally adjacent to each other with the first vertical gate line VG1 therebetween in the first horizontal line of the display panel PNL are connected to the first vertical data line VD1 through the first vertical data line VD1. Charge the data voltage continuously. The first pixel charges the data voltage (+ R) of the first polarity through the first TFT (T1), and the second pixel supplies the data voltage (+ G) of the first polarity through the second TFT Charge. The third and fourth pixels horizontally adjacent to each other with the third vertical gate line VG3 therebetween in the first horizontal line of the display panel PNL are connected to the second vertical data line VD2 through the second vertical data line VD2. Charge the data voltage continuously. The fourth pixel charges the data voltage -R of the second polarity through the fourth TFT T4 and then the third pixel supplies the data voltage -B of the second polarity through the third TFT T3 Charge. The fifth and sixth pixels horizontally adjacent to each other with the fifth vertical gate line VG5 therebetween in the first horizontal line of the display panel PNL are connected to the first vertical data line VD1, Charge the data voltage continuously. The sixth pixel charges the data voltage (+ B) of the first polarity through the sixth TFT (T6), and the fifth pixel supplies the data voltage (+ G) of the first polarity through the fifth TFT Charge. The seventh and eighth pixels horizontally adjacent to each other with the first vertical common line (VC) therebetween in the first horizontal line of the display panel (PNL) are connected to the first vertical line Charge the data voltage continuously. The seventh pixel charges the data voltage (-R) of the second polarity through the seventh TFT (T7), and the eighth pixel supplies the data voltage (-G) of the second polarity through the eighth TFT (T8) Charge.

The ninth and tenth pixels horizontally adjacent to each other with the first vertical gate line VG1 therebetween in the second horizontal line of the display panel PNL are connected to the second vertical data line VD2 through the second vertical data line VD2. Charge the data voltage continuously. The ninth pixel charges the data voltage -R of the second polarity through the ninth TFT T9 and then the tenth pixel supplies the data voltage -G of the second polarity through the tenth TFT T10 Charge. The eleventh and twelfth pixels horizontally adjacent to each other with the third vertical gate line VG3 therebetween in the second horizontal line of the display panel PNL are connected to the first vertical data line VD1, Charge the data voltage continuously. The twelfth pixel charges the data voltage (+ R) of the first polarity through the twelfth TFT (T12), and then the eleventh pixel supplies the data voltage (+ B) of the first polarity through the eleventh TFT Charge. The thirteenth and fourteenth pixels horizontally adjacent to each other with the fifth vertical gate line VG5 therebetween in the second horizontal line of the display panel PNL are connected to the first vertical data line VD2 of the second polarity Charge the data voltage continuously. The fourteenth pixel charges the data voltage -B of the second polarity through the fourteenth TFT T14 and then the thirteenth pixel charges the data voltage G of the second polarity through the thirteenth TFT T13 Charge. The fifteenth and sixteenth pixels horizontally adjacent to each other with the first vertical common line (VC) therebetween in the second horizontal line of the display panel (PNL) are connected to the first vertical data line Charge the data voltage continuously. The fifteenth pixel charges the data voltage (+ R) of the first polarity through the fifteenth TFT (T15) and then the sixteenth pixel supplies the data voltage (+ G) of the first polarity through the sixteenth TFT Charge.

16 is a cross-sectional view showing a cross-sectional structure of a pixel array. 17 is a cross-sectional view showing a cross-sectional structure of the GIP CLK wiring region taken along the line "I-I" in Fig. 16 illustrates the TFT array substrate structure of the FFS mode. However, it should be noted that the liquid crystal display device of the present invention can be implemented in any liquid crystal mode as shown in FIG. 1, and thus is not limited to the FFS mode.

Referring to FIG. 16, gate metal patterns GM are formed on a substrate SUBS. The gate metal patterns GM include horizontal gate lines HG, gate pads GPAD, data pads DPAD, and clock signal lines 11a and 11b of Fig. The gate metal patterns GM can be at least one of copper (Cu), aluminum (Al), molybdenum (Mo) or a double metal layer of Cu / MoTi. Gate pads GPAD are connected 1: 1 to the vertical gate lines VG through the contact holes and 1: 1 to the output terminals of the gate shift register GIP S / R. Data pads GPAD are 1: 1 connected to the vertical data lines VD through contact holes and 1: 1 connected to the output terminals of the source drive IC (SIC).

A gate insulating film GI is covered on the gate metal patterns GM and a semiconductor active pattern ACT is formed on the gate insulating film GI. Source-drain metal patterns SDM are formed on the semiconductor active pattern ACT. . The semiconductor active pattern (ACT) and the source-drain metal patterns (SDM) are simultaneously patterned and stacked in the same form. The source-drain metal patterns SDM include vertical data lines VD, vertical gate lines VG, and vertical common lines VC. The source-drain metal patterns SDM may be formed of at least one of copper (Cu), aluminum (Al), and molybdenum (Mo).

The first passivation layer PAS1 is formed on the gate insulating layer GI so as to cover the source-drain metal patterns SDM and the thick organic protective layer PAC is formed on the first passivation layer PAS1 . The first passivation layer PAS1 may be formed of an inorganic insulating film such as silicon nitride (SiNx). The organic protective layer (PAC) may be formed of photo-acryl. The first passivation layer PAS1 generates a leakage current when the organic passivation layer PAC and the semiconductor active pattern are in direct contact with each other, so that the first passivation layer PAS1 intercepts the leakage current. Transparent electrode patterns are formed on the organic protective film (PAC). The transparent electrode patterns are formed of a transparent conductive material such as ITO (Indium Tin Oxide), and include a common electrode (COM (ITO)) and a link pattern (not shown). The common electrode COM (ITO) is connected to the vertical common line VC through a contact hole exposing the vertical common line VC through the organic passivation layer PAC and the first passivation layer PAS1. The common electrode COM (ITO) forms the fringe field with the pixel electrodes PIX (ITO). The link pattern includes a contact hole exposing the vertical gate line VG3 through the organic passivation layer PAC and the first passivation layer PAS1 and a contact hole exposing the organic passivation layer PAS and the first passivation layer PAS1 and the gate insulating layer GI And connects the vertical gate line VG and the horizontal gate line HG through the contact hole exposing the horizontal gate line HG. A second passivation layer PAS2 is formed on the transparent electrode patterns, and pixel electrodes PIX (ITO) are formed thereon with transparent electrode patterns. The second passivation layer PAS2 may be formed of an inorganic insulating film such as silicon nitride (SiNx).

In Fig. 4, the shorting bar SB may be formed of a transparent electrode pattern (ITO (SB)). The shorting bar (SB) is separated along the scribing line (SL) after the inspection process and has no influence on the clock signal lines or the data voltage since no signal is applied. Further, the shorting bar SB has a small dielectric constant epsilon and overlaps the clock signal lines 11a and 11b with a thick organic protective film PAC therebetween, so that it does not affect the clock signal lines 11a and 11b . In Fig. 4, the shorting bar (SB) can be omitted.

Figs. 18 and 19 are plan views showing another embodiment of the A portion of the display panel PNL in Fig. 20 is a cross-sectional view showing a longitudinal sectional structure of portion A shown in Figs. 18 and 19. Fig.

18-20, the upper or lower bezel of the display panel PNL includes a GIP CLK wiring area 10, a DATA PAD & LINK area 12, and a GIP S / R area 14.

The GIP CLK wiring region 10 is a region close to the top or end of the display panel PNL. The GIP CLK wiring region 10 is formed with clock bus lines 11a and clock links 11b branched from the clock bus lines 11a. The clock bus lines 11a are supplied with the clock signals CLK1 to CLK6 necessary for the operation of the gate shift register GIR S / R. The clock bus lines 11a are elongated along the horizontal direction (x-axis direction in Fig. 1) at the upper or lower end of the substrate of the display panel PNL. The clock links 11b branch vertically (in the y axis direction in FIG. 1) from the clock bus lines 11a to connect the clock bus lines 11a to the clock input terminals of the gate shift register (GIP S / R) Lt; / RTI >

The GIP S / R area 14 is located between the GIP CLK wiring area 10 and the DATA PAD & LINK area 12. In the GIP S / R region 14, a gate shift register (GIP S / R) is formed.

The DATA PAD & LINK area 12 is located between the GIP S / R area 14 and the active area A / A. In the DATA PAD & LINK area 12, data pads DPAD are formed and data links DLINK connected between the data pads DPAD and the vertical data lines VD are formed.

The embodiments of Figs. 18 to 20 can minimize the left and right bezels of the display panel PNL and separate the clock signal lines 11a and 11b from the data links DLINK and the vertical data lines VD It is possible to prevent the distortion of the data voltage due to the clock signal.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

PNL: display panel 10: display panel drive circuit
12: timing controller 14: host system
VD: vertical data line VG: vertical gate line
VC: vertical common line HG: horizontal gate line

Claims (7)

A display panel including a pixel array including vertical data lines, vertical gate lines, and horizontal gate lines connected to the vertical gate lines, the pixels being arranged in a matrix;
A data driving circuit for supplying a data voltage to the vertical data lines; And
And a gate driving circuit formed directly on the substrate of the display panel to supply gate pulses to the vertical gate lines. The method according to claim 1,
The gate drive circuit includes:
And a gate shift register for receiving a start signal and a clock signal and generating a gate pulse and shifting the gate pulse in response to the clock signal. 3. The method of claim 2,
And a clock wiring for supplying the clock signal to the gate driving circuit is formed on the substrate of the display panel. The method of claim 3,
Wherein the upper or lower bezel of the display panel includes a clock wiring region, a data pad and a link region, and a gate shift register region,
Wherein the clock wiring region includes clock bus lines in a horizontal direction in which the clock signal is supplied and a clock link branched vertically from the clock bus lines, the clock link region being located in an area close to an upper end or an end of the display panel,
The data pad and the link region including a data link and a data pad connected between the clock wiring region and the gate shift register region to the vertical data lines,
Wherein the gate shift register region comprises the gate shift register formed between the data pad and the link region and the pixel array,
Wherein the clock links are coupled to the gate shift register across the data pad and the link region. The method of claim 3,
Wherein the upper or lower bezel of the display panel includes a clock wiring region, a data pad and a link region, and a gate shift register region,
Wherein the clock wiring region includes clock bus lines in a horizontal direction in which the clock signal is supplied and a clock link branched vertically from the clock bus lines, the clock link region being located in an area close to an upper end or an end of the display panel,
Wherein the gate shift register region comprises the gate shift register formed between the clock wiring region and the data pad and the link region,
The data pad and the link region including a data link and a data pad connected between the gate shift register region and the pixel array to the vertical data lines,
And the clock links are connected to the gate shift register. The method according to claim 4 or 5,
The data driving circuit
A source drive IC (Integrated Circuit) for outputting the data voltage; And
A chip on film (COF) on which the source drive IC is mounted,
And the output terminals of the COF are bonded to the data pad and the link region in the upper or lower bezel of the display panel. The method according to claim 4 or 5,
The data driving circuit
And a source drive IC (Integrated Circuit) for outputting the data voltage,
The source drive IC is directly bonded on the substrate at the upper or lower bezel of the display panel,
And the output terminals of the source drive IC are bonded to the data pad and the link region in the upper or lower bezel of the display panel.

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