KR20200060941A - Organic Light Emitting Diode display panel - Google Patents

Abstract

The present invention relates to an OLED display panel having a GIP of a gate driving circuit arranged in a pixel array, and capable of improving definition by reducing coupling between the GIP and a pixel. The OLED display panel comprises: a display area where data lines and gate lines cross each other, and sub-pixels arranged in a crossing portion are included; and a plurality of stages which are distributed and arranged in unit pixel areas driven by each gate line inside the display area so as to supply scan pulses to a corresponding gate line, wherein a unit pixel area includes at least three sub-pixel units, a GIP unit where GIP elements forming the stages are arranged, and a GIP internal connection wiring unit where connection wires connecting the GIP elements are arranged, and a shielding line, to which power supply voltage is applied, is arranged between the at least three sub-pixel units and the GIP unit.

Description

OLED display panel {Organic Light Emitting Diode display panel}

The present invention relates to an OLED display panel in which a GIP of a gate driving circuit is disposed in a pixel array, and image quality can be improved by reducing coupling between a GIP and a pixel.

As the information society develops and various portable electronic devices such as mobile communication terminals and notebook computers develop, the demand for a flat panel display device that can be applied thereto is gradually increasing.

As such a flat panel display, an OLED display using a liquid crystal display (LCD) using liquid crystal and an organic light emitting diode (OLED) is used.

These flat panel display devices include a display panel having a plurality of gate lines and a plurality of data lines to display an image, and a driving circuit for driving the display panel.

Among the display devices described above, a sub-pixel is defined by intersecting the plurality of gate lines and a plurality of data lines in the display panel of the OLED display device, and each sub-pixel is between an anode and a cathode and between the anode and the cathode. It has an OLED composed of an organic light emitting layer and a pixel circuit that independently drives the OLED.

The pixel circuit may be variously configured, but includes at least one switching TFT, a capacitor, and a driving TFT.

The at least one switching TFT charges the data voltage to the capacitor in response to the scan pulse. The driving TFT controls the amount of current supplied to the OLED according to the data voltage charged in the capacitor to adjust the amount of light emitted from the OLED.

The display panel for the display device is defined as an active area (AA) that provides an image to a user and a non-active area (NA) that is a peripheral area of the display area (AA).

In addition, the driving circuit for driving the display panel includes a gate driving circuit that sequentially supplies gate pulses (or scan pulses) to the plurality of gate lines of the display panel, and the plurality of data lines of the display panel. It comprises a data driving circuit for supplying a data voltage to the field, a timing controller for supplying image data and various control signals to the gate driving circuit and the data driving circuit.

The gate driving circuit may be composed of at least one gate drive IC, but the display panel is not displayed in the process of forming the plurality of signal lines (gate lines and data lines) and sub pixels of the display panel. It can be formed on the region at the same time.

That is, a gate-in-panel (hereinafter, also referred to as "GIP") method that directly applies the gate driving circuit to the display panel is applied.

The gate driving circuit as described above is configured to include a plurality of stages or more of the number of gate lines to sequentially supply scan pulses to each gate line, and uses oxide semiconductor thin film transistors to improve driving characteristics. .

That is, the gate driving circuit includes a plurality of stages that are connected to each other. Then, each stage is connected to each gate line, an output unit that receives a clock signal, a gate start signal, a gate high voltage and a gate low voltage applied from the timing controller, and generates one carry pulse and one scan pulse Includes.

As described above, since the conventional gate driving circuit is directly integrated into the non-display area of the display panel, it is difficult to design a narrow bezel of the flat panel display device.

The present invention is to solve the conventional problems as described above, it is possible to minimize the bezel and place the GIP in the display area of the display panel regardless of the bezel shape, and when the GIP is disposed in the display area, the GIP and the pixel couple An object of the present invention is to provide an OLED display panel capable of improving image quality by reducing a ring and an OLED display device using the same.

An OLED display panel according to an exemplary embodiment of the present invention for achieving the above object includes: a display area including data pixels and gate lines intersecting and sub-pixels disposed at the intersection; And a plurality of stages that are distributedly disposed in unit pixel areas driven by each gate line in the display area to supply a scan pulse to the corresponding gate line, wherein the unit pixel area includes at least three sub-pixel units, and A GIP unit in which the GIP elements constituting the stage are disposed, and a GIP internal connection wiring unit in which connection wires connecting the GIP elements are disposed, and a power voltage is applied between the at least three sub-pixel units and the GIP unit It is characterized by the fact that the shielding line is arranged.

The shielding line is characterized in that it is arranged not only between the at least three sub-pixel units and the GIP unit, but also to surround the GIP unit.

The shielding line is characterized in that it is arranged not only between the at least three sub-pixel units and the GIP unit, but also to surround the at least three sub-pixel units, the GIP unit, and the GIP internal connection wiring unit.

The shielding line is characterized in that it is formed of at least one of a light blocking layer, a gate electrode metal, and a source/drain electrode metal of the OLED display panel.

A driving TFT is disposed in the at least three sub-pixel portions, a GIP TFT is disposed in the GIP portion, a light shielding layer is disposed on the substrate under the driving TFT, and a clock signal line is formed on the substrate under the GIP TFT. The shielding line is formed of the same metal as the light blocking layer and the clock signal line.

A driving TFT is disposed in the at least three sub-pixel portions, a GIP TFT is disposed in the GIP portion, a light shielding layer is disposed on the substrate under the driving TFT, and a clock signal line is formed on the substrate under the GIP TFT. It is disposed, and the shielding line is formed of the same metal as the gate electrode of the driving TFT and the gate electrode of the GIP TFT.

A driving TFT is disposed in the at least three sub-pixel portions, a GIP TFT is disposed in the GIP portion, a light shielding layer is disposed on the substrate under the driving TFT, and a clock signal line is formed on the substrate under the GIP TFT. The shielding line is formed of the same metal as the source/drain electrode of the driving TFT and the source/drain electrode of the GIP TFT.

A driving TFT is disposed in the at least three sub-pixel portions, a GIP TFT is disposed in the GIP portion, a light shielding layer is disposed on the substrate under the driving TFT, and a clock signal line is formed on the substrate under the GIP TFT. The shielding line is formed of a first metal layer formed of the same metal as the light blocking layer and the clock signal line, and a source/drain electrode of the driving TFT and a source/drain electrode of the GIP TFT. It is characterized in that the second metal layer is laminated.

A driving TFT is disposed in the at least three sub-pixel portions, a GIP TFT is disposed in the GIP portion, a light shielding layer is disposed on the substrate under the driving TFT, and a clock signal line is formed on the substrate under the GIP TFT. The shielding line includes a third metal layer formed of the same metal as the gate electrode of the driving TFT and the gate electrode of the GIP TFT, a source/drain electrode of the driving TFT, and a source/drain electrode of the GIP TFT. It is characterized in that a second metal layer formed of the same metal is stacked.

In the display area, touch sensors are further arranged.

It is characterized in that a constant voltage line for supplying a constant voltage (EVDD) to the display panel is disposed between one or both sides of the unit pixel area and the at least three sub-pixel units and the GIP unit.

The OLED display panel according to the present invention having the above characteristics has the following effects.

Since the GIP elements constituting the stage of the gate driving circuit are distributedly disposed in the unit pixel, at least one stage is disposed in the unit pixels driven by one scan line, thereby minimizing left and right bezels of the display panel.

Since the GIP elements constituting the stage of the gate driving circuit are distributedly disposed in the unit pixel, and the GIP element is shielded with a power supply (EVDD) line, or the unit pixel region is shielded with a power supply (EVDD) line. Coupling between sub-pixel units can be prevented.

In addition, when the GIP elements constituting the stage of the gate driving circuit are distributedly distributed within the unit pixel, a coupling phenomenon is relatively large in the unit pixel in which the GIP element to which the clock signal CLK is applied is disposed, and the clock signal ( Since the coupling phenomenon is relatively small in the unit pixel where the GIP element to which CLK) is not applied is disposed, this causes a luminance deviation between the unit pixel regions. However, as described above, since it is shielded by the power supply (EVDD) line, coupling between the GIP element and at least three sub-pixel sub-pixel regions is prevented, thereby reducing the luminance deviation of the pixel regions.

In addition, since the effective design area can be increased more than when the GIP element is designed to be spaced apart from the pixel region, the aperture ratio can be increased and the drop of the power source EVDD can be reduced.

In addition, since the GIP device is shielded or the unit pixel area is shielded using the power supply (EVDD) line, the power supply (EVDD) inside the panel can be uniformly supplied.

1 is a block diagram schematically showing an OLED display device according to an exemplary embodiment of the present invention.
FIG. 2 is a circuit diagram of one sub-pixel in the OLED display of FIG. 1.
3 is a circuit diagram of the (n)-th stage according to the present invention
4 is a diagram illustrating a display area of a display panel according to an exemplary embodiment of the present invention.
FIG. 5 is a configuration diagram more specifically showing two adjacent unit pixels arranged in a display area of the display panel of FIG. 4.
6 is a diagram illustrating a unit pixel configuration of a display panel in which a shielding line according to the present invention is additionally disposed;
7 is a structural cross-sectional view of a display panel in which a shielding line according to the first embodiment of the present invention is additionally disposed.
8 is a structural cross-sectional view of a display panel in which a shielding line according to a second embodiment of the present invention is additionally disposed.
9 is a structural cross-sectional view of a display panel in which a shielding line according to a third embodiment of the present invention is additionally disposed
10 is a structural cross-sectional view of a display panel in which a shielding line according to a fourth embodiment of the present invention is additionally disposed.
11 is a structural cross-sectional view of a display panel in which a shielding line according to a fifth embodiment of the present invention is further disposed
12 is a graph of a coupling phenomenon occurring between the GIP unit 31 and at least three sub-pixel units R, G, B, and W 33 according to the present invention

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present invention to be complete, and those skilled in the art to which the present invention pertains. It is provided to fully inform the scope of the invention to the present invention, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present invention are exemplary, and the present invention is not limited to the details shown in the drawings. Throughout the specification, the same reference numerals refer to substantially the same components. In addition, in the description of the present invention, when it is determined that detailed descriptions of related known technologies may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

When "equipped", "includes", "haves", "consists of" and the like referred to herein are used, other parts may be added unless'~ only' is used. When a component is expressed in singular, it may be interpreted in plural unless otherwise specified.

In interpreting the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, when the positional relationship between the two components is described as'on the top','on the top','on the bottom','on the side', ' One or more other components may be interposed between those components for which no'direct' or'direct' is used.

First, second, etc. may be used to classify the components, but the functions or structures of these components are not limited by the ordinal number or the name of the component before the component.

The following embodiments may be partially or totally combined or combined with each other, and technically various interlocking and driving are possible. Each of the embodiments may be implemented independently of each other, or may be implemented together in an association relationship.

The circuit of the GIP and the circuit of the sub-pixel according to the present invention may be implemented with an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) TFT. It should be noted that although the n-type TFT is illustrated in the following examples, the present invention is not limited thereto. TFT is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the TFT, carriers begin to flow from the source. The drain is an electrode through which the carrier exits from the TFT. That is, the carrier flow in the MOSFET flows from the source to the drain. In the case of the n-type MOSFET (NMOS), since the carrier is electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In the n-type MOSFET, electrons flow from source to drain, so the direction of current flows from drain to source. In the case of the p-type TFT (PMOS), the source voltage is higher than the drain voltage so that holes can flow from the source to the drain because the carrier is a hole. In the p-type TFT, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET can be changed according to the applied voltage. In the following embodiments, transistors constituting the GIP circuit and the pixel circuit are illustrated as n-type TFTs, but are not limited thereto. Therefore, in the following description, the invention should not be limited due to the source and drain of the TFT.

The gate pulse output from the GIP circuit swings between the gate on voltage (Gate High Voltage, VGH) and the gate off voltage (Gate Low Voltage, VGL). The gate-on voltage VGH is set to a voltage higher than the threshold voltage of the TFT, and the gate-off voltage VGH is set to a voltage lower than the threshold voltage of the TFT. In the case of the n-type TFT, the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In the case of the p-type TFT, the gate-on voltage may be a gate low voltage (VGL), and the gate-off voltage may be a gate high voltage (VGH).

1 is a block diagram schematically showing an OLED display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the OLED display device according to the present invention includes a display panel PNL and a driving circuit for providing image data to the display panel PNL.

The display area AA of the display panel PNL crosses a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn, and the data lines DL1 to DLm. And a plurality of sub-pixels arranged in a matrix form by the plurality of gate lines GL1 to GLn. Touch sensors may be further disposed in the display area AA of the display panel PNL.

The plurality of sub-pixels include red (R), green (G), and blue (B) sub-pixels for color implementation, and the red (R), green (G), and blue (B) sub-pixels In addition to the pixels, a white (W) sub-pixel may be further included.

The red (R), green (G), and blue (B) sub-pixels constitute one unit pixel, or the red (R), green (G), blue (B), and white (W) sub-pixels These constitute one unit pixel.

In addition, GIP elements (TFT, capacitor, etc.) constituting the stage of the gate driving circuit are distributedly disposed in the unit pixel regions.

That is, at least one GIP element (TFT, capacitor, etc.) constituting the stage of the gate driving circuit is distributedly disposed in a plurality of unit pixel areas disposed in each gate line. Of course, a plurality of GIP elements (TFT, Capacitor, etc.) may be distributedly disposed in a plurality of unit pixel areas disposed in each gate line. The method of arranging the GIP elements constituting the stage of the specific gate driving circuit will be described later.

The driving circuit includes a data driving circuit that supplies an image data voltage to the data lines DL1 to DLm of the display panel PNL, and gate lines of a scan pulse synchronized with the image data voltage. And a gate driving circuit supplied to (GL1 to GLn), and a timing controller (T-CON) for controlling the operation timing of the data driving circuit and the gate driving circuit.

The data driving circuit may include one or more source drive ICs (SICs). The source drive IC (SIC) converts digital video data of an input image into an analog gamma compensation voltage under the control of the timing controller (T-CON) to generate a data voltage and converts the data voltage to data lines (DL1 to DLm). Output as The source drive IC (SIC) may be mounted on a flexible circuit board that can be bent, for example, mounted on a chip on film (COF), or directly adhered to a substrate in a non-display area of the display panel PNL by a COG process. .

The COFs are bonded to a pad region of the lower substrate SUBS1 of the display panel PNL and a source PCB (SPCB) through an anisotropic conductive film (ACF). The input pins of the COFs are electrically connected to the output terminals (pads) of the source PCB (SPCB). The output pins of the source COFs COF are electrically connected to data pads formed on the substrate of the display panel PNL through ACF.

The gate driving circuit receives a start pulse (VST), a clock signal (CRCLK, SCCLK), a gate high voltage (VGH), a gate low voltage (VGL), etc. from the timing controller (T-CON), and each gate line ( GL1 to GLn) include a plurality of stages that sequentially output scan pulses. The plurality of stages sequentially supply scan pulses synchronized with the data voltage to each of the gate lines GL1 to GLn under the control of the timing controller T-CON, thereby applying one line of pixels to which the image data voltage is applied. Choose.

The timing controller T-CON is mounted on a control PCB (CPCB), and the control PCB (CPCB) and the source PCB (SPCB) are connected by a flexible flat cable (FFC).

The circuit configuration of one sub-pixel in the OLED display device according to the present invention and one stage configuration of the gate driving circuit according to the present invention are as shown in FIGS. 2 and 3.

2 is a circuit diagram of one sub-pixel in the OLED display of FIG. 1, and FIG. 3 is a circuit diagram of a (k)-th stage of the gate driving circuit according to the present invention.

Each sub-pixel of the OLED display device according to the present invention includes an organic light emitting diode (OLED) and a pixel circuit for driving the organic light emitting diode, as shown in FIG. 2.

The pixel circuit includes first and second switching TFTs T1 and T2, a storage capacitor Cst, and a driving TFT DT.

The first switching TFT T1 charges the data DATA voltage to the storage capacitor Cst in response to the scan pulse Scan. The driving TFT DT controls the amount of light emitted from the OLED by controlling the amount of current supplied to the OLED according to the data voltage charged in the storage capacitor Cst. The second switching TFT T2 senses a threshold voltage and mobility of the driving TFT DT in response to a sensing signal.

The organic light emitting diode (OLED) may be formed of a first electrode (eg, an anode or cathode), an organic light emitting layer, a second electrode (eg, a cathode or anode), or the like.

 The storage capacitor Cst is electrically connected between a gate electrode and a source electrode of the driving TFT DT, and a data voltage corresponding to an image signal voltage or a voltage corresponding thereto is maintained for one frame time. I can keep it.

2 illustrates the configuration of a 3T1C sub-pixel composed of three TFTs (T1, T2, DT) and one storage capacitor (Cst), but is not limited thereto, and each sub-pixel of the OLED display device according to the present invention It may have sub-pixels such as 4T1C, 4T2C, 5T1C, and 5T2C.

On the other hand, the circuit of the (k)-th stage (GIP(k)) according to the present invention, as shown in Figure 3, the transistors (TA, TB, T3qA, T1B, T1C, T5A, T5B) and the capacitor (C1) It is configured to include, and selectively stores the set signal (CP(k)) according to the line select signal (LSP; Line select pulse), and a real-time compensation signal (VRT; Vertical) in the blank period of the stage. Blank section first and second nodes Q and Qb charging the first node Q with the first constant voltage GVDD and discharging the second node Qb with the second constant voltage GVSS2 according to real time) Control units 21 and 26; Transistors (T1, T1A, T3n, T3nA, T3q, T3, T3A, T5) is configured to include the stage in the driving section in accordance with the third front carry pulse (CP (k-3)) according to the first node ( Q) is charged with the carry pulse (CP(k-3)) voltage, and the first node Q and the third node Qh are removed according to the third rear carry pulse CP(k+3). 2 The first to third node control units 23 and 25 that discharge with a constant voltage GVSS2 and charge a third node Qh with the first constant voltage GVDD according to the voltage of the first node Q ); An inverter unit 24 including transistors T4, T4l, T4q, T5q and a capacitor C2 to invert the voltage of the first node Q and apply it to the second node Qb; It is composed of pull-up transistors (T6cr, T6) and pull-down transistors (T7cr, T7) and bootstrapping capacitor (C3), and one clock signal (CRCLK(k)) and multiple scans of a plurality of clock signals for carry pulse output. Receive a clock signal (SCCLK(k)) of one of the clock signals for pulse output, and carry pulses CP(k) and scan pulses SP according to the voltages of the first node Q and the second node Qb an output buffer unit 27 for outputting (k)); Then, the first node (Q) is configured as a second constant voltage (GVSS2) according to the reset signal (RST) output from the timing controller is configured to include the transistors (T3nB, T3nC) in the blank period (Blank time) It is provided with a reset portion 22 for discharging.

The blank section first and second node (Q, Qb) control unit (21, 26) is the transistor (TA, TB, T3q) is turned on when the line selection signal (LSP) is a high level set signal ( CP(k)) is stored in the capacitor C1.

Further, when the real-time compensation signal VRT is at a high level in the blank period, the transistors T1C and T5B are turned on to charge the first node Q with a first constant voltage GVDD, and The second node Qb is discharged to the second constant voltage GVSS2.

The first to third node controllers 23 and 25 of the driving section turn on the transistors T1, T1A, and T5 when the carry pulse CP(k-3) of the third preceding stage is at a high level in the driving section. -On to charge the first node Q with the voltage of the carry pulse CP(k-3) of the third front end and discharge the second node Qb with the second constant voltage GVSS2. As described above, when the first node Q is charged and the second node Qb is discharged, the transistor T3q is turned on to charge the third node Qh with a first constant voltage GVDD. .

The transistors T3n and T3nA are turned on when the third rear carry pulse CP(k+3) is at a high level to turn on the first node Q and the third node Qh. Discharge with constant voltage (GVSS2).

The inverter unit 24 inverts the voltage of the first node Q and applies it to the second node Qb.

In the output buffer unit 27, when the first node Q is at a high level and the second node Qb is at a low level, the pull-up transistor T6cr is turned on and the pull-down transistor T7cr is turned on. -Off to output one clock signal CRCLK(k) of the plurality of clock signals for carry pulse output as a carry pulse CP(k). In addition, when the first node Q is at a high level and the second node Qb is at a low level, the pull-up transistor T6 is turned on and the pull-down transistor T7 is turned off to scan the plurality of scans. One of the clock signals for pulse output (SCCLK(k)) is output as a scan pulse (SP(k)).

At this time, when the clock signal SCCLK(k) for the scan pulse output is applied at a high level, the first node Q is bootstrapping by the bootstrapping capacitor C3 of the output buffer unit 27. (Coupling) has a higher potential.

As described above, in the state where the first node Q is bootstrapping, the output buffer unit 27 respectively inputs a clock signal for carry pulse output CRCLK(k) and a clock signal for scan pulse output (SCCLK(k)). ) Is output as a carry pulse (CP(k)) and a scan pulse (SP(k)), thereby preventing output loss (Loss).

The reset unit 22 is turned on when the transistors T3nB and T3nC are turned on when the reset signal RST output from the timing controller 4 is at a high level in the blank time. The first node Q is discharged to the second constant voltage GVSS2.

In FIG. 3, the stage of the gate driving circuit driven in the six-phase (Phase) is shown, but is not limited thereto, and the stage of the gate driving circuit according to the present invention may be variously configured.

As shown in FIG. 3, the (k)-th stage of the gate driving circuit includes 25 transistors and 3 capacitors.

Accordingly, when the GIP elements (transistors or capacitors) constituting the stage of the gate driving circuit are dispersedly disposed in one unit pixel area, the GIP elements constituting one stage for driving one gate line (scan line) are arranged. It may be arranged in unit pixel areas driven by one gate line (scan line).

4 is a configuration diagram of a display area of a display panel according to an exemplary embodiment of the present invention, and FIG. 5 is a configuration diagram more specifically showing two adjacent unit pixels disposed in a display area of the display panel of FIG. 4.

4 and 5 illustrate that the unit pixel is composed of red (R), green (G), blue (B), and white (W) sub-pixels, but is not limited thereto, and red (R), green ( G) and blue (B) sub-pixels.

The unit pixel area of the display area of the display panel according to the present invention includes at least three sub-pixel parts (R, G, B, W) 33, a GIP part 31, and a GIP internal connection wiring part 32, etc. Are distinguished.

The at least three sub-pixel units R, G, B, and W 33 are a plurality of data lines DL1 to DLm, a plurality of reference voltage lines Vref, and first and second constant voltage lines EVDD and EVSS. ) Are arranged in a vertical direction, and a plurality of gate lines (scan lines) are arranged in a horizontal direction.

The GIP unit 31 corresponds to a GIP element (transistor or capacitor) constituting the stage. That is, in a unit pixel area composed of red (R), green (G), blue (B), and white (W) sub-pixels, a GIP element (transistor or capacitor) constituting the stage shown in FIG. 3 is provided. It is distributed.

That is, one stage for driving one gate line (scan line) is arranged to be distributed over a plurality of unit pixel areas driven by the corresponding gate line (scan line).

Of course, two or more stages for driving one gate line (scan line) may be distributedly disposed in a plurality of unit pixel areas driven by the corresponding gate line (scan line).

If one stage is distributedly disposed in a plurality of unit pixel areas driven by one gate line (scan line), a middle portion of the plurality of unit pixel areas driven by the corresponding gate line (scan line) It is preferable to disperse GIP elements (transistors or capacitors) constituting the stage in a plurality of unit pixel areas.

If two stages for driving one gate line (scan line) are arranged in a plurality of unit pixel areas driven by the corresponding gate line (scan line), the stage is driven by the corresponding gate line (scan line). It is preferable to disperse GIP elements (transistors or capacitors) constituting the stage in a plurality of unit pixel areas at both edge portions of the plurality of unit pixels.

In addition, although FIGS. 4 and 5 show that the GIP unit 31 is disposed in all unit pixel regions, the present invention is not limited thereto, and the GIP unit 31 may not be disposed in some unit pixel regions.

The GIP internal connection wiring unit 32 is a connection wiring (clock signal line, Q node, QB node, device and device connection line, etc.) connecting GIP devices constituting the stage as shown in FIG. 3. ).

In addition, the arrangement positions of the at least three sub-pixel units 33, the GIP unit 31, and the GIP internal connection wiring unit 32 may be varied.

As described above, since the GIP elements constituting the stage of the gate driving circuit are distributedly disposed in the unit pixel, at least one stage is disposed in the unit pixels driven by one scan line, thereby minimizing left and right bezels of the display panel. .

As described above, when the GIP elements constituting the stage of the gate driving circuit are distributedly distributed in the unit pixel, coupling between the GIP unit 31 and at least three sub-pixel units R, G, B, and W 33 is performed. The (Coupling) phenomenon may occur and the image quality may deteriorate.

In addition, when the GIP elements constituting the stage of the gate driving circuit are distributedly distributed within the unit pixel, a coupling phenomenon is relatively large in the unit pixel in which the GIP element to which the clock signal CLK is applied is disposed, and the clock signal ( Since a coupling phenomenon is relatively small in a unit pixel in which a GIP element to which CLK) is not applied is disposed, a luminance deviation may occur between unit pixel regions, thereby deteriorating image quality.

Therefore, in order to prevent coupling between the GIP unit 31 and the pixel region, it is necessary to design the GIP unit 31 and the pixel region with a predetermined distance therebetween.

However, when the GIP unit 31 is designed to be spaced apart from the pixel area by a predetermined interval, the aperture ratio decreases due to a reduction in the effective design area, and a limitation occurs in the line width of the signal line to secure the separation distance.

Accordingly, the present invention prevents coupling between the GIP unit and the pixel region by shielding the GIP unit 31 with a power supply (EVDD) line or shielding the unit pixel region with a power supply (EVDD) line, In addition, the luminance deviation of the pixel regions is reduced. In addition, since the effective design area can be increased more than when the GIP portion is designed to be spaced apart from the pixel region, the aperture ratio is increased and the drop of the power source EVDD is reduced.

This will be described in more detail as follows.

6 is a diagram illustrating a unit pixel configuration of a display panel in which a shielding line according to the present invention is additionally disposed.

As described in FIG. 5, the at least three sub-pixel units R, G, B, and W 33 are a plurality of data lines DL1 to DL8, a plurality of reference voltage lines Vref, and a constant voltage line EVDD. ) Are arranged in a vertical direction, and a plurality of gate lines (scan lines) are arranged in a horizontal direction.

In FIG. 6, the constant voltage line EVDD for supplying the constant voltage EVDD to the display panel is disposed on both sides of the unit pixel, and is disposed between the at least three sub-pixel units 33 and the GIP unit 31. It is not limited to this.

That is, the constant voltage line EVDD may be disposed only on one side of the unit pixel, and may be disposed on both sides of the unit pixel, and one side of the unit pixels and the at least three sub-pixel units 33 and the GIP unit ( 31).

Separately, as illustrated in FIG. 6, a shielding line 40 is formed to surround the at least three sub-pixel units 33, the GIP unit 31, and the GIP internal connection wiring unit 32. The shielding line 40 is in electrical contact with the constant voltage line EVDD, and a constant voltage EVDD is applied to the shielding line 40.

In addition, as illustrated in FIG. 6, the shielding line 40 may extend on the reference voltage line Ref.

In the drawing, although the shielding line 40 is formed to surround the at least three sub-pixel units 33, the GIP unit 31, and the GIP internal connection wiring unit 32, the shielding line 40 is not limited thereto. The line 40 may be formed to wrap only the GIP part 31.

In addition, as mentioned above, when the constant voltage line EVDD is disposed only on one side of the unit pixel or only on both sides of the unit pixel, the shielding line 40 may include the at least three sub-pixel units 33 ) And between the GIP unit 31 and the at least three sub-pixel units 33, the GIP unit 31 and the GIP internal connection wiring unit 32.

In addition, the shielding line 40 includes a light shielding metal (LS), a gate electrode metal and a source/drain metal (S/D metal) constituting an organic light emitting diode (OLED) display panel. It can be configured in various ways.

7 is a structural cross-sectional view of a display panel in which a shielding line according to a first embodiment of the present invention is additionally disposed.

7 is a cross-sectional view showing a driving TFT disposed in the at least three sub-pixel portions 33 and a GIP element TFT disposed in the GIP portion 31, wherein the shielding line 40 is a source/drain metal (S). /D Metal).

That is, the at least three sub-pixel portions 33 (Driving TFT) and the GIP portion 31 (GIP TFT) on the substrate 1 is defined on the at least three sub-pixel portion 33, Driving TFT light-shielding layer (2) ) Is formed, and a clock signal (CLK) line 3 is formed of the same metal as the light-shielding layer 2 on the substrate 1 of the GIP section 31 (GIP TFT).

A buffer layer 4 is formed on the entire surface of the substrate 1 including the light blocking layer 2 and the clock signal (CLK) line 3, and the at least three sub-pixel units 33 (Driving TFT) and the GIP unit ( 31, GIP TFT) First and second active layers 5a and 5b, gate insulating films 6a and 6b, and first and second gate electrodes 7a and 7b are formed on the buffer layer 4, respectively. The first and second active layers 5a and 5b have channel regions and source/drain regions, respectively.

An interlayer insulating film 8 is formed on the entire surface of the buffer layer 4 including the first and second gate electrodes 7a and 7b, and the light blocking layer 2 and the clock signal (CLK) line 3 are exposed. The buffer layer 4 and the interlayer insulating film 8 are selectively removed to form first and second contact holes 14a, 14b, and each source/drain of the first and second active layers 5a, 5b The interlayer insulating film 8 is selectively removed to expose the region to form third to sixth contact holes 15a, 15b, 15c, and 15d.

Then, the drain electrode of the driving TFT is connected to the light blocking layer 2 through the first contact hole 14a and connected to the drain region of the first active layer 5a through the third contact hole 15a ( 9a) is formed, and the source electrode 9b of the driving TFT is formed to be connected to the source region of the first active layer 5a through the fourth contact hole 15b.

The source of the GIP TFT is connected to the clock signal (CLK) line 3 through the second contact hole 14b and connected to the drain region of the second active layer 5b through the sixth contact hole 15d. The electrode 10b is formed, and the drain electrode 10a of the GIP TFT is formed to be connected to the drain region of the second active layer 5b through the fifth contact hole 15c.

In addition, a shielding line 40 is formed on the interlayer insulating film 8 between the at least three sub-pixel parts 33 (Driving TFT) and the GIP part 31 (GIP TFT).

Then, a protective layer 11 is formed on the entire surface including the source/drain electrodes 9a and 9b of the driving TFT, the source/drain electrodes 10a and 10b of the GIP TFT, and the shielding line 40, and the protective layer (11) An overcoat layer 12 is formed on the entire surface.

The protective film 11 and the overcoat layer 12 are selectively removed so that the drain electrode 9a of the driving TFT is exposed to form a seventh contact hole 16. The first electrode 17 of the OLED is formed on the overcoat layer 12 so as to be connected to the drain electrode 9a of the driving TFT through the seventh contact hole 16, and the overcoat excluding the emission region A bank layer 13 is formed on the layer 12. In addition, although not shown in the drawing, a light emitting layer and a second electrode of the OLED are formed on the first electrode 17.

As illustrated in FIG. 7, the shielding line 40 may be formed of the same metal as the source/drain electrodes 9a and 9b of the driving TFT and the source/drain electrodes 10a and 10b of the GIP TFT.

Meanwhile, FIG. 8 is a structural cross-sectional view of a display panel in which a shielding line according to a second embodiment of the present invention is additionally disposed.

8 is a cross-sectional view showing a driving TFT disposed in the at least three sub-pixel portions 33 and a GIP element TFT disposed in the GIP portion 31, wherein the shielding line 40 is formed of a light-shielding layer metal. Shown.

That is, the at least three sub-pixel portions 33 (Driving TFT) and the GIP portion 31 (GIP TFT) on the substrate 1 is defined on the at least three sub-pixel portion 33, Driving TFT light-shielding layer (2) ) Is formed, and a clock signal (CLK) line 3 is formed of the same metal as the light-shielding layer 2 on the substrate 1 of the GIP section 31 (GIP TFT). Then, a shielding line 40 is formed on the substrate 1 between the at least three sub-pixel units 33 (Driving TFT) and the GIP unit 31 (GIP TFT). That is, the light blocking layer 2, the clock signal (CLK) line 3 and the shielding line 40 are formed of the same metal.

A buffer layer 4 is formed on the entire surface of the substrate 1 including the light blocking layer 2, the clock signal (CLK) line 3, and the shielding line 40, and the at least three sub-pixel portions 33, Driving TFT) and first and second active layers 5a, 5b, gate insulating films 6a, 6b, and first and second gate electrodes on the buffer layer 4 of each of the GIP sections 31 and GIP TFTs ( 7a, 7b) are formed. The first and second active layers 5a and 5b have channel regions and source/drain regions, respectively.

An interlayer insulating film 8 is formed on the entire surface of the buffer layer 4 including the first and second gate electrodes 7a and 7b, and the light blocking layer 2 and the clock signal (CLK) line 3 are exposed. The buffer layer 4 and the interlayer insulating film 8 are selectively removed to form first and second contact holes 14a, 14b, and each source/drain of the first and second active layers 5a, 5b The interlayer insulating film 8 is selectively removed to expose the region to form third to sixth contact holes 15a, 15b, 15c, and 15d.

Then, the drain electrode of the driving TFT is connected to the light blocking layer 2 through the first contact hole 14a and connected to the drain region of the first active layer 5a through the third contact hole 15a ( 9a) is formed, and the source electrode 9b of the driving TFT is formed to be connected to the source region of the first active layer 5a through the fourth contact hole 15b.

The source of the GIP TFT is connected to the clock signal (CLK) line 3 through the second contact hole 14b and connected to the drain region of the second active layer 5b through the sixth contact hole 15d. The electrode 10b is formed, and the drain electrode 10a of the GIP TFT is formed to be connected to the drain region of the second active layer 5b through the fifth contact hole 15c.

Then, a protective layer 11 is formed on the entire surface including the source/drain electrodes 9a and 9b of the driving TFT and the source/drain electrodes 10a and 10b of the GIP TFT, and the protective layer 11 is over the entire surface. The coat layer 12 is formed.

The protective film 11 and the overcoat layer 12 are selectively removed so that the drain electrode 9a of the driving TFT is exposed to form a seventh contact hole 16. The first electrode 17 of the OLED is formed on the overcoat layer 12 so as to be connected to the drain electrode 9a of the driving TFT through the seventh contact hole 16, and the overcoat excluding the emission region The bank layer 13 is formed on the layer 12. And, although not shown in the drawing, a light emitting layer and a second electrode of the OLED are formed on the first electrode 17.

As illustrated in FIG. 8, the shielding line 40 may be formed of the same metal as the light blocking layer 2 and the clock signal line 3.

Meanwhile, FIG. 9 is a structural cross-sectional view of a display panel in which a shielding line according to a third embodiment of the present invention is additionally disposed.

9 is a cross-sectional view showing a driving TFT disposed in the at least three sub-pixel units 33 and a GIP element TFT disposed in the GIP unit 31, wherein the shielding line 40 is formed of a gate electrode metal. Shown.

That is, the at least three sub-pixel portions 33 (Driving TFT) and the GIP portion 31, GIP TFT (31, GIP TFT) on the substrate 1 is defined on the at least three sub-pixel portion (33, Driving TFT) light-shielding layer (2 ) Is formed, and a clock signal (CLK) line 3 is formed of the same metal as the light-shielding layer 2 on the substrate 1 of the GIP section 31 (GIP TFT).

A buffer layer 4 is formed on the entire surface of the substrate 1 including the light blocking layer 2 and the clock signal (CLK) line 3, and the at least three sub-pixel units 33 (Driving TFT) and the GIP unit are formed. (31, GIP TFT) First and second active layers 5a and 5b, gate insulating films 6a and 6b, and first and second gate electrodes 7a and 7b are formed on the buffer layer 4, respectively. . The first and second active layers 5a and 5b have channel regions and source/drain regions, respectively.

Here, a shielding line 40 is formed on the buffer layer 4 between the at least three sub-pixel parts 33 (Driving TFT) and the GIP part 31 (GIP TFT). The shielding line 40 is formed of the same metal as the gate electrodes 7a and 7b.

An interlayer insulating film 8 is formed on the entire surface of the buffer layer 4 including the first and second gate electrodes 7a and 7b and the shielding line 40, and the light blocking layer 2 and a clock signal CLK are formed. The buffer layer 4 and the interlayer insulating film 8 are selectively removed so that the line 3 is exposed to form first and second contact holes 14a and 14b, and the first and second active layers 5a, The interlayer insulating film 8 is selectively removed so that each source/drain region of 5b) is exposed to form third to sixth contact holes 15a, 15b, 15c, and 15d.

Then, the drain electrode of the driving TFT is connected to the light blocking layer 2 through the first contact hole 14a and connected to the drain region of the first active layer 5a through the third contact hole 15a ( 9a) is formed, and the source electrode 9b of the driving TFT is formed to be connected to the source region of the first active layer 5a through the fourth contact hole 15b.

The source of the GIP TFT is connected to the clock signal (CLK) line 3 through the second contact hole 14b and connected to the drain region of the second active layer 5b through the sixth contact hole 15d. The electrode 10b is formed, and the drain electrode 10a of the GIP TFT is formed to be connected to the drain region of the second active layer 5b through the fifth contact hole 15c.

Then, a protective layer 11 is formed on the entire surface including the source/drain electrodes 9a and 9b of the driving TFT and the source/drain electrodes 10a and 10b of the GIP TFT, and the protective layer 11 is over the entire surface. The coat layer 12 is formed.

The protective film 11 and the overcoat layer 12 are selectively removed so that the drain electrode 9a of the driving TFT is exposed to form a seventh contact hole 16. The first electrode 17 of the OLED is formed on the overcoat layer 12 so as to be connected to the drain electrode 9a of the driving TFT through the seventh contact hole 16, and the overcoat excluding the emission region A bank layer 13 is formed on the layer 12. In addition, although not shown in the drawing, a light emitting layer and a second electrode of the OLED are formed on the first electrode 17.

9, the shielding line 40 may be formed of the same metal as the gate electrodes 7a and 7b.

In FIGS. 7 to 9, although the shielding line 40 is formed as a single layer, the present invention is not limited thereto, and is formed as a multi-layer in which at least two layers of the light blocking layer metal, the gate electrode metal and the source/drain metal are stacked Can be.

10 is a structural cross-sectional view of a display panel in which a shielding line according to a fourth embodiment of the present invention is additionally disposed.

10 is a cross-sectional view showing a driving TFT disposed in the at least three sub-pixel portions 33 and a GIP element TFT disposed in the GIP portion 31, wherein the shielding line 40 shields the source/drain metal from light. It has been shown that the layer metals are stacked to form a multilayer.

That is, the at least three sub-pixel portions 33 (Driving TFT) and the GIP portion 31, GIP TFT (31, GIP TFT) on the substrate 1 is defined on the at least three sub-pixel portion (33, Driving TFT) light-shielding layer (2 ) Is formed, and a clock signal (CLK) line 3 is formed of the same metal as the light-shielding layer 2 on the substrate 1 of the GIP section 31 (GIP TFT). Then, a first shielding line 40a is formed on the substrate 1 between the at least three sub-pixel units 33 (Driving TFT) and the GIP unit 31 (GIP TFT). That is, the light blocking layer 2, the clock signal (CLK) line 3 and the first shielding line 40a are formed of the same metal.

A buffer layer 4 is formed on the entire surface of the substrate 1 including the light blocking layer 2, the clock signal (CLK) line 3, and the first shielding line 40a, and the at least three sub pixel portions ( 33, Driving TFT) and the first and second active layers 5a and 5b, gate insulating films 6a and 6b and the first and second gates on the buffer layer 4 of the GIP sections 31 and GIP TFTs, respectively. Electrodes 7a, 7b are formed. The first and second active layers 5a and 5b have channel regions and source/drain regions, respectively.

An interlayer insulating film 8 is formed on the entire surface of the buffer layer 4 including the first and second gate electrodes 7a and 7b, and the light blocking layer 2 and the clock signal (CLK) line 3 are exposed. The buffer layer 4 and the interlayer insulating film 8 are selectively removed to form first and second contact holes 14a, 14b, and each source/drain of the first and second active layers 5a, 5b The interlayer insulating film 8 is selectively removed to expose the region to form third to sixth contact holes 15a, 15b, 15c, and 15d. In addition, the buffer layer 4 and the interlayer insulating film 8 are selectively removed so that the first shielding line 40a is exposed to form a seventh contact hole 18.

Then, the drain electrode of the driving TFT is connected to the light blocking layer 2 through the first contact hole 14a and connected to the drain region of the first active layer 5a through the third contact hole 15a ( 9a) is formed, and the source electrode 9b of the driving TFT is formed to be connected to the source region of the first active layer 5a through the fourth contact hole 15b.

The source of the GIP TFT is connected to the clock signal (CLK) line 3 through the second contact hole 14b and connected to the drain region of the second active layer 5b through the sixth contact hole 15d. The electrode 10b is formed, and the drain electrode 10a of the GIP TFT is formed to be connected to the drain region of the second active layer 5b through the fifth contact hole 15c.

Further, the first shielding line 40a through the seventh contact hole 18 on the interlayer insulating film 8 between the at least three sub-pixel portions 33 and the driving TFT and the GIP portion 31 and the GIP TFT. ), the second shielding line 40b is formed. Thus, the first and second shielding lines 40a and 40b are stacked to form the shielding line 40.

Then, a protective layer 11 is formed on the entire surface including the source/drain electrodes 9a and 9b of the driving TFT, the source/drain electrodes 10a and 10b of the GIP TFT, and the shielding line 40, and the protective layer (11) An overcoat layer 12 is formed on the entire surface.

The protective film 11 and the overcoat layer 12 are selectively removed so that the drain electrode 9a of the driving TFT is exposed to form a seventh contact hole 16. The first electrode 17 of the OLED is formed on the overcoat layer 12 so as to be connected to the drain electrode 9a of the driving TFT through the seventh contact hole 16, and the overcoat excluding the emission region The bank layer 13 is formed on the layer 12. And, although not shown in the drawing, a light emitting layer and a second electrode of the OLED are formed on the first electrode 17.

As shown in FIG. 10, the first shielding line 40a formed of the same metal as the light shielding layer 2 and the clock signal (CLK) line 3, and the source/drain electrodes 9a of the driving TFT, 9b) and the second shielding line 40b formed of the same metal as the source/drain electrodes 10a and 10b of the GIP TFT may be stacked to form the shielding line 40.

Meanwhile, FIG. 11 is a structural cross-sectional view of a display panel in which a shielding line according to a fifth embodiment of the present invention is additionally disposed.

11 is a cross-sectional view showing a driving TFT disposed in the at least three sub-pixel portions 33 and a GIP element TFT disposed in the GIP portion 31, wherein the shielding line 40 is a source/drain metal and a gate. It is shown that the metals are stacked to form a multilayer.

That is, the at least three sub-pixel portions 33 (Driving TFT) and the GIP portion 31 (GIP TFT) on the substrate 1 is defined on the at least three sub-pixel portion 33, Driving TFT light-shielding layer (2) ) Is formed, and a clock signal (CLK) line 3 is formed of the same metal as the light-shielding layer 2 on the substrate 1 of the GIP section 31 (GIP TFT).

A buffer layer 4 is formed on the entire surface of the substrate 1 including the light blocking layer 2 and the clock signal (CLK) line 3, and the at least three sub-pixel units 33 (Driving TFT) and the GIP unit are formed. (31, GIP TFT) First and second active layers 5a and 5b, gate insulating films 6a and 6b, and first and second gate electrodes 7a and 7b are formed on the buffer layer 4, respectively. . The first and second active layers 5a and 5b have channel regions and source/drain regions, respectively.

Here, a third shielding line 40c is formed on the buffer layer 4 between the at least three sub-pixel portions 33 and the driving TFT and the GIP portion 31 and the GIP TFT. The third shielding line 40c is formed of the same metal as the gate electrodes 7a and 7b.

An interlayer insulating film 8 is formed on the entire surface of the buffer layer 4 including the first and second gate electrodes 7a and 7b and the third shielding line 40c, and the light blocking layer 2 and the clock signal ( CLK) The buffer layer 4 and the interlayer insulating film 8 are selectively removed so that the line 3 is exposed to form first and second contact holes 14a and 14b, and the first and second active layers ( The interlayer insulating film 8 is selectively removed so that each source/drain region of 5a, 5b) is exposed to form third to sixth contact holes 15a, 15b, 15c, and 15d. In addition, the interlayer insulating film 8 is selectively removed so that the third shielding line 40c is exposed to form an eighth contact hole 18.

Then, the drain electrode of the driving TFT is connected to the light blocking layer 2 through the first contact hole 14a and connected to the drain region of the first active layer 5a through the third contact hole 15a ( 9a) is formed, and the source electrode 9b of the driving TFT is formed to be connected to the source region of the first active layer 5a through the fourth contact hole 15b. The source of the GIP TFT is connected to the clock signal (CLK) line 3 through the second contact hole 14b and connected to the drain region of the second active layer 5b through the sixth contact hole 15d. The electrode 10b is formed, and the drain electrode 10a of the GIP TFT is formed to be connected to the drain region of the second active layer 5b through the fifth contact hole 15c.

In addition, a second shielding line 40b is formed to be connected to the third shielding line 40c through the eighth contact hole 18. Accordingly, a third shielding line 40c is formed of the same metal as the gate electrodes 7a, 7b, and the third shielding line 40c is made of the same metal as the source/drain electrodes 9a, 9b, 10a, 10b. ), the second shielding line 40b is stacked to form a shielding line 40.

Then, a protective layer 11 is formed on the entire surface including the source/drain electrodes 9a, 9b of the driving TFT and the source/drain electrodes 10a, 10b of the GIP TFT and the shielding line 40, and the protection The overcoat layer 12 is formed on the entire surface of the layer 11.

The protective film 11 and the overcoat layer 12 are selectively removed so that the drain electrode 9a of the driving TFT is exposed to form a seventh contact hole 16. The first electrode 17 of the OLED is formed on the overcoat layer 12 so as to be connected to the drain electrode 9a of the driving TFT through the seventh contact hole 16, and the overcoat excluding the emission region The bank layer 13 is formed on the layer 12. And, although not shown in the drawing, a light emitting layer and a second electrode of the OLED are formed on the first electrode 17.

11, the third shielding line 40c formed of the same metal as the gate electrodes 7a, 7b and the same metal as the source/drain electrodes 9a, 9b, 10a, 10b are formed. The second shielding line 40b may be stacked to form the shielding line 40.

On the other hand, although not shown in the drawing, the first shielding line 40a formed of the same metal as the light shielding layer 2 and the clock signal (CLK) line 3 and the same metal as the gate electrodes 7a and 7b A third shielding line 40c formed of, and a second shielding line 40b formed of the same metal as the source/drain electrodes 9a, 9b of the driving TFT and the source/drain electrodes 10a, 10b of the GIP TFT ) May be stacked to form a shielding line 40.

In FIGS. 7 to 11, it has been mainly described that the shielding line 40 is formed of a certain metal and is formed of a single layer and a multi-layer. However, as described with reference to FIG. 6, the shielding line 40 is between the at least three sub-pixel units 33 and the GIP unit 31 and the at least three sub-pixel units 33 and the GIP unit 31 ) And the GIP internal connection wiring part 32. In addition, a power supply voltage EVDD is applied to the shielding line 40.

In the drawing, the shielding line 40 is provided between the at least three sub-pixel units 33 and the GIP unit 31 and the at least three sub-pixel units 33, the GIP unit 31, and the GIP internal connection wiring unit ( 32) is illustrated to form a shielding line 40 to surround, but is not limited thereto, and the shielding line 40 may be formed only between the at least three sub-pixel units 33 and the GIP unit 31. Or, it may be formed to wrap only the GIP portion 31.

12 is a graph of a coupling phenomenon occurring between the GIP unit 31 and at least three sub-pixel units R, G, B, and W 33 according to the present invention.

In FIG. 12, the variation of the gate voltage (DTG) of the driving TFT of the display panel and the source voltage (DTS) of the driving TFT is illustrated, and as described with reference to FIGS. 6 to 11, the GIP device is powered (EVDD) line When shielded with (shielding line) (indicated by the dotted line in FIG. 12), the source voltage variation of the driving TFT due to the GIP output variation is reduced than when the GIP element is not shielded (indicated by solid line in FIG. .

As described above, the GIP elements constituting the stage of the gate driving circuit are distributedly disposed in the unit pixel, and the GIP element is shielded with a power supply (EVDD) line (shielding line), or the unit pixel area is a power supply (EVDD) line. Since it is shielded with a (shielding line), coupling between the GIP element and the pixel region can be prevented, and in addition, the luminance deviation of the pixel regions can be reduced.

In addition, since the effective design area can be increased more than when the GIP element is designed to be spaced apart from the pixel region, the aperture ratio can be increased and the drop of the power source EVDD can be reduced.

Through the above description, those skilled in the art will appreciate that various changes and modifications are possible without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

1: Substrate 2: Light-shielding layer
3: Clock signal line 4: Buffer layer
5a, 5b: active layers 6a, 6b: gate insulating film
7a, 7b: gate electrode 8: interlayer insulating film
9a, 9b, 10a, 10b: source/drain electrodes 11: protective layer
12: overcoat layer 13: bank layer
14a, 14b, 15a, 15b, 15c, 15d, 16, 18: contact hole
17: first electrode

Claims (12)

A display area including data pixels and gate lines intersecting and including sub-pixels disposed at the intersection; And
It is provided with a plurality of stages are distributed in the unit pixel areas driven by each gate line in the display area to supply a scan pulse to the gate line,
The unit pixel area includes at least three sub-pixel units, a GIP unit in which GIP elements constituting the stage are disposed, and a GIP internal connection wiring unit in which connection wires connecting the GIP elements are disposed,
An OLED display panel in which a shielding line to which a power voltage is applied is disposed between the at least three sub-pixel units and the GIP unit. According to claim 1,
The shielding line is an OLED display panel disposed not only between the at least three sub-pixel units and the GIP unit but also surrounding the GIP unit. According to claim 1,
The shielding line is an OLED display panel disposed not only between the at least three sub-pixel units and the GIP unit, but also to surround the at least three sub-pixel units, the GIP unit, and the GIP internal connection wiring unit. According to claim 1,
The shielding line is an OLED display panel formed of at least one of a light blocking layer of the OLED display panel, a gate electrode metal, and a source/drain electrode metal. According to claim 1,
A driving TFT is disposed in the at least three sub-pixel portions, and a GIP TFT is disposed in the GIP portion,
A light blocking layer is disposed on the substrate under the driving TFT, and a clock signal line is disposed on the substrate under the GIP TFT,
The shielding line is an OLED display panel formed of the same metal as the light blocking layer and the clock signal line. According to claim 1,
A driving TFT is disposed in the at least three sub-pixel portions, and a GIP TFT is disposed in the GIP portion,
A light blocking layer is disposed on the substrate under the driving TFT, and a clock signal line is disposed on the substrate under the GIP TFT,
The shielding line is an OLED display panel formed of the same metal as the gate electrode of the driving TFT and the gate electrode of the GIP TFT. According to claim 1,
A driving TFT is disposed in the at least three sub-pixel portions, and a GIP TFT is disposed in the GIP portion,
A light blocking layer is disposed on the substrate under the driving TFT, and a clock signal line is disposed on the substrate under the GIP TFT,
The shielding line is an OLED display panel formed of the same metal as the source/drain electrode of the driving TFT and the source/drain electrode of the GIP TFT. According to claim 1,
A driving TFT is disposed in the at least three sub-pixel portions, and a GIP TFT is disposed in the GIP portion,
A light blocking layer is disposed on the substrate under the driving TFT, and a clock signal line is disposed on the substrate under the GIP TFT,
The shielding line includes a first metal layer formed of the same metal as the light blocking layer and the clock signal line, and a second metal layer formed of the same metal as the source/drain electrode of the driving TFT and the source/drain electrode of the GIP TFT. The OLED display panel to be laminated. According to claim 1,
A driving TFT is disposed in the at least three sub-pixel portions, and a GIP TFT is disposed in the GIP portion,
A light blocking layer is disposed on the substrate under the driving TFT, and a clock signal line is disposed on the substrate under the GIP TFT,
The shielding line is made of a third metal layer formed of the same metal as the gate electrode of the driving TFT and the gate electrode of the GIP TFT, and the same metal as the source/drain electrode of the driving TFT and the source/drain electrode of the GIP TFT. An OLED display panel on which a second metal layer is formed. According to claim 1,
OLED display panel in which touch sensors are further disposed in the display area. The method of claim 1
An OLED display panel in which a constant voltage line for supplying a constant voltage (EVDD) to the display panel is disposed on one or both sides of the unit pixel area. According to claim 1,
An OLED display panel in which a constant voltage line for supplying a constant voltage (EVDD) to the display panel is disposed between one or both sides of the unit pixel area and the at least three sub-pixel units and the GIP unit.

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