KR20170080881A - Display panel and display panel including the same and driving method thereof - Google Patents

Abstract

The present invention relates to a display panel capable of equalizing the voltage drop within a display panel by different line widths of power supply lines disposed on one side edge region and another side edge region of the display panel, ≪ / RTI > The present invention is characterized in that the line width of a power supply line disposed on one side edge region and the other side edge region of a display panel is adjusted in accordance with the amount of current of white (W) and blue (B) sub pixels. According to the present invention, since the voltage drop in the display panel can be made equal, the luminance deviation of the display panel can be minimized compared to the prior art, thereby improving the driving performance of the display panel.

Description

TECHNICAL FIELD [0001] The present invention relates to a display panel, a display device including the display panel, and a driving method of the display device.

The present invention relates to a display panel, a display device including the display panel, and a driving method of the display device.

BACKGROUND ART [0002] With the rapid progress of semiconductor technology, electronic devices have become smaller, thinner, and lighter. As a result, display devices that act as interfaces for users to visually confirm information processed in such new electronic devices have been developed. In recent years, various display devices such as a liquid crystal display device, a plasma display device, and an organic light-emitting diode display device have been used.

Conventionally, an OLED display device includes a display panel in which pixels are formed at intersecting regions of gate lines and data lines, a gate driver for sequentially supplying a scan signal to gate lines formed in a display panel, A data driver for supplying the data voltage to the data lines, and a timing controller for controlling functions of the gate driver and the data driver.

In the display panel, pixels are formed in an area where a plurality of gate lines and data lines cross each other. Each pixel includes an organic light emitting diode (OLED) for outputting light and a driving unit for driving the organic light emitting diode (OLED) .

The driving unit may include a driving transistor, a switching transistor, and a storage capacitor connected to the data line and the gate line to control driving of the organic light emitting diode OLED.

In addition, the driving unit controls the amount of current supplied to the organic light emitting diode OLED according to the data voltage supplied to the data line when the scan signal is supplied to the gate line.

On the other hand, in the structure in which the organic light emitting display device has four unit sub-pixels such as red (R), white (W), blue (B), and green (G), in order to reduce the number of wirings, The reference voltage supply line Vref is disposed at the center of the unit pixel and the power supply line EVDD is disposed at the boundary of the unit pixel sharing the line EVDD and the reference voltage supply line Vref.

Accordingly, one power supply line (EVDD) supplies power to the four sub-pixels to handle the voltage drop of the unit pixel. At this time, the power supply line EVDD supplies current to the organic light emitting diode OLED, and the line widths of all the power supply lines VDD of the display panel are designed to be the same.

However, power is supplied to two sub-pixels of the power supply lines arranged in the left and right edge regions of the display panel, and power supply is provided to the left and right edge regions of the display panel, rather than the number of sub- The number of pixels connected to the line is small. As a result, the voltage drop in the power supply lines disposed in the left and right edge regions of the display panel is reduced.

The present invention relates to a display panel capable of equalizing the voltage drop within a display panel by different line widths of power supply lines disposed on one side edge region and another side edge region of the display panel, The present invention has been made in view of the above problems.

The present invention relates to a display panel capable of adjusting the amount of current of white (W) and blue (B) sub-pixels flowing in a power supply line disposed on one side edge region and another side edge region of a display panel, And a method of driving the same.

It is another object of the present invention to provide a display panel capable of minimizing a luminance deviation of a display panel, a display device including the display panel, and a driving method of the display device.

It is another object of the present invention to provide a display panel capable of improving driving performance of a display panel, a display device including the same, and a driving method of the display device.

According to an aspect of the present invention, there is provided a display panel capable of equalizing a voltage drop in a display panel by changing a line width of a power supply line disposed at one side edge region and another edge side region of the display panel, And a driving method of the display device.

More specifically, in the present invention, the linewidths of the power supply lines disposed on one side edge region and the other side edge region of the display panel are adjusted according to the amount of current of the white (W) and blue (B) sub pixels. Accordingly, the voltage drop in the display panel can be made equal, thereby minimizing the luminance deviation of the display panel.

According to the present invention, there is an effect that the line widths of the power supply lines disposed in one side edge region and the other side edge region of the display panel are different from each other, so that the voltage drop in the display panel can be made equal.

According to the present invention, the amount of current of the white (W) and blue (B) sub-pixels flowing through the power supply lines disposed on one side edge region and the other side edge region of the display panel are adjusted to minimize the luminance deviation of the display panel There is an effect that can be.

Lastly, according to the present invention, the amount of current of the white (W) and blue (B) pixels flowing through the power supply lines disposed on one side edge region and the other side edge region of the display panel are adjusted to improve the driving performance of the display panel There is an effect that can be.

FIG. 1 is a configuration diagram of an organic light emitting display according to an embodiment of the present invention. Referring to FIG.
2 is a configuration diagram of the pixel of Fig.
3 is a diagram showing a pixel structure formed on an array substrate according to an embodiment of the present invention.

The above and other objects, features, and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, which are not intended to limit the scope of the present invention. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to denote the same or similar elements.

FIG. 1 is a configuration diagram of an organic light emitting display according to an embodiment of the present invention. Referring to FIG.

1, an organic light emitting diode display includes a display panel 100 in which pixels 110 are formed at intersections of gate lines GL1 to GLg and data lines DL1 to DLd, A gate driver 200 for sequentially supplying a scan signal to the gate lines GL1 to GLg formed on the panel 100 and a data line DL1 to DLd formed on the display panel 100, A data driver 300 for supplying a data voltage and a timing controller 400 for controlling functions of the gate driver 200 and the data driver 300.

The display panel 100 is formed with sub pixels P 110 in regions where a plurality of gate lines GL1 to GLg and data lines DL1 to DLd intersect each other. Each pixel 110 includes an organic light emitting diode for outputting light and a driving unit for driving the organic light emitting diode. Here, the organic light emitting diode may be configured as a top emission type in which light generated from the organic light emitting diode is emitted to the outside through the upper substrate, light emitted from the organic light emitting diode is emitted to the lower substrate And may be configured as a bottom emission scheme.

The driving unit may include a driving transistor, a switching transistor, and a storage capacitor to be connected to the data line DL and the gate line GL to control driving of the organic light emitting diode OLED.

The anode of the organic light emitting diode (OLED) is connected to the first power source, and the cathode is connected to the second power source. The organic light emitting diode OLED outputs light of a predetermined luminance corresponding to the current supplied from the driving transistor.

In addition, when a scan signal is supplied to the gate line GL, the driving unit controls the amount of current supplied to the organic light emitting diode OLED according to the data voltage supplied to the data line DL.

To this end, the driving transistor is connected between the first power source and the organic light emitting diode, and the switching transistor is connected between the driving transistor and the data line DL and the gate line GL.

The timing controller 400 receives a gate control signal GCS for controlling the gate driver 200 and a clock signal CLK for controlling the data driver 300 using a vertical synchronizing signal and a horizontal synchronizing signal supplied from an external system And outputs a data control signal DCS for controlling the data control signal DCS.

The timing controller 400 samples the input image data input from the external system, rearranges the input image data, and supplies the rearranged digital image data to the data driver 300.

That is, the timing controller 400 rearranges the input image data supplied from the external system, transfers the re-arranged digital image data to the data driver 300, and outputs the clock supplied from the external system, the horizontal synchronizing signal, A gate control signal GCS for controlling the gate driver 200 and a data control signal GCS for controlling the data driver 300 using a signal (clock and signals are simply referred to as timing signals) and a data enable signal DCS) to the gate driver (200) and the data driver (300).

In order to achieve the above-mentioned object, the timing controller 400 includes a receiver for receiving input image data and various signals as described above from an external system, and a controller for rearranging the input image data among the signals received from the receiver according to the display panel A gate control signal GCS and a data control signal DCS for controlling the gate driver 200 and the data driver 300 using the signals received from the receiver, And a transmitter for outputting the video data and control signals generated by the control signal generator and the video data processor to the data driver 300 or the gate driver 200, respectively.

Next, the data driver 300 converts the image data input from the timing controller 400 into an analog data voltage, and supplies a data voltage corresponding to one horizontal line in each horizontal period in which a scan signal is supplied to the gate line, . That is, the data driver 300 converts the image data into a data voltage using the gamma voltages supplied from the gamma voltage generator (not shown), and outputs the data voltage to the data lines.

Here, the data driver 300 generates a sampling signal by shifting a source start pulse (SSP) from the timing controller 400 according to a source shift clock (SSC). The data driver 300 latches the image data input according to the source shift clock signal SSC according to a sampling signal and changes the data voltage to a data voltage and then outputs the data voltage in response to a source output enable And supplies the data voltages to the data lines in units of horizontal lines.

To this end, the data driver 300 may include a shift register, a latch, a digital-analog converter, and an output buffer.

First, the shift register unit outputs a sampling signal using the data control signals received from the timing controller 400. [

Then, the latch unit latches the digital image data sequentially received from the timing controller 400, and simultaneously outputs the latched digital image data to the digital-analog converter.

Then, the digital-analog converter converts the image data transmitted from the latch unit into a data voltage and outputs the data voltage. That is, the digital-to-analog converter converts image data into a data voltage using a gamma voltage supplied from a gamma voltage generator (not shown) and outputs the data voltage to data lines.

The output buffer outputs the data voltage transmitted from the digital-analog converter to the data lines DL of the display panel 100 in accordance with the source output enable signal SOE transmitted from the timing controller 400.

The gate driver 200 sequentially supplies the scan signals to the gate lines GL1 to GLg of the display panel 100 in response to the gate control signals input from the timing controller 400. [ Accordingly, the switching transistors formed in the respective pixels of the corresponding horizontal line to which the scan signal is input are turned on so that an image can be output to each pixel 110.

The gate driver 200 may be formed independently from the display panel 100 and may be electrically connected to the display panel 100 in various ways, (Gate In Panel: GIP) method. In this case, the gate control signal for controlling the gate driver 200 may be the start signal VST and the gate clock GCLK.

To this end, the data driver 300 may include a shift register, a latch, a digital-analog converter, and an output buffer.

First, the shift register unit outputs a sampling signal using the data control signals received from the timing controller 400. [

Then, the latch unit latches the digital image data sequentially received from the timing controller 400, and simultaneously outputs the latched digital image data to the digital-analog converter.

Then, the digital-analog converter converts the image data transmitted from the latch unit into a data voltage and outputs the data voltage. That is, the digital-to-analog converter converts image data into a data voltage using a gamma voltage supplied from a gamma voltage generator (not shown) and outputs the data voltage to data lines.

The output buffer outputs the data voltage transmitted from the digital-analog converter to the data lines DL of the display panel 100 in accordance with the source output enable signal SOE transmitted from the timing controller 400.

The gate driver 200 sequentially supplies the scan signals to the gate lines GL1 to GLg of the display panel 100 in response to the gate control signals input from the timing controller 400. [ Accordingly, the switching transistors formed in the respective pixels of the corresponding horizontal line to which the scan signal is input are turned on so that an image can be output to each pixel 110.

The gate driver 200 may be formed independently from the display panel 100 and may be electrically connected to the display panel 100 in various ways, (Gate In Panel: GIP) method. In this case, the gate control signal for controlling the gate driver 200 may be the start signal VST and the gate clock GCLK.

Although the data driver 300, the gate driver 200 and the timing controller 400 are described as being independently configured, at least one of the data driver 300 and the gate driver 200 may be connected to the timing controller 400 Or may be integrally formed.

2 is a configuration diagram of the sub-pixel of FIG.

Referring to FIG. 2, the sub-pixel of the present invention is connected to a VDD supply line, a VSS supply line, a reference voltage supply line (Vref), and first and second gate lines (S1 and S2). Each sub-pixel includes a driving TFT (T _11), the first to the _{2 TFT (T 12 ~ T 13} ), the capacitor (C) and having an OLED.

A gate connected to the driving TFT (T ₁₁₎ is a drain electrode, a second node (N2) connected to a VDD supply line and the first node (N1) and a source electrode that is applied to VDD connected to the first node (N1) Electrode. The driving TFT (T ₁₁₎ supplies a driving current to the second node (N2) in response to the voltage state of the first node (N1).

The first TFT T ₁₂ switches between the data line V _data and the second node N 2 in response to a gate signal provided from the first gate line S 1. Here, the second node is a node connected to the gate electrode of the driving TFT (T _11).

A second TFT (T ₁₃₎ are switched to each other the sensing line and the first node (N1) between in response to a gate signal supplied from the second gate line (S2). Here, the sensing line is a reference voltage supply line (Vref). And, the first node (N1) is a node connected to a drain electrode of the driving TFT (T _11).

The OLED is connected in series with the driving TFT (T ₁₁ ) between the VDD supply line and the VSS supply line. More specifically, the OLED comprises an anode, a light emitting layer between the cathode and an anode and a cathode connected to the VSS supply line connected to the driving TFT (T _11).

The light emitting layer includes an electron injection layer, an electron transport layer, an organic light emitting layer, a hole transport layer, and a hole injection layer sequentially stacked between the cathode and the anode.

In this OLED, when a positive bias is applied between the anode and the cathode, electrons from the cathode are supplied to the organic light emitting layer via the electron injection layer and the electron transport layer, and holes are supplied from the anode to the organic light emitting layer via the hole injection layer and the hole transport layer do.

Accordingly, the fluorescent or phosphorescent material is caused to emit light by the recombination of electrons and holes supplied from the organic light emitting layer, thereby generating a luminance proportional to the current density.

The capacitor C is connected between the first and second nodes N1 and N2. This capacitor C stores the voltage applied to the first node N1, for example, the data voltage Vdata or the sensing voltage Vref.

3 is a diagram showing a pixel structure formed on an array substrate according to an embodiment of the present invention.

3, each pixel emits red (R), white (W), blue (B), and green (G) W, blue (B), and green (G) sub-pixels are arranged in the row direction. The second to Nth power supply lines EVDD_2 to EVDD_N are disposed between the green (G) sub pixel row and the red (R) sub pixel row and the first to Nth reference voltage supply lines Vref_1 to Vref_N are white W) sub-pixel column and a blue (B) sub-pixel column.

In detail, the red (R) and white (W) sub-pixels of the first pixel P1 share the first power supply line EVDD_1 and the blue (B) and green And the supply line EVDD_2. The red (R), white (W), blue (B), and green (G) of the first pixel P1 share the first reference voltage supply line Vref_1.

The red (R) and white (W) sub-pixels of the second pixel P2 share the second power supply line EVDD_2 and the blue (B) and green (G) sub-pixels share the third power supply line EVDD_3 ). The red (R), white (W), blue (B), and green (G) of the second pixel P2 share the second reference voltage supply line Vref_2.

The red (R) and white (W) subpixels of the (N-1) th pixel P (N-1) share the (N-1) power supply line EVDD_ (B) and the green (G) sub-pixel share the Nth power supply line (EVDD_N). The red (R), white (W), blue (B), and green (G) of the (N-1) (N-1)).

The red (R) and white (W) subpixels of the Nth pixel P (N) share the Nth power supply line EVDD_N and the blue (B) and green 1) power supply line EVDD_ (N + 1). The red (R), white (W), blue (B), and green (G) of the Nth pixel P (N) share the Nth reference voltage supply line (EVDD_N).

The first power supply line EVDD_1 formed on one edge region A of the display panel 100 supplies power to blue (B), green (G), red (R), and white (W) Only the red (R) and white (W) sub-pixels are supplied with power, so that only half of the actual power is supplied to the first power supply line (EVDD_1).

The (N + 1) power supply line EVDD_ (N + 1) formed on the other side edge region B of the display panel is formed of blue (B), green (G), red (R) Half of the actual power is supplied to the (N + 1) th power supply line EVDD_ (N + 1) since only the blue (B) and green (G) sub- .

At this time, white (W) and blue (B) sub-pixels are used for different display currents, and the first power supply line EVDD_1 is white (N + 1) -th power supply line EVDD_ (N + 1) supplies current only to the blue (B) sub-pixel and the second to Nth power supply lines EVDD_2 to EVDD_N ) Supplies current to the white (W) and blue (B) sub-pixels. Therefore, the voltage drop occurring at one side and the other edge region (A, B) of the display panel is changed, and a luminance deviation occurs in the display panel.

The first power supply line EVDD_1 disposed at one side edge region A of the display panel 100 and the second power supply line EVDD_1 disposed at the other side edge region B may be disposed in order to minimize a luminance deviation of the display panel. The line width of the (N + 1) power supply line EVDD_ (N + 1) is adjusted according to the amount of current of the white (W) and blue (B) pixels.

The (N + 1) -th power supply line (N + 1) formed in the other edge region B of the display panel 100 is connected to the first power supply line EVDD_1, The voltage drop of the first power supply line EVDD_1 formed in one edge region A of the display panel 100 can be made larger than the voltage drop of the first power supply line EVDD_ (N + 1).

For example, when white (W) is displayed on a panel having 2160 horizontal lines, white (W) and blue (B) sub-pixels are used. (N + 1) th power supply line EVDD_ (N + 1) is 1.922 mA and the second power supply line EVDD_2 (N + 1) is supplied to the first power supply line EVDD_1, ) To the N-th power supply line (EVDD_N) can flow a current of 4.277 mA each.

Therefore, if the line widths of the second power supply lines EVDD_2 to EVDD_N are 20 μm, the line width of the first power supply line EVDD_1 is 11.3 μm and the line width of the (N + 1) EVDD_ (N + 1)) can be set to 8.7 mu m.

Accordingly, three types of voltages corresponding to white (W), blue (B), white (W), and blue (B) flow in the display panel 100 to cause a voltage drop in the display panel 100 differently.

Therefore, in the present invention, the first power supply line EVDD_1 disposed at one side edge region A of the display panel 100 and the (N + 1) th power supply line EVDD_ (N + 1) 1) can be adjusted in accordance with the amount of current of the white (W) and blue (B) pixels.

The width of the first power supply line EVDD_1 formed in one edge region A of the display panel 100 is smaller than the line width of the Nth power supply line EVDD_N formed in the other edge region B of the display panel 100 The line width can be made larger and the voltage drop of the first power supply line EVDD_1 can be made larger than the voltage drop occurring in the Nth power supply line EVDD_N.

Accordingly, the voltage drop across the entire display panel 100 can be equalized, thereby minimizing the luminance variation of the display panel 100. [ Further, the driving performance of the display panel can be improved.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, But the present invention is not limited thereto.

100: display panel 200: gate driver
300: Data driver 400: Timing controller

Claims (9)

A plurality of gate lines formed on the substrate;
A plurality of data lines arranged to cross the gate lines; And
And a plurality of sub pixel regions defined by the gate lines and the data lines,
The sub-pixel region includes red (R), white (W), blue (B), and green (G)
A power supply line for supplying power to the sub-pixel; And
Wherein the line width of the power supply line formed on one side edge region of the substrate and the power supply line formed on the other edge region of the substrate are adjusted according to the amount of current of the white (W) pixel and the blue (B) sub pixel. The method according to claim 1,
Wherein the power supply line is disposed between a green (G) sub pixel and a red (R) sub pixel column. The method according to claim 1,
And a reference voltage supply line for supplying a reference voltage to the pixel. The method of claim 3,
Wherein the reference voltage supply line is disposed between the white (W) sub pixel column and the blue (B) sub pixel column. A plurality of gate lines formed on the substrate, a plurality of data lines arranged to intersect with the gate lines, and a plurality of sub pixel regions defined by the gate lines and the data lines, (R), white (W), blue (B), and green (G)
A power supply line for supplying power to the sub-pixel;
A line width of a power supply line formed on one side edge region of the substrate and a power supply line formed on the other side edge region of the substrate are adjusted according to the amount of current of a white (W) subpixel and a blue (B) subpixel;
A gate driver for supplying a gate signal to the gate line; And
And a data driver for supplying a data signal to the data line. 6. The method of claim 5,
Wherein the power supply line is disposed between a green (G) sub pixel and a red (R) sub pixel column. 6. The method of claim 5,
And a reference voltage supply line for supplying a reference voltage to the pixel. 8. The method of claim 7,
Wherein the reference voltage supply line is disposed between the white (W) sub pixel column and the blue (B) sub pixel column. A plurality of gate lines formed on the substrate, a plurality of data lines arranged to intersect with the gate lines, and a plurality of sub pixel regions defined by the gate lines and the data lines, A power supply line for supplying power to the sub-pixel, and a power supply line formed on one side edge region of the substrate, the power supply line including a red (R), white (W), blue (B) A line width of a power supply line formed in the other edge region of the display panel is controlled by a current amount of a white (W) sub pixel and a blue (B) sub pixel, a gate driver for supplying a gate signal to the gate line, A display device including a data driver for supplying a data signal,
Scanning one gate line in response to the gate voltage;
Displaying a block region made up of pixel regions sharing one gate line of the plurality of pixel regions in response to the data signal; And
And repeating the step of scanning the gate line and the step of displaying the block area.

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