KR20150027906A - Organic electro luminescent display device, and display panel and driving method thereof - Google Patents

Abstract

The present invention relates to an organic electroluminescent display device, a display panel, and a driving method thereof. Each pixel is defined by the intersection of a data line and a gate line. The each pixel includes: an organic light emitting diode, a driving transistor for driving the organic light emitting diode, a first transistor which is controlled by a scan signal supplied from the gate line and is connected between a first node of the driving transistor and a reference voltage line or a connection pattern which is connected to the reference voltage line, a second transistor which is controlled by the scan signal commonly supplied from the gate line and is connected between the data line and a second node of the driving transistor, and a capacitor which is connected between the first node and the second node of the driving transistor.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic electroluminescence display, an organic electroluminescent display device, a display panel,

The present invention relates to an organic light emitting display, a display panel, and a driving method thereof.

2. Description of the Related Art In recent years, an organic light emitting display device that has been spotlighted as a display device has advantages of high response speed, high luminous efficiency, high brightness, and a wide viewing angle by using an organic light emitting diode (OLED)

Such an organic light emitting display device arranges pixels including organic light emitting diodes in a matrix form and controls the brightness of the pixels selected by the scan signals according to the gradation of the data.

Each pixel of the organic light emitting display device includes, in addition to the organic light emitting diode, a data line and a gate line intersecting with each other, and a transistor and a storage capacitor having a connection structure.

Each of these pixels may further include a transistor suitable for performing various functions, thereby increasing the number of signal lines for supplying various signals to the transistors and also complicating the pixel structure. For example, when an internal or external compensation circuit for compensating the luminance non-uniformity between pixels is applied to the pixel structure, a transistor involved in the sensing operation for compensation must be added, which increases the number of required signal lines, As shown in FIG.

Also, as the demand for a large area or a high resolution increases, the number of signal lines must be increased to such a large extent, and the pixel structure becomes more complicated.

As described above, the number of signal lines increases due to addition of various functions such as sensing and compensating functions, increase in demand for a large area or a high resolution, and the number of IC pads and ICs accordingly increases. The structure also becomes more complicated.

This may cause difficulties in manufacturing, increase the probability of occurrence of defects, significantly lower the aperture ratio, and shorten the lifetime of the organic light emitting diode. Ultimately, the quality of the display panel can not be obtained and the yield is reduced.

In view of the foregoing, it is an object of the present invention to provide a display panel having a simple and compact structure and an organic light emitting display device including the same.

Another object of the present invention is to provide a display panel having a pixel structure for increasing the aperture ratio, lengthening the life of the light emitting diode, and lowering the probability of occurrence of defects, and an organic light emitting display device including the display panel .

Still another object of the present invention is to provide a display panel having a simple and compact structure by designing the pixel structure to be symmetrical, and an organic light emitting display device including the same.

It is still another object of the present invention to provide an organic light emitting display device having a sensing and compensation function for a simple and compact pixel structure and a driving method thereof for providing an efficient sensing and compensation function for compensating a luminance deviation between pixels .

In order to achieve the above-mentioned object, in one aspect, the present invention provides a display device comprising: a display panel including a plurality of pixels arranged at intersecting regions of a data line and a gate line; A data driver for supplying a data voltage through the data line; A gate driver for supplying a scan signal through the gate line; And a timing controller for controlling the driving timings of the data driver and the gate driver, wherein each of the plurality of pixels includes an organic light emitting diode, a driving transistor for driving the organic light emitting diode, A first transistor connected between a reference voltage line or a connection pattern connected to the reference voltage line and a first node of the driving transistor, the first transistor being controlled by a scan signal applied to the scan line, A second transistor connected between the data line and the second node of the driving transistor, and a capacitor connected between the first node and the second node of the driving transistor, .

In another aspect, the present invention provides a liquid crystal display comprising: a data line formed in one direction; A gate line formed in the other direction crossing the data line; And a plurality of pixels defined by intersecting the data line and the gate line, wherein each of the plurality of pixels comprises: an organic light emitting diode; a driving transistor for driving the organic light emitting diode; A first transistor which is controlled by a scan signal and is connected between a connection pattern connected to a reference voltage line or the reference voltage line and a first node of the driving transistor, A second transistor connected between the data line and a second node of the driving transistor, and a capacitor connected between a first node and a second node of the driving transistor.

According to another aspect of the present invention, there is provided a liquid crystal display comprising: a plurality of data lines formed in one direction; A plurality of gate lines formed in the other direction crossing the plurality of data lines; And a plurality of pixels connected to the plurality of data lines and the plurality of gate lines, wherein a pixel structure of a pixel connected to the (4n-3) th data line and a pixel structure of a pixel connected to the (4n) th data line are symmetrical , The pixel structure of the pixel connected to the (4n-2) th data line and the pixel structure of the pixel connected to the (4n-1) th data line are symmetrical to each other.

According to another aspect of the present invention, there is provided a method of driving an organic light emitting display including a display panel including a pixel including a driving transistor and an organic light emitting diode and a data line connected to the pixel, And a second transistor connected between the first node of the driving transistor and the second node of the data line and the driving transistor, and a second transistor connected between the data line and the second node of the driving transistor, Supplying a reference voltage and a data voltage to the first node and the second node of the driving transistor through the first transistor and the second transistor, respectively; And controlling supply of at least one of the reference voltage, the data voltage and the scan signal so that the pixel operates in one of a driving mode and a sensing mode. .

According to another aspect of the present invention, there is provided a data driver comprising: a data driver for driving a data line formed in one direction; A first gate driver for supplying a first scan signal through a first gate line formed in the other direction crossing the data line; A second gate driver for supplying a second scan signal to a second gate line formed in parallel with the first gate line; A timing controller for controlling the driving timings of the data driver, the first gate driver, and the second gate driver; And a display panel including a plurality of pixels connected to the data line, the first gate line, and the second gate line, wherein each of the plurality of pixels includes an organic light emitting diode, A first transistor connected between a first node of the driving transistor and a connection pattern which is controlled by the first scan signal and is connected to a reference voltage line or the reference voltage line; A second transistor connected between the data line and the second node of the driving transistor, and a capacitor connected between the first node and the second node of the driving transistor, .

In another aspect, the present invention provides a liquid crystal display comprising: a data line formed in one direction; A first gate line formed in the other direction crossing the data line; A second gate line formed in parallel with the one gate line; And a plurality of pixels connected to the data line, the first gate line, and the second gate line, wherein each of the plurality of pixels includes an organic light emitting diode, a driving transistor for driving the organic light emitting diode, A first transistor connected between a reference voltage line or a connection pattern connected to the reference voltage line and a first node of the driving transistor, the first transistor being controlled by a first scan signal supplied from a first gate line, A second transistor controlled by a second scan signal supplied and connected between the data line and a second node of the driving transistor; and a capacitor connected between the first node and the second node of the driving transistor. An electroluminescent display panel is provided.

In another aspect, the present invention provides a liquid crystal display comprising: a plurality of data lines formed in one direction; A plurality of first gate lines formed in the other direction crossing the plurality of data lines; A plurality of second gate lines formed in parallel with the plurality of first gate lines; A plurality of data lines, a plurality of first gate lines, and a plurality of pixels connected to the plurality of second gate lines, wherein a pixel structure of a pixel connected to the (4n-3) th data line and a And the pixel structure of the pixel coupled to the (4n-2) th data line and the pixel structure of the pixel connected to the (4n-1) th data line are symmetrical with respect to each other. Lt; / RTI >

As described above, according to the present invention, it is possible to provide a display panel having a simple and compact structure and an organic light emitting display device including the same.

According to the present invention, there is provided a display panel having a pixel structure for increasing the aperture ratio, lengthening the lifetime of the light emitting diode, and lowering the probability of occurrence of defects, and an organic electroluminescent display device including the same have.

In addition, according to the present invention, a display panel having a simple and compact structure by designing the pixel structure to be symmetrical, and an organic light emitting display device including the same are provided.

According to the present invention, there is provided an organic light emitting display having a sensing and compensating function according to a simple and compact pixel structure and a driving method thereof in providing an efficient sensing and compensating function for compensating a luminance deviation between pixels .

With these points, a high-quality display panel can be manufactured with a high yield.

These points will be more effective when applied to high resolution and large area display panels.

1 is an overall system configuration diagram of an organic light emitting display according to a first embodiment of the present invention.
2 is an equivalent circuit diagram of one pixel in a display panel of an organic light emitting display according to a first embodiment of the present invention.
3 is a plan view schematically showing a part of a display panel of an organic light emitting display according to a first embodiment of the present invention.
4 is a plan view showing in detail FIG.
FIG. 5 is an equivalent circuit diagram of FIG. 4, which is a circuit diagram in which an equivalent circuit diagram for one pixel shown in FIG. 2 is applied to four pixels.
FIG. 6A is a graph showing the relationship between the voltages applied to the four data lines DL (4n-3), DL (4n-2), DL (4n-1) and DL (4n), the driving voltage line DVL and the reference voltage line RVL 4 is a cross-sectional view taken along the line I-I 'in Fig. 4 for confirming the formation position structure.
6B is a cross-sectional view taken along the line II-II 'in FIG. 4 for confirming the driving voltage line connection structure.
6C is a cross-sectional view taken along a line III-III 'and a line IV-IV' in FIG. 4 for confirming a reference voltage line connection structure.
7 is a cross-sectional view illustrating a structure for connecting the source electrode of the driving transistor and the first electrode of the organic light emitting diode, taken along line V-V 'in FIG.
8 is a simplified plan view illustrating symmetrical structural features of a display panel of an organic light emitting display according to a first embodiment of the present invention.
FIG. 9 is a simplified diagram illustrating an external compensation structure included in the organic light emitting display according to the first embodiment of the present invention. Referring to FIG.
10 is a view illustrating an embodiment of an external compensation structure included in the organic light emitting display according to the first embodiment of the present invention.
11 is a diagram showing, for the implementation of FIG. 10, an external compensation configuration, together with an equivalent circuit for one pixel.
12 is a diagram illustrating an external compensation structure and a plurality of pixels together according to the implementation of FIG.
13 is a view illustrating another embodiment of the external compensation structure included in the organic light emitting display according to the first embodiment of the present invention.
14 is a view illustrating another embodiment of the external compensation structure included in the organic light emitting display according to the first embodiment of the present invention
15A and 15B are block diagrams of a data driver included in the organic light emitting display according to the first embodiment of the present invention.
16 is a configuration diagram of a gate driver included in the organic light emitting display according to the first embodiment of the present invention.
17 is a flowchart illustrating a method of driving the organic light emitting display according to the first embodiment of the present invention.
18 is a waveform diagram of scan signals and operation timing diagrams for the first switch and the second switch for three operation modes in which pixels of the organic light emitting display according to the first embodiment of the present invention operate.
19A and 19B are circuit diagrams when a pixel of an organic light emitting display according to the first embodiment of the present invention operates in a driving mode.
20 is a graph of voltage change when a pixel of the organic light emitting display according to the first embodiment of the present invention operates in a driving mode.
FIGS. 21A and 21B are circuit diagrams of a pixel of an organic light emitting display according to the first embodiment of the present invention operating in an S-sensing mode.
22A is a graph of voltage change when a pixel of the organic light emitting display according to the first embodiment of the present invention operates in the S-sensing mode.
22B is a graph of Vgs-Ids showing a threshold voltage deviation of the driving transistor of each pixel.
23A and 23B are circuit diagrams when a pixel of the organic light emitting display according to the first embodiment of the present invention operates in the F-sensing mode.
24A is a graph of voltage change when a pixel of the organic light emitting display according to the first embodiment of the present invention operates in the F-sensing mode.
FIG. 24B is a Vgs-Ids graph showing the drift deviation of the driving transistor of each pixel.
25A to 25F are views illustrating a process for a display panel of an organic light emitting display according to a first embodiment of the present invention.
26 is an overall system configuration diagram of an organic light emitting display according to a second embodiment of the present invention.
27 is an equivalent circuit diagram of one pixel in a display panel of an organic light emitting display according to a second embodiment of the present invention.
28 is a plan view schematically showing a part of a display panel of an organic light emitting display according to a second embodiment of the present invention.
29 is a plan view showing in detail FIG. 28,
FIG. 30 is an equivalent circuit diagram of FIG. 29, which is a circuit diagram in which an equivalent circuit diagram for one pixel shown in FIG. 27 is applied to four pixels.
31 is a simplified plan view for explaining symmetrical structural features of a display panel of an organic light emitting display according to a second embodiment of the present invention.
FIG. 32 is a diagram showing an external compensation structure of an organic light emitting display according to a second embodiment of the present invention, together with an equivalent circuit for one pixel P. FIG.
FIG. 33 is a timing chart of a driving mode and two sensing modes of the organic light emitting display according to the second embodiment of the present invention. Referring to FIG.
FIG. 34 is a view showing a compensation effect of mobility deviation according to the first and second embodiments of the present invention. FIG.
FIG. 35 is a diagram comparing aperture ratios according to the first and second embodiments of the present invention. FIG.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

Before describing some embodiments of the present invention, the technical background and technical idea of the present invention will be briefly described.

Some embodiments of the present invention are directed to a pixel structure in which the pixel structure for a formation position of a transistor, a capacitor, an organic light emitting diode, etc., a signal line connection position, etc. is symmetric So as to provide a simple and compact panel structure.

Accordingly, the aperture ratio can be increased, the probability of occurrence of defects can be lowered, manufacturing can be further facilitated, and a high-quality panel can be manufactured with a high yield. Particularly, such an effect will become even larger when an organic light emitting display having a panel of a high resolution or a large area is manufactured.

In some embodiments of the present invention, the first embodiment has a basic pixel structure of a one-scan structure in which each pixel uses one scan signal, and a second basic structure in which each pixel uses a two- Structure according to the second embodiment of the present invention.

According to the first embodiment of the present invention, although the driving operation and sensing operation of each pixel (sensing operation for compensating the unevenness of luminance between pixels) are normally performed, each pixel uses only one scan signal Therefore, the number of gate lines connected to each pixel can be reduced, and the aperture ratio can be further increased as compared with the second embodiment in which each pixel uses two scan signals.

Hereinafter, an organic light emitting display device based on a one scan structure and a driving method thereof will be described first as a first embodiment of the present invention. Next, as a second embodiment of the present invention, an organic light emitting display device And a driving method thereof will be described.

<First Example >

1 is an overall system configuration diagram of an organic light emitting display device 10 according to a first embodiment of the present invention.

1, an organic light emitting display device 10 according to a first embodiment of the present invention includes a plurality of data lines DL formed in one direction and a plurality of data lines A display panel 11 including a plurality of pixels P arranged in an intersecting region of a plurality of gate lines GL to be formed, a data driver 12 for supplying a data voltage through the data lines, A gate driver 13 for supplying a scan signal through a gate line, and a timing controller 14 for controlling driving timings of the data driver 12 and the gate driver 13.

1, a plurality of data lines DL (1) to DL (4N) are formed in one direction on a display panel 11 and a plurality of data lines DL (1) to DL (4N) And a plurality of gate lines GL (1) to GL (M) are formed in the other direction. In this specification, for convenience of explanation, it is assumed that the number of data lines and gate lines formed on the display panel 11 is 4N and M. Here, N and M are natural numbers of 1 or more. The number n used for identifying each data line in all 4N data lines is a natural number of 1 or more and 1/4 or less of the number of data lines (1? N? (4N / 4)).

In this display panel 11, pixels P are arranged in an area where 4N data lines DL (1) to DL (4N) and M gate lines GL (1) to GL (M) Respectively. The pixel structure for each pixel P will be described in more detail with reference to FIG.

2 is an equivalent circuit diagram of one pixel in the display panel 11 of the organic light emitting display device 10 according to the first embodiment of the present invention.

Referring to FIG. 2, each pixel P is connected to one data line DL and receives only one scan signal SCAN through one gate line GL

Each of these pixels includes an organic light emitting diode (OLED) as shown in FIG. 2, and includes a driving transistor (DT), a first transistor T1, a second transistor T2, And a storage capacitor Cst. Since each pixel includes three transistors DT, T1, and T2 and one storage capacitor Cst, each pixel has a 3T (Capacitor) structure.

The driving transistor DT in each pixel is supplied with the driving voltage EVDD supplied from the driving voltage line DVL and the voltage of the gate node N2 applied through the second transistor T2 Data voltage) to drive the organic light emitting diode OLED.

The driving transistor DT has a first node N1, a second node N2 and a third node N3. The first transistor N1 is connected to the first transistor T1, The node N2 is connected to the second transistor T2 and the third node N3 is supplied with the driving voltage EVDD.

Here, the first node of the driving transistor DT is a source node (also referred to as a 'source electrode'), the second node is a gate node (also referred to as a gate electrode) The third node N3 may be a drain node (also referred to as a drain electrode). The first node, the second node, and the third node of the driving transistor DT may be changed depending on the type of the transistor, the circuit change, and the like.

The first transistor T1 is controlled by a scan signal SCAN supplied from the gate line GL and is connected to a reference voltage line RVL for supplying a reference voltage Vref And is connected between a connection pattern CP connected to the reference voltage line RVL and the first node N1 of the driving transistor DT. The first transistor T1 is also referred to as a &quot; sensor transistor &quot;.

The second transistor T2 is controlled by a scan signal SCAN commonly supplied from the gate line GL and is connected between the corresponding data line DL and the second node N2 of the driving transistor DT do. The second transistor T2 is also referred to as a &quot; switching transistor &quot;.

The storage capacitor Cst may be connected between the first node N1 and the second node N2 of the driving transistor DT to maintain the data voltage for one frame.

As described above, the first transistor T1 and the second transistor T2 are controlled by a single scan signal supplied through one and the same gate line (common gate line). As described above, since each pixel uses one scan signal, each pixel in the first embodiment of the present invention has a basic pixel structure of &quot; 3T1C-based one scan structure &quot;.

The first transistor T1 is basically a transistor associated with driving by applying a data voltage to the gate node N2 of the driving transistor DT and the second transistor T2 is a transistor associated with driving, Since the two transistors T1 and T2 have different uses and functions, the transistors T1 and T2 are related to the sensing for compensating for the luminance deviation between the pixels, (Driving operation, sensing operation) is also affected. Therefore, in order to properly perform the driving operation and the sensing operation of the pixel, it may be necessary to change the operation mode (for example, the operation timing) with a separate device (e.g., a second switch) The compensation configuration (function) will be explained together with the explanation.

As described above, each pixel according to the organic light emitting display device 10 of the first embodiment of the present invention has a structure of 3T1C (hereinafter referred to as &quot; 3T1C &quot;) which receives only one scan signal SCAN through one gate line GL under the 3T1C structure. Based scan structure (common scan structure) &quot;. That is, the scan signals (common scan signals) supplied through one gate line (GL, common gate line) are not commonly applied to the gate node of the first transistor and the gate node of the second transistor, .

The pixel structure of the organic light emitting display device 10 according to the first embodiment of the present invention is different from the pixel structure of the basic pixel structure (one scan structure based on 3T1C) described with reference to FIG. 2, Signal line connection structure &quot; relating to being connected to various signal lines such as a data line DL, a gate line GL, a driving voltage line DVL, and a reference voltage line RVL.

Here, the signal lines include not only a data line for supplying a data voltage to each pixel, a gate line for supplying a scan signal but also a reference voltage line (RVL) for supplying a reference voltage (Vref) to each pixel , A driving voltage line (DVL) for supplying a driving voltage (EVDD), and the like.

The reference voltage line RVL and the driving voltage line DVL described above are formed in parallel with the data line DL, and each number may be equal to or less than the number of data lines.

If the number of reference voltage lines and the number of driving voltage lines are equal to the number of data lines, each pixel is connected to one data line DL and one gate line GL, ) And one reference voltage line (RVL).

In this case, the signal line connection structures of the respective pixels may be the same. That is, the basic unit of the signal line connection structure is one pixel, and the regularity of the signal line connection structure may be one pixel (one pixel column).

If the number of reference voltage lines and the number of driving voltage lines are smaller than the number of data lines, some of the pixels may be directly connected to the driving voltage line DVL and the reference voltage line RVL, The driving voltage line DVL and the reference voltage line RVL may be connected to the reference voltage line RVL through the connection pattern CP without being directly connected to the reference voltage line DVL and the reference voltage line RVL.

In this case, the signal line connection structures of the respective pixels may not be all the same. However, even if the structure in which each pixel is connected to the signal line is not the same, the structure in which the signal line is connected to every pixel can be the same. That is, the unit of the signal line connection structure may be a plurality of pixels instead of one pixel P, and the regularity of the signal line connection structure may repeatedly appear for a plurality of pixels (a plurality of pixel columns).

For example, the signal line connection structure may be repeated for each of the four pixels P1 to P4, that is, the regularity of the signal line connection structure may repeatedly appear for every four pixels (four pixel columns) In this case, the basic unit of the signal line connection structure may be four pixels (four pixel columns).

Thus, when the basic unit of the signal line connection structure is four pixels (four pixel columns), the number of reference voltage lines may be one fourth of the number of data lines. That is, when the number of data lines is 4N, the number of reference voltage lines may be N.

As described above, when the basic unit of the signal line connection structure is four pixels (four pixel columns), the reference voltage line connection structure may be as follows.

A pixel capable of receiving a data voltage from each of four arbitrary data lines DL (4n-3), DL (4n-2), DL (4n-1), DL (4n) Only the pixels P1 through P4 connected to the four data lines DL (4n-3), DL (4n-2), DL (4n-1) and DL (4n) One reference voltage line RVL is connected to the pixels P1 to P4 connected to the four data lines DL (4n-3), DL (4n-2), DL (4n-1) And is formed on the display panel 11 in parallel with the data lines.

The one reference voltage line RVL is connected to two data lines among the four data lines DL (4n-3), DL (4n-2), DL (4n-1) (4n-2) and DL (4n-1), and supplies the remaining two data lines (for example, DL (4n-3) The reference voltage Vref can be supplied to each pixel connected to the pixel through the connection pattern.

On the other hand, when the basic unit of the signal line connection structure is four pixels, the number of driving voltage lines may be 1/2 or 1/4 of the number of data lines. That is, when the number of data voltage lines is 4N, the number of driving voltage lines may be 2N or N. [

For example, if the number of driving voltage lines is 2N, the number of pixels connected to the four data lines DL (4n-3), DL (4n-2), DL (4n-1) To P4 are connected to four data lines DL (4n-3), DL (4n-2), DL (4n-1) and DL (4n) The two driving voltage line connection structures for the pixels P1 to P4 are as follows.

The two driving voltage lines DVL are connected to one of the pixels P1 to P4 connected to the four data lines DL (4n-3), DL (4n-2), DL (4n-3), DL (4n-3), and DL (4n) are supplied directly to the pixels connected to the two data lines (E.g., DL (4n-2), DL (4n-1)) among the pixels P1 through P4 connected to the data lines DL (4n-1) The driving voltage EVDD can be supplied through the connected connection pattern.

In this specification and the drawings, the P1 pixel refers to all the pixels (i.e., a pixel column) connected to the 4n-3th data line DL (4n-3) May mean only. The pixel P2 may refer to all the pixels connected to the (4n-2) -th data line DL (4n-2), or may denote only a specific pixel connected to the selected gate line among all pixels. The pixel P3 may refer to all the pixels connected to the (4n-1) -th data line DL (4n-1), or may be a specific pixel connected to the selected gate line among all the pixels. The pixel P4 may refer to all the pixels connected to the 4n-th data line DL (4n) or may denote only a specific pixel connected to the selected gate line among all the pixels.

In this specification and the figures, the pixel connected to the 4n-3th data line DL (4n-3), the pixel connected to the 4n-2th data line DL (4n-2) A red pixel, a green pixel, a blue pixel, and a blue pixel, which are connected to a pixel connected to the first data line DL (4n-1) and a 4nth data line DL (4n) White) pixel.

Although the transistors DT, T1, and T2 are shown and described as being of the N type in the present specification and the drawings, ) May all be changed to P type, or some of transistors DT, T1, T2 may be implemented as N type and others as P type. In addition, the organic light emitting diode (OLED) may be changed to an inverted type.

In addition, the transistors DT, T1, T2 described herein are also referred to as thin film transistors (TFTs).

Hereinafter, the pixel structure including the basic pixel structure (one scanning structure based on 3T1C) and the signal line connecting structure briefly described above will be described in more detail with reference to FIGS. 3 to 5. FIG. 3 to 5 show the case where the basic unit of the signal line connection structure is four pixels.

As described above, the basic unit of the signal line connection structure is divided into four pixels (four pixels) connected to the four data lines DL (4n-3), DL (4n-2) P1 to P4), one reference voltage line RVL for supplying the reference voltage Vref is formed for the four pixels P1 to P4, and a driving voltage Vdd for supplying the driving voltage EVDD Two lines DVL may be formed.

FIG. 3 is a plan view schematically showing a part of the display panel 11 of the organic light emitting display device 10 according to the first embodiment of the present invention, FIG. 4 is a plan view showing details of FIG. 3, 4 is an equivalent circuit diagram of the equivalent circuit diagram for one pixel shown in FIG. 2 applied to four pixels.

3 to 5, the basic unit of the signal line connection structure is connected to four data lines DL (4n-3), DL (4n-2), DL (4n-1) and DL (4n) In the case of four pixels (P1 to P4), the basic pixel structure and the signal line connection structure of 1T scan based on 3T1C can be confirmed.

3 to 5, each of the four data lines DL (4n-3), DL (4n-2), DL (4n-1) Respectively. Further, one gate line GL (m), 1? M? M is connected to four pixels P1 to P4.

Four pixels P1 to P4 connected to four data lines DL (4n-3), DL (4n-2), DL (4n-1) and DL (4n) Each of the driving transistors DT includes a driving transistor DT receiving a driving voltage EVDD and driving the organic light emitting diode and a first transistor N1 receiving a reference voltage Vref and transmitting the reference voltage Vref to a first node N1 of the driving transistor DT. A second transistor T2 receiving the data voltage Vdata and transferring the data voltage Vdata to the second node N2 of the driving transistor DT; A capacitor Cst connected between the two nodes N2, and the like.

Each of the four pixels P1 to P4 connected to the four data lines DL (4n-3), DL (4n-2), DL (4n-1) A structure in which only one scan signal is supplied to the first transistor T1 and the second transistor T2 is used as well as a 3T1C structure including one transistor DT, T1 and T2 and one capacitor Cst I have. As described above, the pixel structure of each of these pixels is referred to as &quot; 3T1C-based one-scan structure &quot;.

Each of the four pixels P1 to P4 connected to the four data lines DL (4n-3), DL (4n-2), DL (4n-1) And the number of scan signals are the same, signal line connection structures (signal applying methods) for receiving data voltages, driving voltages, reference voltages, and the like may be different from each other. However, the signal line connection structure between the four pixels P1 to P4 connected to the four data lines DL (4n-3), DL (4n-2), DL (4n-1) There is regularity and symmetry. 3 to 5, the signal line connection structure will be described in detail below.

First, the reference voltage line connection structure will be described.

(N = 1 to n? N), that is, for four pixel columns when the number of data lines is 4N and the number of reference voltage lines is N in the display panel 11, (4n-1) -th data line DL (4n-2) connected to the first data line DL (4n-3) 1) corresponding to the first voltage line for supplying the first voltage (Vref) to the pixel P1 connected to the pixel P3 and the 4n-th data line DL (4n) RVL are formed in a direction parallel to the data lines.

According to the number of the reference voltage lines RVL, the display panel 11 is connected to the (4n-2) th data line DL (4n-2) when the number of data lines is 4N and the number of reference voltage lines is N (Reference voltage, Vref) for supplying a first voltage (reference voltage, Vref) between the region of the pixel P2 and the region of the pixel P3 connected to the 4n-1th data line DL (4n-1) One reference voltage line RVL may be formed. That is, one reference voltage line RVL is connected to the pixels P1 through P4 connected to the four data lines DL (4n-3), DL (4n-2), DL (4n- As shown in FIG.

The position of formation of these reference voltage lines enables a symmetrical pixel structure.

The first transistor T1 and the (4n-1) th data line DL (4n-2) of the pixel P2 connected to the (4n-2) th data line DL The first transistor T1 of the pixel P3 connected to the first data line DLn (4n-1) is directly connected to the reference voltage line RVL and the pixel P1 connected to the (4n-3) The first transistor T1 of the pixel P4 connected to the first transistor T1 and the 4n th data line DL 4n is connected to a connection pattern CP connected to the reference voltage line RVL .

According to this reference voltage line connection structure, the first transistor T1 and the (4n-1) th data line DL (4n-1) of the pixel P2 connected to the (4n- The first transistor T1 of the pixel P3 connected to the first data line DL is directly supplied with the reference voltage Vref from the reference voltage line RVL and the pixel connected to the (4n-3) th data line DL (4n-3) The first transistor T1 of the pixel P4 connected to the first transistor T1 and the 4nth data line DL 4n of the first transistor P1 is connected to the reference voltage line RVL through a connection pattern CP And receives the reference voltage Vref.

Next, the driving voltage line connection structure will be described.

When the number of data lines is 4N and the number of driving voltage lines is 2N in the display panel 11, the pixel P1 connected to the (4n-3) th data line DL (4n-3) (4n-2), a pixel P3 connected to the (4n-1) th data line DL (4n-1) Two driving voltage lines DVL corresponding to the second voltage lines for supplying the second voltage EVDD are formed in a direction parallel to the data lines.

When the number of data lines is 4N and the number of driving voltage lines is 2N in the display panel 11 according to the number of the driving voltage lines DVL, the number of pixels connected to the (4n-3) th data line DL (4n-3) (Drive voltage, EVDD) for supplying the second voltage (drive voltage, EVDD) to the left side of the region of the pixel P1 and the right side of the region of the pixel P4 connected to the 4nth data line DL (4n) Two driving voltage lines RVL may be formed.

The formation position of such a driving voltage line enables a symmetric pixel structure.

The driving transistor DT and the 4n-th data line DL (4n) of the pixel P1 connected to the (4n-3) th data line DL (4n-3) The driving transistor DT of the pixel P4 connected to the driving voltage line RVL is directly connected to the driving voltage line RVL.

That is, the driving transistor DT of the pixel P1 connected to the (4n-3) th data line DL (4n-3) is connected to the And the driving transistor DT of the pixel P4 connected to the 4n-th data line DL (4n) is directly connected to the driving voltage line RVL formed on the 4n-th data line DL (4n) And is directly connected to the driving voltage line RVL formed on the right side of the area of the connected pixel P4.

The driving transistor DT of the pixel P2 connected to the (4n-2) th data line DL (4n-2) is connected to the pixel P1 connected to the (4n- And connected to the connection pattern CP connected to the driving voltage line RVL formed on the left side of the region. The driving transistor DT of the pixel P3 connected to the (4n-1) th data line DL (4n-1) is formed on the right side of the region of the pixel P4 connected to the 4nth data line DL And connected to a connection pattern CP connected to the driving voltage line RVL.

According to such a driving voltage line connection structure, a pixel connected to the driving transistor DT and the 4n-th data line DL (4n) of the pixel P1 connected to the 4n-3th data line DL (4n-3) P4 are directly supplied with the driving voltage EVDD from the different driving voltage lines RVL.

The driving transistor DT of the pixel P2 connected to the (4n-2) th data line DL (4n-2) is connected to the pixel P1 connected to the (4n-3) The driving voltage EVDD is applied from the connection pattern CP connected to the driving voltage line RVL at the left side of the region of the pixel P3 and the driving of the pixel P3 connected to the (4n-1) th data line DL (4n-1) The transistor DT receives the driving voltage EVDD from the connection pattern CP connected to the driving voltage line RVL on the right side of the pixel P4 connected to the 4nth data line DL 4n.

Next, the data line connection structure will be described.

Each of the four data lines DL (4n-3), DL (4n-2), DL (4n-1) and DL (4n) is connected to pixels in each of four pixel columns.

(4n-3) th data line DL (4n-3) and the (4n-3) th data line DLn Each of the data lines DL (4n-1) is formed on the right side of the area of the corresponding pixel P1 or P3 connected thereto. Each of the even-numbered data lines, that is, the (4n-2) th data line DL (4n-2) and the 4nth data line DL (4n) do.

The formation position of such a data line enables a symmetrical pixel structure.

Next, the gate line connection structure will be described.

(4n-3), DL (4n-2), DL (4n-1), and DL (4n) with respect to one pixel row (Pixel Row) Only one gate line GL (m) is formed on the display panel 11 as a signal line to be formed.

One gate line GL (m) formed with respect to one pixel row is connected to the first transistor T1 (m) included in each of all the pixels (including four pixels P1 to P4) And the gate electrode of the second transistor T2.

Each of the first transistor T1 and the second transistor T2 included in each of the pixels (including the four pixels P1 to P4) in one pixel row is connected to one gate line GL (m) And simultaneously applies a scan signal (common scan signal) to the gate electrode.

The first transistor T1 is basically a transistor that applies a data voltage to the gate node N2 of the driving transistor DT and is a transistor associated with the driving of the organic light emitting diode. In contrast, although the second transistor T2 may be related to the driving of the organic light emitting diode, it is basically a transistor related to sensing to compensate for the luminance deviation between pixels.

As described above, since the two transistors T1 and T2 have different uses and functions, the common application of the scan signals from one gate line controls the driving operation related to the two transistors T1 and T2, It can have a great influence on the operation. Accordingly, the first embodiment of the present invention is a driving method for realizing a simple and compact pixel structure, that is, a 1-scan structure based on a 3T1C, without any problems in the driving operation and the sensing operation of the pixel For example, a signal supply timing for each of the driving mode, the S-sensing mode, and the F-sensing mode, a switching operation timing, etc.) and an additional configuration (for example, the second switch SW2). A driving method suitable for such a 3T1C-based one-scan structure will be described in detail later with reference to FIGS. 17 to 24B.

Hereinafter, the signal line connection structure described above with reference to Figs. 3 to 5 will be described again with reference to Figs. 6A, 6B and 6C.

FIG. 6A is a graph showing the relationship between the voltages applied to the four data lines DL (4n-3), DL (4n-2), DL (4n-1) and DL (4n), the driving voltage line DVL and the reference voltage line RVL 4 is a cross-sectional view taken along the line I-I 'in Fig. 4 for confirming the formation position structure.

Sectional view of FIG. 6A shows four pixels P1 to P4 connected to four data lines DL (4n-3), DL (4n-2), DL (4n-1) and DL (4n) In the row direction.

Referring to FIG. 6A, in the region of four pixels P1 to P4 connected to the four data lines DL (4n-3), DL (4n-2), DL (4n-1) , The driving voltage line DVL and the reference voltage line RVL are arranged at any positions of the four data lines DL 4n-3, DL 4n-2, DL 4n-1 and DL 4n, Is formed. The process for forming the signal lines is described in further detail with reference to FIGS. 25A to 25F.

6A, the reference voltage line RVL is formed on the gate insulating film 61 formed on the substrate 60, and may be formed between the four pixel regions, that is, between the P2 pixel region and the P3 pixel region have.

Referring to FIG. 6A, a driving voltage line DVL is formed on the left and right sides of four pixel regions. The driving voltage line DVL on the left side of the P1 pixel region of the two driving voltage lines DVL is connected to the connection pattern CP and the connection pattern CP is connected to the drain of the driving transistor DT 3 node N3. The driving voltage line DVL on the right side of the P4 pixel region of the two driving voltage lines DVL is connected to the connection pattern CP and the connection pattern CP is connected to the driving transistor DT included in the P3 pixel. And the third node N3.

Referring to FIG. 6A, the odd-numbered data lines, that is, the (4n-3) th data lines DL (4n-3) (4n-2) th data line DL (4n-3) and the 4n-1th data line DL (4n-1) are formed on the right side of the pixel P1, P3 on the right side of the pixel region.

Referring to FIG. 6A, the positions and the connection structures of the signal lines in the P 1 pixel region are symmetrical with respect to the position and connection structure of the signal lines in the P 4 pixel region and the reference voltage line RVL. In addition, the positions and the connection structures of the signal lines in the P2 pixel region are symmetrical with respect to the position and connection structure of the signal lines in the P3 pixel region and the reference voltage line (RVL).

FIG. 6B is a cross-sectional view taken along the line II-II 'in FIG. 4 for confirming the drive voltage line connection structure, FIG. 6C is a cross-sectional view taken along line III-III' and FIG. to be.

First, referring to FIG. 6B and FIG. 4, a driving voltage line connection structure will be described.

6B, the pixel P1 connected to the (4n-3) th data line DL (4n-3) and the (4n-2) th data line DL (4n-2) The gate electrode N2 in the driving transistor DT of each connected pixel P2 is formed on the substrate 60. [ At this time, a connection pattern CP is formed on the substrate 60 as well.

The gate insulating film 61 is formed on the connection pattern CP and the gate electrode N2 of each driving transistor DT.

A semiconductor layer 62 is formed on the gate insulating film 61 at a position where a channel between the source electrode N1 and the drain electrode N2 of each driving transistor DT is to be formed, An electrode N2 and a drain electrode N3 are formed. At this time, the driving voltage line DVL and the data lines DL (4n-3) and DL (4n-2) are also formed. After the formation process, a planarization layer 63, a first electrode (E) of the organic light emitting diode, and the like are formed.

Through this formation process, the drain electrode N3 of the driving transistor DT of the pixel P1 connected to the (4n-3) th data line DL (4n-3) 2) connected directly to the driving voltage line RVL to the left of the region of the pixel P1 connected to the (4n-2) -th data line DL (-3n-3) DT is connected to a connection pattern CP connected to the driving voltage line RVL through a contact hole to form a driving voltage line connection structure.

6B is a sectional view showing a structure in which the driving voltage line RVL is connected to the two pixels P1 and P2 on the left side of the region of the pixel P1 connected to the (4n-3) th data line DL (4n-3) Is the same as the cross-sectional view showing a structure in which the driving voltage line RVL is connected to the remaining two pixels P3 and P4 to the right of the region of the pixel P4 connected to the 4n-th data line DL (4n) Do. This relates to the symmetry structure of the display panel 11 to be described later with reference to Fig.

Next, referring to FIG. 6C, the reference voltage line connection structure is checked.

First, the pixel connected to the (4n-2) th data line DL (4n-2) and the (4n-1) th data line DL (4n-1) are connected through the sectional view of III- A reference voltage line connection structure in which the first transistor T1 of each pixel P3 is directly connected to the reference voltage line RVL will be described.

First, the first transistor T1 of each of the pixels P3 connected to the 4n-2th data line DL (4n-2) and the pixel P3 connected to the 4n-1th data line DL (4n-1) Gate electrodes 64c and 65c are formed on the substrate 60. [

A gate insulating film 61 is formed on the gate electrodes 64c and 65c of each first transistor T1.

A semiconductor layer 62 serving as a channel of the source and drain electrodes 64b, 64c, 65b and 65c of each first transistor T1 is formed on the gate insulating film 61, T1 and the source and drain electrodes 64a, 64b, 65a, and 65b are formed.

The reference voltage lines RVL are formed together or integrally when the drain electrodes 64a and 65a of the first transistors T1 are formed.

Therefore, the first transistor T1 (T1) of each of the pixels P3 connected to the (4n-2) th data line DL (4n-2) and the pixel P3 connected to the (4n- Is directly connected to the reference voltage line RVL.

Next, the pixel connected to the 4n-3th data line (DL (4n-3)) and the pixel connected to the 4nth data line (DL (4n)) through the section IV-IV ' ) Are connected to a connection pattern (CP) connected to the reference voltage line (RVL).

The gate electrode of the first transistor T1 of each pixel P4 connected to the 4n-3th data line DL (4n-3) and the pixel P4 connected to the 4nth data line DL (4n) (66c, 67c) are formed on the substrate (60). At this time, a connection pattern CP of a metal material is also formed.

A gate insulating film 61 is formed on the gate electrodes 66c and 67c and the connection pattern CP of each first transistor T1.

A semiconductor layer 62 serving as a channel of the source and drain electrodes 66a, 66b, 67a and 67b of each first transistor T1 is formed on the gate insulating film 61, T1 and source and drain electrodes 66a, 66b, 67a, 67b are formed.

The drain electrodes 66a and 67a of each first transistor T1 are connected to the connection pattern CP through the contact holes.

According to this formation process, the first transistor T1 (T1) of each of the pixels P4 connected to the 4n-3th data line DL (4n-3) and the pixel P4 connected to the 4nth data line DL Is connected to the connection pattern CP connected to the reference voltage line RVL.

Hereinafter, the structure in which the first electrode E of the organic light emitting diode is formed in the pixel having the above-described pixel structure will be described with reference to FIG.

7 is a cross-sectional view illustrating a structure for connecting the source electrode N1 of the driving transistor DT and the first electrode (E: Electrode) of the organic light emitting diode, taken along line IV-IV 'in FIG.

Referring to Fig. 7, the gate electrode N2 of the driving transistor DT and the gate electrode 67c of the first transistor T1 are formed on the substrate 60. Fig. At this time, the source electrode N1 of the driving transistor DT is connected to the source electrode 67b of the first transistor T1, and the first plate 68 of metal material, which is one surface of the storage capacitor Cst, Are formed together on the substrate (60). Thereafter, a gate insulating film 61 is formed.

The semiconductor layer 62 serving as the channel of the source / drain electrodes N1 and N3 of the driving transistor DT and the semiconductor layer 62 serving as the channel of the source / drain electrodes 67b and 67a of the first transistor T1, Is formed on the gate insulating film 61.

Thereafter, the source / drain electrodes N1 and N3 of the driving transistor DT and the source / drain electrodes 67b and 67a of the first transistor T1 are formed.

At this time, the source electrode N1 of the driving transistor DT is connected to the first plate 68 formed together with the gate electrode N2 of the driving transistor DT and the gate electrode 67c of the first transistor T1 And the source electrode 67b of the first transistor T1 is connected to the first plate 68 formed together with the gate electrode N2 of the driving transistor DT and the gate electrode 67c of the first transistor T1, Respectively. At this time, in order to form the storage capacitor Cst, the second plate 69 is also formed on the gate insulating film 61 so as to correspond to the first plate 68 mentioned above.

Subsequently, a planarization layer 63 is formed on the organic light emitting diode, and an auxiliary electrode (SE: Sub Electrode) connected to the source electrode 67b of the first transistor T1 in the form of a contact hole is formed. A first electrode (E) is formed.

Here, the first electrode E of the organic light emitting diode is an anode electrode in the circuit configuration exemplified in the first embodiment, but may be a cathode electrode according to a change in circuit design. The auxiliary electrode SE is an electrode for assisting the connection of the first electrode E and the source electrode N1 of the driving transistor DT.

The first electrode E of the organic light emitting diode may be a transparent electrode such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium-Tin-Zinc-Oxide) The auxiliary electrode SE may be a metallic electrode such as silver (Ag) or aluminum (Al), for example. The auxiliary electrode SE may be formed of a material that supports the connection between the first electrode E and the source electrode N1 of the driving transistor DT It can also serve as a reflector as well as a role.

The source electrode N1 of the driving transistor DT, the source electrode 67b of the first transistor T1, the first plate 68 of the storage capacitor Cst and the first electrode E of the storage capacitor Cst in accordance with the above- ).

The pixel structure of the organic light emitting display device 10 according to the first embodiment of the present invention, that is, the 1-scan structure based on 3T1C (basic pixel structure) and the signal line connection structure have been described above. Hereinafter, the symmetrical structural features of the display panel 11 related to the above-described pixel structure will be described with reference to Fig.

8 is a simplified plan view for explaining symmetrical structural features of the display panel 11 of the organic light emitting display device 10 according to the first embodiment of the present invention.

8, the display panel 11 of the organic light emitting display device 10 according to the first embodiment of the present invention includes a 4n-th data line DL (4n- 3) and the pixel structure of the pixel P2 connected to the (4n-2) th data line DL (4n-2) are symmetrical to each other, and the pixel structure of the (4n-1) and the pixel structure of the pixel P4 connected to the (4n) th data line DL (4n) are symmetrical to each other.

The pixel structure connected to the (4n-2) th data line DL (4n-2) and the pixel structure of the pixel P1 connected to the 4n-3th data line DL (4n- Is symmetrical with respect to a virtual symmetry line between the (4n-3) th data line DL (4n-3) and the (4n-2) th data line DL (4n-2). The pixel structure of the pixel P3 connected to the (4n-1) th data line DL (4n-1) and the pixel structure of the pixel P4 connected to the 4nth data line DL (4n) Is symmetrical with respect to a virtual symmetry line between the data line DL (4n-1) and the 4nth data line DL (4n).

8, the display panel 11 of the organic light emitting display device 10 according to the first embodiment of the present invention includes a pixel 11 connected to the (4n-3) th data line DL (4n-3) The pixel structure of the pixel P1 connected to the 4n-th data line DL (4n-2) and the pixel structure of the pixel P4 connected to the 4n-th data line DL (4n) And the pixel structure of the pixel P3 connected to the (4n-1) th data line DL (4n-1) have a quadratic symmetric structure symmetrical to each other.

The pixel structure of the pixel P1 connected to the (4n-3) th data line DL (4n-3) and the pixel structure of the pixel P4 connected to the 4n th data line DL (4n) And is symmetrical with respect to the reference voltage line RVL. The pixel structure of the pixel P3 connected to the 4n-2th data line DL (4n-2) and the pixel structure of the pixel P3 connected to the 4n-1th data line DL (4n-1) And symmetrical with respect to the reference voltage line RVL.

As described above, in the display panel 11 of the organic light emitting display device 10 according to the first embodiment of the present invention, four data lines DL (4n-3), DL (4n-2), DL The four pixels P1 to P4 connected to the pixels 4n-1 and 4n have a first symmetry structure and a second symmetry structure simultaneously.

The pixel structure associated with such a double symmetric structure may include a 3T1C forming position and may further include an organic light emitting diode forming position. Here, the 3T1C forming position includes a transistor forming position, a capacitor forming position, and the like.

Each pixel region is divided into a light emitting region 81 in which organic light emitting diodes are emitted and a non-light emitting region 82 in which three transistors DT, T1 and T2 and a storage capacitor Cst are formed. ) And the position of the organic light emitting diode formation will be described in more detail with reference to FIG.

The forming positions of the driving transistor DT and the storage capacitor Cst of the P1 pixel and the forming positions of the driving transistor DT and the storage capacitor Cst of the P2 pixel are set so that the P1 pixel and the P2 pixel boundary And the formation positions of the drive transistor DT and the storage capacitor Cst and the formation positions of the drive transistor DT and storage capacitor Cst of the P4 pixel are symmetrical with respect to the P3 pixel and the P4 pixel boundary It is symmetrical by reference.

The formation positions of the first and second transistors T1 and T2 of the P1 pixel and the formation positions of the first and second transistors T1 and T2 of the P2 pixel are symmetrical with respect to the P1 pixel and the P2 pixel boundary , The formation positions of the first and second transistors T1 and T2 of the P3 pixel and the formation positions of the first and second transistors T1 and T2 of the P4 pixel are symmetrical with respect to the P3 pixel and the P4 pixel boundary.

The forming position of the organic light emitting diode forming position of the P1 pixel and the organic light emitting diode forming position of the P2 pixel are symmetrical to each other. The formation position of the organic light emitting diode forming position of the P3 pixel and the organic light emitting diode forming position of the P4 pixel are symmetrical to each other.

Here, the formation position of the organic light emitting diode may be a position where the first electrode 52 (anode electrode, but may be a cathode electrode when the circuit configuration is different) of the organic light emitting diode or the first electrode E of the organic light emitting diode And may be connected to the first node N1 of the driving transistor DT.

Regarding the quadratic symmetry structure, the formation positions of the driving transistor DT and the storage capacitor Cst of the P1 pixel and the formation positions of the driving transistor DT and the storage capacitor Cst of the P4 pixel are the reference voltage line RVL, And the formation positions of the drive transistor DT and the storage capacitor Cst and the formation position of the drive transistor DT and the storage capacitor Cst of the P3 pixel are symmetrical with respect to the reference voltage line RVL It is symmetrical by reference.

The formation positions of the first and second transistors T1 and T2 of the P1 pixel and the formation positions of the first and second transistors T1 and T2 of the P4 pixel are symmetrical with respect to the reference voltage line RVL , The formation positions of the first and second transistors T1 and T2 of the P2 pixel and the formation positions of the first and second transistors T1 and T2 of the P3 pixel are symmetrical with respect to the reference voltage line RVL.

The forming position of the organic light emitting diode forming position of the P1 pixel and the organic light emitting diode forming position of the P4 pixel are symmetrical to each other. The formation position of the organic light emitting diode forming position of the P2 pixel and the organic light emitting diode forming position of the P3 pixel are symmetrical to each other.

On the other hand, in the quadratic symmetric structure, the P1 pixel and the P4 pixel are symmetrical with respect to the reference voltage line (RVL) in the signal line connection structure, and the P2 pixel and the P3 pixel are connected to the reference voltage line RVL).

More specifically, the P1 pixel and the P4 pixel are directly connected to the driving voltage line DVL, and the positions to which the driving voltage EVDD is supplied are symmetrical with respect to the position of the reference voltage line RVL. The P1 and P4 pixels are not directly connected to the reference voltage line RVL but are supplied with the reference voltage Vref from the connection pattern CP connected to the reference voltage line RVL, RVL) are symmetrical with respect to each other.

The P2 pixel and the P3 pixel are connected directly to the connection pattern CP connected to the driving voltage line RVL without being directly connected to the driving voltage line DVL, and the driving voltage EVDD is supplied to the reference voltage line RVL ) Are symmetrical with respect to each other. The P2 and P3 pixels are directly connected to the reference voltage line RVL and are supplied with the reference voltage Vref and the supplied positions are symmetrical with respect to the reference voltage line RVL.

As described above, since the display panel 11 has a symmetrical structure (single symmetrical structure) in units of four pixel columns P1 to P4, the panel structure can be simplified and compact even under the 3T1C pixel structure, Probability can also be reduced by that much. Further, the aperture ratio can be further increased by changing the structure to use one scan signal in the 3T1C pixel structure in which two scan signals are necessarily required. As a result, a high-quality panel can be produced with a high yield. In particular, high resolution and large area panels can be manufactured with higher quality and higher yield.

8 is a panel structure of the display panel 11 of the organic light emitting display device 10, the double symmetric structure may be a liquid crystal display (LCD) or a graphene A quantum dot display device, and the like. In addition, the present invention can be equally applied to a display panel of any display device as long as a pixel can be defined in a matrix form. At this time, the pixel structure related to the double symmetric structure may include a transistor forming position, a capacitor forming position, and the like.

The display panel 11 of the organic light emitting display device 10 according to the first embodiment of the present invention and the symmetry of the pixel structure in the display panel 11 have been described above.

According to the pixel structure and the symmetry thereof of the first embodiment of the present invention, due to the regular signal line connection structure and the double symmetrical structure, a simple and compact panel design is possible, The probability of occurrence of defects can be reduced, and a high quality panel can be produced with a high yield.

According to the pixel structure and the symmetry of the pixel structure of the first embodiment of the present invention, since only one scan signal is used in the 3T1C pixel structure in which two scan signals are necessarily required, only one scan line is applied to one pixel row Only the lines can be formed on the display panel 11, thereby increasing the aperture ratio and reducing the probability of occurrence of defects.

The pixel structure of the first embodiment of the present invention and the aforementioned advantages in terms of its symmetry can have even greater advantages, especially in high resolution and large area panel design and manufacture.

On the other hand, the 3T1C pixel structure basically includes two scan signals (a scan signal for controlling the second transistor T2 serving as a switching transistor for applying a data voltage to the gate node N2 of the driving transistor DT, (A scan signal for controlling the first transistor T1 used for voltage sensing to grasp characteristic information (threshold voltage, mobility) of the data DT) must be discriminated and used.

However, since the first embodiment of the present invention uses only one scan signal for the various advantages described above, all operations (driving operation, sensing operation) of the pixel can be normally performed even if only one scan signal is used The driving operation and the sensing operation corresponding to the 3T1C based one scan structure must be performed.

Accordingly, the organic light emitting display device 10 according to the first embodiment of the present invention provides a driving method for a 3T1C-based one-scan structure.

The organic light emitting display 10 according to the first embodiment of the present invention includes an efficient driving operation (driving function or light emitting function) for driving the organic light emitting diode corresponding to a 1T scan structure based on 3T1C, A sensing operation for sensing a voltage for grasping characteristic information of the driving transistor DT in each pixel corresponding to one scanning structure of the pixel and compensating for the characteristic deviation between the driving transistors in each pixel by using the sensed voltage Vsen, A method for performing the operation will also be described. However, it is also referred to as a compensation configuration (external compensation configuration or external compensation circuit) including both configurations for sensing operation and compensation operation.

9 is a view schematically showing an external compensation structure included in the organic light emitting display device 10 according to the first embodiment of the present invention.

Referring to FIG. 9, in the compensation structure of the organic light emitting display device 10 according to the first embodiment of the present invention, the driving transistor DT in each pixel P capable of generating a luminance unbalance between pixels A sensing section 91 for sensing a voltage for grasping characteristic information (e.g., threshold voltage, mobility, etc.) of the driving transistor DT to compensate for the characteristic deviation (e.g., threshold voltage deviation, mobility deviation, A memory 92 for storing the sensed voltage, and a compensation unit 93 for sensing characteristic information of the driving transistor DT based on the sensed voltage and compensating for the characteristic information.

The sensing unit 91 senses the voltage for holding the characteristic information of the driving transistor DT in each pixel P and detects the voltage of the first node N1 of the driving transistor DT of each pixel P Voltage can be sensed.

9, the sensing unit 91 includes a digital-analog converter (DAC) 911 for converting a reference voltage Vref supplied from a reference voltage source into an analog value, a sensing unit An analog digital converter (ADC) 912 for converting the sensed voltage at the first node N1 of the driving transistor DT of each pixel P which can be connected to the driving transistor NT to a digital value, One of the reference voltage supply node 9131 to which the reference voltage Vref converted from the analog to digital conversion section 911 is supplied and the sensing node 9132 to which the analog to digital conversion section 912 is connected is connected to the reference voltage line RVL A first switch 913 for switching to be connected to the first switch 913, and the like.

It is necessary to apply a constant voltage to each of the first node N1 and the second node N2 of the driving transistor DT to sense the voltage for grasping the characteristic information of the driving transistor DT, The voltage must be changed at the first node N1 of the transistor N1 and the changed voltage must be measured as the sensing voltage.

In this regard, when the first switch 913 is connected to the reference voltage supply node 9131 and the reference voltage line RVL, the reference voltage Vref converted from the analog-to-digital conversion unit 911 to the analog voltage is supplied to the driving transistor Is applied to the first node N1 of the data line DT. In the first embodiment of the present invention, the data voltage Vdata is applied from the data line DL connected to the corresponding pixel to the driving transistor DT To the second node N2. 9, in order to sense the changed voltage at the first node N1 of the driving transistor DT, the first embodiment of the present invention is arranged so that the data voltage output point of the data driver 12 (ON) to be connected to the corresponding data line DL or to turn OFF the data voltage output point 9141 of the data driver 12 to be floated with the corresponding data line DL, One switch 914 may be provided for each data line. The second switch 914 may be functionally included in the sensing unit 91 corresponding to the pixel P. For example,

The second switch 914 described above is a configuration necessary for controlling the sensing timing for sensing the changed voltage at the first node N1 of the driving transistor DT.

In this regard, the same first scan signal is applied to the first transistor T1 and the second transistor T2 in each pixel. This makes it difficult to control the sensing timing by the first transistor T1, which is a sensor transistor In order to compensate for this, the second switch 914 may be additionally provided to implement the sensing timing.

The first switch 913 and the second switch 914 are turned on to sense the changed voltage at the first node N1 of the driving transistor DT in each pixel P The switching operation must be accurately performed to match the sensing operation.

The timing controller 14 is turned off so that the reference voltage line RVL is connected to the reference voltage supply node 9131 or the reference voltage line RVL is connected to the sensing node 9132, A first switch 913 for switching the data voltage output point 9141 of the data driver 12 to be connected to the data line DL or a data voltage output point 9141 of the data driver 12, ) To the data line DL can be controlled in accordance with the timing of the sensing operation so that the switching operation for the second switch 914 for switching to OFF is performed. The switching operation timing of the first switch 913 and the second switch 914 by the timing controller 14 will be described in more detail with reference to FIG.

The sensing unit 91 described above may be included in the data driver 12 or included in the data driver 12.

There may be a plurality of sensing units 91, and each sensing unit 91 may be provided for one data line or one for several data lines. In addition, each sensing unit 91 may be provided for each reference voltage line RVL.

The sensing unit 91 stores the sensed voltage in the memory 92 in a digital form or transmits the sensed voltage to the compensating unit 93 to compensate the characteristic information of the driving transistor DT.

The compensating unit 93 receiving the sensed voltage from the sensing unit 91 receives the voltage of the digital form received from the sensing unit 91 and receives the voltage of the driving transistor DT ) Can be performed.

The compensation unit 93 may be independent of any position in the organic light emitting display 10 only by receiving the voltage sensed from the sensing unit 91 in digital form.

For example, the compensation unit 93 may be included in the timing controller 14, included in the data driver 12, included outside the timing controller 14 and the data driver 12, .

10 is a diagram illustrating a case where the compensation unit 93 of the external compensation scheme included in the organic light emitting display device 10 according to the first embodiment of the present invention is implemented by being included in the timing controller 14, (B) implemented in the timing controller 14 and outside the data driver 12, and (c) included in the data driver 12, respectively .

10, it is assumed that the sensing unit 91 is included in the data driver 12 and implemented.

Referring to FIG. 10A, when the compensation unit 93 is implemented in the data driver 12, the sensing unit 91 outputs a voltage SI sensed by the pixel P, The compensation unit 93 included in the data driver 12 supplies the driving transistor DT to the compensation unit 93 based on the voltage SI transmitted from the sensing unit 91, And supplies the externally supplied data Data to the DAC (Digital Analog Converter) inside the data driver 12 by converting the externally supplied data Data into the received compensated data Data '. Accordingly, a digital analog converter (DAC) in the data driver 12 converts the digital compensation data Data supplied from the compensation unit 93 into analog data and supplies the analog data to the corresponding pixel P.

10 (b), when the compensation unit 93 is embodied outside the timing controller 14 and the data driver 12, the sensing unit 91 senses the pixel P The compensating unit 93 transmits the voltage SI to the compensating unit 93 outside the data driving unit 12 and the timing controller 14. The compensating unit 93 compensates the voltage SI based on the voltage SI transmitted from the sensing unit 91 The characteristic data of the transistor DT can be grasped and the data Data supplied from the timing controller 14 can be converted into the compensation data Data ' The data driver 12 converts the digital compensation data Data 'supplied from the compensation unit 93 through a DAC (Digital Analog Converter) provided therein and converts the compensated data Data' into analog data and supplies the analog data to the pixel P.

10 (c), when the compensation unit 93 is included in the data driver 12, the sensing unit 91 in the data driver 12 may sense The compensating unit 93 transmits a voltage SI to the compensating unit 93 in the data driving unit 12. The compensating unit 93 compensates the characteristic information of the driving transistor DT based on the voltage SI transmitted from the sensing unit 91, And supplies data (Data) supplied from the timing controller 14 to the DAC (Digital Analog Converter) by converting the data (Data) into the compensation data (Data '). Accordingly, the DAC (Digital Analog Converter) converts the compensation data (Data ') of the digital form supplied from the compensation unit 93 to analog, and supplies the compensation data (data voltage) Supply.

10 (b) and 10 (c), the compensation unit 93 may be supplied directly from the timing controller 14 in the method of receiving the data Data, but the timing controller 14 may supply data , It can be supplied by reading the data stored in the memory.

An example of the compensation unit 93 shown in FIGS. 10A to 10C is a digital-based compensation method for converting digital data Data into digital compensation data Data ' (Data conversion method). In this case, it is possible to generate digital type compensation data Data 'through calculation processing such as adding or subtracting the digital value of the characteristic information of the driving transistor DT to the digital type data Data.

11 is a circuit diagram showing an example in which the external compensation configuration (the sensing section 91, the memory 92 and the compensation section 93) is applied to the equivalent circuit for one pixel (P) Fig.

On the other hand, when the number of reference voltage lines is equal to the number of data lines, that is, when one reference voltage line is formed for each pixel P arranged in the horizontal direction (the other direction) There may be a sensing unit 91 corresponding to each pixel P. [ In this case, the sensing operation can be performed simultaneously on all the pixels arranged in the horizontal direction (the other direction). In other words, if the reference voltage line RVL is formed in correspondence with each of the four pixels P1 to P4 in FIG. 5, at the same time, It is possible to sense the changed voltage at the node N1.

However, when the number of reference voltage lines is smaller than the number of data lines, for example, when the number of reference voltage lines is 1/4 of the number of data lines, that is, every four pixels P arranged in the horizontal direction When one reference voltage line is formed, a sensing operation can not be performed for all the pixels arranged in the horizontal direction (the other direction) at the same time, and a sensing operation can be performed for one pixel for every four pixels. That is, if one reference voltage line RVL is formed for the four pixels P1 to P4 as shown in FIG. 5, the first node of the driving transistor DT of each of the four pixels P1 to P4 N1 can not be sensed at the same time and only the changed voltage at the first node N1 of the driving transistor DT of one of the four pixels P1 to P4 can be sensed at a specific point in time .

Therefore, it may be necessary to select a pixel for sensing the changed voltage at the first node N1 of the driving transistor DT among the four pixels P1 to P4 at a specific point in time.

As a method for this, there is a first method of selecting pixels by controlling on / off of the second switch SW2, a first method of turning on the second switch SW2, and a second method of turning on the second switch SW2, There can be a way.

(4n-3) th data line DL (4n-2), 4n-1 th data line DL Th data lines DL (4n-1) and the 4n-th data lines DL (4n) by controlling only one of the second switches SW2 connected to the first data line DL (4n-1) th pixel connected to the (4n-2) th data line DL (4n-1) The data voltage Vdata may be applied only to the second node N2 of the driving transistor DT included in one of the pixels connected to the data line DL (4n). This allows the sensing unit 91 to control so that a pixel for sensing the changed voltage at the first node N1 of the driving transistor DT is selected. The pixel selection method for such sensing will be described by way of example with reference to FIG.

FIG. 12 is a diagram illustrating an external compensation structure according to the embodiment of FIG. 10 and a plurality of pixels P1 to P4.

FIG. 12 is a circuit diagram of a pixel driving circuit in which a pixel P3 connected to the 4n-1th data line DL (4n-1) among the four pixels P1 to P4 is selected and the first node N1 (Threshold voltage, mobility) of the driving transistor DT of the selected pixel to sense and compensate for the characteristic information (threshold voltage, mobility) of the selected pixel.

12, in order to select the pixel P3 connected to the (4n-1) th data line DL (4n-1) among the four pixels P1 to P4, the timing controller 14 selects four pixels (4n-3), DL (4n-2), DL (4n-1) and DL (4n) capable of supplying data voltages to the data lines DL Only the second switch 914c for switching the connection with the (4n-1) -th data line DL (4n-1) among the first to third switches 914a, 914b, 914c and 914d is turned on, The switches 914a, 914b and 914d can send a control signal (second switch control signal) to each sensing part 91 or the data driving part 12 to be turned off.

On the other hand, all of the second switches SW2 connected to the 4n-3th data line, the 4n-2th data line, the 4n-1th data line and the 4nth data line are all turned on (4n-3) th data line, the (4n-2) th data line, the (4n-1) th data line and the 4nth data line, A pixel connected to the data line DL (4n-1), a pixel connected to the (4n-1) th data line DL (4n-1) The data voltage Vdata may be applied only to the second node N2 of the driving transistor DT included in one of the pixels connected to the 4nth data line DL (4n). This allows the sensing unit 91 to control so that a pixel for sensing the changed voltage at the first node N1 of the driving transistor DT is selected.

12, the timing controller 14 selects the pixel P3 connected to the (4n-1) th data line DL (4n-1) among the four pixels P1 to P4, A data voltage Vdata necessary for sensing is input to only the pixel P3 for sensing and a constant voltage (a voltage which is turned off, for example, 0.5 V) different from the data voltage is applied to the remaining pixels P1, P2, It is possible to control the pixel to be selected for sensing by controlling the input voltage to be input.

13, in addition to the embodiment of the compensation unit 93 shown in FIGS. 10A to 10C, that is, the digital-based compensation scheme (data conversion scheme), the data driver 12 Receives the digital data Data from the timing controller 14 and the DAC of the data driver 12 converts the digital data Data into an analog signal using the gamma reference voltage, Converts the characteristic information SI of the transistor DT received from the sensing unit 91 into an analog value and converts the analog data into analog data based on the characteristic information converted into the analog value, And may generate a data voltage as data. This method is a complete analog-based compensation method (data conversion method).

14, the data driver 12 receives the digital data Data from the timing controller 14 and outputs the digital data Data to the DAC (compensator) of the data driver 12 93) generates the compensation data Data 'using the characteristic information of the transistor DT received from the sensing unit 91 when converting the digital data Data to analog using the gamma reference voltage And convert it into an analog form to generate a data voltage. This method is also referred to as an analog-based compensation method (data conversion method) because the data is strictly converted in a digital form, but is performed in a step of converting to an analogue (DAC step).

The sensing operation (sensing function) and compensation function (sensing operation) briefly described above will be described in more detail with reference to Figs. 17 to 24 together with the driving operation (driving function).

The display panel 11, the sensing unit 91, the compensation unit 93, and the like have been described in the overall system configuration of the organic light emitting display device 10 according to the first embodiment of the present invention, Hereinafter, the data driver 12 and the gate driver 13 will be briefly described with reference to FIGS. 15A, 15B, and 16. FIG.

15A and 15B are block diagrams of a data driver 12 included in the organic light emitting display device 10 according to the first embodiment of the present invention.

15A is a diagram showing the data driver 12 when the data driver 12 receives the compensation data and drives the data line and FIG. 15B shows the data driver 12 including the compensator 93 Fig.

15A, the data driver 12 included in the organic light emitting display device 10 according to the first embodiment of the present invention includes a shift register 151, a first data register 152, A register 153, a digital / analog converter (DAC) 154, an output buffer 155, a data receiving unit 156, and the like.

The data receiving unit 156 receives the compensation data Data 'from the compensating unit 93 included in the timing controller 14 or the data driving unit 12 or included in the outside of the timing controller 14 and the data driving unit 12, And converts them into predetermined bit digital data for each RGB and outputs them.

The shift register 151 controls the operation time by using a horizontal clock signal Hclock and a horizontal synchronization signal Hsync for driving a line by line, All the data Data 'corresponding to one gate line GL which receives the clock signal Hclock from the timing controller 14 and selects the horizontal synchronizing signal Hsync as the start signal is inputted to the horizontal clock signal Hclock Synchronized and sequentially sampled and stored in the first data register 152.

The first data register 152 sequentially stores the data Data 'to be implemented by the pixels of the (m-1) th gate line GL (m-1).

The second data register 153 stores the data Data 'stored in the first data register 152 according to the next horizontal synchronization signal Hsync. At this time, data (Data ') to be implemented by the pixels of the m-th gate line GL (m) are sequentially stored in the first data register 152.

Each of the first data register 152 and the second data register 153 described above may be implemented as a latch in which an output and an input are connected to each other through two inverters, 152 and the second data register 153 are also referred to as a first latch and a second latch.

The DAC 154 converts the digital data (Data ') stored in the second data register 153 into an analog data voltage on the basis of the gamma reference voltage supplied from the outside.

The output buffer 155 supplies the data voltage through the data line so as to amplify the pixel driving force, that is, to have sufficient current driving capability for driving the data line.

FIG. 15B is a diagram showing a data driver 12 including a compensation unit 93. FIG.

Referring to FIG. 15B, the data driver 12 receives uncompensated data from the timing controller 14, and the compensator 93 included therein can compensate the data to drive the data line.

Since the data driver 12 shown in FIG. 15B receives uncompensated data differently from the data driver 12 shown in FIG. 15A, the functions of the data receiver 156 and the DAC 154 are different.

Referring to FIG. 15B, the data receiving unit 156 receives the data Data before being compensated from the timing controller 14, and converts the data into predetermined bit digital data for each RGB.

The DAC 154 further converts the digital data Data stored in the second data register 153 into an analog data voltage on the basis of the gamma reference voltage supplied from the outside, The sensing voltage SI received may be further converted. Therefore, the DAC 154 included in the data driver 12 of FIG. 15B includes the compensator 93 as an internal configuration.

16 is a configuration diagram of the gate driver 13 included in the organic light emitting display device 10 according to the first embodiment of the present invention.

16, the gate driver 13 included in the organic light emitting display 10 according to the first embodiment of the present invention includes a shift register 161, a level shifter 162, an output buffer 163, And the like.

The shift register 161 receives a vertical synchronization signal Vsync notifying the start of one frame from the timing controller 14 and starts generating a scan pulse so that the output of the scan pulse is sequentially turned on in accordance with the vertical clock signal Vclock do. Further, a logic operation circuit such as preventing the influence of the signal delay by shortening the charging time of the gate line by using the output enable signal (OE) can be included.

The level shifter 162 converts the scan pulse into a voltage capable of turning on and off the first and second transistors T1 and T2. That is, the on-voltage Von and the constant voltage Von, which are lower than a predetermined voltage necessary for turning on or turning on the first and second transistors T1 and T2, may be set in accordance with the on-voltage signal Von and the off- To a turn-off voltage (Voff) below.

The output buffer 163 may be formed of a circuit for outputting a scan signal by improving the current driving capability so as to be suitable for driving the gate line GL having an RC load.

The gate driver 13 supplies the scan signals to the gate nodes of the first and second transistors T1 and T2 through one gate line GL.

The gate driver 13 applies a scan signal level (a second level VGH or a first level VGL) for turning on the first and second transistors T1 and T2 according to the control signal of the timing controller 14, ) Is greater than or equal to one horizontal time (HT). Here, one horizontal time may be a time at which the data voltage is applied to the second level (VGH). From this point of view, the fact that the scan signals for turning on the first and second transistors T1 and T2 are supplied for one horizontal time or longer means that the scan signals for turning on the first and second transistors T1 and T2 are supplied The time for which the data voltage is supplied to the second level VGH may be longer than the time for which the data voltage is supplied to the second level VGH, Lt; RTI ID = 0.0 &gt; of the &lt; / RTI &gt; data voltage.

The gate driver 13 applies a scan signal level (a second level VGH or a first level VGL) for turning on the first and second transistors T1 and T2 according to the control signal of the timing controller 14, ) Can supply a scan signal faster than the application time of the data voltage.

As described above, when the time for which the levels of the first and second transistors T1 and T2 are turned on (the second level VGH or the first level VGL) becomes equal to or longer than one horizontal time HT The time point at which the scan signal is supplied or the level at which the first and second transistors T1 and T2 are turned on (the second level VGH or the first level VGL) The reason for supplying the signal is for data charging.

In this case, when the length of the gate line GL, which is the supply path of the scan signal, becomes long, the time taken for the scan signal to reach each of the pixels connected to the selected gate line GL may vary from pixel to pixel. That is, the time taken for the scan signal to reach the backward from the pixel located first in the direction in which the scan signal is supplied may take longer. In this case, a pixel supplied with a scan signal at a later time may have a shorter data-charging time than a pixel supplied with a scan signal earlier, resulting in a delay in the emission timing of the pixel or a failure to achieve a desired brightness. This phenomenon may occur more seriously in the large-area or high-resolution display panel 11. [ Therefore, as described above, by applying the scan signal to the scan signal for a long time before the data voltage is applied, it is possible to reduce a phenomenon in which the data charging is insufficient or the image quality is lowered due to the scan signal arrival time difference between the pixels.

The gate driver 13 may control the sensing time to be able to sense the changed voltage at the first node N1 of the driving transistor DT to be longer or shorter in accordance with the control signal of the timing controller 14 , And supply a scan signal for turning on the first and second transistors (T1, T2) for a time corresponding to the length of the sensing time. This is necessary for the pixel to operate separately from the S-sensing mode and the F-sensing mode during the sensing mode.

Hereinafter, a driving method of the organic light emitting display device 10 according to the first embodiment of the present invention will be described with reference to FIGS. 17 to 24. FIG.

17 is a flowchart of a method of driving the organic light emitting display device 10 according to the first embodiment of the present invention.

Referring to FIG. 17, a method of driving an organic light emitting display 10 according to a first embodiment of the present invention includes a connection pattern CP connected to a reference voltage line RVL or a reference voltage line RVL, A scan signal is commonly supplied to the first transistor T1 for connecting between the first node of the driving transistor DT and the second transistor T2 for connecting the data line and the second node of the driving transistor DT, And supplying a reference voltage and a data voltage to the first node and the second node of the driving transistor DT through the first transistor T1 and the second transistor T2 commonly controlled by the scan signal S170) and controlling supply of at least one of the reference voltage, the data voltage, and the scan signal (S172) so that the pixel operates in one of the driving mode and the sensing mode.

17, in step S172, the level of the scan signal is changed from the first level to the second level to turn on the first transistor T1 and the second transistor T2 to turn on the first node T1 of the driving transistor DT, The reference voltage Vref and the data voltage Vdata are respectively applied to the first node N1 and the second node N2 and then the level of the scan signal is changed to the first level, And driving the organic light emitting diode (S174). At this time, it is assumed that the pixel operates in a driving mode.

17, in step S172, the level of the scan signal is changed from the first level to the second level to turn on the first transistor T1 and the second transistor T2 to turn off the driving transistor DT The reference voltage Vref and the data voltage Vdata are applied to the first node N1 and the second node N2 respectively and then the reference voltage Vref applied to the first node N1 of the driving transistor DT (Slow-Sensing) step S176 for sensing a voltage changed at the first node N1 of the driving transistor DT by floating only the first node N1 of the driving transistor DT. At this time, the pixel is assumed to operate in the S-sensing mode.

17, in step S172, the level of the scan signal is changed to turn on the first transistor T1 and the second transistor T2 to turn on the first node N1 of the driving transistor DT and the second node N1 of the driving transistor DT. The reference voltage Vref and the data voltage Vdata are respectively applied to the node N2 and the reference voltage Vref and the reference voltage Vref are applied to the first node N1 and the second node N2 of the driving transistor DT, A F-sensing step of sensing the voltage changed at the first node N1 of the driving transistor DT by floating all of the data voltage Vdata or floating only the reference voltage Vref S178). At this time, the pixel is assumed to operate in the F-sensing mode.

In the above-described S-sensing step S176, from the time when only the reference voltage Vref applied to the first node N1 of the driving transistor DT is floated, until the level of the scan signal is changed back to the first level It is possible to sense the voltage changed at the first node N1 of the driving transistor DT by setting the time to &quot; S-sensing time &quot;.

The reference voltage Vref and the data voltage Vdata are both floated or the reference voltage Vdata is applied to the first node N1 and the second node N2 of the driving transistor DT in the F- The time until the level of the scan signal is changed back to the first level from the time when only the floating gate Vref is turned on is referred to as &quot; F-sensing time &quot;, and the time from the first node N1 of the driving transistor DT The changed voltage can be sensed.

The above-mentioned S-sensing time is longer than F-sensing time. The S-sensing time and the F-sensing time may vary depending on the device characteristics of the driving transistor DT and the like in the pixel. For example, the S-sensing time is about 10 msec and the F-sensing time is about 100 μsec .

The length of the S-sensing time and the F-sensing time can be controlled by a scan signal supplied to the first and second transistors in the gate driver 13 in accordance with the control signal of the timing controller 14. [ That is, the length of the S-sensing time and the F-sensing time can be controlled by adjusting the time during which the level of the scan signal for turning on the first and second transistors T1 and T2 is maintained.

The aforementioned S-sensing step S176 is a stage which is operated only before shipment of the organic light emitting display device 10 and the above-described F-sensing step S178 is performed before and after shipment of the organic light emitting display device 10 It can be set as a step that can be operated all after that. Here, before and after shipment of the organic light emitting display device 10 may be classified according to whether the serial number of the organic light emitting display device 10, shipping information, or sensing step identification information that can be operated is stored .

17, after the S-sensing step S176 or the F-sensing step S178, a compensation for compensating for at least one of the threshold voltage and the mobility of the driving transistor DT on the basis of the sensed voltage, Step S180 may be further included.

As described above, the pixel can operate in one of a driving mode and a sensing mode (S-sensing mode, F-sensing mode), and the timing controller 14 can control the operation mode of the pixel.

For example, the timing controller 14 controls the switching operation (ON / OFF) of the first switch SW1 and the second switch SW2 and the waveform of the scan signal so that the data voltage To be operated in one of the driving mode and the sensing mode.

18 shows waveforms of scan signals for three modes (drive mode, S-sensing mode, and F-sensing mode) in which pixels of the organic light emitting display device 10 according to the first embodiment of the present invention operate, 1 switches SW1, 913 and the second switches SW2, 914, respectively.

18, the level of the scan signal may be the first level or the second level. When the level of the scan signal is the second level, the first transistor T1 and the second transistor T2 are turned on ). In this specification, since the first transistor T1 and the second transistor T2 are N-type, the first level is the low level (VGL) and the second level is the high level (VGH). When the type of the first transistor T1 and the second transistor T2 is changed to P type, the second level may be a low level (VGL) and the first level may be a high level (VGH)

First, referring to Fig. 18A showing the timing chart of the drive mode, the timing controller 14 controls the first switch SW1 and the second switch SW2 to be always on, The scan signal level is changed from the first level (VGL) to the second level (VGH) and then the scan signal is changed to the first level (VGL) To operate in the drive mode.

That is, the timing controller 14 supplies a scan signal for turning on the first transistor T1 and the second transistor T2 for a predetermined time, and the first switch SW1 and the second switch SW2 It can be controlled so as to be always on so that the pixel capable of supplying the data voltage by the second switch SW2 can be controlled to operate in the driving mode.

In this driving mode, a period during which the scan signal for turning on the first transistor T1 and the second transistor T2 is supplied for a predetermined time, that is, a period during which the scan signal level is the second level (VGH) (STEP1), and the period after the scan signal level is changed to the first level (VGL) is the drive step (STEP2).

In relation to the driving mode, the gate driving unit 130 changes the level of the scan signal from the first level (VGL) to the second level (VGH) so that the data voltage is applied to the second node (N2) ), And supply the scan signal in such a manner that the high second level (VGH) of the scan signal is equal to or longer than one horizontal time according to the control signal. That is, the gate driver 130 may supply the scan signal for at least one horizontal time such that the first transistor T1 and the second transistor T2 are turned on.

The gate driving unit 130 may control the timing at which the level of the scan signal is changed from the first level VGL to the second level VGH when the level of the data voltage is changed to the second level VGH, The scan signal can be controlled according to the control signal so as to be ahead of the scan signal application time. That is, the gate driver 130 may supply a scan signal for turning on the first transistor T1 and the second transistor T2 before the data voltage supply time.

Next, referring to FIG. 18 (b) showing the timing chart of the S-sensing mode, the timing controller 14 controls the first switch SW1 to be turned off and the second switch SW2, So that the pixel capable of supplying the data voltage by the second switch SW2 can start to operate in the S-sensing mode during the sensing mode.

That is, the timing controller 14 controls the first switch SW1 while the scan signal for turning on the first transistor T1 and the second transistor T2 is supplied for a predetermined period of time (the entire S-sensing mode) And the second switch SW2 are turned on so that only the first switch SW1 is turned off so that the pixel capable of supplying the data voltage by the second switch SW2 operates in the S-sensing mode during the sensing mode Can be controlled.

More specifically, the timing controller 14 turns on the first switch SW1 when the second switch SW2 is turned on so that the first switch SW1 and the second switch SW2 are turned on together The first transistor T1 and the second transistor T2 are controlled by the scan signal so that the first node N1 and the second node N2 of the driving transistor DT receive the reference voltage Vref and data The voltage at the first node N1 of the driving transistor DT can be controlled to be changed by controlling only the first switch SW1 to be turned off after the voltage Vdata is applied to the driving transistor DT.

The sensing unit 91 senses the timing at which supply of the scan signal for turning on the first transistor T1 and the second transistor T2 from the time when only the first switch SW1 is turned off (The time point at which the level of the scan signal changes from the second level VGH to the first level VGL) is set to the S-sensing time, and the first node N1 of the driving transistor DT during the S- (Vdata-Vth) of the first transistor Q1 can be sensed.

The period in which the scan signal level is the second level (VGH) is the entire S-sensing mode. In the entire S-sensing mode, a period in which the first switch (SW1) and the second switch (SW2) (STEP1), and the section in which only the first switch SW1 is turned off is the sensing step STEP2.

Next, referring to FIG. 18 (c) showing the timing chart of the F-sensing mode, the timing controller 14 controls the first switch SW1 and the second switch SW2 to be turned off together So that the pixel capable of supplying the data voltage by the second switch SW2 can start to operate in the F-sensing mode during the sensing mode.

That is, the timing controller 14 controls the first switch SW1 while the scan signal for turning on the first transistor T1 and the second transistor T2 is supplied for a predetermined time (F-sensing mode full period) And the second switch SW2 are turned on and all of them are turned off or only the first switch SW1 is turned off so that the pixel capable of supplying the data voltage by the second switch SW2 is turned off in the F- As shown in Fig.

More specifically, the timing controller 14 controls the first switch SW1 and the second switch SW2 to be on together so that the first node N1 of the driving transistor DT and the second node N1 of the driving transistor DT are turned on, The first switch SW1 and the second switch SW2 are both turned off or only the first switch SW1 is turned off so that the reference voltage Vref and the data voltage Vdata are applied to the node N2, The reference voltage Vref and the data voltage Vdata supplied to the first node N1 and the second node N2 of the driving transistor DT are floated or only the reference voltage Vref is floated , So that the voltage at the first node N1 of the driving transistor DT can be controlled to change.

Accordingly, the sensing unit 91 is turned on when the first switch SW1 and the second switch SW2 are both turned off, or when the first switch SW1 is turned off, The time from when the supply of the scan signal for turning on the transistor T2 is completed (the time point at which the level of the scan signal changes from the second level (VGH) to the first level (VGL)) is taken as the F- It is possible to sense the changed voltage at the first node N1 of the driving transistor DT during the sensing time. Here, the F-sensing time is considerably shorter than the S-sensing time.

The period during which the scan signal for turning on the first transistor T1 and the second transistor T2 is supplied, that is, the period during which the scan signal level is the second level (VGH), is the entire F-sensing mode. In the entire F-sensing mode, a period in which both the first switch SW1 and the second switch SW2 are ON is an initialization step (STEP1). When the first switch SW1 and the second switch SW2 are both off Or the section in which only the first switch SW1 is turned off is the sensing step STEP2.

Here, the sensing step STEP2 of the F-sensing mode is considerably shorter than the sensing step STEP2 of the S-sensing mode. That is, the F-sensing time is considerably shorter than the S-sensing time. This is because the gate driver 13 controls the first transistor T1 and the second transistor T2 to be turned on in the F-sensing mode rather than the S-sensing mode under the control of the timing controller 14 The time for supplying the signal can be made much shorter.

In FIG. 18, the first level (VGL) of the scan signal and the first level (VGL) of the first switch (SW1) and the second switch (SW2) may have the same or different voltage values. The second level (VGH) of the scan signal and the second level (VGH) of the first switch (SW1) and the second switch (SW2) may have the same or different voltage values.

In the following, three operation modes (drive mode, S-sensing mode, F-sensing mode) briefly described above will be described in more detail.

First, the drive mode will be described with reference to Figs. 19A, 19B and 20.

19A and 19B are circuit diagrams when a pixel of the organic light emitting display device 10 according to the first embodiment of the present invention operates in a driving mode. FIG. 20 is a graph of voltage change when a pixel of the organic light emitting display device 10 according to the first embodiment of the present invention operates in a driving mode.

FIG. 19A is a circuit diagram for the drive mode initialization step (STEP1) in FIG. 18A, and FIG. 19B is a circuit diagram for the drive step STEP2 in FIG.

19A, in the initialization step (STEP1) of the drive mode, the first switch SW1 and the second switch SW2 are turned on and the scan signal level is changed from the first level VGL to the second level Level (VGH) is maintained. At this time, the first and second transistors T1 and T2 are turned on and the reference voltage Vref is applied to the first node N1 of the driving transistor DT and the data voltage Vdata is applied to the second node N2. Is applied.

Here, the potential difference (Vgs = Vdata-Vth) between the first node N1 (source node) and the second node N2 (gate node) of the driving transistor DT is higher than the threshold voltage Vth of the driving transistor DT The reference voltage Vref and the data voltage Vdata can be set.

The voltage of the first node N1 of the driving transistor DT must be higher than the sum of the threshold voltage of the organic light emitting diode and the ground voltage EVSS to allow current to flow through the organic light emitting diode.

Since the voltage of the first node N1 of the driving transistor DT in the initializing step STEP1 is the reference voltage Vref and the reference voltage Vref is lower than the voltage at which the current can flow in the organic light emitting diode, In the initialization step (STEP1), no current flows through the organic light emitting diode. Here, the reference voltage Vref may be set to be lower than a voltage which is higher than the threshold voltage Vth 'of the organic light emitting diode at the base voltage EVSS so that the current can flow through the organic light emitting diode (Vref &Lt; EVSS + Vth '). For example, when the ground voltage EVSS is set to the ground (GND) voltage, the reference voltage Vref may be set to be lower than the threshold voltage of the organic light emitting diode.

A constant voltage capable of turning on the driving transistor DT is applied to the first node N1 and the second node N2 of the driving transistor DT and the driving transistor DT is turned on in the initialization step STEP1, The voltage Vref applied to the first node N1 of the driving transistor DT is set such that the current does not flow to the organic light emitting diode and therefore the current Ids flowing through the driving transistor DT flows through the first node N1 Voltage line RVL. At this time, the voltage of the first node N1 of the driving transistor DT is not changed.

20, when the voltage of the scan signal becomes lower between t2 and t3, that is, when the level of the scan signal, which turns on the first transistor T1 and the second transistor T2, When the first transistor T1 and the second transistor T2 are turned off by the level VGL, the driving step STEP2 starts from this point. At this point in time, the level of the scan signal is changed to the first level (VGL) in FIG. 18 (b).

FIG. 19B shows a circuit diagram in the driving step STEP2.

19B and 20, in the driving step STEP2, the voltage of the first node N1 and the voltage of the second node N2 of the driving transistor DT become constant And the conduction current Ids of the driving transistor DT which has flowed from the reference voltage line RVL via the first node N1 to the reference voltage line RVL in the initializing step STEP1 is supplied to the reference voltage line RVL through the first node N1, (RVL) and flows into the organic light emitting diode, and the organic light emitting diode starts to emit light.

As the conduction current Ids of the driving transistor DT flows into the organic light emitting diode, the voltage of the first node N1 of the driving transistor DT gradually increases, The node N2 also increases gradually. This voltage increase occurs until the voltage of the first node N1 of the driving transistor DT becomes equal to the sum of the ground voltage EVSS and the threshold voltage of the organic light emitting diode, Lt; / RTI &gt;

Next, the S-sensing mode, which is a type of sensing mode, will be described with reference to Figs. 21A, 21B, 22A, and 22B.

21A and 21B are circuit diagrams when a pixel of the organic light emitting display device 10 according to the first embodiment of the present invention operates in the S-sensing mode. 22A is a voltage change graph when a pixel of the organic light emitting display device 10 according to the first embodiment of the present invention operates in the S-sensing mode. 22B is a graph of Vgs-Ids showing a threshold voltage deviation of the driving transistor DT of each pixel.

FIG. 21A is a circuit diagram for the S-sensing mode initialization step (STEP1) in FIG. 18B, and FIG. 21B is a circuit diagram for the sensing step STEP2 in FIG. 18B.

21A, in the initializing step (STEP1) of the S-sensing mode, when the first switch SW1 and the second switch SW2 are ON and the scan signal level is changed at the first level VGL And the second level (VGH) is maintained. At this time, the first and second transistors T1 and T2 are turned on and the reference voltage Vref is applied to the first node N1 of the driving transistor DT and the data voltage Vdata is applied to the second node N2. Is applied. At this time, the storage capacitor Cst is charged and stores a constant potential difference (Vdata-Vref) at both ends N1 and N2.

Referring to (b) of FIG. 18, by turning off only the first switch SW1, the sensing step STEP2 starts and continues until the level of the scan signal is changed to the first level VGL. The time length of the sensing step (STEP2) is the S-sensing time in the S-sensing mode.

The circuit diagram in the sensing step STEP2 is shown in Fig. 21B.

21B and 22A, since the second switch SW2 is turned on in the sensing step STEP2, the voltage (gate voltage) of the second node N2 of the driving transistor DT becomes the positive voltage Vdata, And the voltage (source voltage) of the first node N1 of the driving transistor DT gradually rises as the charge Q charged in the storage capacitor Cst is discharged in the initializing step STEP1 (Boosting).

22A, the rise of the voltage (source voltage) of the first node N1 of the driving transistor DT causes a voltage difference between the first node N1 and the second node N2 of the driving transistor DT And reaches the threshold voltage Vth of the driving transistor DT. This is because the current Ids flowing between the drain node N3 and the source node N1 of the driving transistor DT becomes equal to the threshold voltage Vth when Vgs of the driving transistor DT becomes equal to the threshold voltage Vth, Is 0, which can be confirmed also in the Vgs-Ids graph shown in Fig. 22B.

Ids is the current flowing between the drain node N3 and the source node N1 of the driving transistor DT and Vgs is the current flowing between the first node N1 of the driving transistor DT and the second node N2 ), And Vth is the threshold voltage of the driving transistor DT. k is a component for the mobility of the driving transistor DT, μ is a mobility, Cox is an oxide capacitance, W is a channel width, and is a channel length. Lt; / RTI &gt;

22A, when the rise of the voltage (source voltage) of the first node N1 of the driving transistor DT is stopped, the sensing section 91 is turned on at the first node N1 of the driving transistor DT And the voltage of the output terminal is sensed. The voltage (Vsen) sensed at this time is expressed by the following equation (2).

In the expression (2), Vsen is the voltage sensed at the first node N1 of the driving transistor DT, Vdata is the data voltage as the constant voltage applied to the second node N2 of the driving transistor DT, Is the threshold voltage of the driving transistor DT.

If the voltage Vdata-Vth sensed by the sensing unit 91 is converted into a digital value and the digital value of the sensing voltage is subtracted from the digital value of the already known data voltage Vdata, The threshold voltage Vth can be obtained. The threshold voltage (Vth) of the found drive transistor (DT) can be stored in the memory (92). Since the data voltage Vdata is already known, the digital value of the sensing voltage Vdata-Vth may be stored in the memory 92 as it is.

22B, when the threshold voltage (or sensing voltage) of the driving transistor DT for each pixel stored in the memory 92 is compared, the driving transistor DT for each pixel, which can generate the luminance deviation of each pixel, The compensating unit 93 can perform data conversion processing for compensating the threshold voltage deviation for each pixel in order to compensate for the threshold voltage deviation.

Referring to FIG. 22B, when the threshold voltage REF_Vth is 0 [volt], when the threshold voltage is found to be Vth in a certain pixel, when the data voltage is supplied to the pixel, (Vth = Vth-REF_Vth = Vth-0 = Vth) between the threshold voltage and the reference threshold voltage detected in this pixel with reference to the reference threshold voltage REF_Vth stored in a lookup table in the pixel , The compensation data voltage (Vdata + Vth) generated by adding the threshold voltage (Vth) to the original data voltage (Vdata) can be supplied to eliminate the threshold voltage deviation. By supplying the compensation data voltage to other pixels in the same manner as described above, it is possible to eliminate the imbalance of the inter-pixel luminance according to the threshold voltage deviation of the driving transistor DT.

Next, the F-sensing mode, which is a type of sensing mode, will be described with reference to FIGS. 23A, 23B, 24A, and 24B.

23A and 23B are circuit diagrams when a pixel of the organic light emitting display device 10 according to the first embodiment of the present invention operates in the F-sensing mode. 24A is a graph of voltage change when the pixel of the organic light emitting display device 10 according to the first embodiment of the present invention operates in the F-sensing mode. FIG. 24B is a graph of Vgs-Ids showing the mobility deviation of the driving transistor DT of each pixel.

Fig. 23A is a circuit diagram for the initializing step (STEP1) of the F-sensing mode in Fig. 18C, and Fig. 23B is a circuit diagram for the sensing step (STEP2) in Fig.

23A, in the initializing step (STEP1) of the F-sensing mode, when the first switch SW1 and the second switch SW2 are ON and the scan signal level is changed at the first level VGL And the second level (VGH) is maintained. At this time, the first and second transistors T1 and T2 are turned on and the reference voltage Vref is applied to the first node N1 of the driving transistor DT and the data voltage Vdata is applied to the second node N2. Is applied. At this time, the storage capacitor Cst is charged and a constant potential difference (Vdata-Vref) is applied to both ends N1 and N2.

Meanwhile, a capacitor Cdl is connected to or formed on the data line DL connected to the drain node of the second transistor T. The same data voltage Vdata is applied to the capacitor Cdl of the data line DL when a constant data voltage Vdata is applied to the second node N2 of the driving transistor DT. Here, the capacitor Cdl of the data line DL is a capacitor which serves to keep the voltage of the second node N2 of the driving transistor DT constant, and is larger than the capacitance of the storage capacitor Cst Capacitance value.

Referring to (c) of FIG. 18, when both the first switch SW1 and the second switch SW2 are turned off, the sensing step STEP2 starts and the level of the scan signal is changed to the first level VGL .

The time length of the sensing step (STEP2) of the F-sensing mode is shorter than the S-sensing time in the S-sensing mode as the F-sensing time in the F-sensing mode.

The circuit diagram in the sensing step STEP2 is shown in Fig. 23B.

Referring to FIGS. 23B and 24A, in the sensing step STEP2, when the first switch SW1 and the second switch SW2 are turned off, the voltage of the second node N2 of the driving transistor DT Is constantly maintained at a constant voltage Vdata for a certain period of time by the capacitor Cdl of the data line DL and the charge Q charged in the storage capacitor Cst is discharged in the initialization step STEP1, The voltage (source voltage) of the first node N1 of the transistor DT starts to increase and gradually increases until the level of the scan signal is changed to the first level VGL.

18 (c) and 23 (b), in the sensing step STEP2 of the F-sensing mode, the voltage (gate voltage) of the second node N2 of the driving transistor DT is set to a constant voltage Vdata , A data voltage source (not shown) for supplying the data voltage Vdata may be used as in the sensing step STEP2 of the S-sensing mode . 18 (c) corresponding to the case where the capacitor Cdl of the data line DL is used as the constant voltage source for the switching operation of the second switch SW2 in the sensing step STEP2 of the F-sensing mode, The timing diagram of the second switch SW2 in Fig. 18B corresponding to the case where the data voltage source is used as the constant voltage source can be used without using the timing chart for the second switch SW2.

Referring to FIG. 24B, the mobility k of the driving transistor DT corresponds to the slope of the Vgs-Ids graph. When the slope difference occurs, the mobility deviation of the driving transistor DT occurs. In order to compensate for the deviation, the data to be supplied to the pixel (s) is converted into compensation data and supplied, so that the deviation of the mobility of the driving transistor DT of each pixel can be reduced. The mobility deviation can be reduced by generating the compensation data so that the mobility of the driving transistor DT of each pixel becomes the reference mobility REF_k that can be referred to in a lookup table in the memory 92 . Accordingly, it is possible to eliminate the unevenness of the inter-pixel luminance due to the drift variation of the driving transistor DT.

Hereinafter, a method of processing the display panel 11 of the organic light emitting display device 10 according to the first embodiment of the present invention described above will be briefly described with reference to FIGS. 25A to 25F.

25A to 25F are views showing a manufacturing process of the display panel 11 of the organic light emitting display device 10 according to the first embodiment of the present invention. However, in FIGS. 25B to 25F, for convenience of explanation, the drawing numbers shown in the previous step are not displayed in the next step.

25A, a gate line 251a for forming the gate electrodes of the first transistor T1 and the second transistor T2, a gate line 251b for forming the gate electrode of each driving transistor DT, A connection pattern 252a connected to each driving voltage line DVL and a connection pattern 252b connected to each reference voltage line RVL and a first plate 252b for forming each storage capacitor Cst, (252c) are formed on the substrate (250).

Here, the gate line 251b is a common gate line for commonly applying a scan signal to the gate electrodes of the first transistor T1 and the second transistor T2 included in each of the connected pixels. Therefore, the portion where the gate electrode is to be formed in the gate line 251b is formed wider than the other portion in consideration of the designed channel length L. In addition, the portion where the gate electrode is not formed in the gate line 251b may be narrowed so as to minimize the parasitic capacitance.

25B, the semiconductor layer 253a of the source-drain region of each driving transistor DT, the semiconductor layer 253b of the source-drain region of each first transistor T1, The semiconductor layer 253c of the source-drain region of the second transistor T2 is connected to the gate electrode 251a, the gate line 251b, and the driving voltage line DVL of each driving transistor DT, A connection pattern 252b connected to each reference voltage line RVL and a first plate 252c for forming each storage capacitor Cst are formed on a substrate 250. The substrate 252a is connected to the reference voltage line RVL,

In the second process step, the semiconductor layer 253a of the source-drain region of each driving transistor DT is for forming a channel, and the gate electrode 251a of each driving transistor DT formed in the first process step, As shown in Fig. The semiconductor layer 253b of the source-drain region of each first transistor T1 is formed at a position corresponding to a portion serving as a gate electrode of each first transistor T1 in the gate line 251b. The semiconductor layer 253c of the source-drain region of each second transistor T2 is formed at a position corresponding to a portion serving as a gate electrode of each second transistor T2 in the gate line 251b.

In the third process step, referring to Fig. 25C, one reference voltage line 254 for every four pixel columns, two driving voltage lines 255a and 255b for every four pixel columns, And signal lines such as data lines 256a, 256b, 256c, and 256d are formed.

Referring to FIG. 25C, the reference voltage line 254 formed in the third process step is connected to the drain electrode of the first transistor T1 of the pixel connected to the (4n-2) th data line 256b and the drain electrode of the And a protrusion serving as a drain electrode of the first transistor T1 of the pixel connected to the first transistor M1.

The driving voltage lines 255a and 255b formed in the third process step are connected to the drain electrode of the driving transistor DT of the pixel connected to the 4n-3th data line 256a and the 4nth data line 256d And a projection serving as a drain electrode of the driving transistor DT of the pixel.

Further, the data lines 256a, 256b, 256c, and 256d formed in the third process step include protrusions serving as drain electrodes of the second transistors T2 of all the pixels.

25C, the connection pattern 252b (connection pattern of the reference voltage line 254) formed in the first process step and the drain electrode of the first transistor T1 connected to the contact hole And a drain electrode 257b of the driving transistor DT connected to the contact hole by a contact pattern formed in the first process step and a connection pattern 252a (connection pattern of driving voltage lines 255a and 255b) The source electrode 257c of the transistor DT and the portion connected to the gate electrode 251a of the driving transistor DT of each pixel through the contact hole and the portion serving as the source electrode of the second transistor DT of each pixel And a source electrode 257e of the first transistor T1 of each pixel connected to the first plate 252c and the contact hole are formed on the first plate 252c and the second plate 257d, .

The drain electrode 257a connected to the connection pattern 252b (connection pattern of the reference voltage line 254) in the third process step is connected to the (4n-3) th data line 256a The drain electrode of the first transistor T1 of the pixel and the drain electrode of the first transistor T1 of the pixel connected to the 4nth data line 256d.

Referring to FIG. 25C, the drain electrode 257b connected to the connection pattern 252a (the connection pattern of the driving voltage lines 255a and 255b) in the third process step is connected to the (4n-2) th data line 256b and The drain electrode of the driving transistor DT of the pixel to be connected and the drain electrode of the driving transistor DT of the pixel connected to the (4n-1) th data line 256c.

25D, the first plate 252c connected to the source electrode 257c of the driving transistor DT of each pixel and the source electrode 257e of the first transistor T1 at each pixel An anode auxiliary electrode 258a connected to each other is formed in each contact hole.

In the fifth process step, referring to FIG. 25E, the anode electrode 258b of the organic light emitting diode connected to the anode auxiliary electrode 258a formed previously is formed.

In the sixth process step, referring to FIG. 25F, a pixel defining layer 259 (also referred to as a &quot; bank &quot;) defining a pixel is formed. An organic layer (not shown) including a light emitting layer corresponding to each pixel may be stacked on the pixel defining layer 259 of each pixel, and common electrodes for all the pixels may be stacked on the organic layer. On the other hand, in the case of WOLED (White Organic Light Emitting Diode), a color filter can be formed in a direction in which organic layers including the same light emitting layer are laminated and emitted in all the pixels.

In the process for the display panel 11 of the organic light emitting display device 10 according to the first embodiment described with reference to Figs. 25A to 25F, the gate electrode 251a is located below the semiconductor layer 253b However, the gate electrode 251a may be a top gate located on the semiconductor layer 253b, which is an example only for convenience of explanation. In case of a top gate, the above-described process steps can be modified to match the top gate structure. On the other hand, in the case of a bottom gate, the semiconductor layer 253b may be, for example, amorphous silicon or an oxide semiconductor. In the case of a top gate, the semiconductor layer 253b may be, for example, a polycrystalline silicon But is not limited thereto.

The first embodiment having the one scan structure has been described above, and the second embodiment having the two scan structure will be described below.

<2nd Example >

26 is an overall system configuration diagram of an organic light emitting display device 260 according to a second embodiment of the present invention.

26, an organic light emitting display 260 according to a second embodiment of the present invention includes a display panel 261 including a plurality of pixels P, A data driver 262 for supplying a data voltage through the formed data lines DL (1) to DL (4N) and a data driver 262 for crossing the data lines DL (1) to DL (4N) A first gate driver 263 for supplying a first scan signal through the first gate lines GL1 (1) to GL1 (M) formed in the other direction; A second gate driver 264 for supplying a second scan signal through the second gate lines GL2 (1) to GL2 (M) formed in parallel with the first gate driver GL2 A timing controller 265 for controlling the driving timing of the first gate driver 263 and the second gate driver 264, and the like.

Here, the number of data lines is 4N, and the number of the first gate lines and the number of the second gate lines are M, respectively. N and M are natural numbers of 1 or more. In addition, n used for identifying each data line in the entire 4N data lines is a natural number of 1 or more and 1/4 or less of the number of data lines (1? N? (4N / 4)).

The first gate driver 263 and the second gate driver 264 described above may be separately implemented, and in some cases, they may be included in one gate driver.

Each pixel P is connected to one data line DL, one first gate line GL1, and one second gate line GL2. The pixel structure of each pixel P will be described with reference to FIG.

27 is an equivalent circuit diagram of one pixel P in the display panel 261 of the organic light emitting display device 260 according to the second embodiment of the present invention.

27, one pixel P in the display panel 261 of the organic light emitting display device 260 according to the second embodiment of the present invention basically includes three transistors DT, T1, T2 ) And one capacitor (Cst).

That is, each pixel P is controlled by the organic light emitting diode OLED, the driving transistor DT for driving the organic light emitting diode, the first scan signal supplied from the first gate line GL1, A first transistor T1 connected between the connection pattern CP connected to the voltage line RVL or the reference voltage line RVL and the first node N1 of the driving transistor DT, A second transistor T2 controlled by a second scan signal supplied from the scan driver GL2 and connected between a data line DL and a second node N2 of the driving transistor DT, And a storage capacitor Cst connected between the first node N1 and the second node N2.

As described above, each pixel P is supplied with two scan signals (a first scan signal and a second scan signal) through two gate lines (a first gate line and a second gate line). Hereinafter, the first scan signal is also referred to as a "sense signal (SENSE)", and the second scan signal is also referred to as a "scan signal (SCAN)".

Since the two scan signals SCAN and SENSE are supplied to each pixel P in this way, the basic pixel structure of the second embodiment of the present invention is referred to as a &quot; 2 scan structure &quot;.

The driving transistor DT in each pixel P receives the driving voltage EVDD supplied from the driving voltage line DVL and the voltage of the gate node N2 applied through the second transistor T2 ) To drive the organic light emitting diode (OLED).

The driving transistor DT has a first node N1, a second node N2 and a third node N3. The first node N1 is connected to the first transistor T1, The second node N2 is connected to the second transistor T2 and the third node N3 is supplied with the driving voltage EVDD.

Here, the first node of the driving transistor DT is a source node (also referred to as a "source electrode"), the second node is a gate node (also referred to as a gate electrode) The third node N3 may be a drain node (also referred to as a drain electrode). Depending on the circuit implementation, the first, second and third nodes of the driving transistor DT may be switched.

The first transistor T1 is controlled by the first scan signal SENSE supplied from the first gate line GL1 and is connected to the reference voltage line RVL or the reference voltage line RVL for supplying the reference voltage Vref, And the first node N1 of the driving transistor DT. The first transistor T1 is also referred to as a &quot; sensor transistor &quot;.

The second transistor T2 is controlled by a second scan signal SCAN commonly supplied from the second gate line GL2 and is connected to the second node N2 of the data line DL and the driving transistor DT . The second transistor T2 is also referred to as a &quot; switching transistor &quot;.

The storage capacitor Cst may be connected between the first node N1 and the second node N2 of the driving transistor DT to maintain the data voltage for one frame.

The pixel structure of the organic light emitting display device 260 according to the second embodiment of the present invention is different from the pixel structure of the basic pixel structure (2T scan based on 3T1C) described with reference to FIG. 27, A data line DL for supplying a data voltage, a first gate line GL1 for supplying a first scan signal SENSE, a second gate line GL2 for supplying a second scan signal SCAN, A driving voltage line DVL for supplying a driving voltage EVDD, and a reference voltage line RVL for supplying a reference voltage Vref.

The plurality of signal lines include not only a data line for supplying a data voltage to each pixel, a first gate line for supplying a first scan signal, a second gate line for supplying a second scan signal, A reference voltage line RVL for supplying the reference voltage Vref to the pixel, and a driving voltage line DVL for supplying the driving voltage EVDD.

The reference voltage line RVL and the driving voltage line DVL described above are formed in parallel with the data line DL, and each number may be equal to or less than the number of data lines.

If the number of reference voltage lines and the number of driving voltage lines are equal to the number of data lines, each pixel is connected to one data line DL and one gate line GL, ) And one reference voltage line (RVL).

In this case, the signal line connection structures of the respective pixels may be the same. That is, the basic unit of the signal line connection structure is one pixel, and the regularity of the signal line connection structure may be one pixel (one pixel column).

If the number of reference voltage lines and the number of driving voltage lines are smaller than the number of data lines, some of the pixels may be directly connected to the driving voltage line DVL and the reference voltage line RVL, The driving voltage line DVL and the reference voltage line RVL may be connected to the reference voltage line RVL through the connection pattern CP without being directly connected to the reference voltage line DVL and the reference voltage line RVL.

In this case, the signal line connection structures of the respective pixels may not be all the same. However, even if the structure in which each pixel is connected to the signal line is not the same, the structure in which the signal line is connected to every pixel can be the same. That is, the unit of the signal line connection structure may be a plurality of pixels instead of one pixel P, and the regularity of the signal line connection structure may repeatedly appear for a plurality of pixels (a plurality of pixel columns).

For example, the signal line connection structure can be repeated for each of the four pixels P1, P2, P3, and P4, that is, the regularity of the signal line connection structure is repeated for every four pixels (four pixel columns) In this case, the basic unit of the signal line connection structure may be four pixels (four pixel columns).

Thus, when the basic unit of the signal line connection structure is four pixels (four pixel columns), the number of reference voltage lines may be one fourth of the number of data lines. That is, when the number of data lines is 4N, the number of reference voltage lines may be N.

As described above, when the basic unit of the signal line connection structure is four pixels (four pixel columns), the reference voltage line connection structure may be as follows.

A pixel capable of receiving a data voltage from each of four arbitrary data lines DL (4n-3), DL (4n-2), DL (4n-1), DL (4n) Only the pixels P1 through P4 connected to the four data lines DL (4n-3), DL (4n-2), DL (4n-1) and DL (4n) One reference voltage line RVL is connected to the pixels P1 to P4 connected to the four data lines DL (4n-3), DL (4n-2), DL (4n-1) And is formed on the display panel 11 in parallel with the data lines.

The one reference voltage line RVL is connected to two data lines among the four data lines DL (4n-3), DL (4n-2), DL (4n-1) (4n-2) and DL (4n-1), and supplies the remaining two data lines (for example, DL (4n-3) The reference voltage Vref can be supplied to each pixel connected to the pixel through the connection pattern.

On the other hand, when the basic unit of the signal line connection structure is four pixels, the number of driving voltage lines may be 1/2 or 1/4 of the number of data lines. That is, when the number of data voltage lines is 4N, the number of driving voltage lines may be 2N or N. [

For example, if the number of driving voltage lines is 2N, the number of pixels connected to the four data lines DL (4n-3), DL (4n-2), DL (4n-1) To P4 are connected to four data lines DL (4n-3), DL (4n-2), DL (4n-1) and DL (4n) The two driving voltage line connection structures for the pixels P1 to P4 are as follows.

The two driving voltage lines DVL are connected to one of the pixels P1 to P4 connected to the four data lines DL (4n-3), DL (4n-2), DL (4n-3), DL (4n-3), and DL (4n) are supplied directly to the pixels connected to the two data lines (E.g., DL (4n-2), DL (4n-1)) among the pixels P1 through P4 connected to the data lines DL (4n-1) The driving voltage EVDD can be supplied through the connected connection pattern.

In this specification and the drawings, the P1 pixel refers to all the pixels (i.e., a pixel column) connected to the 4n-3th data line DL (4n-3) May mean only. The pixel P2 may refer to all the pixels connected to the (4n-2) -th data line DL (4n-2), or may denote only a specific pixel connected to the selected gate line among all pixels. The pixel P3 may refer to all the pixels connected to the (4n-1) -th data line DL (4n-1), or may be a specific pixel connected to the selected gate line among all the pixels. The pixel P4 may refer to all the pixels connected to the 4n-th data line DL (4n) or may denote only a specific pixel connected to the selected gate line among all the pixels.

In this specification and the figures, the pixel connected to the 4n-3th data line DL (4n-3), the pixel connected to the 4n-2th data line DL (4n-2) A red pixel, a green pixel, a blue pixel, and a blue pixel, which are connected to a pixel connected to the first data line DL (4n-1) and a 4nth data line DL (4n) White) pixel.

Although the transistors DT, T1, and T2 are shown and described as being of the N type in the present specification and the drawings, ) May all be changed to P type, or some of transistors DT, T1, T2 may be implemented as N type and others as P type. In addition, the organic light emitting diode (OLED) may be changed to an inverted type.

In addition, the transistors DT, T1, T2 described herein are also referred to as thin film transistors (TFTs).

Hereinafter, the pixel structure including the basic pixel structure (one scan structure based on 3T1C) and the signal line connecting structure briefly described above will be described in more detail with reference to FIG. 28 to FIG. However, Figs. 28 to 30 show the case where the basic unit of the signal line connection structure is four pixels.

28 is a plan view schematically showing a part of a display panel 261 of an organic light emitting display device 260 according to a second embodiment of the present invention. 29 is a plan view showing in detail FIG. FIG. 30 is an equivalent circuit diagram of FIG. 29, which is a circuit diagram in which an equivalent circuit diagram for one pixel shown in FIG. 27 is applied to four pixels.

28 to 30, if the basic unit of the signal line connection structure is four data lines (DL (4n-3), DL (4n-2), DL (4n-1) and DL The signal connection structure and the basic pixel structure (1 scan structure based on 3T1C) can be confirmed for four pixels (P1 to P4).

28 to 29, four data lines DL (4n-3), DL (4n-2), DL (4n-1) and DL (4n) And P4, respectively. Each of the first gate line GL1 (m), 1? M? M and the second gate line GL2 (m), 1? M? M is connected to four pixels P1, P2, P3 and P4 .

27, four pixels P1 to Pn connected to the four data lines DL (4n-3), DL (4n-2), DL (4n- P4 are controlled by a first scan signal and are supplied with a reference voltage Vref to apply a first voltage Vdd to the first voltage Vref of the driving transistor DT, And a second transistor N2 which is controlled by a second scan signal and receives a data voltage Vdata and transmits the data voltage Vdata to a second node N2 of the driving transistor DT. T2 and a capacitor Cst connected between the first node N1 and the second node N2 of the driving transistor DT.

Each of the four pixels P1 to P4 connected to the four data lines DL (4n-3), DL (4n-2), DL (4n-1) A first scan signal and a second scan signal are applied to the first transistor T1 and the second transistor T2 in common to the 3T1C structure including the data lines DT, T1 and T2 and the one capacitor Cst, And has a structure to be supplied. As described above, the pixel structure of each of these pixels is referred to as &quot; 3T1C-based 2-scan structure &quot;.

Each of the four pixels P1 to P4 connected to the four data lines DL (4n-3), DL (4n-2), DL (4n-1) And the number of scan signals are the same, signal line connection structures (signal applying methods) for receiving data voltages, driving voltages, reference voltages, and the like may be different from each other. However, the signal line connection structure between the four pixels P1 to P4 connected to the four data lines DL (4n-3), DL (4n-2), DL (4n-1) There is regularity and symmetry. 28 to 30, the signal line connection structure will be described in detail below.

As described above, since the basic unit of the signal line connection structure is four pixels (4n-3), DL (4n-2), DL (4n-1) P1 to P4), one reference voltage line RVL for supplying the reference voltage Vref is formed for the four pixels P1 to P4, and a driving voltage Vdd for supplying the driving voltage EVDD Two lines DVL may be formed.

First, the reference voltage line connection structure will be described.

In the display panel 261, when the number of data lines is 4N and the number of reference voltage lines is N, the pixel P1 connected to the (4n-3) th data line DL (4n-3) The pixel P3 connected to the 4n-th data line DL (4n-2), the pixel P3 connected to the 4n-1th data line DL (4n- One reference voltage line RVL corresponding to the first voltage line for supplying the first voltage Vref is formed in one direction parallel to the data lines.

The region of the pixel P2 connected to the (4n-2) th data line DL (4n-2) and the region of the pixel P2 connected to the (4n-1) th data line DL (4n-1) depend on the number of the reference voltage lines RVL formed. One reference voltage line RVL corresponding to the first voltage line for supplying the first voltage (reference voltage, Vref) may be formed between the regions of the pixel P3 connected to the pixel P3. That is, one reference voltage line RVL is connected to the pixels P1 through P4 connected to the four data lines DL (4n-3), DL (4n-2), DL (4n- In the middle of the entire area of the image.

The position of formation of these reference voltage lines enables a symmetrical pixel structure.

(4n-1)) connected to the (4n-2) th data line DL (4n-2) according to the formation position of the reference voltage line RVL The first transistor T1 included in each of the pixels P3 is connected directly to the reference voltage line RVL and includes a pixel P1 connected to the (4n-3) th data line DL (4n-3) The first transistor T1 included in each of the pixels P4 connected to the line DL 4n is connected to a connection pattern CP connected to the reference voltage line RVL.

According to this reference voltage line connection structure, the pixel P3 connected to the pixel P2 connected to the 4n-2th data line DL (4n-2) and the 4n-1th data line DL (4n-1) The first transistor T1 included in each of the pixels T1 and T2 receives the reference voltage Vref directly from the reference voltage line RVL and is connected to the pixel P1 connected to the (4n-3) th data line DL (4n-3) The first transistor T1 included in each of the pixels P4 connected to the 4n-th data line DL (4n) applies the reference voltage Vref from the connection pattern CP connected to the reference voltage line RVL Receive.

Next, the driving voltage line connection structure will be described.

In the display panel 261, when the number of data lines is 4N and the number of reference voltage lines is N, the pixel P1 connected to the (4n-3) th data line DL (4n-3) The pixel P3 connected to the 4n-th data line DL (4n-2), the pixel P3 connected to the 4n-1th data line DL (4n- The driving voltage line DVL corresponding to the second voltage line for supplying the second voltage EVDD is formed in a direction parallel to the data lines.

With respect to the number of the driving voltage lines DVL, the number of the data lines DL (4n-3) is set to 4n-3 when the number of data lines is 4N and the number of driving voltage lines is 2N in the display panel 11 To a second voltage line for supplying a second voltage (drive voltage, EVDD) to the right side of the region of the connected pixel P1 and the right side of the region of the pixel P4 connected to the 4nth data line DL (4n) Two corresponding driving voltage lines RVL may be formed.

The formation position of such a driving voltage line enables a symmetric pixel structure.

The driving transistor DT and the 4n-th data line DL (4n) of the pixel P1 connected to the (4n-3) th data line DL (4n-3) The driving transistor DT of the pixel P4 connected to the driving voltage line RVL is directly connected to the driving voltage line RVL.

The driving transistor DT of the pixel P2 connected to the (4n-2) th data line DL (4n-2) is connected to the pixel P1 connected to the (4n-3) And a connection pattern CP connected to the driving voltage line RVL formed on the left side of the area of the driving voltage line RVL. The driving transistor DT of the pixel P3 connected to the (4n-1) th data line DL (4n-1) is formed on the right side of the pixel P4 connected to the 4nth data line DL And is connected to a connection pattern CP connected to the driving voltage line RVL.

According to such a driving voltage line connection structure, the pixel P4 connected to the 4n-3th data line DL (4n-3) and the pixel P4 connected to the 4nth data line DL (4n) The driving transistor DT receives the driving voltage EVDD directly from the different driving voltage lines RVL.

The driving transistor DT included in the pixel P2 connected to the (4n-2) th data line DL (4n-2) is connected to the pixel connected to the (4n-3) th data line DL 1) th data line DL (4n-1) to which the driving voltage EVDD is applied from the connection pattern CP connected to the driving voltage line RVL formed on the left side of the region of the (4n-1) The driving transistor DT of the pixel P3 is driven from the connection pattern CP connected to the driving voltage line RVL formed on the right side of the region of the pixel P4 connected to the (4n) th data line DL (4n) ).

Next, the data line connection structure will be described.

Each of the four data lines DL (4n-3), DL (4n-2), DL (4n-1) and DL (4n) is connected to pixels in each of four pixel columns.

(4n-3) th data line DL (4n-3) and the (4n-3) th data line DLn Each of the data lines DL (4n-1) is formed on the right side of the area of the corresponding pixel P1 or P3 connected thereto. Each of the even-numbered data lines, that is, the (4n-2) th data line DL (4n-2) and the 4nth data line DL (4n) do.

The formation position of such a data line enables a symmetrical pixel structure.

Next, the gate line connection structure will be described.

The 4N data lines DL (4n-3), DL (4n-2), DL (4n-1), and DL (4n) are sequentially connected to one pixel row (Pixel Row) A first gate line GL1 (m) for supplying a first scan signal SENSE to the first transistor T1 of each pixel, and a second gate line GL2 A second gate line GL2 (m) for supplying a second scan signal SCAN to the second transistor T2 of each pixel is formed.

As described above, by forming the two gate lines GL1 (m) and GL2 (m) with respect to one pixel row, it is possible to reduce the number of pixels included in each pixel in one pixel row The first transistor T1 and the second transistor T2 can be controlled differently. This is because the basic pixel structure of the second embodiment of the present invention has a 3T1C-based 2-scan structure.

The pixel structure of the organic light emitting display device 260 according to the second embodiment of the present invention, that is, the 2-scan structure based on 3T1C (basic pixel structure) and the signal line connection structure have been described above. Hereinafter, with reference to Fig. 31, symmetrical structural features of the display panel 261 related to the above-described pixel structure will be described.

31 is a simplified plan view for explaining symmetrical structural features of the display panel 261 of the organic light emitting display device 260 according to the second embodiment of the present invention.

31, the display panel 261 of the organic light emitting display device 260 according to the second embodiment of the present invention includes a 4n-th data line DL (4n- 3) and the pixel structure of the pixel P4 connected to the 4n-th data line DL (4n) are symmetrical to each other and the pixel structure of the 4n-2th data line DL (4n-2) ) And the pixel structure of the pixel P3 connected to the (4n-1) th data line DL (4n-1) are symmetrical to each other.

In this symmetric structure, the pixel structure of the pixel P1 connected to the 4n-3th data line DL (4n-3) and the pixel structure of the pixel P4 connected to the 4nth data line DL (4n) 1 is symmetrical with respect to the reference voltage line RVL corresponding to the first voltage line supplying the first voltage. The pixel structure of the pixel P3 connected to the 4n-2th data line DL (4n-2) and the pixel structure of the pixel P3 connected to the 4n-1th data line DL (4n-1) And is symmetrical with respect to the reference voltage line (RVL) corresponding to the first voltage line supplying the first voltage.

As described above, in the display panel 261 of the organic light emitting display device 260 according to the second embodiment of the present invention, four data lines DL (4n-3), DL (4n-2), DL The four pixels P1 to P4 connected to the pixel electrodes 4n-1 and 4n have a single symmetrical structure with respect to the reference voltage line RVL.

The pixel structure associated with the single symmetric structure may include a 3T1C forming position, and may further include a signal line connecting method (position) and an organic light emitting diode forming position. Here, the 3T1C forming position includes a transistor forming position, a capacitor forming position, and the like.

Each pixel region is divided into a light emitting region 311 in which organic light emitting diodes are emitted and a non-emitting region 312 in which three transistors DT, T1 and T2 and a storage capacitor Cst are formed. (Single symmetrical structure) related to the 3T1C formation position, the signal line connection method (position) and the organic light emitting diode formation position in the light emitting diode (OLED) will be described in more detail with reference to FIG.

Regarding the symmetrical structure, the forming positions of the driving transistor DT and the storage capacitor Cst and the forming positions of the driving transistor DT and the storage capacitor Cst of the P4 pixel are the same as the reference voltage line RVL And the formation positions of the drive transistor DT and the storage capacitor Cst and the formation position of the drive transistor DT and the storage capacitor Cst of the P3 pixel are symmetrical with respect to the reference voltage line RVL It becomes symmetrical.

The formation positions of the first and second transistors T1 and T2 of the P1 pixel and the formation positions of the first and second transistors T1 and T2 of the P4 pixel are symmetrical with respect to the reference voltage line RVL , The formation positions of the first and second transistors T1 and T2 of the P2 pixel and the formation positions of the first and second transistors T1 and T2 of the P3 pixel are symmetrical with respect to the reference voltage line RVL.

In addition, the organic light emitting diode forming position of the P1 pixel and the organic light emitting diode forming position of the P4 pixel are symmetrical to each other. The positions where the organic light emitting diode is formed in the P2 pixel and the positions where the organic light emitting diode is formed in the pixel P3 are symmetrical to each other.

The signal line connection method of the P1 pixel and the signal line connection method of the P4 pixel are symmetrical to each other, and the signal line connection method of the P2 pixel and the signal line connection method of the P3 pixel are symmetrical to each other.

More specifically, the P1 pixel and the P4 pixel are directly connected to the driving voltage line DVL, and the positions to which the driving voltage EVDD is supplied are symmetrical with respect to the position of the reference voltage line RVL. The P1 and P4 pixels are not directly connected to the reference voltage line RVL but are supplied with the reference voltage Vref from the connection pattern CP connected to the reference voltage line RVL, RVL) are symmetrical with respect to each other.

The P2 pixel and the P3 pixel are connected directly to the connection pattern CP connected to the driving voltage line RVL without being directly connected to the driving voltage line DVL, and the driving voltage EVDD is supplied to the reference voltage line RVL ) Are symmetrical with respect to each other. The P2 and P3 pixels are directly connected to the reference voltage line RVL and are supplied with the reference voltage Vref and the supplied positions are symmetrical with respect to the reference voltage line RVL.

As described above, since the display panel 261 has a symmetrical structure (single symmetrical structure) in units of four pixel columns (P1 to P4), even under the 3T1C pixel structure in which two scan signals (SENSE, SCAN) The panel structure can be simplified and compact, the probability of occurrence of defects can be reduced as much, and the aperture ratio can be increased. As a result, a high-quality panel can be produced with a high yield. In particular, high resolution and large area panels can be manufactured with higher quality and higher yield.

Meanwhile, the organic light emitting display device 260 according to the second embodiment of the present invention includes an efficient sensing function for enabling the characteristic information of the driving transistor DT included in each pixel to be grasped, A compensating function capable of compensating for the characteristic information of the driving transistor DT included in the pixel to reduce the characteristic deviation between the driving transistors DT in each pixel and to provide a sensing function and a compensating function efficiently Will be described with reference to Figs. 32 and 33. Fig.

The external compensation function (sensing function and compensation function) of the organic light emitting display device 260 according to the second embodiment of the present invention is similar to that of the organic light emitting display device 10 according to the first embodiment of the present invention, It is basically the same as the function. Particularly, the compensation function is the same as the first embodiment and the second embodiment. However, since the first embodiment has a one scan structure, the second embodiment of the present invention is only a two scan structure, and there is only a slight difference in the method for controlling the sensing time with respect to the sensing function. Therefore, the description of the same compensation function (i.e., compensation section) as that of the first embodiment will be omitted below, and a description will be made mainly of the difference from the first embodiment.

FIG. 32 is a diagram showing an external compensation structure of the organic light emitting display device 260 according to the second embodiment of the present invention, together with an equivalent circuit for one pixel P. In FIG.

32, the organic light emitting display device 260 according to the second embodiment of the present invention is characterized in that a characteristic deviation (i.e., a variation in luminance) of the driving transistor DT in each pixel P A sensing unit 320 for sensing a voltage for grasping characteristic information (e.g., threshold voltage, mobility, and the like) of the driving transistor DT to compensate for variations in the threshold voltage And a compensation unit 340 for compensating the characteristic information of the driving transistor DT based on the sensed voltage.

The sensing unit 320 senses a voltage for grasping the characteristic information of the driving transistor DT in each pixel P and detects the voltage of the first node N1 of the driving transistor DT of each pixel P 32, a digital-to-analog converter (DAC) 321 for converting a reference voltage Vref supplied from a reference voltage source to an analog value, a sensing unit 320 for sensing a voltage Vsen, An analog-to-digital converter (ADC) 322 for converting the sensed voltage at the first node N1 of the driving transistor DT of each pixel P connectable to the digital-analog converter One of the reference voltage supply node 3231 to which the reference voltage Vref converted from the analog voltage conversion unit 321 is supplied and the sensing node 3232 connected to the analog digital conversion unit 912 is connected to the reference voltage line RVL, The first switch 323 and the like.

The sensing unit 320, the memory 330 and the compensating unit 340 of the second embodiment of the present invention are the same as the sensing unit 91, the memory 92 and the compensating unit 93 of the first embodiment, Operation and the like are all the same.

Particularly, when the voltage for sensing the characteristic information (e.g., threshold voltage, mobility, etc.) of the driving transistor DT is sensed in the sensing unit 320 of the second embodiment of the present invention, the sensed voltage Vsen The operation of compensating the characteristic information of the driving transistor DT based on the voltage Vsen stored in the memory 330 and compensated by the compensating unit 340 is the same as that of the first embodiment of the present invention.

However, there is a pixel structure difference in that the first embodiment has a one scan structure and the second embodiment has a two scan structure. In the first embodiment, whether or not the data voltage is supplied to the data line DL is switched The second switches SW2 and 914 used for controlling whether to apply a constant voltage to the second node N2 of the driving transistor DT in the S-sensing mode and / or the F-sensing mode There is a difference in that it is eliminated in the second embodiment.

Due to these two differences (first embodiment: one scan structure, with SW2, second embodiment: two scan structure, no SW2), operation timing in each of drive mode, S- There are some differences.

It is necessary to apply a constant voltage to each of the first node N1 and the second node N2 of the driving transistor DT to sense the voltage for grasping the characteristic information of the driving transistor DT, The voltage must be changed at the first node N1 of the transistor N1 and the changed voltage must be measured as the sensing voltage.

In this connection, the first switch 323 turns on the first switch 323 to be connected to the reference voltage supply node 3231 and the reference voltage line RVL by the first switch 323, The reference voltage Vref converted to the analogue voltage may be applied to the first node N1 of the driving transistor DT. This is the same as the first embodiment.

In order to apply a constant voltage Vdata to the second node N2 of the driving transistor DT, it is necessary to turn on the second switch 914 in the first embodiment, but in the second embodiment, The second switch 914 in the first embodiment does not exist and therefore when the second transistor T2 is turned on only a certain voltage Vdata may be applied to the second node N2 of the driving transistor DT .

A constant voltage is applied to each of the first node N1 and the second node N2 of the driving transistor DT so that the voltage at the first node N1 of the driving transistor DT changes, A first scan signal SENSE for controlling the switching operation of the first switch 323, a turn-on / turn-off of the first transistor Tl, a turn-on / turn-off of the second transistor T2, It is necessary to control the second scan signal SCAN for controlling the turn-off.

Timing control of the first switch 323, the first scan signal SENSE, and the second scan signal SCAN can be performed by the timing controller 265, which will be described in more detail with reference to FIG. 33 .

FIG. 33 is an operation timing diagram for the driving mode and the two sensing modes (S-sensing mode and F-sensing mode) of the organic light emitting display device 260 according to the second embodiment of the present invention.

First, a case where a pixel operates in a driving mode will be described with reference to Fig. 33 (a).

Referring to FIG. 33 (a), in the drive mode, the first switches SW1 and 323 may be always on, and may be off in some cases.

33A, a first scan signal SENSE of a second level VGH is applied to the first transistor Tl in a state in which the first switch 323 is always on, The step of the second transistor T2 becoming the second scan signal SCAN of the second level VGH is the initialization step of the drive mode STEP1.

When the level of the first scan signal SENSE applied to the first transistor T1 is changed to the first level VGL and the level of the second scan signal SCAN applied to the second transistor T2 is changed to the first level VGL, 1 level (VGL), and the step in which the data voltage (Vdata) is not applied is the driving step (STEP2) of the driving mode.

The first transistor T1 and the second transistor T2 are all turned on and the first node N1 and the second node N2 of the driving transistor DT are turned on The reference voltage Vref and the data voltage Vdata are applied.

At this time, the reference voltage Vref and the data voltage Vdata are applied to both ends of the storage capacitor Cst to charge charges corresponding to the potential difference between the data voltage Vdata and the reference voltage Vref.

In the driving step STEP2 of the drive mode, no constant voltage is applied to the first node N1 and the second node N2 of the driving transistor DT, and the first node N1 of the driving transistor DT The voltage (source voltage) of the first node N1 of the driving transistor DT becomes higher than the voltage (source voltage) of the second node N2, When the voltage becomes higher than a voltage at which a current can flow through the diode OLED, a current starts to flow to the organic light emitting diode and the organic light emitting diode emits light.

The voltage change graph when the pixel is operated in the drive mode is the same as in Fig.

Next, a case where the pixel operates in the S-sensing mode will be described with reference to FIG. 33 (b).

Referring to FIG. 33 (b), in the S-sensing mode, when the first switch 323 is turned off, the first transistor T1 is supplied with the first scan signal of the second level VGH SENSE) is applied to the second transistor T2 and the second scan signal SCAN of the second level VGH is applied to the second transistor T2.

The first switch 323 is turned off and the level of the first scan signal SENSE applied to the first transistor T1 is maintained at the second level VGH for a predetermined time (S-sensing time) The level of the second scan signal SCAN is maintained at the second level VGH for a predetermined time (this time may be shorter than the S-sensing time) in the second transistor T2, (STEP2) in the S-sensing mode until the level of the first level (VGL) is changed to the first level (VGL).

At this time, the time from when the first switch 323 is turned off until the level of the first scan signal SENSE changes to the first level VGL is the S-sensing time. During this S-sensing time, the changed voltage at the first node N1 of the driving transistor DT can be sensed.

The first transistor T1 and the second transistor T2 are all turned on and the first node N1 and the second node N2 of the driving transistor DT are turned on in the initializing step of the S- A reference voltage Vref and a data voltage Vdata, which are constant voltages, are applied.

At this time, the reference voltage Vref and the data voltage Vdata are applied to both ends of the storage capacitor Cst to charge charges corresponding to the potential difference between the data voltage Vdata and the reference voltage Vref.

The second transistor T2 is turned on and the constant voltage Vdata is applied to the second node N2 of the driving transistor DT and the driving transistor DT is turned on in the sensing step STEP2 of the S- The voltage difference between the first node N1 and the second node N2 of the driving transistor DT is lower than the threshold voltage Vth of the driving transistor DT, It happens until it becomes.

Therefore, the changed voltage at the first node N1 of the driving transistor DT during the S-sensing time becomes Vdata-Vth, and this voltage can be sensed as the sensing voltage Vsen. The change in the voltage (Vsen) sensed in the S-sensing mode is shown in FIG.

Next, the case where the pixel operates in the F-sensing mode will be described with reference to Fig. 33 (c).

Referring to (c) of FIG. 33, in the F-sensing mode, when the first switch 323 is turned off, the first transistor T1 is supplied with the first scan signal of the second level VGH (STEP1) while the second scan signal SCAN of the second level VGH is applied to the second transistor T2.

The first switch 323 is turned off and the level of the first scan signal SENSE applied to the first transistor T1 is maintained at the second level VGH for a predetermined time (S-sensing time) Until the level of the first scan signal SENSE changes to the first level VGL after the level of the second scan signal SCAN applied to the second transistor T2 is changed to the first level VGL, Sensing step of the S-sensing mode (STEP2).

The time from when the first switch 323 is turned off until the level of the first scan signal SENSE changes to the first level VGL is the F-sensing time. During this F-sensing time, the changed voltage at the first node N1 of the driving transistor DT can be sensed. The F-sensing time is much shorter than the S-sensing time. To this end, the time for which the first scan signal of the second level (VGH) is applied for the F-sensing mode is applied to the second The timing controller 265 can control the generation of the first scan signal so that the first scan signal of the level VGH is applied.

The first transistor T1 and the second transistor T2 are both turned on and the first node N1 and the second node N2 of the driving transistor DT are turned on in the initializing step of the F- A reference voltage Vref and a data voltage Vdata, which are constant voltages, are applied.

At this time, the reference voltage Vref and the data voltage Vdata are applied to both ends of the storage capacitor Cst to charge charges corresponding to the potential difference between the data voltage Vdata and the reference voltage Vref.

In the sensing step STEP2 of the F-sensing mode, although the second transistor T2 is turned off, due to the capacitor (Cgs) component between the gate node and the source node of the second transistor T2, The voltage at the second node N2 of the transistors DT can be maintained at Vdata for a short time.

Therefore, when the voltage at the second node N2 of the driving transistor DT is held at Vdata for a short time due to the capacitor (Cgs) component of the second transistor T2, The voltage at the node N1 may be finely changed between the F-sensing time.

Thus, during the F-sensing time, the changed voltage at the first node N1 of the driving transistor DT can be sensed as the sensing voltage Vsen.

Therefore, the changed voltage at the first node N1 of the driving transistor DT during the S-sensing time becomes Vdata-Vth, and this voltage can be sensed as the sensing voltage Vsen. The change in the voltage (Vsen) sensed in the S-sensing mode is shown in FIG.

(Threshold voltage, mobility) of the driving transistor DT using the voltage Vsen sensed in the S-sensing mode and the F-sensing mode described with reference to FIGS. 33 (b) and 33 The luminance imbalance between pixels can be reduced.

In the following, the compensation capability for the mobility deviation of the driving transistor DT of each pixel according to the external compensation function according to the first and second embodiments of the present invention described above is shown in an experiment result table And graphs.

FIG. 34 is a view showing a compensation effect of mobility deviation according to the first and second embodiments of the present invention. FIG.

34, when there are five pixels and the mobility of the driving transistor DT of each pixel is different by 0.8, 0.9, 1, 1.1, and 1.2, that is, When the mobility is different, the current flowing through the organic light emitting diode (OLED) is actually measured based on the current (200 nit current) such that the luminance of all five pixels is 200 nit. The difference was calculated as? Ioled. These measurements were performed before and after compensation according to the first embodiment (1 scan structure) and the second embodiment (2 scan structure), respectively.

Fig. 34 (a) shows the results of the measurement, and Fig. 34 (b) shows the results.

34 (b), before the compensation according to the first embodiment (1 SCAN) and before the compensation according to the second embodiment (1 SCAN), due to the mobility deviation between the five driving transistors DT, It can be seen that the difference (ΔIoled) between the target current (200 nit current) and the current actually flowing through the organic light emitting diode for all the pixels has a large variation with the mobility deviation.

However, after the compensation according to the first embodiment (1 SCAN) and the compensation according to the second embodiment (1 SCAN), as shown in the dotted box portion in Figure 34 (b), five driving transistors DT ), The difference between the target current (200 nit current) for causing all the five pixels to have the same luminance and the current actually flowing through the organic light emitting diode, ΔIoled is smaller than the mobility It can be confirmed that it does not greatly change according to the deviation.

Therefore, it can be confirmed from the experimental result of FIG. 34 that the compensation effect of the mobility deviation according to both the first embodiment and the second embodiment of the present invention is significant.

On the other hand, as described above, the display panel 11 of the first embodiment of the present invention and the display panel 261 of the second embodiment of the present invention are designed to have a symmetrical structure for every four pixel columns, The structure can be made simple and compact, the aperture ratio can be increased, the lifetime of the organic light emitting diode can be extended, the probability of occurrence of defects can be lowered, and the manufacture of the panel can be made easier. As a result, a high-quality panel can be produced with a high yield. Particularly, the first and second embodiments of the present invention will be more effective when applied to a high-resolution or large-area organic light emitting display device.

However, the first embodiment of the present invention discloses a pixel structure designed to enable a driving / sensing operation using only one scan signal without using two scan signals required in a 3T1C structure. There is a further advantage in terms of aperture ratio as compared with the second embodiment used.

The difference in aperture ratio between the first embodiment and the second embodiment of the present invention can be seen from FIG.

FIG. 35 is a diagram comparing aperture ratios according to the first and second embodiments of the present invention. FIG.

Referring to FIG. 35, two gate lines GL1 and GL2 are formed in one pixel row in the second embodiment (two scan structure) of the present invention. However, in the first embodiment (one scan structure) of the present invention, only one gate line GL is formed. That is, for one pixel row, the first embodiment of the present invention has one gate line reduced compared to the second embodiment.

Therefore, it can be seen that the display area (light emitting area) is larger and the aperture ratio is larger in the first embodiment of the present invention as compared with the second embodiment. It is expected that a larger aperture ratio can be expected if the resolution is increased or the area is increased.

As described above, according to the present invention, it is possible to provide an organic light emitting display device (10, 260) having a simple and compact panel structure.

Also, according to the present invention, there is provided an organic light emitting display device (10, 260) having a pixel structure for increasing the aperture ratio, lengthening the lifetime of the light emitting diode, and lowering the probability of occurrence of defects.

Further, according to the present invention, it is possible to provide an organic light emitting display device (10, 260) having a simple and compact panel structure by designing the pixel structure to be symmetrical.

According to the present invention, an organic light emitting display device (10, 260) having a sensing and compensating function suitable for a simple and compact pixel structure is provided in order to provide an efficient sensing and compensation function for compensating a luminance deviation between pixels There is an effect of providing the driving method thereof.

Due to these points, it is possible to manufacture the high-quality panels 11 and 261 with high yield.

These points will be even more effective when applied to panels 11 and 261 of high resolution and large area.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

10, 260: organic electroluminescence display device
11, 261: display panel
12, 262:
13, 263, 264: Gate driver
14, 265: Timing controller
DT: driving transistor
T1: first transistor
T2: second transistor
DL: Data line
GL, GL1, GL2: gate line
DVL: drive voltage line
RVL: Reference voltage line

Claims (59)

A display panel including a plurality of pixels arranged at intersecting regions of the data line and the gate line;
A data driver for supplying a data voltage through the data line;
A gate driver for supplying a scan signal through the gate line; And
And a timing controller for controlling driving timings of the data driver and the gate driver,
Wherein each of the plurality of pixels comprises:
A driving transistor connected between the first node of the driving transistor and a connection pattern connected to the reference voltage line or the reference voltage line, the driving transistor being controlled by the scan signal, the organic light emitting diode, A second transistor coupled between the data line and a second node of the driving transistor, the second transistor being controlled by the scan signal supplied in common to the gate line, and a second transistor coupled between the first node and the second node of the driving transistor, And a capacitor connected between the first electrode and the second electrode. The method according to claim 1,
Wherein the reference voltage line is formed on the display panel in parallel with the data line, and the number of reference voltage lines is equal to or less than the number of data lines. 3. The method of claim 2,
The number of reference voltage lines may be,
And the number of the data lines is 1/4 of the number of the data lines. The method of claim 3,
The reference voltage line may include:
And between the pixel region connected to the (4n-2) th data line and the pixel region connected to the (4n-1) th data line. 5. The method of claim 4,
The first transistor included in each of the pixels coupled to the (4n-2) th data line and the (4n-1) th data line is directly connected to the reference voltage line,
And the first transistor included in each of the pixels connected to the (4n-3) th data line and the pixel connected to the (4n) th data line is connected to the connection pattern connected to the reference voltage line. The method according to claim 1,
Wherein a driving voltage line for supplying a driving voltage to a third node of the driving transistor included in each of the plurality of pixels is formed in parallel with the data line, the number of driving voltage lines being equal to the number of data lines Wherein the organic electroluminescent display device comprises: The method according to claim 6,
The number of the driving voltage lines may be,
And the number of the data lines is 1/2 or 1/4 of the number of the data lines. The method according to claim 6,
When the number of the driving voltage lines is 1/4 of the number of the data lines,
And the driving voltage line is formed on the left side of the pixel region connected to the (4n-3) th data line and the right side of the pixel region connected to the (4n) th data line. 9. The method of claim 8,
The driving transistor included in the pixel connected to the (4n-3) th data line is directly connected to the driving voltage line formed on the left of the pixel region connected to the (4n-3) th data line,
The driving transistor included in the pixel connected to the 4n-th data line is directly connected to the driving voltage line formed on the right side of the area of the pixel connected to the 4n-th data line,
The driving transistor included in the pixel connected to the (4n-2) th data line is connected to the connection pattern connected to the driving voltage line formed on the left of the pixel region connected to the (4n-3)
And the driving transistor included in the pixel connected to the (4n-1) th data line is connected to a connection pattern connected to the driving voltage line formed on the right side of the pixel region connected to the (4n) th data line. The method according to claim 1,
The 4n-3th data line and the 4n-1th data line are formed on the right side of the connected pixel region, and the 4n-2th data line and the 4nth data line are formed on the left side of the connected pixel region, And the organic electroluminescent display device. The method according to claim 1,
In the display panel,
The pixel structure of the pixel connected to the (4n-3) th data line and the pixel structure of the pixel connected to the (4n-2) th data line are symmetrical to each other, and the pixel structure of the pixel connected to the Wherein the pixel structure of the pixel has a first-order symmetry structure symmetrical to each other. 12. The method of claim 11,
The pixel structure of the pixel connected to the (4n-3) th data line and the pixel structure of the pixel connected to the (4n-2) th data line are symmetrical with respect to the imaginary symmetry line between the (4n- Lt; / RTI &
The pixel structure of the pixel connected to the (4n-1) th data line and the pixel structure of the pixel connected to the (4n) th data line are symmetric with respect to each other with respect to a virtual symmetry line between the (4n- And an organic light emitting diode (OLED). 12. The method of claim 11,
In the display panel,
The pixel structure of the pixel connected to the (4n-3) th data line and the pixel structure of the pixel connected to the (4n) th data line are symmetrical to each other, and the pixel structure of the pixel connected to the Wherein the pixel structure of the pixel is symmetric with respect to the pixel structure of the pixel. 14. The method of claim 13,
The pixel structure of the pixel connected to the (4n-3) th data line and the pixel structure of the pixel connected to the (4n) th data line are symmetrical with respect to the reference voltage line,
The pixel structure of the pixel connected to the (4n-2) th data line and the pixel structure of the pixel connected to the (4n-1) th data line are symmetrical with respect to the reference voltage line. 12. The method of claim 11,
The pixel structure includes:
A capacitor formation position, and an organic light emitting diode formation position of the pixel. The method according to claim 1,
And a sensing unit sensing a voltage of a first node of the driving transistor. 17. The method of claim 16,
The sensing unit includes:
An analog-digital converter for converting the sensed voltage into a digital value; And
And a first switch for switching one of a reference voltage supply node to which a reference voltage is supplied and a sensing node connected to the analog-digital conversion section to be connected to the reference voltage line. 17. The method of claim 16,
The sensing unit includes:
The number of data lines or the number of reference voltage lines. 17. The method of claim 16,
The timing controller includes:
A first switch for turning on the reference voltage line to be connected to the reference voltage supply node or turning off the reference voltage line to be connected to the sensing node,
And a switching operation for a second switch for switching a data voltage output point of the data driver to be connected to the data line or to be turned off by floating the data line, Device. 20. The method of claim 19,
The timing controller includes:
One of the second switches connected to the (4n-3) th data line, the (4n-2) th data line, the (4n-1) th data line and the 4nth data line,
Th data line, the (4n-3) th data line, the (4n-2) th data line, the (4n-1) th data line and the The voltages inputted through the second switches connected to the (4n-1) -th data line and the (4n-1) -th data line are controlled differently,
And controls the sensing unit to be a pixel for sensing a changed voltage at the first node of the driving transistor. 20. The method of claim 19,
The timing controller includes:
And controlling the switching operation of the first switch and the second switch and the waveform of the scan signal so that the pixel capable of supplying the data voltage by the second switch operates in one of the driving mode and the sensing mode The organic light emitting display device comprising: 22. The method of claim 21,
The timing controller includes:
The scan signal for turning on the first transistor and the second transistor is supplied for a predetermined time and the first switch and the second switch are controlled to be always on, And controls the pixel capable of supplying the data voltage to operate in the driving mode. 23. The method of claim 22,
Wherein the gate driver comprises:
And the scan signal for turning on the first transistor and the second transistor is supplied for at least one horizontal time. 23. The method of claim 22,
Wherein the gate driver comprises:
And supplies the scan signal before the data voltage supply time so that the first transistor and the second transistor are turned on. 22. The method of claim 21,
The timing controller includes:
The first switch and the second switch are turned on while only the first switch is turned off while the scan signal for turning on the first transistor and the second transistor is supplied for a predetermined time, And the second switch controls the pixel capable of supplying the data voltage to operate in the S-sensing mode during the sensing mode. 26. The method of claim 25,
The sensing unit includes:
Sensing time until a supply of the scan signal to turn on the first transistor and the second transistor is turned on from the time when only the first switch is turned off, And sensing a changed voltage at a first node of the transistor. 22. The method of claim 21,
The timing controller includes:
While the scan signal for turning on the first transistor and the second transistor is supplied for a predetermined time, the first switch and the second switch are turned on and all are turned off or only the first switch is turned off And a pixel capable of supplying a data voltage by the second switch operates in the F-sensing mode during the sensing mode. 28. The method of claim 27,
Wherein a capacitor is connected to or formed on the data line so that a voltage of a second node of the driving transistor is kept constant when both the first switching and the second switching are off. 28. The method of claim 27,
The sensing unit includes:
The first transistor and the second transistor are turned on from the time point when the first switch and the second switch are both turned off or the time when the first switch is turned off to the time when the scan signal is supplied, And sensing the changed voltage at the first node of the driving transistor during the F-sensing time as the sensing time. 17. The method of claim 16,
A compensation unit for performing data conversion processing for compensating characteristic information of the driving transistor based on the sensed voltage; And
And a memory for storing the sensed voltage or characteristic information of the driving transistor. 31. The method of claim 30,
Wherein the compensation unit comprises:
Wherein the timing controller is included in the timing controller, is included in the data driver, or is included outside the timing controller and the data driver. 32. The method of claim 31,
Wherein the compensation unit comprises:
And supplies the data supplied from the outside to the data driver in the case of being included in the timing controller, into the compensation data based on the characteristic information of the driving transistor,
The data supplied from the timing controller is converted into compensation data before or after conversion to analog based on the characteristic information of the driving transistor when included in the data driver,
And supplies the data supplied from the timing controller to the data driver when the data is included outside the timing controller and the data driver, Device. A data line formed in one direction;
A gate line formed in the other direction crossing the data line; And
And a plurality of pixels defined by intersecting the data line and the gate line,
Wherein each of the plurality of pixels comprises:
A driving transistor for driving the organic light emitting diode; a connection pattern which is controlled by a scan signal supplied through the gate line and is connected to a reference voltage line or the reference voltage line; A second transistor connected between the data line and a second node of the driving transistor, the second transistor being controlled by the scan signal supplied in common through the gate line, And a capacitor connected between the first node and the second node. A plurality of data lines formed in one direction;
A plurality of gate lines formed in the other direction crossing the plurality of data lines; And
A plurality of data lines and a plurality of pixels connected to the plurality of gate lines,
The pixel structure of the pixel connected to the (4n-3) th data line and the pixel structure of the pixel connected to the (4n) th data line are symmetrical with each other. And the pixel structures of the pixels are symmetrical to each other. 35. The method of claim 34,
A first voltage line for supplying a first voltage to a pixel connected to the (4n-3) th data line, a pixel connected to the (4n-2) th data line, a pixel connected to the Wherein the first electrode is formed in one direction. 36. The method of claim 35,
The pixel structure of the pixel connected to the (4n-3) th data line and the pixel structure of the pixel connected to the (4n) th data line are symmetrical with respect to the first voltage line,
And a pixel structure of a pixel coupled to a (4n-2) th data line and a pixel structure of a pixel connected to a (4n-1) th data line are symmetrical with respect to the first voltage line. 37. The method of claim 36,
The first transistor included in each of the pixels connected to the (4n-2) th data line and the pixel connected to the (4n-1) th data line is directly connected to the first voltage line,
The first transistor included in each of the pixels connected to the (4n-3) th data line and the pixel connected to the (4n) th data line is connected to the connection pattern connected to the first voltage line and is supplied with the first voltage. Display device. 35. The method of claim 34,
The pixel structure of the pixel connected to the (4n-3) th data line and the pixel structure of the pixel connected to the (4n-2) th data line are symmetrical to each other,
And the pixel structure of the pixel connected to the (4n-1) th data line and the pixel structure of the pixel connected to the (4n) th data line are symmetrical to each other. 39. The method of claim 38,
The pixel structure of the pixel connected to the (4n-3) th data line and the pixel structure of the pixel connected to the (4n-2) th data line are symmetrical with respect to the imaginary symmetry line between the (4n- Lt; / RTI &
The pixel structure of the pixel connected to the (4n-1) th data line and the pixel structure of the pixel connected to the (4n) th data line are symmetrical with respect to the imaginary symmetry line between the (4n-1) th data line and the The organic electroluminescent display device comprising: 35. The method of claim 34,
A second voltage line for supplying a second voltage to each of the left side of the pixel region connected to the (4n-3) th data line and the right side of the pixel region connected to the (4n) th data line is formed in the one direction. An electroluminescent display device. 41. The method of claim 40,
The driving transistor included in the pixel connected to the (4n-3) th data line is directly connected to the second voltage line formed on the left of the pixel region connected to the (4n-3) th data line,
The driving transistor included in the pixel connected to the 4n-th data line is directly connected to the second voltage line formed on the right side of the region of the pixel connected to the 4n-th data line to receive the second voltage,
The driving transistor included in the pixel connected to the (4n-2) th data line is connected to the connection pattern connected to the second voltage line formed on the left of the pixel region connected to the (4n-3) th data line,
The driving transistor included in the pixel connected to the (4n-1) th data line is connected to the connection pattern connected to the second voltage line formed on the right side of the pixel region connected to the (4n) th data line to receive the second voltage. An electroluminescent display device. 35. The method of claim 34,
The pixel structure includes:
And a transistor forming position and a capacitor forming position of the corresponding pixel. 43. The method of claim 42,
The pixel structure includes:
Further comprising an organic light emitting diode forming position of the corresponding pixel. A method of driving an organic light emitting display device including a display panel including a pixel including a driving transistor and an organic light emitting diode and having a data line connected to the pixel,
To a reference voltage line or a connection pattern connected to the reference voltage line and a first node of the driving transistor and a second transistor which connects between the data line and a second node of the driving transistor, Supplying a reference voltage and a data voltage to the first node and the second node of the driving transistor through the first transistor and the second transistor, respectively; And
And controlling supply of at least one of the reference voltage, the data voltage, and the scan signal so that the pixel operates in one of an operation mode and a sensing mode. 45. The method of claim 44,
Wherein the control signal turns the level of the scan signal from a first level to a second level to turn on the first transistor and the second transistor so that the first node and the second node of the driving transistor receive the reference voltage and data And driving the organic light emitting diode by the driving transistor by changing the level of the scan signal to a first level,
Wherein the control signal turns the level of the scan signal from a first level to a second level to turn on the first transistor and the second transistor so that the first node and the second node of the driving transistor receive the reference voltage and data Further comprising an S-sensing step of sensing a voltage changed at a first node of the driving transistor by allowing only a reference voltage applied to a first node of the driving transistor to float,
In the controlling step, the level of the scan signal is changed to turn on the first transistor and the second transistor so that the reference voltage and the data voltage are respectively applied to the first node and the second node of the driving transistor, Sensing the changed voltage at the first node of the driving transistor by floating both the reference voltage and the data voltage at the first node and the second node of the driving transistor or by floating only the reference voltage And a driving method of the organic light emitting display device. 46. The method of claim 45,
In the S-sensing step, the time from when only the reference voltage applied to the first node of the driving transistor is floated to when the level of the scan signal is changed back to the first level is S- Sensing a changed voltage at a first node of the first node,
In the F-sensing step, the reference voltage and the data voltage are both floated to the first node and the second node of the driving transistor, or until the level of the scanning signal is changed back to the first level Sensing the changed voltage at the first node of the driving transistor by using the F-sensing time. 47. The method of claim 46,
Wherein the S-sensing time is longer than the F-sensing time. 46. The method of claim 45,
Wherein the S-sensing step is a step of operating only before shipment of the organic light emitting display device, and the F-sensing step is a step of operating both before and after shipment of the organic light emitting display device. A method of driving an organic electroluminescent display device. 46. The method of claim 45,
After the S-sensing step or the F-sensing step,
And compensating at least one of a threshold voltage and a mobility of the driving transistor based on the sensed voltage. A data driver driving a data line formed in one direction;
A first gate driver for supplying a first scan signal through a first gate line formed in the other direction crossing the data line;
A second gate driver for supplying a second scan signal through a second gate line formed in parallel with the first gate line;
A timing controller for controlling the driving timings of the data driver, the first gate driver, and the second gate driver; And
And a display panel including a plurality of pixels connected to the data line, the first gate line, and the second gate line,
Wherein each of the plurality of pixels comprises:
A driving transistor connected between the first node of the driving transistor and a connection pattern which is controlled by the first scan signal and is connected to the reference voltage line or the reference voltage line, A second transistor coupled between the data line and a second node of the driving transistor, the second transistor being controlled by the second scan signal and coupled between a first node and a second node of the driving transistor; Wherein the organic electroluminescent display device comprises a capacitor. A data line formed in one direction;
A first gate line formed in the other direction crossing the data line;
A second gate line formed in parallel with the one gate line;
A plurality of pixels coupled to the data line, the first gate line, and the second gate line,
Wherein each of the plurality of pixels comprises:
A driving transistor for driving the organic light emitting diode; a connection pattern which is controlled by a first scan signal supplied from the first gate line and is connected to a reference voltage line or the reference voltage line; A second transistor coupled between the data line and a second node of the driving transistor, the second transistor being controlled by a second scan signal supplied from the second gate line, And a capacitor connected between the first node and the second node of the driving transistor. A plurality of data lines formed in one direction;
A plurality of first gate lines formed in the other direction crossing the plurality of data lines;
A plurality of second gate lines formed in parallel with the plurality of first gate lines;
And a plurality of pixels coupled to the plurality of data lines, the plurality of first gate lines, and the plurality of second gate lines,
The pixel structure of the pixel connected to the (4n-3) th data line and the pixel structure of the pixel connected to the (4n) th data line are symmetrical to each other, And the pixel structures of the connected pixels are symmetrical to each other. 53. The method of claim 52,
A first voltage line for supplying a first voltage to a pixel connected to the (4n-3) th data line, a pixel connected to the (4n-2) th data line, a pixel connected to the Wherein the first electrode is formed in one direction. 54. The method of claim 53,
The pixel structure of the pixel connected to the (4n-3) th data line and the pixel structure of the pixel connected to the (4n) th data line are symmetrical with respect to the first voltage line,
And a pixel structure of a pixel coupled to a (4n-2) th data line and a pixel structure of a pixel connected to a (4n-1) th data line are symmetrical with respect to the first voltage line. 53. The method of claim 52,
The first transistor included in each of the pixels connected to the (4n-2) th data line and the pixel connected to the (4n-1) th data line is directly connected to the first voltage line,
The first transistor included in each of the pixels connected to the (4n-3) th data line and the pixel connected to the (4n) th data line is connected to the connection pattern connected to the first voltage line and is supplied with the first voltage. Display device. 53. The method of claim 52,
A second voltage line for supplying a second voltage to each of the left side of the pixel region connected to the (4n-3) th data line and the right side of the pixel region connected to the (4n) th data line is formed in the one direction. An electroluminescent display device. 57. The method of claim 56,
The driving transistor included in the pixel connected to the (4n-3) th data line is directly connected to the second voltage line formed on the left of the pixel region connected to the (4n-3) th data line,
The driving transistor included in the pixel connected to the 4n-th data line is directly connected to the second voltage line formed on the right side of the region of the pixel connected to the 4n-th data line to receive the second voltage,
The driving transistor included in the pixel connected to the (4n-2) th data line is connected to the connection pattern connected to the second voltage line formed on the left of the pixel region connected to the (4n-3) th data line,
The driving transistor included in the pixel connected to the (4n-1) th data line is connected to the connection pattern connected to the second voltage line formed on the right side of the pixel region connected to the (4n) th data line to receive the second voltage. An electroluminescent display device. 53. The method of claim 52,
The pixel structure includes:
And a transistor forming position and a capacitor forming position of the corresponding pixel. 58. The method of claim 58,
The pixel structure includes:
Further comprising an organic light emitting diode forming position of the corresponding pixel.

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