KR20170081036A - Organic light emitting display panel and organic light emitting display device - Google Patents

Abstract

The present invention relates to an organic light emitting display panel and an organic light emitting diode (OLED) display device, and more particularly, to a method of driving an organic light emitting display And a plurality of second transistors, each of the plurality of first transistors being located in each subpixel row, the plurality of first transistors being located in each subpixel row, Shielding pattern structure including a transistor or a long-shielding pattern formed across the region of the plurality of second transistors and connected in a non-active region with gate lines arranged in sub-pixel rows. As a result, the effect of the body effect can be effectively reduced for each type of transistor, thereby preventing abnormal driving of the transistor and abnormal screen phenomenon.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting display panel and an organic light emitting display device,

The present embodiments relate to an organic light emitting display panel and an organic light emitting display.

2. Description of the Related Art Recently, an organic light emitting display device that has been spotlighted as a display device has advantages of high response speed, high luminous efficiency, high brightness, and a wide viewing angle by using an organic light emitting diode (OLED)

The organic light emitting display panel of the OLED display device includes an organic light emitting diode and various transistors for each subpixel.

In an organic light emitting display panel, a circuit element such as a transistor may be deteriorated due to deterioration of the circuit element due to driving time, but may be exposed to light (e.g., external light) to change the device characteristics.

As described above, when the device characteristics of the circuit elements of the organic light emitting display panel are changed according to the driving time, or when the device characteristics are changed by exposure to external light, the circuit may be abnormally driven to cause a screen abnormal phenomenon.

It is an object of the present embodiments to provide an organic light emitting display panel and an organic light emitting display device having a light shielding pattern structure capable of reducing a change in characteristics of a transistor in a subpixel to prevent abnormal driving of a transistor.

Another object of the present embodiments is to provide a light emitting device capable of reducing the influence of a body effect that may be generated in a transistor while reducing a change in characteristics of a transistor by placing a light shielding pattern in a lower portion of the transistor in the sub- And an organic light emitting diode (OLED) display device.

It is still another object of the present embodiments to provide an image display device capable of effectively reducing the influence of a body effect by changing the shape of a light shielding pattern and the connection position for each type of transistor in a sub pixel, An organic light emitting display panel having a light-shielding pattern structure and an organic light emitting display device.

It is a further object of the present embodiments to provide a method of driving a plasma display panel in which when a subpixel includes first and second transistors connected to the same gate line as the driving transistor, Emitting display panel and an organic light-emitting display device capable of effectively preventing an abnormal driving phenomenon according to a transistor type by having a light-shielding pattern structure including a long light-shielding pattern (s).

It is another object of the present embodiments to provide an organic light emitting display panel and an organic light emitting display device having a light shielding pattern structure capable of increasing an aperture ratio.

In one aspect, the embodiments provide an organic light emitting display panel in which a plurality of subpixels defined by a plurality of data lines and a plurality of gate lines are arranged in a matrix type, a data driver for driving a plurality of data lines, And a gate driver for driving a gate line of the organic light emitting display device.

In such an OLED display device, each sub-pixel includes an organic light emitting diode, a driving transistor for driving the organic light emitting diode, and a scan signal applied to the gate node through the gate line, A second transistor electrically connected between the second node of the driving transistor and the reference voltage line, the second transistor being controlled by a scan signal applied to the gate node through the gate line; And a storage capacitor electrically connected between the first node and the second node.

In such an organic light emitting display device, a short shielding pattern may be located in each driving transistor region of each subpixel.

Such a short shielding pattern can be electrically connected to the second node of the corresponding driving transistor.

Further, in the organic light emitting diode display device, one long light shielding pattern for each subpixel row is located in the row direction. In this specification, the row direction is a reference direction described for the sake of convenience of explanation, and the row direction may be viewed in the column direction in some cases.

The long shading pattern may be located across a plurality of first transistor regions and a plurality of second transistor regions located in a corresponding subpixel row.

In addition, the long light-shielding pattern can be electrically connected in the non-active region with gate lines commonly connected to gate nodes of all the first transistors and gate nodes of all the second transistors located in corresponding subpixel rows.

In another aspect, the present embodiments relate to an organic light emitting display panel including a plurality of data lines, a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels arranged in a matrix type, Can be provided.

Each subpixel in the organic light emitting display panel is controlled by an organic light emitting diode, a driving transistor for driving the organic light emitting diode, and a scan signal applied to a gate node through a gate line, A second transistor electrically connected between the second node of the driving transistor and the reference voltage line, the second transistor being controlled by a scan signal applied to the gate node through the gate line, A storage capacitor electrically connected between the first node and the second node may be disposed.

In such an organic light emitting display panel, a short shielding pattern may be placed in each driving transistor region of each subpixel.

Such a short shielding pattern can be electrically connected to the second node of the corresponding driving transistor.

Further, in the organic light emitting display panel, one long light shielding pattern may be positioned in the row direction for each subpixel row.

The long shading pattern may be located across a plurality of first transistor regions and a plurality of second transistor regions located in a corresponding subpixel row.

In addition, the long light-shielding pattern can be electrically connected in the non-active region with gate lines commonly connected to gate nodes of all the first transistors and gate nodes of all the second transistors located in corresponding subpixel rows.

According to another aspect of the present invention, there is provided an organic light emitting diode display panel including a plurality of data lines, An organic light emitting display device including a gate driver for driving a plurality of gate lines can be provided.

In such an organic light emitting display, each sub-pixel is controlled by an organic light emitting diode, a driving transistor for driving the organic light emitting diode, and a first scan signal applied to the gate node through the first gate line, A first transistor electrically connected between the first node and the data line and a second scan signal applied to the gate node through the second gate line and electrically connected between the second node of the drive transistor and the reference voltage line, And a storage capacitor electrically connected between the first node and the second node of the driving transistor.

In such an organic light emitting display device, a short shielding pattern may be located in each driving transistor region of each subpixel.

Such a short shielding pattern can be electrically connected to the second node of the corresponding driving transistor.

Further, in the organic light emitting display device, the first long light shielding pattern and the second long light shielding pattern may be positioned in the row direction for each subpixel row.

The first long light-shielding pattern is located passing through a plurality of first transistor regions located in a corresponding subpixel row, and the second long light-shielding pattern is located passing through a plurality of second transistor regions located in the corresponding subpixel row .

The first long light shielding pattern may be electrically connected in the non-active region with the first gate line connected to the gate node of all the first transistors located in the subpixel row.

Also, the second long-shielding pattern may be electrically connected to the second gate line connected to the gate node of all the second transistors located in the subpixel row in the non-active region.

In yet another aspect, the present embodiments provide an organic light emitting display comprising a plurality of data lines, a plurality of gate lines, a plurality of data lines and a plurality of sub-pixels arranged in a matrix type, Panel can be provided.

Each subpixel in the organic light emitting display panel is controlled by an organic light emitting diode, a driving transistor for driving the organic light emitting diode, and a first scan signal applied to the gate node through the first gate line, A first transistor electrically connected between the first node and the data line and a second scan signal applied to the gate node through the second gate line and electrically connected between the second node of the drive transistor and the reference voltage line A storage capacitor electrically connected between the second transistor and the first node and the second node of the driving transistor may be disposed.

In such an organic light emitting display panel, a short shielding pattern may be located in each driving transistor region of each subpixel.

Such a short shielding pattern can be electrically connected to the second node of the corresponding driving transistor.

In this organic light emitting display panel, the first long-shielding pattern and the second long-shielding pattern may be located in the row direction for each subpixel row.

The first long-light-shielding pattern may be positioned passing through a plurality of regions of the first transistors located in corresponding subpixel rows.

And the second long-shielding pattern may be located passing through the area of the plurality of second transistors located in the corresponding subpixel row.

The first long light shielding pattern may be electrically connected in the non-active region with the first gate line connected to the gate node of all the first transistors located in the subpixel row.

And the second long light shielding pattern may be electrically connected to the second gate line connected to the gate node of all the second transistors located in the subpixel row in the non-active region.

According to the exemplary embodiments of the present invention described above, it is possible to provide an organic light emitting display panel and an OLED display device having a light-shielding pattern structure capable of reducing a change in characteristics of a transistor in a sub- .

In addition, according to the embodiments, a light-shielding pattern can be placed under the transistor in the sub-pixel to reduce variations in characteristics of the transistor, and a light-shielding effect that can reduce the influence of a body effect, An organic light emitting display panel having a pattern structure and an organic light emitting display device can be provided.

In addition, according to the embodiments, the shape of the light-shielding pattern and the connection position are different depending on the type of transistor in the sub-pixel, thereby effectively reducing the influence of the body effect, An organic light emitting display panel having a light-shielding pattern structure and an organic light emitting display device can be provided.

In addition, according to the present embodiments, when the sub-pixel includes the first transistor and the second transistor connected to the same gate line as the driving transistor, a region where the short-shielding pattern and the regions of the first and second transistors The organic light emitting display panel and the organic light emitting display device capable of effectively preventing the abnormal driving phenomenon according to the transistor type can be provided by having the light shielding pattern structure including the long light shielding pattern (s).

In addition, according to the embodiments, an organic light emitting display panel and an organic light emitting display device having a light shielding pattern structure capable of increasing the aperture ratio can be provided.

1 is a system configuration diagram of an organic light emitting display according to the present embodiments.
FIGS. 2 and 3 are exemplary views of a sub-pixel structure of an organic light emitting display according to the present embodiments.
FIG. 4 is a view illustrating a light blocking pattern formed below a transistor in order to prevent the characteristic value of the transistor from changing due to light in the organic light emitting display according to the present embodiments.
5 is an equivalent circuit of a light-shielding pattern formed in a circuit region of each subpixel and a subpixel in which a light-shielding pattern is formed in the organic light emitting display according to the present embodiments.
6 is a diagram illustrating a structure of a single light-shielding pattern in which a light-shielding pattern is connected to a second node of the driving transistor in order to improve the operating characteristics of the driving transistor in the organic light emitting display according to the present embodiments.
FIGS. 7 and 8 are views for explaining an abnormal driving phenomenon that may be caused by the single light-shielding pattern structure in the organic light emitting diode display according to the present embodiments.
FIGS. 9 to 11 are diagrams illustrating a double light-shielding pattern structure for preventing abnormal driving phenomenon when each sub-pixel of the organic light emitting display according to the present embodiments has a one-scan structure.
FIG. 12 is a diagram schematically illustrating a long-light-shielding pattern in a double-shielding pattern structure when each subpixel of the organic light emitting display according to the present embodiments has a one-scan structure.
FIG. 13 is a diagram showing a layout structure of a long-shielding pattern and a gate line in a double-shielding pattern structure when each subpixel of the organic light emitting display according to the present embodiments has a one-scan structure.
FIGS. 14 and 15 are views showing a connection structure between a long-shielding pattern and a gate line in a double-shielding pattern structure when each subpixel of the organic light emitting display according to the present embodiments has a one-scan structure.
FIGS. 16 to 18 are diagrams illustrating a triple shielding pattern structure for preventing an abnormal driving phenomenon when each subpixel of the organic light emitting display according to the present embodiments has a two-scan structure.
FIG. 19 is a diagram schematically showing a first long light-shielding pattern and a second long light-shielding pattern in a triple light-shielding pattern structure when each sub-pixel of the organic light emitting display according to the present embodiment has a two-scan structure.
20 is a diagram illustrating a structure in which, in a triple-light-shielding pattern structure, each subpixel of the organic light emitting display according to the present embodiment has a two-scan structure, a layout structure between a first long-shielding pattern and a first gate line, Pattern and the second gate line.
21 and 22 are diagrams for explaining the connection structure between the first long-shielding pattern and the first gate line and the connection structure between the first long-shielding pattern and the first gate line in the triple shielding pattern structure when each subpixel of the OLED display according to the present embodiments has a two- 2 long shielding pattern and the second gate line.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

FIG. 1 is a system configuration diagram of an organic light emitting diode display 100 according to the present embodiments.

1, the OLED display 100 includes a plurality of data lines DL and a plurality of gate lines GL, a plurality of sub pixels (SP) A data driver 120 for driving the plurality of data lines DL; a gate driver 130 for driving the plurality of gate lines GL; a data driver 120 And a controller 140 for controlling the gate driver 130 and the like.

The controller 140 supplies various control signals to the data driver 120 and the gate driver 130 to control the data driver 120 and the gate driver 130.

The controller 140 starts scanning according to the timing implemented in each frame, switches the input image data input from the outside according to the data signal format used by the data driver 120, and outputs the converted image data , And controls the data driving at a suitable time according to the scan.

The controller 140 may be a timing controller used in a conventional display technology or a control device including a timing controller to perform other control functions.

The data driver 120 drives the plurality of data lines DL by supplying data voltages to the plurality of data lines DL. Here, the data driver 120 is also referred to as a 'source driver'.

The gate driver 130 sequentially supplies the scan signals to the plurality of gate lines GL to sequentially drive the plurality of gate lines GL. Here, the gate driver 130 is also referred to as a " scan driver ".

The gate driver 130 sequentially supplies a scan signal of an On voltage or an Off voltage to the plurality of gate lines GL under the control of the controller 140.

When a specific gate line is opened by the gate driver 130, the data driver 120 converts the image data received from the controller 140 into an analog data voltage and supplies the data voltage to a plurality of data lines DL.

1, the data driver 120 is located only on one side (e.g., on the upper side or the lower side) of the organic light emitting display panel 110, : Upper side and lower side).

1, the gate driver 130 is located only on one side (e.g., the left side or the right side) of the organic light emitting display panel 110. However, the gate driver 130 may be disposed on both sides of the organic light emitting display panel 110 For example, left and right).

The controller 140 described above is capable of outputting various kinds of signals including the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the input data enable signal (DE), and the clock signal (CLK) Timing signals from the outside (e.g., the host system).

The controller 140 outputs the converted image data by switching the input image data inputted from the outside in accordance with the data signal format used by the data driver 120 and outputs the converted image data to the data driver 120 and the gate driver 130, A timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input DE signal and a clock signal and generates various control signals to control the data driver 120 and the gate driver 130, .

For example, in order to control the gate driver 130, the controller 140 generates a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal GOE Gate Output Enable), and the like.

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits constituting the gate driver 130. The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits, and controls the shift timing of the scan signal (gate pulse). The gate output enable signal GOE specifies the timing information of one or more gate driver ICs.

In order to control the data driver 120, the controller 140 may further include a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE) And outputs various data control signals (DCS: Data Control Signals).

Here, the source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits constituting the data driver 120. The source sampling clock SSC is a clock signal for controlling sampling timing of data in each of the source driver integrated circuits. The source output enable signal SOE controls the output timing of the data driver 120.

The data driver 120 may drive a plurality of data lines including at least one source driver integrated circuit (SDIC).

Each source driver integrated circuit (SDIC) is connected to a bonding pad of the organic light emitting display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) Or may be directly disposed on the organic light emitting display panel 110, and may be integrated and disposed on the organic light emitting display panel 110, as the case may be. In addition, each source driver integrated circuit (SDIC) may be implemented by a chip on film (COF) method, which is mounted on a film connected to the organic light emitting display panel 110.

Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, and the like.

Each source driver integrated circuit (SDIC) may further include an analog to digital converter (ADC), as the case may be.

The gate driver 130 may include at least one gate driver integrated circuit (GDIC).

Each gate driver integrated circuit GDIC may be connected to a bonding pad of the organic light emitting display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) ) Type and may be directly disposed on the organic light emitting display panel 110 or may be integrated on the organic light emitting display panel 110 as the case may be. In addition, each gate driver IC (GDIC) may be implemented by a chip on film (COF) method, which is mounted on a film connected to the organic light emitting display panel 110.

Each gate driver IC (GDIC) may include a shift register, a level shifter, and the like.

The OLED display 100 according to the present embodiments includes at least one source printed circuit board (S-PCB) necessary for circuit connection to at least one source driver IC (SDIC) And a control printed circuit board (C-PCB) for mounting control components and various electric devices.

At least one source driver integrated circuit (SDIC) may be mounted on at least one source printed circuit board (S-PCB), or a film on which at least one source driver integrated circuit (SDIC) is mounted may be connected.

The control printed circuit board (C-PCB) is provided with a controller 140 for controlling the operation of the data driver 120 and the gate driver 130 and the like, and a controller 140 for controlling operations of the organic light emitting display panel 110, the data driver 120, A power controller for controlling various voltages or currents to supply or supply various voltages or currents to the battery 130, or the like.

The at least one source printed circuit board (S-PCB) and the control printed circuit board (C-PCB) may be circuitly connected via at least one connecting member.

Here, the connecting member may be a flexible printed circuit (FPC), a flexible flat cable (FFC), or the like.

At least one source printed circuit board (S-PCB) and a control printed circuit board (C-PCB) may be integrated into one printed circuit board.

Each sub-pixel SP disposed in the organic light emitting display panel 110 may include a circuit element such as a transistor.

For example, when the organic light emitting display panel 110 is an organic light emitting display panel, each sub pixel SP includes an organic light emitting diode (OLED) and a driving transistor for driving the organic light emitting diode Circuit elements.

The types and the number of the circuit elements constituting each subpixel SP can be variously determined depending on the providing function, the design method, and the like.

2 and 3 are exemplary views of the sub-pixel structure of the OLED display 100 according to the present embodiments.

2 and 3, each of the sub-pixels SP arranged in the organic light emitting display panel 110 includes an organic light emitting diode (OLED), a driving circuit for driving the organic light emitting diode OLED A first transistor (DT) which is controlled by the first scan signal (SCAN1) and is electrically connected between a first node (N1) of the driving transistor (DT) and a data line (DL) A second transistor T2 controlled by a second scan signal SCAN2 and electrically coupled between a second node N2 of the driving transistor DT and a reference voltage line RVL, And a storage capacitor C1 electrically connected between the first node N1 and the second node N2 of the driving transistor DT.

As shown in FIGS. 2 and 3, a structure in which one subpixel SP includes three transistors DT, T1, and T2 and one capacitor C1 is referred to as a 3T (Capacitor) .

The organic light emitting diode OLED may include a first electrode (e.g., an anode electrode), an organic layer, and a second electrode (e.g., a cathode electrode).

The driving transistor DT is a driving transistor for driving the organic light emitting diode OLED and supplies driving current to the organic light emitting diode OLED to drive the organic light emitting diode OLED.

In this driving transistor DT, the first node N1 may be electrically connected to the source node or the drain node of the first transistor T1, and may be a gate node. The second node N2 may be electrically connected to a source node or a drain node of the first electrode of the organic light emitting diode OLED and the second transistor T2 and may be a source node or a drain node. The third node N3 may be electrically connected to a driving voltage line (DVL) for supplying a driving voltage EVDD, and may be a drain node or a source node.

The first transistor T1 is electrically connected between the data line DL and the first node N1 of the driving transistor DT and is turned on and off by the first scan signal SCAN1 applied to the gate node Lt; / RTI >

The first transistor T1 is turned on by the first scan signal SCAN1 to transfer the data voltage Vdata supplied from the data line DL to the first node N1 of the driving transistor DT .

The second transistor T2 is electrically connected between the reference voltage line RVL and the second node N2 of the driving transistor DT and is turned on and off by the second scan signal SCAN2 applied to the gate node. Can be controlled.

The second transistor T2 is turned on by the second scan signal SCAN2 to transfer the reference voltage Vref supplied from the reference voltage line RVL to the second node N2 of the driving transistor DT I can do it.

The second transistor T2 may be turned on by the second scan signal SCAN2 to transfer the voltage of the second node N2 of the driving transistor DT to the reference voltage line RVL. This is a phenomenon that occurs when sensing characteristic values (e.g., threshold voltage, mobility, etc.) for circuit elements such as the driving transistor DT and the organic light emitting diode OLED in each subpixel SP.

The storage capacitor C1 is electrically connected between the first node N1 and the second node N2 of the driving transistor DT to maintain a constant voltage for one frame time.

The storage capacitor C1 is not a parasitic capacitor (e.g., Cgs or Cgd) which is an internal capacitor existing between the first node N1 and the second node N2 of the driving transistor DT, And is an external capacitor intentionally designed outside the driving transistor DT.

The driving transistor DT, the first transistor T1 and the second transistor T2 may be either n-type transistors or p-type transistors.

Referring to FIG. 2, the gate node of the first transistor T1 and the gate node of the second transistor T2 may be connected to the same gate line GL.

Accordingly, the first scan signal SCAN1 applied to the gate node of the first transistor T1 and the second scan signal SCAN2 applied to the gate node of the second transistor T2 are the same scan signal SCAN .

2, when the gate node of the first transistor T1 and the gate node of the second transistor T2 are commonly connected to one gate line GL, the subpixel SP has a "one scan structure" .

3, the gate node of the first transistor T1 is coupled to the first gate line GL1, and the gate node of the second transistor T2 is coupled to the first gate line GL1 And may be connected to the second gate line GL2.

Accordingly, the first scan signal SCAN1 applied to the gate node of the first transistor T1 and the second scan signal SCAN2 applied to the gate node of the second transistor T2 are separate signals.

3, when the gate node of the first transistor T1 and the gate node of the second transistor T2 are connected in correspondence with the two gate lines GL1 and GL2, the subpixel SP is " ".

On the other hand, the transistor such as the driving transistor DT may be deteriorated as the driving time becomes longer, and the characteristic value such as the threshold voltage and the mobility may be changed.

Further, since there is a difference in driving time for each transistor, the degree of deterioration may be different, and the characteristic value change between the transistors may be different from each other. Thus, a characteristic value deviation between the transistors may occur.

The deviation of the characteristic values between the respective transistors may cause unevenness of luminance of the organic light emitting display panel 110, and the image quality may be greatly deteriorated.

As described above, a change in the characteristic value of a transistor, which is a factor of image quality degradation, can also be caused by light.

For example, when an external light touches a transistor (particularly, a channel region), a phenomenon occurs in which the threshold voltage of the transistor shifts in a negative (-) direction, and transistor characteristics are deteriorated.

4 is a diagram showing a light shield pattern (LS) formed under the transistor in order to prevent the characteristic value of the transistor from changing due to light in the organic light emitting display according to the present embodiments.

4, when light is irradiated to a transistor including a source node S, a drain node D and a gate node G, particularly, when light is irradiated to a channel of the transistor, (E.g., threshold voltage, etc.) can vary greatly.

Thus, a light shielding pattern LS is formed in a region (for example, a lower portion) of the transistor.

As a result, it is possible to prevent light from reaching the transistor by the light-shielding pattern LS, and the change of the device characteristics of the transistor can be prevented.

The light-shielding pattern LS may be made of a metal material capable of blocking the transmission of light.

On the other hand, the light shielding pattern LS is located under the gate node (gate electrode) of the transistor with the insulating layer interposed therebetween, and can serve as the body B of the transistor.

5 is a sectional view illustrating a light blocking pattern LS formed in a circuit area (CA) of each subpixel SP in the organic light emitting diode display 100 according to the present embodiment, (SP).

5, each of the sub-pixels SP includes a light emitting area (EA) emitting light by the organic light emitting diode (OLED) and a circuit area CA formed with a circuit for driving the organic light emitting diode (OLED) Lt; / RTI >

Referring to FIG. 5, the light blocking pattern LS may be patterned on the entire surface of the circuit region CA where the transistors DT, T1, and T2 are located, in order to prevent the transistor characteristics from being changed by light.

In this case, the light-shielding pattern LS is a floating pattern to which no voltage is applied.

On the other hand, as described above, the shielding pattern LS serves as the body of each of the transistors DT, T1, and T2.

Thus, the light-shielding pattern LS can serve as another gate node (also referred to as a back gate node) of each of the transistors DT, T1, and T2. As a result, the threshold voltage of each of the transistors DT, T1, and T2 may change, or a desired operation may not be performed. This phenomenon is called "body effect ".

In order to improve the operation characteristics of the driving transistor DT in the OLED display 100 according to the present embodiment, the light-shielding pattern LS is connected to the second node N2 of the driving transistor DT Shielding pattern structure.

6, in order to prevent the drive transistor DT, which greatly affects the overall drive characteristics of each sub-pixel SP, from being affected by the body effect and to improve the operation characteristics of the drive transistor DT, The shielding pattern LS patterned on the front surface of the area CA can be connected to the second node N2 of the driving transistor DT.

Such a light-shielding pattern structure is referred to as a "single light-shielding pattern structure" since there is one light-shielding pattern LS connected to the second node N2 of the driving transistor DT for each subpixel SP.

FIGS. 7 and 8 are views for explaining an abnormal driving phenomenon that may be caused by a single light-shielding pattern structure in the organic light emitting diode display 100 according to the present embodiments.

7 and 8, according to the single light-shielding pattern structure, the voltage of the second node N2 of the driving transistor DT is applied to the light-shielding pattern LS as the bias voltage BV.

7, in order to turn off the first transistor T1, a first scan signal SCAN1 corresponding to the turn-off level voltage VGL is applied to the gate node of the first transistor T1 The bias voltage BV applied to the shielding pattern LS serves as another gate voltage of the first transistor T1 so that a body effect may be generated so that the first transistor T1 It may be turned on unwantedly.

8, a second scan signal SCAN2 corresponding to the turn-off level voltage VGL is applied to the gate node of the second transistor T2 in order to turn off the second transistor T2. The bias voltage BV applied to the light shielding pattern LS serves as another gate voltage of the second transistor T2 so that a body effect can be generated and thus the second transistor T2 ) May be turned on unwantedly.

7 and 8, the situation in which the first transistor T1 and / or the second transistor T2 are turned on unwantedly due to the influence of the body effect may occur even during image driving , And may also occur at the time of sensing driving.

For example, when the first transistor (T1) to be turned off is turned on, the data voltage supplied to the subpixel in the previous line (previous subpixel row) or the next line (next subpixel row) Is supplied to the sub-pixel having the first transistor (T1), so that an image abnormal phenomenon may occur. This phenomenon is called data mixing phenomenon.

For example, the threshold voltage of the driving transistor DT may be sensed for a first sub-pixel electrically connected to a reference voltage line RVL electrically connected to an analog-to-digital converter (serving as a sensing line) When the second transistor T2 to be turned off in the second sub-pixel electrically connected with the reference voltage line RVL in another sub-pixel row is unnecessarily turned on while the sensing operation for performing the sensing operation for the second sub- The unnecessarily turned-on second transistor T2 transfers the voltage of the second node N2 of the driving transistor DT to the reference voltage line RVL.

Because of this, the analog digital converter can not accurately sense the voltage of the second node N2 of the driving transistor DT in the first sub-pixel, so that a sensing error may occur. Such a sensing error may also cause an error in the calculation of the compensation value for the threshold voltage deviation, thereby causing an image abnormal phenomenon.

Therefore, the embodiments of the present invention can provide a light-shielding pattern structure capable of preventing abnormal driving phenomenon (unnecessarily turning on phenomenon) of the first transistor T1 and / or the second transistor T2 due to the influence of the body effect I suggest.

First, referring to Figs. 9 to 15, a double shielding pattern structure will be described. Next, with reference to Figs. 16 to 22, a triple shield pattern structure will be described.

The double shielding pattern structure is a shielding pattern structure applicable to one scan structure and has two shielding patterns (LS_SHORT, LS_LONG) connected to different points.

The triple shielding pattern structure is a shielding pattern structure applicable to a two-scan structure and has three shielding patterns (LS_SHORT, LS_LONG1, LS_LONG2) connected to different points.

9 to 11 are views showing a double shielding pattern structure for preventing abnormal driving phenomenon when each subpixel SP of the organic light emitting diode display 100 according to the present embodiment has a one scan structure.

FIG. 9 is an equivalent circuit of two sub-pixels SP1 and SP2 to which a double light-shielding pattern structure is applied, and FIG. 10 is a diagram showing double light-shielding patterns LS_SHORT and LS_LONG in two sub-pixels SP1 and SP2. 11 is a diagram showing a double light-shielding pattern LS_SHORT, LS_LONG in the four sub-pixels SP1, SP2, SP3 and SP4.

9 to 11, each sub-pixel of one scan structure includes an organic light emitting diode OLED, a driving transistor DT for driving the organic light emitting diode OLED, A first transistor T1 which is controlled by a scan signal SCAN applied to the node and is electrically connected between the first node N1 of the driving transistor DT and the data line DL, A second transistor T2 controlled by a scan signal SCAN applied to the gate node through the second node N2 and electrically connected between the second node N2 of the driving transistor DT and the reference voltage line RVL, And a storage capacitor C1 electrically connected between the first node N1 and the second node N2 of the data driver DT.

Referring to FIGS. 9 to 11, a short light shield pattern (LS_SHORT) is positioned for each region of the driving transistor DT of each subpixel.

The short-shielding pattern LS_SHORT, which exists for each sub-pixel, is electrically connected to the second node N2 of the corresponding driving transistor DT.

The short shading pattern LS_SHORT may be connected to the second node N2 of the driving transistor DT through the connection pattern CPS.

9 to 11, one long light shield pattern (LS_LONG) is positioned in the row direction for each subpixel row.

The long light-shielding pattern LS_LONG, which is present for each subpixel row, is located passing through a plurality of regions of the first transistor T1 and a plurality of the second transistors T2 located in the corresponding subpixel row.

The long light-shielding pattern LS_LONG includes a gate line GL and a non-active region GL connected in common to the gate node of all the first transistors T1 and the gate nodes of all the second transistors T2, N / A). ≪ / RTI >

This long shading pattern LS_LONG enables the double gate operation of all the first transistor T1 and all the second transistors T2 located in the subpixel row.

In addition, the long light-shielding pattern LS_LONG may be electrically connected to the gate line GL and the non-active region N / A through the connection pattern CPL.

According to the double shielding pattern structure described above, the first transistor T1 and the second transistor T2 are prevented from being turned on unintentionally according to the voltage of the second node N2 of the driving transistor DT That is, the first transistor T1 and the second transistor T2 are less influenced by the body effect. Thus, it is possible to prevent the abnormal driving phenomenon (unnecessarily turning on phenomenon) of the first transistor (T1) and the second transistor (T2), thereby preventing the image abnormal phenomenon and improving the image quality have.

In addition, for the double gate operation, the long light-shielding pattern LS_LONG is not individually connected to the gate node of the first transistor T1 and the gate node of the second transistor T2 in each subpixel, ) And the non-active region N / A, so that it is not necessary to form a connection structure in the active region A / A. Accordingly, the aperture ratio of the OLED display panel 110 can be increased.

12 is a diagram illustrating a long light-shielding pattern LS_LONG in a double-shielding pattern structure when each sub-pixel SP of the OLED display 100 according to the present embodiment has a one-scan structure.

12, the long light-shielding pattern LS_LONG includes a line portion L extending in the row direction in the corresponding subpixel row, a first transistor T1 located in the corresponding subpixel row in the line portion L, And a second protrusion E2 protruding into the area of each second transistor T2 located in the corresponding subpixel row in the line section L. The first protrusion E1 protrudes into the region of the second transistor T2,

According to the above description, it is possible to make a light-shielding pattern structure in the regions of all the first transistors T1 and all the second transistors T2 located in the subpixel row by using only one long light-shielding pattern LS_LONG.

13 is a graph showing the relationship between the long-shielding pattern LS_LONG and the gate line GL in the double-shielding pattern structure when each subpixel SP of the OLED display 100 according to the present embodiment has a one- Fig.

13, the organic light emitting display panel 110 includes an active area (A / A) where an image is displayed, a non-visible area corresponding to an outer area of the active area A / A, And an active area N / A (Non-Active Area).

A plurality of subpixel rows SPR1, ..., SPRn exist in the organic light emitting display panel 110. [

Referring to FIG. 13, in the case of a one scan structure, one gate line GL may be arranged in the row direction for each one subpixel row.

In addition, in the case of one scan structure, one long light shield pattern LS_LONG may be arranged in the row direction for each one subpixel row.

Referring to FIG. 13, the gate line GL and the long light-shielding pattern LS_LONG arranged for each subpixel row can be electrically connected through the connection pattern CPL in the non-active region N / A .

The long shield pattern LS_LONG may be connected to one end of the gate line GL or may be connected to both ends of the gate line GL as shown in FIG. That is, the connection point of the long light-shielding pattern LS_LONG may be one or two.

Referring to FIG. 13, the long light-shielding pattern LS_LONG is located corresponding to the gate line GL.

As an example, the long light-shielding pattern LS_LONG may be positioned below the gate line GL.

Accordingly, the formation space of the long shielding pattern LS_LONG can be reduced, and the gate line GL and the long shielding pattern LS_LONG can be easily connected through the short connection pattern CPL.

FIGS. 14 and 15 are diagrams for explaining a case where each subpixel SP of the organic light emitting diode display 100 according to the present embodiment has a one scan structure. In the double shield pattern structure, the long shield pattern LS_LONG and the gate line 0.0 > GL). ≪ / RTI >

Fig. 14 is an enlarged view of a portion A in Fig. 13, and Fig. 15 is a cross-sectional view of A 'in Fig.

14 and 15, the long light blocking pattern LS_LONG and the gate line GL are connected through the connection pattern CPL in the non-active area A / A.

14, when the gate protrusion GE is located in the non-active region N / A in the gate line GL and the contact protrusion LE is located in the non-active region N / A in the long shield pattern LS_LONG, A).

14 and 15, the gate protrusion GE of the gate line GL and the contact protrusion LE of the long light-shielding pattern LS_LONG may be electrically connected through the connection pattern CPL.

The long shield pattern LS_LONG and the gate line GL can be easily connected through the protruded connection structure.

Referring to FIG. 15, a lower buffer layer 1520 is disposed on a substrate 1510.

The gate line GL, that is, the gate projection GE of the gate line GL is located on the gate insulating layer 1530 located above the lower buffer layer 1520. [

The contact protrusion LE of the long light blocking pattern LS_LONG, that is, the long light blocking pattern LS_LONG, is located on the lower buffer layer 1520. [

The buffer layer 1540 is located on the contact projection LE of the long-shielding pattern LS_LONG.

An interlayer insulating film 1550 is located on the buffer layer 1540 and the gate projection GE of the gate line GL.

The connection pattern CPL connects the gate protrusion GE of the gate line GL and the contact protrusion LE of the long light blocking pattern LS_LONG through the hole of the interlayer insulating film 155.

A passivation layer 1560 is placed on this connection pattern CPL.

Referring to FIG. 15, the connection pattern CPL may be a metal of a different type from the long-shielding pattern LS_LONG and the gate line GL. In one example, the connection pattern (CPL) may be a source-drain material.

The organic light emitting display panel 110 forms a connection pattern CPL for connecting the long light shielding pattern LS_LONG and the gate line GL by using the layer of the material located on the gate material layer and used for voltage wiring and the like as it is. can do.

Hereinafter, a triple shielding pattern structure that can be utilized for a two-scan structure will be described with reference to FIGS. 16 to 22. FIG.

16 to 18 are views showing a triple shielding pattern structure for preventing abnormal driving phenomenon when each subpixel SP of the organic light emitting diode display 100 according to the present embodiments has a two scan structure.

16 is an equivalent circuit of two sub-pixels SP1 and SP2 to which a triple light-shielding pattern structure is applied, and FIG. 17 is a diagram showing triple light-shielding patterns LS_SHORT, LS_LONG1 and LS_LONG2 in two sub-pixels SP1 and SP2 . 18 is a diagram showing triple shielding patterns LS_SHORT, LS_LONG1 and LS_LONG2 in the four sub-pixels SP1, SP2, SP3 and SP4.

16 to 18, each sub-pixel having a two scan structure includes an organic light emitting diode OLED, a driving transistor DT for driving the organic light emitting diode OLED, a first gate line GL1, A first transistor T1 which is controlled by a first scan signal SCAN1 applied to the gate node through the first node N1 and is electrically connected between the first node N1 of the driving transistor DT and the data line DL, Is controlled by the second scan signal SCAN2 applied to the gate node through the second gate line GL2 and is electrically connected between the second node N2 of the drive transistor DT and the reference voltage line RVL A second transistor T2 and a storage capacitor C1 electrically connected between the first node N1 and the second node N2 of the driving transistor DT.

Referring to Figs. 16 to 18, a short-shielding pattern LS_SHORT is provided for each region of the driving transistor DT of each subpixel SP.

The short shield pattern LS_SHORT, which is provided for each subpixel, can be electrically connected to the second node N2 of the driving transistor DT through a connection pattern CPS.

16 to 18, for each row of sub-pixels, the first long light blocking pattern LS_LONG1 and the second long light blocking pattern LS_LONG2 are located in the row direction.

The first long light-shielding pattern LS_LONG1, which is present for each subpixel row, is located passing through a region of the plurality of first transistors T1 located in the corresponding subpixel row.

The second long light-shielding pattern LS_LONG2, which exists in one row for each subpixel row, is located passing through the area of the plurality of second transistors T2 located in the corresponding subpixel row.

The first long light shielding pattern LS_LONG1 is formed in the first gate line GL1 and the non-active region N / A connected to the gate nodes of all the first transistors T1 located in the subpixel row, CPL1. ≪ / RTI >

The second long light shielding pattern LS_LONG2 is formed in the second gate line GL2 connected to the gate node of all the second transistors T2 located in the corresponding subpixel row and in the non-active region N / ), As shown in Fig.

According to the triple shield pattern structure described above, the first transistor T1 and the second transistor T2 are prevented from being turned on unintentionally according to the voltage of the second node N2 of the driving transistor DT That is, the first transistor T1 and the second transistor T2 are less influenced by the body effect. Thus, it is possible to prevent the abnormal driving phenomenon (unnecessarily turning on phenomenon) of the first transistor (T1) and the second transistor (T2), thereby preventing the image abnormal phenomenon and improving the image quality have.

In addition, for the double gate operation, the first long-shielding pattern LS_LONG1 is not separately connected to the gate node of the first transistor T1 in each sub-pixel, and the first gate line GL1 and the non- (N / A), it is not necessary to form a connection structure in the active area A / A. Accordingly, the aperture ratio of the OLED display panel 110 can be increased. Similarly, for the double gate operation, the second long-shielding pattern LS_LONG2 is not individually connected to the gate node of the second transistor T2 in each subpixel, but is connected to the second gate line GL2 and the non- It is not necessary to form a connection structure in the active area A / A by being connected only once in the area N / A. Accordingly, the aperture ratio of the OLED display panel 110 can be increased.

FIG. 19 is a diagram for explaining a case where each subpixel SP of the OLED display 100 according to the present embodiment has a two-scan structure. In the triple light-shielding pattern structure, the first long-shielding pattern LS_LONG1 and the second long- And a pattern LS_LONG2.

19, the first long light-shielding pattern LS_LONG1 includes a first line portion L1 extending in the row direction in the corresponding subpixel row and a second line portion L1 extending in the first line portion L1 in the subpixel row And a first protrusion E1 protruding into the region of the first transistor T1.

The second long light-shielding pattern LS_LONG2 includes a second line portion L2 extending in the row direction of the corresponding subpixel row and a second line portion L2 extending in the second line portion L2 of each second transistor T2, And a second protrusion E2 protruding into the area of the second protrusion E2.

According to the above description, even if only one first long light-shielding pattern LS_LONG1 is provided, a light-shielding pattern structure can be formed in the area of all the first transistors T1 located in the subpixel row, and one second long light- ), It is possible to make a light-shielding pattern structure in the region of all the second transistors T2 located in the subpixel row.

FIG. 20 is a diagram illustrating a relationship between a first long-shielding pattern LS_LONG1 and a first gate line GL in a triple-shielding pattern structure when each sub-pixel SP of the OLED display 100 according to the present embodiment has a two- Shielding pattern GL1 and the arrangement structure between the second long-shielding pattern LS_LONG2 and the second gate line GL2.

20, the organic light emitting display panel 110 includes an active area (A / A) where an image is displayed, a non-visible area corresponding to an outer area of the active area (A / A) And an active area N / A (Non-Active Area).

A plurality of subpixel rows SPR1, ..., SPRn exist in the organic light emitting display panel 110. [

Referring to FIG. 20, in the case of a two scan structure, two gate lines GL1 and GL2 may be arranged in the row direction for each one subpixel row.

In the case of a two-scan structure, two long light-shielding patterns LS_LONG1 and LS_LONG2 may be arranged in the row direction for each one subpixel row.

Referring to FIG. 20, the first gate line GL1 and the first long light-shielding pattern LS_LONG1 arranged for each subpixel row are electrically connected through the connection pattern CPL1 in the non-active region N / A .

The second gate line GL2 and the second long light shielding pattern LS_LONG2 arranged for each subpixel row can be electrically connected through the connection pattern CPL2 in the non-active region N / A.

The first long light shield pattern LS_LONG1 may be connected to one end of the first gate line GL1 or may be connected to both ends of the first gate line GL1 as shown in FIG. That is, the connection point of the first long light shielding pattern LS_LONG1 may be one or two.

The second long light shield pattern LS_LONG2 may be connected to one end of the second gate line GL2 or may be connected to both ends of the second gate line GL2 as shown in FIG. That is, the connection point of the second long light shielding pattern LS_LONG2 may be one or two.

Referring to FIG. 20, the first long light-shielding pattern LS_LONG1 is located in correspondence with the first gate line GL1, and the second long light-shielding pattern LS_LONG2 is located in correspondence with the second gate line GL2.

For example, the first long light-shielding pattern LS_LONG1 may be positioned below the first gate line GL1, and the second long light-shielding pattern LS_LONG2 may be located below the second gate line GL2.

Accordingly, a space for forming two long light-shielding patterns LS_LONG1 and LS_LONG2 existing for each subpixel row can be reduced, and two gate lines GL1 and GL2 and two The long light-shielding patterns LS_LONG1 and LS_LONG2 can be easily connected to each other.

Figs. 21 and 22 are diagrams illustrating a case where each subpixel SP of the organic light emitting diode display 100 according to the present embodiment has a two-scan structure. In the triple light-shielding pattern structure, the first long- 1 gate line GL1 and a connection structure between the second long-shielding pattern LS_LONG2 and the second gate line GL2.

FIG. 21 is an enlarged view of a portion B in FIG. 20, and FIG. 22 is a sectional view of B 'in FIG.

21 and 22, the first gate protrusion GE1 is located in the non-active region N / A in the first gate line GL1 and the first contact protrusion GE1 is located in the first long- (LE1) is located in the non-active area N / A.

The first gate protrusion GE1 and the first contact protrusion LE1 are electrically connected through the first connection pattern CPL1.

 21 and 22, the second gate protrusion GE2 is located in the non-active region N / A in the second gate line GL2, the second contact protrusion GE2 is located in the second long- (LE2) is located in the non-active area N / A.

The second gate protrusion GE2 and the second contact protrusion LE2 are electrically connected through the second connection pattern CPL2.

The first long light-shielding pattern LS_LONG1 and the first gate line GL1 can be easily connected to each other through the protruded connection structure and the second long-shielding pattern LS_LONG2 can be easily connected to the second gate line GL1 .

The first connection pattern CPL1 and the second connection pattern CPL2 are formed by connecting the first long shielding pattern LS_LONG1 and the second long shielding pattern LS_LONG2 and the first gate line GL1 and the second gate line GL2 ) And a different kind of metal. For example, the first connection pattern CPL1 and the second connection pattern CPL2 may be source-drain materials.

The first and second long light shield patterns LS_LONG1 and LS_LONG2 and the first and second gate lines GL1 and GL_LONG2 are formed on the organic light emitting display panel 110 using the material layer used for the voltage wiring, The first and second connection patterns CPL1 and CPL2 for connecting the first and second connection patterns GL1 and GL2 may be formed.

According to the exemplary embodiments of the present invention described above, the organic light emitting display panel 110 and the organic light emitting display device 100 ). ≪ / RTI >

In addition, according to the embodiments, a light-shielding pattern can be placed under the transistor in the sub-pixel to reduce variations in characteristics of the transistor, and a light-shielding effect that can reduce the influence of a body effect, The organic light emitting display panel 110 having the pattern structure and the OLED display 100 can be provided.

In addition, according to the embodiments, the shape of the light-shielding pattern and the connection position are different depending on the type of transistor in the sub-pixel, thereby effectively reducing the influence of the body effect, The organic light emitting display panel 110 having the light-shielding pattern structure and the OLED display 100 can be provided.

In addition, according to the present embodiments, when the sub-pixel includes the first transistor and the second transistor connected to the same gate line as the driving transistor, a region where the short-shielding pattern and the regions of the first and second transistors The organic light emitting display panel 100 and the organic light emitting display panel 110 that can effectively prevent the abnormal driving phenomenon according to the transistor type can be provided by having the light shielding pattern structure including the long light shielding pattern (s).

In addition, according to the embodiments, it is possible to provide the organic light emitting display panel 110 and the organic light emitting display 100 having the light shielding pattern structure capable of increasing the aperture ratio.

The light shielding pattern structure described above can be applied to the 2T1C subpixel structure composed of the driving transistor DT and the first transistor T1 and the storage capacitor C1 and can be applied to various subpixel structures in addition to the 3T1C structure and the 2T1C structure .

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: organic light emitting display
110: organic light emitting display panel
120: Data driver
130: gate driver
140: controller

Claims (12)

An organic light emitting display panel in which a plurality of subpixels defined by a plurality of data lines and a plurality of gate lines are arranged in a matrix type;
A data driver for driving the plurality of data lines; And
And a gate driver for driving the plurality of gate lines,
Each of the sub-
A first transistor controlled by a scan signal applied to a gate node through a gate line and electrically connected between a first node of the drive transistor and the data line, A second transistor electrically connected between a second node of the driving transistor and the reference voltage line, the second transistor being controlled by the scan signal applied to the gate node through the gate line, And a storage capacitor electrically connected between the first electrode and the second electrode,
A short shielding pattern is located in each of the regions of the driving transistor of each subpixel, the short shielding pattern is electrically connected to a second node of the driving transistor,
One long shading pattern is positioned in the row direction for each subpixel row and the long shading pattern is located passing through a region of a plurality of first transistors located in the corresponding subpixel row and a region of a plurality of second transistors, Wherein the shielding pattern is electrically connected to the gate node of the plurality of first transistors located in the corresponding subpixel row and the gate line commonly connected to the gate nodes of the plurality of second transistors in the non-active region. The method according to claim 1,
The long-
A line portion extending in the row direction in the corresponding subpixel row;
A first protrusion protruding into a region of each first transistor located in a corresponding subpixel row in the line portion; And
And a second protrusion protruding into a region of each second transistor located in a corresponding subpixel row in the line portion. The method according to claim 1,
A gate protrusion is located in the non-active region in the gate line,
Wherein the contact protrusion is located in the non-active region in the long-shielding pattern,
And the gate protrusion and the contact protrusion are electrically connected through a connection pattern. The method of claim 3,
The connection pattern
Wherein the long light-shielding pattern and the gate line are made of a different kind of metal. The method according to claim 1,
Wherein the long-shielding pattern is located below the gate line. A plurality of data lines;
A plurality of gate lines; And
And a plurality of subpixels defined by the plurality of data lines and the plurality of gate lines and arranged in a matrix type,
In each subpixel,
A first transistor coupled between a first node of the driving transistor and a data line, the first transistor being controlled by a scan signal applied to a gate node through a gate line, A second transistor electrically connected between a second node of the driving transistor and the reference voltage line, the second transistor being controlled by the scan signal applied to the gate node through the gate line; A storage capacitor electrically connected between two nodes is disposed,
A short shielding pattern is located in each of the regions of the driving transistor of each subpixel, the short shielding pattern is electrically connected to a second node of the driving transistor,
One long shading pattern is positioned in the row direction for each subpixel row and the long shading pattern is located passing through a region of a plurality of first transistors located in the corresponding subpixel row and a region of a plurality of second transistors, Wherein the light shielding pattern is electrically connected to the gate node of the plurality of first transistors located in the corresponding subpixel row and the gate line commonly connected to the gate nodes of the plurality of second transistors in the non-active region. An organic light emitting display panel in which a plurality of subpixels defined by a plurality of data lines and a plurality of gate lines are arranged in a matrix type;
A data driver for driving the plurality of data lines; And
And a gate driver for driving the plurality of gate lines,
Each of the sub-
A driving transistor for driving the organic light emitting diode; a first scan signal applied to the gate node through the first gate line; and a first scan signal applied to the gate node through the first node and the data line, A second transistor electrically connected between a second node of the driving transistor and a reference voltage line, the second transistor being controlled by a second scan signal applied to a gate node through a second gate line, And a storage capacitor electrically connected between the first node and the second node of the storage capacitor,
A short shielding pattern is located in each of the regions of the driving transistor of each subpixel, the short shielding pattern is electrically connected to a second node of the driving transistor,
The first long light-shielding pattern and the second long light-shielding pattern are located in the row direction for each subpixel row,
The first long light-shielding pattern is located passing through a plurality of first transistors located in a corresponding subpixel row, and the second long light-shielding pattern is located passing through a plurality of second transistor regions located in the corresponding subpixel row ,
The first long-shielding pattern is electrically connected to the first gate line connected to the gate nodes of the plurality of first transistors located in the corresponding subpixel row in the non-active region, and the second long- And the second gate line connected to the gate node of the plurality of second transistors located in the non-active region. 8. The method of claim 7,
Shielding pattern,
A first line portion extending in the row direction in the corresponding subpixel row; And
And a first protrusion protruding into a region of each first transistor located in a corresponding subpixel row in the first line portion,
The second long-shielding pattern is a light-
A second line portion extending in the row direction in the corresponding subpixel row; And
And a second protrusion protruding into a region of each second transistor located in a corresponding subpixel row in the second line portion. 8. The method of claim 7,
Wherein the first gate protrusion and the first contact protrusion are located in the non-active region in the first gate line, the first contact protrusion is located in the non-active region in the first long-light-shielding pattern, And electrically connected through the first connection pattern,
Wherein the second gate protrusion and the second contact protrusion are located in a non-active region in the second gate line, the second gate protrusion is located in the non-active region, the second contact protrusion is located in the non- And the second connection pattern is electrically connected. 10. The method of claim 9,
Wherein the first connection pattern and the second connection pattern are formed by:
The first long light-shielding pattern, the second long light-shielding pattern, and the first gate line and the second gate line. 8. The method of claim 7,
Wherein the first long-shielding pattern is located below the first gate line,
And the second long-shielding pattern is located below the second gate line. A plurality of data lines;
A plurality of gate lines; And
And a plurality of subpixels defined by the plurality of data lines and the plurality of gate lines and arranged in a matrix type,
In each subpixel,
A driving transistor for driving the organic light emitting diode; a first scan signal applied to the gate node through the first gate line; and a first scan signal applied to the gate node through the first node and the data line, A second transistor electrically connected between a second node of the driving transistor and a reference voltage line, the second transistor being controlled by a second scan signal applied to a gate node through a second gate line, A storage capacitor electrically connected between the first node and the second node of the first transistor is disposed,
A short shielding pattern is located in each of the regions of the driving transistor of each subpixel, the short shielding pattern is electrically connected to a second node of the driving transistor,
The first long light-shielding pattern and the second long light-shielding pattern are located in the row direction for each subpixel row,
The first long light-shielding pattern is located passing through a plurality of first transistors located in a corresponding subpixel row, and the second long light-shielding pattern is located passing through a plurality of second transistor regions located in the corresponding subpixel row ,
The first long-shielding pattern is electrically connected to the first gate line connected to the gate nodes of the plurality of first transistors located in the corresponding subpixel row in the non-active region, and the second long- And the second gate line connected to the gate node of the plurality of second transistors located in the non-active region.

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