KR20190036461A - Organic Light Emitting Diode display panel and Organic Light Emitting Diode display device using the same - Google Patents

Abstract

The present invention relates to a display panel in which a GIP of a gate driving circuit is arranged in a pixel array, and an OLED display device using the same. The display panel comprises: a display region in which data lines and gate lines are intersecting, and which includes sub-pixels arranged at the intersections where the data lines and gate lines are intersecting; and a plurality of GIPs which is distributed in unit pixel regions driven by each gate line in the display region and supplies scan pulse to the gate lines.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode (OLED) display panel and an organic light emitting diode (OLED) display using the organic light emitting diode display panel.

The present invention relates to an OLED display panel in which a GIP of a gate driving circuit is disposed in a pixel array and an image quality defect due to GIP arrangement can be improved, and an OLED display using the OLED display panel.

As an information-oriented society develops and various portable electronic devices such as a mobile communication terminal and a notebook computer develop, a demand for a flat panel display device that can be applied to the portable electronic device is gradually increasing.

As such a flat panel display device, an OLED display device using a liquid crystal display (LCD) and an organic light emitting diode (OLED) is used.

Such flat panel display devices include a display panel having a plurality of gate lines and a plurality of data lines for displaying an image, and a driving circuit for driving the display panel.

A display panel of the liquid crystal display device among the display devices includes a thin film transistor array substrate on which a thin film transistor array is formed on a glass substrate, a color filter array substrate on which a color filter array is formed, And a liquid crystal layer filled between the array substrate and the color filter array substrate.

The thin film transistor array substrate includes a plurality of gate lines GL extending in a first direction and a plurality of data lines DL extending in a second direction perpendicular to the first direction, And one sub pixel region (Pixel P) is defined by each data line. One thin film transistor and a pixel electrode are formed in one sub pixel region (P).

In the display panel of such a liquid crystal display device, a voltage is applied to an electric field generating electrode (pixel electrode and common electrode) to generate an electric field in the liquid crystal layer, and the arrangement state of the liquid crystal molecules in the liquid crystal layer is adjusted by the electric field, The image is displayed by controlling the polarization.

In the display panel of the OLED display device among the above-described display devices, a plurality of gate lines and a plurality of data lines intersect to define sub-pixels, and each sub-pixel includes an anode and a cathode, And a pixel circuit for independently driving the OLED.

The pixel circuit may be variously configured, but includes at least one switching TFT, a capacitor, and a driving TFT.

The at least one switching TFT charges the capacitor with a data voltage in response to a scan pulse. The driving TFT controls the amount of current supplied to the OLED according to the data voltage charged in the capacitor to control the amount of light emitted from the OLED.

The display panel for a display device is defined as a non-active area (NA) that is a peripheral area of the display area AA and a display area (AA) that provides an image to the user.

The driving circuit for driving the display panel may further include: a gate driving circuit for sequentially supplying gate pulses (or scan pulses) to the plurality of gate lines of the display panel; And a timing controller for supplying video data and various control signals to the gate driving circuit and the data driving circuit, and the like.

The gate driving circuit may be constituted by at least one gate drive IC, but it is preferable that in the process of forming the sub-pixel and the plurality of signal lines (gate lines and data lines) of the display panel, Region can be formed simultaneously.

In other words, a gate-in-panel (hereinafter referred to as "GIP") method of directly driving the gate driving circuit to the display panel is applied.

The gate driving circuit includes a plurality of stages (hereinafter, referred to as "GIP") equal to or greater than the number of gate lines in order to sequentially supply scan pulses to the respective gate lines, Oxide semiconductor thin film transistors.

That is, the gate driving circuit includes a plurality of stages (GIP) that are connected in a dependent manner. Each stage GIP is connected to each gate line and receives a clock signal, a gate start signal, a gate high voltage and a gate low voltage applied from the timing controller to generate one carry pulse and one scan pulse .

1 is a block diagram of a general (n) -th GIP.

As shown in FIG. 1, each of the GIPs is set by a start pulse or a carry pulse SET output from the GIP of the preceding stage, and is set by a carry pulse RST output from the GIP of the following stage. A node controller 100 for controlling the voltages of the first and second nodes Q and Qb and a scan pulse output clock signal SCCLKs for a plurality of scan pulse output signals, And one carry pulse (So (n)) according to the voltage levels of the first and second nodes (Q, Qb), and a carry pulse output clock signal of one of the clock signals (CRCLKs) And an output unit 200 for outputting Co (n).

In the case of the GIP driven by the 6-phase clock signal, the node control unit 100 is set by the carry pulse Co (n-3) outputted from the GIP of the third previous stage, and output by the GIP of the third And is reset by the carry pulse Co (n + 3) to control the voltages of the first and second nodes Q and Qb.

Although not shown in the figure, the output unit 200 of the GIP includes a carry pulse output unit and a scan pulse output unit.

The carry pulse output unit includes a first pull-up transistor and a second pull-down transistor connected in series between a carry signal output clock signal for applying a carry pulse output clock signal of a plurality of carry clock signals and a first gate low voltage signal line (VGL1) And a transistor.

The first pull-up transistor is turned on / off according to a voltage level of the first node (Q), and the first pull-down transistor is turned on / off according to a voltage level of the second node (Qb) And outputs the output clock signal as a carry pulse Co (n).

The scan pulse output unit includes a second pull-up transistor connected in series between a clock signal output clock pulse signal for applying one scan pulse output clock signal of the plurality of scan pulse output clock signals and a second gate low voltage terminal (VGL2) A pull-down transistor, and a bootstrap capacitor connected between a gate electrode of the second pull-up transistor and a source electrode.

The second pull-up transistor is turned on / off according to the voltage level of the second node (Qb), and the second pull- And outputs the output clock signal as a scan pulse So (n).

FIG. 2 is a waveform diagram showing the operation of the (n) -th GIP shown in FIG.

2, the node controller 100 sets the carry pulse Co (n-3) output from the third preceding GIP and the carry pulse Co (n-3) (n + 3)) to control the voltages of the first and second nodes Q and Qb.

The (n) -th GIP (GIP (n)) is set by the carry pulse Co (n-3) output from the GIP of the third previous stage to turn the first node Q to the gate high voltage VGH , And discharges the second node (Qb) to a gate low voltage (VGL) state. Therefore, the first pull-up transistor of the carry pulse output unit and the second pull-up transistor of the scan pulse output unit are turned on, and the first pull-down transistor of the carry pulse output unit and the second pull- do.

Clock signals (CRCLK and SCCLK) having the same phase are applied to the drain electrode of the first pull-up transistor of the carry pulse output unit and the drain electrode of the second pull-up transistor of the scan pulse output unit.

When high level clock signals (CRCLK, SCCLK) are applied to the drain electrode of the first pull-up transistor and the drain electrode of the second pull-up transistor, the voltage of the floating first node (Q) And is bootstrapped and raised by 2VGH.

In the state where the first node Q is bootstrapped, the carry pulse output unit and the scan pulse output unit convert the input clock pulses CRCLK and SCCLK into carry pulses Co (n) (So (n)).

The first node Q is reset by the carry pulse Co (n + 3) output from the third rear-end GIP, and the second node Qb becomes a high state. Accordingly, the first pull-up transistor of the carry pulse output unit and the second pull-up transistor of the scan pulse output unit are turned off, and the first pull-down transistor of the carry pulse output unit and the second pull- And outputs the gate low voltage VGL to the carry pulse Co (n) and the scan pulse So (n).

Thus, since the conventional gate driving circuit is directly formed in the non-display region of the display panel, it is difficult to design a narrow bezel of the flat panel display device.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to minimize the bezel and to arrange the GIP in the display area of the display panel regardless of the bezel shape, And an OLED display device using the OLED display panel.

According to an aspect of the present invention, there is provided an OLED display panel including: a display region including data lines and gate lines intersecting each other and including sub-pixels arranged at the intersections; And a plurality of GIPs distributed in unit pixel regions driven by the gate lines in the display region and supplying scan pulses to the gate lines, wherein one unit pixel region includes one element constituting the GIP Wherein the unit pixel region includes at least three sub-pixel portions, a GIP portion in which one element constituting the GIP is disposed, and a GIP internal connection wiring portion in which connection wirings connecting the elements of the GIP are disposed The GIP portion is disposed on the upper side of the GIP internal connection wiring portion and on the right side of the at least three sub pixel portions or the GIP portion is disposed on the upper side of the GIP internal connection wiring portion and on the left side of the at least three sub pixel portions .

Herein, at least one GIP is distributed and arranged in the unit pixel regions driven by the gate lines.

And the touch sensor is further disposed in the display area.

According to another aspect of the present invention, there is provided an OLED display panel including: a display region including data lines and gate lines intersecting each other and including sub-pixels arranged at the intersections; And a plurality of GIPs distributed in unit pixel regions driven by the gate lines in the display region and supplying scan pulses to the gate lines, wherein the first unit pixel region includes at least three sub- A GIP section in which one element constituting the GIP is arranged and connection wirings connecting the elements of the GIP are arranged and the second unit pixel section is composed of at least three sub-pixel sections, a dummy GIP section, Another feature is that the connection wires connecting the respective elements and the dummy connection wires are disposed.

Here, the dummy GIP unit may have the same structure as the GIP unit or may have a structure different from that of the GIP unit.

The dummy GIP unit is formed of a combination of a light shielding metal pattern, a gate electrode pattern, and a source / drain electrode pattern.

According to another aspect of the present invention, there is provided an OLED display panel including: a display region including data lines and gate lines intersecting each other and including sub-pixels arranged at the intersections; And a plurality of GIPs distributed in unit pixel regions driven by the gate lines in the display region and supplying scan pulses to the gate lines, wherein the unit pixel region includes at least three sub-pixel portions, A plurality of GIP signal lines for supplying a GIP signal to the GIP unit are disposed, and the GIP signal lines for supplying the GIP signal to the GIP unit are disposed. And a light shielding layer for blocking light is formed on at least one GIP signal line among the signal lines.

Here, the light-shielding layer may be formed by stacking at least two color filter layers of R, G, and B color filter layers or a black bank layer.

Wherein the at least one GIP signal line is applied with a carry pulse output clock signal or a scan pulse output clock signal.

The GIP internal connection wiring portion includes a first node and a second node controlling the output buffer portion of the GIP according to a voltage applied thereto, and further includes a light shielding layer blocking light on the first node or the second node .

According to another aspect of the present invention, there is provided an OLED display comprising: a display region including a plurality of data lines and a plurality of gate lines intersecting each other and including sub-pixels arranged at the intersections; A plurality of source drive ICs for dividing the plurality of data lines into a plurality of groups and driving data lines of each group; And a plurality of source driver ICs, each of which is divided into a plurality of unit pixel regions driven by respective gate lines in each of the divided display region groups, for supplying scan pulses to the corresponding gate lines, One GIP, one element constituting the GIP is arranged in one unit pixel region, and the unit pixel region includes at least three sub-pixel portions and a GIP portion in which one element constituting the GIP is arranged. And a GIP internal connection wiring portion in which connection wirings for connecting the respective elements of the GIP are disposed. The GIP portion is disposed on the upper side of the GIP internal connection wiring portion and on the right side of the at least three sub pixel portions, And the GIP unit is disposed on the left side of the at least three sub-pixel units.

Here, each source driver IC not only supplies a data voltage and various power supplies for driving pixels, but also carries out a carry pulse for driving a GIP, a scan pulse for a scan pulse, a power supply, a start signal, a reset signal, Or the like.

Each of the gate lines is electrically independent for each display region driven by each source drive IC or is integrally formed in a display region driven by each source drive IC.

According to another aspect of the present invention, there is provided an OLED display comprising: a display region including a plurality of data lines and a plurality of gate lines intersecting each other and including sub-pixels arranged at the intersections; A plurality of source drive ICs for dividing the plurality of data lines into a plurality of groups and driving data lines of each group; And the display region is divided into groups driven by two or more adjacent source drive ICs. The display regions are distributed and arranged in the unit pixel regions driven by the respective gate lines in the divided display region groups, And one unit constituting the GIP is arranged in one unit pixel region, and the unit pixel region comprises at least three sub-pixel units and one element constituting the GIP And a GIP internal connection wiring portion in which connection wirings for connecting the respective elements of the GIP are arranged. The GIP portion is disposed on the upper side of the GIP internal connection wiring portion and on the right side of the at least three sub pixel portions, The GIP portion is disposed on the upper side of the GIP internal connection wiring portion and on the left side of the at least three sub-pixel portions .

The OLED display panel according to the present invention having the above characteristics and the OLED display using the OLED display panel have the following effects.

First, since the GIPs are dispersedly arranged in the display area, the left and right bezels of the display panel can be minimized as compared with the conventional display panel constituting the GIP in the non-display areas on the left and right sides of the display area.

Second, when one GIP is arranged in one gate line (scan line) while arranging the GIP in the display region, it is effective in the uniformity of image quality and the like because it is arranged in the middle portion or two or more GIPs are arranged in one scan line .

Third, the GIP internal wiring connections can be simplified by arranging the GIP configurations separately for each function.

Fourth, since a device having a relatively large size can be divided and arranged in parallel, it is possible to sufficiently disperse the elements constituting the GIP in the display area.

Fifth, since at least three sub-pixel units and GIP units are separately arranged in the unit pixel region within the display region, signal interference between the pixel and the GIP can be minimized.

Sixthly, the display area is divided into groups driven by the respective source drive ICs, and the elements constituting the GIP are distributed and arranged in the unit pixel areas driven by the gate lines in the divided display area groups, And can supply signals for driving the GIP through the drive IC.

Seventh, a dummy GIP unit is arranged in the unit pixel in which the GIP unit is not arranged, and the dummy wiring is arranged in the GIP internal connection wiring unit 32, so that the design deviation in the non-driving of the display unit can be prevented.

G, and B color filter layers are laminated on the GIP signal line to which the carry pulse output clock signal or the scan pulse output clock signal is applied, or on the Q node or the Qb node disposed in the GIP internal connection wiring portion, A low gradation light emission phenomenon can be prevented even if an abnormal light emission phenomenon occurs due to the GIP signal line to which the carry pulse output clock signal or the scan pulse output clock signal is applied and the Q node or the Qb node .

1 is a block diagram of a general (n) -th GIP;
Fig. 2 is an operation waveform diagram of the (n) -th GIP shown in Fig. 1
3 is a block diagram schematically showing an OLED display device according to an embodiment of the present invention.
FIG. 4 is a circuit diagram of one sub-pixel in the OLED display of FIG.
5 is a circuit configuration diagram of the (n) -th GIP according to the present invention
Fig. 6 is a view showing a display region configuration diagram of the display panel according to the first embodiment of the present invention
Fig. 7 is a configuration diagram more specifically showing two adjacent unit pixels arranged in the display region of the display panel of Fig. 6
8A to 8D are explanatory diagrams showing the arrangement positions of the GIP unit according to the present invention;
FIG. 9 is an explanatory view showing the arrangement state of GIP devices according to the present invention
10 is an explanatory view showing the arrangement state of thin film transistors having a large size among the GIP devices according to the present invention
11 is a view showing a display region configuration diagram of a display panel according to a second embodiment of the present invention
12A is a configuration diagram of a unit pixel in which a GIP section is arranged in a display panel according to the present invention
12B is a diagram showing a unit pixel in which the GIP unit is not disposed in the display panel according to the present invention
13 is a diagram showing a configuration in which a dummy GIP portion is arranged in a unit pixel in which a GIP portion is not arranged in a display panel according to the present invention and a dummy wiring is arranged in a GIP internal connecting wiring portion of a unit pixel having a relatively small number of wirings
Fig. 14 is a structural cross-sectional view of the GIP portion in the display panel according to the present invention shown in Fig.
15 is a structural cross-sectional view of the dummy GIP portion according to the first embodiment in the display panel according to the present invention
16 is a structural cross-sectional view of the dummy GIP portion according to the second embodiment in the display panel according to the present invention
17 is a structural cross-sectional view of the dummy GIP portion according to the third embodiment in the display panel according to the present invention
18 is a structural cross-sectional view of a GIP signal line (GIP S / L) to which a carry pulse output clock signal or a scan pulse output clock signal according to the first embodiment is applied in the OLED display panel according to the present invention
19 is a structural cross-sectional view of a GIP signal line (GIP S / L) to which a carry pulse output clock signal or a scan pulse output clock signal according to the second embodiment is applied in the OLED display panel according to the present invention
20 is a cross-sectional view of a structure on a Q-node or Qb node according to the first embodiment in an OLED display panel according to the present invention
21 is a cross-sectional view of a structure on a Q-node or Qb node according to the second embodiment in an OLED display panel according to the present invention

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. To fully disclose the scope of the invention, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited to those shown in the drawings. Like reference numerals refer to like elements throughout the specification. In the following description of the present invention, detailed description of known related arts will be omitted when it is determined that the gist of the present invention may be unnecessarily blurred.

Where the term "comprises", "comprising", "having", "having", or the like is used herein, other parts may be added as long as "only" is not used. The singular forms of the components may be construed in plural unless otherwise expressly stated.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two components is described as 'on', 'on top', 'under', or 'next to' Quot; directly " or " direct " may be interposed between those components that are not used.

The first, second, etc. may be used to distinguish the components, but these components are not limited to the function or structure of the component or the names of components attached to the components.

The following embodiments can be combined or combined with each other partly or entirely, and technically various interlocking and driving are possible. Each embodiment may be feasible independently of one another and may be feasible in conjunction.

The circuit of the GIP and the circuit of the sub-pixel according to the present invention can be realized by a TFT of an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. Although the n-type TFT is exemplified in the following embodiments, it should be noted that the present invention is not limited to this. A TFT is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the TFT, carriers begin to flow from the source. The drain is an electrode in which the carrier exits from the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of the p-type TFT (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type TFT, the current flows from the source to the drain because the holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed depending on the applied voltage. In the following embodiments, the transistors constituting the GIP circuit and the pixel circuit are illustrated as n-type TFTs, but the present invention is not limited thereto. Therefore, the invention should not be limited by the source and drain of the TFT in the following description.

The gate pulse output from the GIP circuit swings between the gate high voltage (VGH) and the gate low voltage (VGL). The gate-on voltage VGH is set to a voltage higher than the threshold voltage of the TFT, and the gate-off voltage VGH is set to a voltage lower than the threshold voltage of the TFT. In the case of an n-type TFT, the gate-on voltage may be a gate high voltage (VGH) and the gate-off voltage may be a gate low voltage (VGL). In the case of a p-type TFT, the gate-on voltage may be a gate-low voltage (VGL) and the gate-off voltage may be a gate-high voltage (VGH).

3 is a block diagram of a configuration of an OLED display device according to an embodiment of the present invention.

Referring to FIG. 3, an OLED display device according to the present invention includes a display panel (PNL) and a driving circuit for providing image data to the display panel (PNL).

The display area AA of the display panel PNL includes a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, And a plurality of sub-pixels arranged in a matrix form by the plurality of gate lines GL1 to GLn. A touch sensor may further be disposed in the display area AA of the display panel PNL.

The plurality of sub-pixels may include red (R), green (G), and blue (B) sub-pixels for color implementation and the red (R), green (G), and blue (W) sub-pixel in addition to the pixels.

The red (R), green (G), and blue (B) subpixels constitute one unit pixel or the red (R), green Constitute one unit pixel.

In the unit pixel regions, elements (TFT, capacitor, etc.) constituting the GIP of the gate driving circuit are distributed and arranged.

That is, elements (TFT, capacitor, etc.) constituting at least one GIP of the gate driving circuit are distributedly arranged in a plurality of unit pixel regions arranged in each gate line. Of course, elements (TFTs, capacitors, etc.) constituting a plurality of GIPs may be distributedly arranged in a plurality of unit pixel regions arranged in each gate line. The concrete method of arranging the GIP will be described later.

The driving circuit includes a data driving circuit for supplying a video data voltage to the data lines DL1 to DLm of the display panel PNL and a scan pulse synchronized with the video data voltage to gate lines And a timing controller (T-CON) for controlling the operation timings of the data driving circuit and the gate driving circuit.

The data drive circuit may include one or more source drive ICs (SIC). The source driver IC SIC generates a data voltage by converting the digital video data of the input image into an analog gamma compensation voltage under the control of the timing controller T-CON and supplies the data voltage to the data lines DL1 to DLm. . The source driver IC (SIC) may be mounted on a flexible circuit board, for example, a chip on film (COF) that can be bent, or may be directly adhered on a substrate in the non-display area of the display panel (PNL) .

The COFs are adhered to the pad area of the lower substrate SUBS1 of the display panel PNL and the source PCB SPCB through an ACF (anisotropic conductive film). The input pins of the COFs are electrically connected to the output terminals (pads) of the source PCB (SPCB). The output pins of the source COFs (COFs) are electrically connected to data pads formed on the substrate of the display panel (PNL) through the ACF.

The gate driving circuit receives the start pulse VST, the clock signals CRCLK and SCCLK, the gate high voltage VGH and the gate low voltage VGL from the timing controller T-CON and outputs the gate pulse And a plurality of GIPs sequentially outputting scan pulses to the scan lines GL1 to GLn. The plurality of GIPs sequentially supply scan pulses synchronized with the data voltages to the gate lines GL1 to GLn under the control of the timing controller T-CON, Select.

The timing controller T-CON is mounted on a control PCB CPCB and the control PCB CPCB and the source PCB SPCB are connected by a flexible flat cable (FFC).

The circuit configuration of one sub-pixel in the OLED display according to the present invention and the circuit of one GIP according to the present invention are as shown in FIGS.

FIG. 4 is a circuit configuration diagram of one sub-pixel in the OLED display device of FIG. 3, and FIG. 5 is a circuit configuration diagram of the (n) th GIP according to the present invention.

Each sub-pixel of the OLED display according to the present invention includes an organic light emitting diode (OLED) and a pixel circuit for driving the organic light emitting diode, as shown in FIG.

The pixel circuit includes first and second switching TFTs T1 and T2, a storage capacitor Cst, and a driving TFT DT.

The first switching TFT Tl charges the storage capacitor Cst with a data voltage in response to a scan pulse Scan. The driving TFT DT controls the amount of current supplied to the OLED according to the data voltage charged in the storage capacitor Cst to control the amount of light emitted from the OLED. The second switching TFT (T2) senses the threshold voltage and the mobility of the driving TFT (DT) in response to a sensing signal.

The organic light emitting diode OLED may include a first electrode (e.g., an anode electrode or a cathode electrode), an organic light emitting layer, and a second electrode (e.g., a cathode electrode or an anode electrode).

 The storage capacitor Cst is electrically connected between a gate electrode of the driving TFT DT and a source electrode so that a data voltage corresponding to a video signal voltage or a voltage corresponding thereto is applied for one frame time I can keep it.

4 shows a structure of a 3T1C sub-pixel composed of three TFTs (T1, T2, DT) and one storage capacitor (Cst), but the present invention is not limited thereto. 4T1C, 4T2C, 5T1C, 5T2C, and the like.

5, the circuit of the (k) th GIP according to the present invention includes transistors TA, TB, T3qA, T1B, T1C, T5A and T5B and a capacitor C1, And selectively stores the set signal CP (k) in accordance with a line select pulse (LSP) and outputs the set signal CP (k) in accordance with a real time compensation signal (VRT) at a blank time The first and second node Q and Qb control sections 21 and 26 for charging one node Q with the first constant voltage GVDD and discharging the second node Qb with the second constant voltage GVSS2, ; The driving circuit includes a plurality of transistors T1, T1A, T3n, T3nA, T3q, T3, T3A and T5. The first node Q and the third node Qh are charged with the carry pulse CP (k-3) and the carry pulse CP (k + 3) The first to third node controllers 23 and 25 for discharging the first node Q1 to the second constant voltage GVSS2 and charging the third node Qh to the first constant voltage GVDD according to the voltage of the first node Q, ); An inverter unit 24 having transistors T4, T4l, T4q and T5q and a capacitor C2 for inverting the voltage of the first node Q and applying the inverted voltage to the second node Qb; (K) of the plurality of carry pulse output clock signals CRCLK (k) and a plurality of scan signals RCLK (k) constituted by pull-up transistors T6cr and T6, pull-down transistors T7cr and T7 and bootstrapping capacitor C3, (K) and a scan pulse SP (k) according to the voltage of the first node Q and the second node Qb, receiving one of the clock signals SCCLK (k) (k) output from the output buffer unit 27; The first node Q is configured to have a second constant voltage GVSS2 according to a reset signal RST output from the timing controller during the blank period in which the transistors T3nB and T3nC are provided. And a resetting unit 22 for discharging.

When the line selection signal LSP is at a high level, the transistors TA, TB, and T3q are turned on and the set signals (Q, Qb) are applied to the first and second nodes Q and Qb of the blank section CP (k) is stored in the capacitor C1.

The transistors T1C and T5B are turned on to charge the first node Q with the first constant voltage GVDD when the real time compensation signal VRT is at a high level in the blank section, And discharges the second node Qb to the second constant voltage GVSS2.

The first to third node control sections 23 and 25 of the driving section turn on the transistors T1, T1A and T5 when the third preceding carry pulse CP (k-3) - on to charge the first node Q with the third preceding carry pulse CP (k-3) and discharge the second node Qb with the second constant voltage GVSS2. Thus, when the first node Q is charged and the second node Qb is discharged, the transistor T3q is turned on to charge the third node Qh with the first constant voltage GVDD .

The transistors T3n and T3nA are turned on when the carry pulse CP (k + 3) at the third trailing end is at the high level to turn the first node Q and the third node Qh to the second And discharges to the constant voltage (GVSS2).

The inverter unit 24 inverts the voltage of the first node Q and applies the inverted voltage to the second node Qb.

The output buffer unit 27 is turned on when the first node Q is at the high level and the second node Qb is at the low level and the pull-down transistor T7cr is turned on when the pull- - off and outputs one of the plurality of carry pulse output clock signals CRCLK (k) as a carry pulse CP (k). Also, when the first node Q is at a high level and the second node Qb is at a low level, the pull-up transistor T6 is turned on and the pull-down transistor T7 is turned off, And outputs one clock signal SCCLK (k) of the pulse output clock signal as the scan pulse SP (k).

At this time, when the scan pulse output clock signal SCCLK (k) is applied at a high level, the first node Q is activated by the bootstrapping capacitor C3 of the output buffer unit 27, (Or coupled) to have a higher potential.

The output buffer unit 27 outputs the inputted carry pulse output clock signal CRCLK (k) and the scan pulse output clock signal SCCLK (k), respectively, in the state where the first node Q is bootstrapped, Is output as the carry pulse CP (k) and the scan pulse SP (k), so that the output loss Loss can be prevented.

The reset unit 22 turns on the transistors T3nB and T3nC when the reset signal RST outputted from the timing controller 4 is at a high level during the blank period, And discharges one node Q to the second constant voltage GVSS2.

Although FIG. 5 shows a GIP driven in six phases, the present invention is not limited thereto, and the GIP according to the present invention can be variously configured.

As shown in FIG. 5, the GIP includes 25 transistors and 3 capacitors.

Therefore, if one unit element (transistor or capacitor) constituting the circuit of the GIP is dispersedly arranged in one unit pixel area, one GIP circuit for driving one gate line (scan line) can be arranged have.

FIG. 6 is a diagram showing the configuration of a display area of the display panel according to the first embodiment of the present invention, and FIG. 7 is a diagram showing more specifically two adjacent unit pixels arranged in the display area of the display panel of FIG.

6 and 7 illustrate that the unit pixel includes red (R), green (G), blue (B), and white (W) subpixels, G) and blue (B) sub-pixels.

The unit pixel region of the display region of the display panel according to the present invention includes at least three sub-pixel portions (R, G, B, W) 33, a GIP portion 31 and a GIP internal connection wiring portion 32 Respectively.

The at least three sub-pixel units R, G, B, and W may include a plurality of data lines DL1 to DLm, a plurality of reference voltage lines Vref, and first and second constant voltage lines EVDD and EVDD, Are arranged in the vertical direction and a plurality of gate lines (scan lines) are arranged in the horizontal direction.

The GIP unit 31 corresponds to one unit element (transistor or capacitor) constituting a GIP circuit. In other words, one unit element (transistor) constituting the GIP circuit shown in Fig. 5 is formed in the unit pixel region composed of the red (R), green (G), blue (B) Or capacitors) are distributed and arranged.

That is, one GIP for driving one gate line (scan line) is dispersedly disposed in a plurality of unit pixel regions driven by the corresponding gate line (scan line).

Of course, a GIP for driving one gate line (scan line) may be distributed and arranged in a plurality of unit pixel regions driven by two or more gate lines (scan lines).

If one GIP is arranged, elements (transistors or capacitors) constituting the GIP are dispersed in a plurality of unit pixel regions in the middle of a plurality of unit pixel regions driven by the corresponding gate line (scan line) .

If two GIPs for driving one gate line (scan line) are arranged, a plurality of unit pixel regions on both edge portions of a plurality of unit pixels driven by the corresponding gate line (scan line) It is preferable to dispersively arrange the elements (transistors or capacitors) constituting the GIP.

Although FIGS. 6 and 7 illustrate that the GIP unit 31 is disposed in all the unit pixel regions, the present invention is not limited thereto, and the GIP unit 31 may not be disposed in some unit pixel regions.

As shown in FIG. 5, the GIP internal connection wiring portion 32 is an area in which connection wirings (Q node, QB node, device and device connection line, etc.) for connecting the respective elements of the GIP are arranged.

In addition, the arrangement positions of the at least three sub-pixel units 33, the GIP unit 31, and the GIP internal connection wiring unit 32 can be varied.

8A to 8D are explanatory diagrams showing the arrangement positions of the GIP units according to the present invention.

That is, as shown in FIG. 8A, the GIP unit 31 can be disposed on the upper side of the GIP internal connection wiring unit 32 and on the right side of at least three sub-pixel units 33 of the unit.

The GIP portion 31 may be disposed on the upper side of the GIP internal connection wiring portion 32 and on the left side of the at least three sub-pixel portions 33, as shown in FIG. 8B.

The GIP unit 31 may be disposed between the GIP internal connection wiring unit 32 and the at least three sub-pixel units 33, as shown in FIG. 8C.

8D, the GIP unit 31 may be disposed below the GIP internal connection wiring unit 32, which is opposite to the at least three sub-pixel units 33. As shown in FIG.

On the other hand, when the respective elements of the GIP are arranged in the display area by function, the wiring of the GIP internal connection wiring part 32 can be simplified.

FIG. 9 is an explanatory view showing an arrangement state of GIP devices according to the present invention.

5, the circuit of the GIP according to the present invention includes first and second node (Q, Qb) control sections 21, 26 for the blank section, first to third node control sections 23, 25 An inverter unit 24, an output buffer unit 27, and a reset unit 22. The inverter unit 24 includes an output buffer unit 27,

The output buffer unit 27 includes a carry pulse output buffer unit including the pull-up transistor T6cr and the pull-down transistor T7cr and outputting a carry pulse CP (k) And a scan pulse output buffer unit composed of the pull-down transistor T7 and the bootstrapping capacitor C3 and outputting the scan pulse SP (k).

Therefore, in disposing the elements of the GIP in the display area, the scan pulse output buffer units T6, T7, and C3 of the output buffer unit 27 are arranged first, The control section 21 and 26 of the blank section and the first and second nodes Q and Qb of the blank section and the carry pulse output buffer sections T6cr and T7cr of the output buffer section 27, The wiring of the GIP internal connection wiring part 32 can be simplified by disposing the driving section in the order of the first to third node control parts 23 and 25 and the reset part 22 in this order.

In addition, as described above, when the elements of the GIP are arranged in the display region, the transistor T6 constituting the scan pulse output buffer portion of the output buffer portion 27 among the elements of the GIP, A relatively large width is required.

That is, the transistor T6 constituting the scan pulse output buffer unit must output the scan pulse output clock signal SCCLK with a minimum delay time when outputting the scan pulse SCCLK as a scan pulse. Therefore, the width of the transistor T6 constituting the scan pulse output buffer unit is relatively larger than the width of the other transistors.

For the same reason, the transistors T1 of the first through third node control sections 23 of the driving period are required to have a relatively larger width than the other transistors.

As described above, the width of the transistor T6 constituting the scan pulse output buffer unit and the width of the transistor T1 of the first through third node control units 23 in the driving period should be designed to be relatively larger than the widths of the other transistors , The transistor unit T6 constituting the scan pulse output buffer unit can not be arranged in one unit pixel region since the unit pixel region is limited. Therefore, the transistor T6 constituting the scan pulse output buffer section and the transistor T1 of the first through third node control sections 23 of the drive section are divided into a plurality of devices in parallel spreading), so that a large-sized thin film transistor can be arranged in a limited unit pixel region.

10 is an explanatory view showing the arrangement state of thin film transistors having a large size among the GIP devices according to the present invention.

In FIG. 10, the transistors T6 constituting the scan pulse output buffer section are divided and arranged in the horizontal direction in a spreading manner. The transistors T1 of the first to third node control units 23 of the driving period may be divided and arranged in the horizontal direction in the same manner.

That is, as shown in FIG. 10, the transistor T6 constituting the scan pulse output buffer section can be divided into four unit pixel regions and arranged in the horizontal direction in a spreading manner.

The transistors T6 constituting the scan pulse output buffer section and the transistors T1 of the first through third node control sections 23 of the drive section as well as the thin film transistors having other large sizes And can be arranged in the horizontal direction in a spreading manner. Further, even if the wiring width needs to be increased in order to reduce drop and rising of signals required for GIP driving in the display panel, it is possible to arrange them separately for each unit pixel region.

As described above, since the elements constituting the GIP are arranged in a unit pixel and at least one GIP is disposed in one scan line, the left and right bezels of the display panel can be minimized.

In FIGS. 6 to 10, at least one GIP is arranged in one scan line in the display area.

As shown in FIG. 3, the data driving circuit includes a plurality of source drive ICs (SIC). In FIG. 3, six source drive ICs are shown.

Thus, in another embodiment, a GIP can be placed along each scan line for each source drive IC (SIC).

11 is a view showing the configuration of a display area of a display panel according to a second embodiment of the present invention.

Referring to FIG. 11, the OLED display according to the second embodiment of the present invention includes a display panel PNL and a driving circuit for providing image data to the display panel PNL.

The display area AA of the display panel PNL includes a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, And a plurality of sub-pixels arranged in a matrix form by the plurality of gate lines GL1 to GLn. A touch sensor may further be disposed in the display area AA of the display panel PNL.

The plurality of sub-pixels may include red (R), green (G), and blue (B) sub-pixels for color implementation and the red (R), green (G), and blue (W) sub-pixel in addition to the pixels.

The red (R), green (G), and blue (B) subpixels constitute one unit pixel or the red (R), green Constitute one unit pixel.

In addition, elements (TFT, capacitor, etc.) constituting the GIP of the gate driving circuit are distributedly arranged in the unit pixel regions.

More specifically, it is as follows.

The driving circuit includes a data driving circuit for supplying a video data voltage to the data lines DL1 to DLm of the display panel PNL and a scan pulse synchronized with the video data voltage to gate lines A timing controller (see T-CON in FIG. 3) for controlling the operation timings of the data driving circuit and the gate driving circuit, and the like.

The data driving circuit includes a plurality of source drive ICs (SIC1 to SIC6). In FIG. 11, the data driving circuit includes six source drive ICs (SIC1 to SIC6).

Therefore, the six source drive ICs (SIC1 to SIC6) are respectively mounted on six COFs (Chip on Film), and the respective COFs are connected to the pad region of the lower substrate SUBS1 of the display panel (PNL) Source PCB (SPCB). The input pins of the COFs are electrically connected to the output terminals (pads) of the source PCB (SPCB), and the output pins of the source COFs (COF) are connected to the substrate of the display panel And are electrically connected to the formed data pads.

The gate driving circuit receives the start pulse VST, the clock signals CRCLK and SCCLK, the gate high voltage VGH and the gate low voltage VGL from the timing controller and outputs the gate pulses to the gate lines GL1 to GLn And a plurality of GIPs sequentially outputting scan pulses.

The plurality of GIPs sequentially supply scan pulses synchronized with the data voltages to the gate lines GL1 to GLn under the control of the timing controller to select one line of pixels to which the image data voltage is applied.

Here, the plurality of GIPs are divided into the plurality of source drive ICs (SIC1 to SIC6), and each of the source drive ICs (SIC1 to SIC6) has at least one GIP in a plurality of unit pixel regions of each gate line (TFT, capacitor, etc.) are distributed and arranged.

That is, one GIP block having a plurality of GIPs is arranged for each display region driven by each source drive IC (SIC1, SIC2, SIC3, SIC4, SIC5, SIC6). At this time, elements (TFT, capacitor, etc.) constituting a GIP are distributedly arranged in a plurality of unit pixel regions of each of a plurality of gate lines (scan lines) of each block.

For example, if the display panel is a UHD (3840 * 2160) model, 2160 GIPs are arranged for each display region driven by each source drive IC (SIC1, SIC2, SIC3, SIC4, SIC5, SIC6).

In addition, as mentioned above, the GIPs are arranged by the display regions driven by the source drive ICs (SIC1 to SIC6), and a plurality of unit pixel regions arranged in each gate line (scan line) Two or more GIPs may be deployed.

Therefore, a configuration in which GIPs are arranged for each display region driven by each of the source drive ICs (SIC1 to SIC6), and elements (TFTs, capacitors, etc.) constituting a GIP are distributed and arranged in a unit pixel region, G, B, and W, a GIP 31, and a GIP internal connection wiring portion 32, as described with reference to FIG.

In addition, the GIPs are divided according to the display regions driven by the source drive ICs SIC1 to SIC6, and the at least three sub-pixel portions (R, G, B, and W), the GIP portion 31, The arrangement positions of the GIP internal connection wiring portions 32 can be variously arranged as described in FIGS. 8A to 8D.

9, the scan pulse output buffer unit T6 (T6) of the output buffer unit 27 is connected to the scan pulse output buffer unit T6 The first and second nodes Q and Qb of the blank section 21 and 26 and the output buffer section 27 of the output buffer section 27, The pulse output buffer units T6cr and T7cr, the first to third node control units 23 and 25 and the reset unit 22 are arranged in this order to simplify the wiring of the GIP internal connection wiring unit 32 .

In addition, the GIPs are divided according to the display regions driven by the respective source drive ICs (SIC1 to SIC6). As described with reference to FIG. 10, the devices requiring a relatively large width are divided into parallel spreading), so that a large-sized thin film transistor can be arranged in a limited unit pixel region.

In addition, the GIPs are divided according to the display areas driven by the respective source drive ICs (SIC1 to SIC6), and the GIPs arranged in the same gate line (scan line) for each source drive IC (SIC1 to SIC6) Is driven by a carry pulse (CRCLK) for pulse output and a scan pulse (SCCLK) for outputting the same scan pulse, and simultaneously outputs a carry pulse and a scan pulse.

Although the GIPs are divided into the display areas driven by the respective source drive ICs SIC1 to SIC6, the gate lines (scan lines) are divided into the display areas driven by the respective source drive ICs (SIC1 to SIC6) And may be integrally formed in a display region driven by each of the source drive ICs SIC1 to SIC6.

Each of the source drive ICs (SIC1 to SIC6) not only supplies data voltages and various power supplies for driving pixels, but also carries out carry-pulse output driving for driving GIP when the GIP is a 6-phase GIP for each GIP group The scan signals SCCLK1 to SCCLK6 for the scan pulses, the power supply signals GVDD, GVSS0, GVSS1 and GVSS2, the start signal VST, the reset signals RESET and RST, and the line selection signals LSP To the GIP unit 31 and the GIP internal connection wiring unit 32.

11, at least one GIP block is arranged in a display area driven by one source drive IC (SIC1, SIC2, SIC3, SIC4, SIC5, or SIC6). However, One GIP block can be arranged in the display area driven by the source drive ICs (SIC1 and SIC2, SIC3 and SIC4, or SIC5 and SIC6), and three adjacent source drive ICs (SIC1 to SIC3, or SIC4 to SIC6) One GIP block may be arranged in the display area driven by the GIP block.

Meanwhile, as described above, when at least one GIP for driving one gate line (scan line) is dispersed and arranged in a plurality of unit pixel regions driven by the corresponding gate line (scan line), the GIP portion The unit pixel in which the GIP unit 31 is arranged and the unit pixel in which the GIP unit 31 is not arranged exist.

There is a difference in the number of wirings disposed in the GIP internal connection wiring portion 32 in accordance with the elements of the GIP portion 31. [

As described above, depending on the difference between the unit pixel in which the GIP unit 31 is arranged and the unit pixel in which the GIP unit 31 is not arranged and the number of wiring lines arranged in the GIP internal connection wiring unit 32, And the design deviation of the display device during non-operation can be recognized.

In order to prevent such a problem, a dummy GIP unit may be disposed in a unit pixel in which the GIP unit 31 is not disposed, and a dummy wiring may be disposed in the GIP internal connection wiring unit 32. [

A method of arranging the dummy GIP portion and the dummy wiring in this way will be described in more detail as follows.

12A is a configuration diagram of a unit pixel in which a GIP unit is arranged in a display panel according to the present invention, and FIG. 12B is a configuration diagram of a unit pixel in which a GIP unit is not arranged in a display panel according to the present invention.

As described with reference to FIG. 5, one GIP for driving one gate line includes 25 transistors and three capacitors, and the number of unit pixels driven by one gate line corresponds to the number of GIPs 12A, the GIP unit 31 may be arranged in a unit pixel, and as shown in FIG. 12B, a unit pixel may be provided with a plurality of pixels The GIP unit may not be disposed.

12A, even if the GIP unit 31 is arranged in the unit pixel, the number of wiring lines arranged in the GIP internal connection wiring unit 32 in accordance with the element of the GIP unit 31 arranged in the unit pixel .

As described above, there is a difference in reflectivity and transmittance between the GIP unit 31 and the GIP internal connection wiring unit 32 depending on the unit pixel. Therefore, a design deviation may occur when the display panel is not driven, and the image quality may deteriorate due to the design deviation.

That is, as shown in FIG. 12B, if the GIP unit is not arranged in any unit pixel, the unit pixel in which the GIP unit is not disposed is formed to have a smaller metal layer than the unit pixel in which the GIP unit is disposed. Therefore, the unit pixel in which the GIP unit is not disposed has a lower reflectivity than the unit pixel in which the GIP unit is disposed.

Similarly, when the number of wirings disposed in the GIP internal connection wiring portion 32 of any unit pixel is smaller than the number of wirings arranged in the GIP internal connection wiring portion 32 of another unit pixel, The reflectivity of the other unit pixel is lowered.

In order to solve such problems, the present invention arranges a dummy GIP unit in a unit pixel in which a GIP unit is not arranged, and a dummy wiring in a GIP internal connecting wiring unit of a unit pixel in which the wiring is relatively small.

13 is a view showing a configuration in which a dummy GIP unit is arranged in a unit pixel in which a GIP unit is not arranged in a display panel according to the present invention and a dummy wiring is arranged in a GIP internal connection wiring unit of a unit pixel having a relatively small number of wirings.

As shown in Fig. 13, in a display panel in which a GIP for supplying a scan signal to a gate line is embedded in a display area, a dummy GIP unit (not shown) is formed in a unit pixel in which a GIP unit corresponding to one of the elements constituting the GIP is not arranged 34).

The dummy GIP unit 34 is formed by using a material used in an OLED display panel process, irrespective of elements constituting the GIP.

That is, the dummy GIP unit 34 may have the same structure as that of the GIP unit 31, or may have a structure different from that of the GIP unit 31.

The dummy GIP section 34 is preferably formed by patterning a metal layer in the structure of the OLED display panel so as to have the same reflectivity and transmittance as the unit pixel in which the GIP section 31 is disposed.

For reference, the OLED display panel has a structure in which three metal layers (a light-shielding metal pattern, a gate electrode pattern, and a source / drain electrode pattern) are stacked.

12A, 12B and 13, reference numerals not shown are a data line Data, a reference voltage line Ref, a power supply line EVDD of a pixel, and a GIP signal line GIP S / L.

The cross-sectional structure of the GIP unit 31 and the dummy GIP unit 34 will be described in more detail as follows.

FIG. 14 is a cross-sectional view of the GIP portion in the display panel according to the present invention shown in FIG. 12A.

5, assuming that a thin film transistor is formed in an arbitrary unit pixel, a light shielding metal pattern 3 is formed on a glass substrate 1 as shown in Fig. 14, A buffer layer (2) is formed on the entire surface of the substrate (1) including the light shielding metal pattern (3). The light shielding metal pattern 3 is used as the GIP signal line (GIP S / L) in Figs. 12A, 12B and 13.

An active layer 4 is formed on the buffer layer 2 and a gate insulating film 5 and a gate electrode 6 are formed on a predetermined region of the active layer 4. An interlayer insulating film 7 is formed on the entire surface of the substrate including the gate electrode 6 and source and drain electrodes 8 and 9 are formed on the interlayer insulating film 7.

The source / drain electrodes 8 and 9 are electrically connected to a source / drain region of the active layer 4 through a contact hole formed in the interlayer insulating film 7.

Also, the dummy GIP section 34 described with reference to FIG. 12B may be formed in the same structure as the GIP section 31, as shown in FIG.

In the dummy GIP section 34, the active layer 4 may not be formed in the GIP section 31 as shown in FIG.

Meanwhile, the dummy GIP unit 34 may have a structure different from that of the GIP unit 31.

15 is a structural cross-sectional view of a dummy GIP portion according to the first embodiment of the display panel of the present invention.

The dummy GIP portion according to the first embodiment of the present invention is formed by forming a light shielding metal pattern 13 used as the GIP signal line (GIP S / L) on a glass substrate 11 And a buffer layer 12 is formed on the entire surface of the substrate 11 including the light shielding metal pattern 13. [

An active layer pattern 14 is formed on the buffer layer 12 and a gate insulating film pattern 15 and a gate electrode pattern 16 are formed on a predetermined region of the active layer pattern 14. An interlayer insulating film 17 is formed on the entire surface of the substrate including the gate electrode pattern 16 and source and drain electrode patterns 18 and 19 are formed on the interlayer insulating film 17.

The source / drain electrode patterns 18 and 19 are not electrically connected to the active layer pattern 14.

Although the active layer pattern 14 is illustrated in FIG. 15, the active layer pattern 14 may not be formed.

That is, the gate electrode pattern 16 and the source / drain electrode patterns 18 and 19 are formed to have the same structure as that of the thin film transistor.

16 is a structural cross-sectional view of the dummy GIP portion according to the second embodiment in the display panel of the present invention.

The dummy GIP portion according to the second embodiment of the present invention is formed by forming a light shielding metal pattern 13 used as the GIP signal line (GIP S / L) on a glass substrate 11 And two light shielding metal patterns 13a and 13b are further formed on the dummy GIP section 34 and a buffer layer 12 is formed on the entire surface of the substrate 11 including the light shielding metal patterns 13 and 13a and 13b. Is formed. The two light-shielding metal patterns 13a and 13b are formed at positions corresponding to the source / drain electrodes 8 and 9 described with reference to FIG.

An active layer pattern 14 is formed on the buffer layer 12 and a gate insulating film pattern 15 and a gate electrode pattern 16 are formed on a predetermined region of the active layer pattern 14. An interlayer insulating film 17 is formed on the entire surface of the substrate including the gate electrode pattern 16.

Similarly, although the active layer pattern 14 is shown in FIG. 16, the active layer pattern 14 may not be formed.

That is, the gate electrode pattern 16 and the two shielding metal patterns 13a and 13b are formed to have the same structure as that of the thin film transistor.

17 is a structural cross-sectional view of a dummy GIP portion according to the third embodiment in the display panel of the present invention.

The dummy GIP unit according to the third embodiment of the present invention is formed by forming a light shielding metal pattern 13 used as the GIP signal line (GIP S / L) on a glass substrate 11 And a buffer layer 12 is formed on the entire surface of the substrate 11 including the light shielding metal pattern 13. [

An active layer pattern 14 is formed on the buffer layer 12 and three gate insulating film patterns 15 and three gate electrode patterns 16 are formed on a predetermined region of the active layer pattern 14.

The two gate insulating film patterns 15 and the two gate electrode patterns 16 formed on both sides of the three gate insulating film patterns 15 and the three gate electrode patterns 16 are the same as the source / Drain electrodes 8 and 9, respectively.

An interlayer insulating film 17 is formed on the entire surface of the substrate including the gate electrode pattern 16.

Similarly, although the active layer pattern 14 is illustrated in FIG. 17, the active layer pattern 14 may not be formed.

That is, the gate electrode patterns 16 are formed to have the same structure as that of the thin film transistors.

The dummy GIP unit according to the present invention is not limited to the embodiments described with reference to Figs. 15 to 17, but may be applied to various combinations of three metal layers (light-shielding metal pattern, gate electrode pattern, and source / drain electrode pattern) .

For example, the dummy GIP portion may be formed by a combination of one source or drain electrode pattern (18 or 19), one gate electrode pattern (16), and one light shielding metal pattern (13a or 13b) The source and drain electrode patterns 18 and 19 and the two gate electrode patterns 16 can be formed by a combination of one source or drain electrode pattern 18 and 19 and two gate electrode patterns 16, , 13b), and can be formed by a combination of three source or drain electrode patterns (18 or 19).

The dummy GIP portion may be formed by a combination of the source / drain electrode patterns 18 and 19 and one light-shielding metal pattern 13a or 13b, And a combination of two gate electrode patterns 16 and one light-shielding metal pattern 13a or 13b) can be formed.

12A to 17, a dummy GIP unit is arranged in the unit pixel in which the GIP unit 31 is not arranged, and the dummy wiring is arranged in the GIP internal connection wiring unit 32, It is possible to prevent the design deviation from being recognized.

On the other hand, in the present invention, the GIP of the gate driving circuit is arranged in the pixel array, and various GIP signals are supplied from the outside in order to drive the GIP of the gate driving circuit.

5, a line selection signal LSP is applied to the gate electrodes of the transistors TA of the control sections 21 and 26 of the blank section first and second node Q and Qb, And a real time compensation signal VRT is supplied to the gate electrode of the transistor T5A of the first and second node Q and Qb control sections 21 and 26 of the blank section.

One of the clock signals CRCLK (k) and the plurality of scan pulse output clock signals among the plurality of carry pulse output clock signals is supplied to the source electrodes of the pull-up transistors T6cr and T6 of the output buffer unit 27 The reset signal RST is supplied to the gate electrodes of the transistors T3nB and T3nC of the reset unit 22. The clock signal SCCLK

The power source voltage GVDD is supplied to the source electrodes of the transistors T3qA, T1B, T3q and T4 and the drain electrodes of the transistors T3nC, T3nA, T3A, T5qT4q, T5 and T5B and the pulldown transistors T7cr And T7 are supplied with the ground voltages GVSS0, GVSS1 and GVSS2.

Therefore, the transistor TA, the transistor T5A, the pull-up transistors T6cr and T6, the transistors T3nB and T3nC, and the transistors T3qA The transistors T3nC, T3nA, T3A, T5qT4q, T5 and T5B and the pull-down transistors T7cr and T7 are arranged in the GIP signal line GIP S / L).

The signals such as the line selection signal LSP, the real-time compensation signal VRT, the reset signal RST, the power supply voltage GVDD and the ground voltages GVSS0, GVSS1 and GVSS2 are low in frequency , The carry pulse output clock signal and the scan pulse output clock signal are relatively high voltage and have a very high frequency.

Therefore, an abnormal light emission phenomenon may occur along the GIP signal line (GIP S / L) to which the carry pulse output clock signal and the scan pulse output clock signal are applied, resulting in low gradation light generation.

The present invention is intended to prevent a light emission phenomenon that may occur along the GIP signal line (GIP S / L) to which the carry pulse output clock signal and the scan pulse output clock signal are applied.

This will be described in detail as follows.

18 is a structural cross-sectional view of a GIP signal line (GIP S / L) to which a carry pulse output clock signal or a scan pulse output clock signal according to the first embodiment is applied in the OLED display panel of the present invention.

A GIP signal line 41 to which a clock pulse for outputting a carry pulse or a clock pulse for outputting a scan pulse is applied is formed on the glass substrate 40. The GIP signal line 41 for the carry pulse output, A buffer layer 42 is formed on the entire surface of the substrate 40 including the GIP signal line 41 to which the clock signal for pulse output is applied.

An interlayer insulating film 43 and a protective layer 44 are sequentially formed on the buffer layer 42.

Although not shown in the drawing, an active layer, a gate insulating film, and a gate electrode are formed on the buffer layer 42 in the sub pixel area and the GIP area 31, A pixel circuit for driving an organic light emitting diode as shown in FIG. 4 is formed in each sub-pixel region, and each GIP portion 31 of each unit pixel is formed with a source / drain electrode on the interlayer insulating film 43, An element constituting the GIP is formed (see Fig. 14).

The R, G, and B color filter layers 45R, 45B, and 45G are stacked on the protective layer 44. [ The order of lamination of the R, G, and B color filter layers 45R, 45B, and 45G is not greatly affected.

Of course, only the R color filter layer 45R, the G color filter layer 45G, and the B color filter layer 45B are formed in each of the R, G, and B sub-pixels shown in FIG.

The overcoat layer 46, the bank layer 47, the light emitting layer 48 and the second electrode (cathode electrode) 49 of the light emitting element are sequentially formed on the R, G, and B color filter layers 45R, 45B, .

Of course, although not shown in the drawing, the bank layer 47 is selectively removed in each sub pixel region, and the first electrode (not shown) is formed on the overcoat layer 46 so as to be connected to the drain electrode of the thin film transistor An anode electrode) is formed on the first electrode, and the light emitting layer 48 is formed on the first electrode.

In another embodiment, a black bank layer capable of blocking light from the bank layer 47 without stacking the R, G, and B color filter layers 45R, 45B, and 45G can be used.

19 is a structural cross-sectional view of a GIP signal line (GIP S / L) to which a carry pulse output clock signal or a scan pulse output clock signal according to the second embodiment is applied in the OLED display panel of the present invention.

A GIP signal line 41 to which a clock pulse for outputting a carry pulse or a clock pulse for outputting a scan pulse is applied is formed on the glass substrate 40. The GIP signal line 41 for the carry pulse output, A buffer layer 42 is formed on the entire surface of the substrate 40 including the GIP signal line 41 to which the clock signal for pulse output is applied.

An interlayer insulating film 43 and a protective layer 44 are sequentially formed on the buffer layer 42.

Although not shown in the drawing, an active layer, a gate insulating film, and a gate electrode are formed on the buffer layer 42 in the sub pixel area and the GIP area 31, A pixel circuit for driving an organic light emitting diode as shown in FIG. 4 is formed in each sub-pixel region, and each GIP portion 31 of each unit pixel is formed with a source / drain electrode on the interlayer insulating film 43, An element constituting the GIP is formed (see Fig. 14).

An overcoat layer 46 is formed on the protective layer 44 and a black bank layer 47a is formed on the overcoat layer 46. A black bank layer 47a is formed on the black bank layer 47a, A light emitting layer 48 and a second electrode (cathode electrode) 49 of the light emitting element are formed in order.

Similarly, although not shown in the drawing, the black bank layer 47a is selectively removed in each sub pixel region, and the first electrode (not shown) is formed on the overcoat layer 46 so as to be connected to the drain electrode of the thin film transistor (Anode electrode) is formed, and the light emitting layer 48 is formed on the first electrode.

On the other hand, not only the GIP signal line (GIP S / L) to which the carry pulse output clock signal and the scan pulse output clock signal are applied, but also the GIP signal line Since a high voltage of a relatively high frequency is applied to the node Q and the second node Qb, the first node Q and the second node Q2 of the wirings disposed in the GIP internal connection wiring portion 32 of the unit pixel, An abnormal light emission phenomenon may occur even at the node Qb, and low-level light emission phenomenon may occur.

As described above, the present invention is intended to prevent a light emission phenomenon that may be caused by the first node (Q) and the second node (Qb).

This will be described in detail as follows.

20 is a structural cross-sectional view of a first node (Q) and a second node (Qb) according to the first embodiment in the OLED display panel of the present invention.

A buffer layer 42 is formed on the glass substrate 40 and an interlayer insulating film 43 is formed on the buffer layer 42. A first node Q and a second node Qb 50 are formed on the interlayer insulating layer 43 and the substrate including the first node Q and the second node Qb 50 And a protective layer 44 is formed on the entire surface.

Although not shown in the drawing, an active layer, a gate insulating film, and a gate electrode are formed on the buffer layer 42 in the sub pixel area and the GIP area 31, A pixel circuit for driving an organic light emitting diode as shown in FIG. 4 is formed in each sub-pixel region, and each GIP portion 31 of each unit pixel is formed with a source / drain electrode on the interlayer insulating film 43, An element constituting the GIP is formed (see Fig. 14).

The R, G, and B color filter layers 45R, 45B, and 45G are stacked on the protective layer 44. [ The order of lamination of the R, G, and B color filter layers 45R, 45B, and 45G is not greatly affected.

Of course, only the R color filter layer 45R, the G color filter layer 45G, and the B color filter layer 45B are formed in each of the R, G, and B sub-pixels shown in FIG.

The overcoat layer 46, the bank layer 47, the light emitting layer 48 and the second electrode (cathode electrode) 49 of the light emitting element are sequentially formed on the R, G, and B color filter layers 45R, 45B, .

Although not shown in the figure, in each sub pixel region, the bank layer 47 is selectively removed, and the first electrode (the anode electrode) is formed on the overcoat layer 46 so as to be connected to the drain electrode of the thin film transistor And the light emitting layer 48 is formed on the first electrode.

In another embodiment, a black bank layer capable of blocking light from the bank layer 47 without stacking the R, G, and B color filter layers 45R, 45B, and 45G can be used.

21 is a structural cross-sectional view of a first node (Q) and a second node (Qb) according to the second embodiment in the OLED display panel of the present invention.

A buffer layer 42 is formed on the glass substrate 40 and an interlayer insulating film 43 is formed on the buffer layer 42. A first node Q and a second node Qb 50 are formed on the interlayer insulating layer 43 and the substrate including the first node Q and the second node Qb 50 And a protective layer 44 is formed on the entire surface.

An interlayer insulating film 43 and a protective layer 44 are sequentially formed on the buffer layer 42.

Although not shown in the drawing, an active layer, a gate insulating film, and a gate electrode are formed on the buffer layer 42 in the sub pixel area and the GIP area 31, A pixel circuit for driving an organic light emitting diode as shown in FIG. 4 is formed in each sub-pixel region, and each GIP portion 31 of each unit pixel is formed with a source / drain electrode on the interlayer insulating film 43, An element constituting the GIP is formed (see Fig. 14).

An overcoat layer 46 is formed on the protective layer 44 and a black bank layer 47a is formed on the overcoat layer 46. A black bank layer 47a is formed on the black bank layer 47a, A light emitting layer 48 and a second electrode (cathode electrode) 49 of the light emitting element are formed in order.

Similarly, although not shown in the drawing, the black bank layer 47a is selectively removed in each sub pixel region, and the first electrode (not shown) is formed on the overcoat layer 46 so as to be connected to the drain electrode of the thin film transistor (Anode electrode) is formed, and the light emitting layer 48 is formed on the first electrode.

As described with reference to FIGS. 18 and 21, the GIP signal line (GIP S / L) to which the carry pulse output clock signal and the scan pulse output clock signal are applied or the Q The GIP signal line (GIP S / L) to which the carry pulse output clock signal or the scan pulse output clock signal is applied, and the GIP signal line (GIP S / L) to which the carry pulse output clock signal or the scan pulse output clock signal is applied, Even if an abnormal light emission phenomenon occurs by the Q node or the Qb node, the low gradation light emission phenomenon can be prevented.

In FIGS. 18 to 21, R, G, and G are shown only on the GIP signal line (GIP S / L) to which the carry pulse output clock signal or the scan pulse output clock signal is applied and the Q- (GIP S / L) and the GIP internal connection wiring portion 32 are formed on the mode wirings R, G, and B, respectively. However, the present invention is not limited to this, , A B color filter layer may be laminated or a black bank layer may be formed.

18 and 20, three color filter layers are stacked on the GIP signal line (GIP S / L), the Q node or the Qb node. However, the present invention is not limited thereto. Layer may be stacked.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

PNL: Display panel SIC1 to SIC: Source drive IC
1, 11, 40: glass substrate 2, 12, 42: buffer layer
3, 13: shielding metal pattern 4, 14: active layer
5, 15: gate insulating film 6: gate electrode
7, 17, 43: interlayer insulating film 8, 9: source / drain electrode
16: gate electrode pattern 18, 19: source / drain electrode pattern
21, 26: the first and second nodes (Q, Qb)
22: reset section 24: inverter section
23, 25: Driving section The first to third node control sections
27: output buffer unit 31: GIP circuit unit
32: GIP internal connection wiring portion 33: Sub-pixel portion
41: GIP signal line 44: protective film
45R, 45G, 45B: color filter layer 46: overcoat layer
47: bank layer 47a: black bank layer
48: light emitting layer 49: second electrode
50: Q node or Qb node

Claims (28)

A display region including data lines and gate lines intersecting each other and including sub pixels arranged at the intersections; And
And a plurality of GIPs distributed in the unit pixel regions driven by the gate lines in the display region and supplying scan pulses to the gate lines,
One element constituting the GIP is disposed in one unit pixel region,
Wherein the unit pixel region includes at least three sub-pixel portions, a GIP portion in which one element constituting the GIP is disposed, and a GIP internal connection wiring portion in which connection wirings connecting the elements of the GIP are arranged,
The GIP portion is disposed on the upper side of the GIP internal connection wiring portion and on the right side of the at least three sub-pixel portions,
Wherein the GIP unit is disposed on the upper side of the GIP internal connection wiring unit and on the left side of the at least three sub pixel units. The method according to claim 1,
And at least one GIP is distributed and arranged in unit pixel regions driven by the gate lines. The method according to claim 1,
The GIP,
A blank section for selectively storing a set signal according to a line selection signal and charging the first node to a first constant voltage and discharging a second node to a second constant voltage in accordance with a signal for real- A second node controller,
The stage is charged with the carry pulse voltage of the previous stage in accordance with the carry pulse of the previous stage in the driving period and the first node and the third node are discharged to the second constant voltage in accordance with the carry pulse of the following stage, A first node controller for charging the third node to the first constant voltage according to a voltage of the first node,
An inverter unit for inverting the voltage of the first node and applying the inverted voltage to the second node,
An output for receiving one clock signal among a plurality of carry pulse output clock signals and one clock signal for a plurality of scan pulse output signals and outputting a carry pulse and a scan pulse according to the voltages of the first node and the second node; A buffer unit,
And a reset unit for discharging the first node to a second constant voltage in accordance with a reset signal output from the timing controller in the blank interval,
The scan pulse output buffer unit of the output buffer unit, the inverter unit, the blank interval first and second node control units, the carry pulse output buffer unit of the output buffer unit, the drive period first through third node control units, OLED display panel. The method according to claim 1,
Wherein at least one of the elements constituting the GIP is divided and arranged in parallel in a plurality of unit pixel regions along a direction of the gate line. The method according to claim 1,
And the touch sensors are further disposed in the display area. A display region including a plurality of data lines and a plurality of gate lines intersecting each other and including sub-pixels arranged at the intersections;
A plurality of source drive ICs for dividing the plurality of data lines into a plurality of groups and driving data lines of each group; And
The display area is divided into groups driven by respective source drive ICs. The display areas are divided into unit pixel areas driven by gate lines in each of the divided display area groups, and a plurality of GIP,
One element constituting the GIP is disposed in one unit pixel region,
Wherein the unit pixel region includes at least three sub-pixel portions, a GIP portion in which one element constituting the GIP is disposed, and a GIP internal connection wiring portion in which connection wirings connecting the elements of the GIP are arranged,
The GIP portion is disposed on the upper side of the GIP internal connection wiring portion and on the right side of the at least three sub-pixel portions,
Wherein the GIP unit is disposed on the upper side of the GIP internal connection wiring unit and on the left side of the at least three sub-pixel units. The method according to claim 6,
Wherein the display region is divided into groups driven by respective source drive ICs and at least one GIP is distributedly arranged in unit pixel regions driven by gate lines in the divided display region groups. The method according to claim 6,
The GIP,
A blank section for selectively storing a set signal according to a line selection signal and charging the first node to a first constant voltage and discharging a second node to a second constant voltage in accordance with a signal for real- A second node controller,
The stage is charged with the carry pulse voltage of the previous stage in accordance with the carry pulse of the previous stage in the driving period and the first node and the third node are discharged to the second constant voltage in accordance with the carry pulse of the following stage, A first node controller for charging the third node to the first constant voltage according to a voltage of the first node,
An inverter unit for inverting the voltage of the first node and applying the inverted voltage to the second node,
An output for receiving one clock signal among a plurality of carry pulse output clock signals and one clock signal for a plurality of scan pulse output signals and outputting a carry pulse and a scan pulse according to the voltages of the first node and the second node; A buffer unit,
And a reset unit for discharging the first node to a second constant voltage in accordance with a reset signal output from the timing controller in the blank interval,
The scan pulse output buffer unit of the output buffer unit, the inverter unit, the blank interval first and second node control units, the carry pulse output buffer unit of the output buffer unit, the drive period first through third node control units, The OLED display comprising: The method according to claim 6,
Wherein at least one of the elements constituting the GIP is divided and arranged in parallel in a plurality of unit pixel regions along the gate line direction. The method according to claim 6,
Each source driver IC not only supplies a data voltage and various power supplies for driving pixels, but also carries a carry pulse for driving a GIP, a scan pulse for a scan pulse, a power supply, a start signal, a reset signal, An OLED display that supplies one. The method according to claim 6,
Wherein each of the gate lines is electrically independent for each display region driven by each source drive IC or integrally formed in a display region driven by each source drive IC. A display region including a plurality of data lines and a plurality of gate lines intersecting each other and including sub-pixels arranged at the intersections;
A plurality of source drive ICs for dividing the plurality of data lines into a plurality of groups and driving data lines of each group; And
The display region is divided into groups driven by two or more adjacent source drive ICs, and the gate lines are distributed in the unit pixel regions driven by the respective gate lines in the divided display region groups, and scan pulses are applied to the gate lines A plurality of GIPs to be supplied,
One element constituting the GIP is disposed in one unit pixel region,
Wherein the unit pixel region includes at least three sub-pixel portions, a GIP portion in which one element constituting the GIP is disposed, and a GIP internal connection wiring portion in which connection wirings connecting the elements of the GIP are arranged,
The GIP portion is disposed on the upper side of the GIP internal connection wiring portion and on the right side of the at least three sub-pixel portions,
Wherein the GIP unit is disposed on the upper side of the GIP internal connection wiring unit and on the left side of the at least three sub-pixel units. A display region including data lines and gate lines intersecting each other and including sub pixels arranged at the intersections; And
And a plurality of GIPs distributed in the unit pixel regions driven by the gate lines in the display region and supplying scan pulses to the gate lines,
The first unit pixel region includes at least three sub-pixel portions, a GIP portion in which one element constituting the GIP is disposed, and connection wirings connecting the elements of the GIP,
The second unit pixel region includes at least three sub-pixel portions, a dummy GIP portion, connection wirings connecting the elements of the GIP, and dummy connection wirings. 14. The method of claim 13,
Wherein the dummy GIP unit has the same structure as the GIP unit or has a different structure from the GIP unit. 14. The method of claim 13,
Wherein the dummy GIP portion is formed of a combination of a light shielding metal pattern, a gate electrode pattern, and a source / drain electrode pattern. 14. The method of claim 13,
The dummy GIP unit,
Board;
A light shielding metal pattern formed on the glass substrate;
A buffer layer formed on the entire surface of the substrate including the light-shielding metal pattern;
A gate insulating film and a gate electrode pattern formed on the buffer layer;
An interlayer insulating film formed on the entire surface of the substrate including the gate electrode; And
And a source / drain electrode pattern formed on the interlayer insulating film. 17. The method of claim 16,
The dummy GIP unit,
And an active layer formed between the buffer layer and the gate insulating layer and the gate electrode pattern. 18. The method of claim 17,
The dummy GIP unit,
And the source / drain electrode pattern is electrically connected to the active layer. 14. The method of claim 13,
The dummy GIP unit,
Board;
A first light-shielding metal pattern for GIP signal lines and two second light-shielding metal patterns formed on the substrate;
A buffer layer formed on the entire surface of the substrate including the first and second light-shielding metal patterns;
A gate insulating film and a gate electrode pattern formed on the buffer layer; And
And an interlayer insulating film formed on the entire surface of the substrate including the gate electrode pattern. 14. The method of claim 13,
The dummy GIP unit,
Board;
A shielding metal pattern for a GIP signal line formed on the substrate;
A buffer layer formed on the entire surface of the substrate including the light-shielding metal pattern;
Three gate insulating films and gate electrode patterns formed on the buffer layer; And
And an interlayer insulating film formed on the entire surface of the substrate including the three gate electrode patterns. 21. The method according to claim 19 or 20,
The dummy GIP unit,
And an active layer formed between the buffer layer and the gate insulating layer and the gate electrode pattern. A display region including data lines and gate lines intersecting each other and including sub pixels arranged at the intersections; And
And a plurality of GIPs distributed in the unit pixel regions driven by the gate lines in the display region and supplying scan pulses to the gate lines,
Wherein the unit pixel region includes at least three sub-pixel portions, a GIP portion in which one element constituting the GIP is arranged, and a GIP internal connection wiring portion connecting the elements of the GIP,
A plurality of GIP signal lines for supplying a GIP signal to the GIP unit are arranged,
And a light shielding layer for blocking light is formed on at least one GIP signal line among the GIP signal lines. 23. The method of claim 22,
Wherein the light shielding layer is formed by stacking at least two color filter layers of R, G, and B color filter layers. 23. The method of claim 22,
Wherein the light-shielding layer comprises a black bank layer. 23. The method of claim 22,
Wherein the at least one GIP signal line is applied with a carry pulse output clock signal or a scan pulse output clock signal. 23. The method of claim 22,
Wherein the GIP internal connection wiring portion includes a first node and a second node for controlling an output buffer portion of the GIP according to an applied voltage,
And a light shielding layer for blocking light is further formed on the first node or the second node. 27. The method of claim 26,
Wherein the light shielding layer is formed by stacking at least two color filter layers of R, G, and B color filter layers. 27. The method of claim 26,
Wherein the light-shielding layer comprises a black bank layer.

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