KR102467881B1 - OLED display Panel - Google Patents

Abstract

The present invention relates to an OLED display panel for arranging a GIP driving circuit in a display area to minimize a bezel and minimizing a luminance deviation between adjacent pixels, wherein data lines and scan lines intersect and are disposed at each intersection. a display area including sub-pixels; and a GIP driving circuit including a plurality of stages that are distributed in unit pixel areas within the display area and supply scan pulses to corresponding gate lines, wherein the unit pixel areas include at least three sub-pixel units, and a GIP drive circuit. A GIP unit in which one element constituting the driving circuit is disposed, and a GIP internal connection wiring unit in which connection wires connecting each element of the GIP driving circuit are disposed, and in the GIP unit, a signal for driving the GIP driving circuit is provided. A line is disposed, and one of the electrodes of the elements constituting the GIP driving circuit is disposed overlapping with the signal line.

Description

OLED display panel {OLED display Panel}

The present invention relates to an OLED display panel for reducing a luminance deviation between adjacent pixels in an OLED display panel in which a stage of a GIP driving circuit is disposed in a pixel array.

As the information society develops and various portable electronic devices such as mobile communication terminals and notebook computers develop, the demand for a flat panel display device applicable thereto is gradually increasing.

As such a flat panel display, a liquid crystal display (LCD) using a liquid crystal and an OLED display using an organic light emitting diode (OLED) are used.

These flat panel display devices are composed of a display panel having a plurality of gate lines and a plurality of data lines to display an image, and a driving circuit for driving the display panel.

Among the above display devices, a display panel of a liquid crystal display device includes a thin film transistor array substrate having a thin film transistor array formed on a glass substrate, a color filter array substrate having a color filter array formed on a glass substrate, and the thin film transistors A liquid crystal layer filled between the array substrate and the color filter array substrate is provided.

The thin film transistor array substrate includes a plurality of gate lines GL extending in a first direction and a plurality of data lines DL extending in a second direction perpendicular to the first direction, each gate line One sub-pixel area (Pixel; P) is defined by and each data line. One thin film transistor and one pixel electrode are formed in one sub-pixel region P.

In the display panel of such a liquid crystal display device, an electric field is generated in the liquid crystal layer by applying a voltage to an electric field generating electrode (a pixel electrode and a common electrode), and an arrangement state of liquid crystal molecules in the liquid crystal layer is controlled by the electric field, thereby reducing incident light. An image is displayed by controlling the polarization.

In addition, in the display panel of an OLED display device among the above display devices, sub-pixels are defined by crossing the plurality of gate lines and the plurality of data lines, and each sub-pixel has an anode and a cathode and the anode and cathode An OLED composed of an organic light emitting layer therebetween, and a pixel circuit independently driving the OLED.

The pixel circuit may be configured in various ways, but includes at least one switching TFT, a capacitor, and a driving TFT.

The at least one switching TFT charges the capacitor with a data voltage in response to a scan pulse. The driving TFT controls the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED according to the data voltage charged in the capacitor.

A display panel for such a display device is defined by an active area (AA) providing images to a user and a non-active area (NA) that is a peripheral area of the display area (AA).

In addition, the driving circuit for driving the display panel includes a gate driving circuit for sequentially supplying gate pulses (or scan pulses) to the plurality of gate lines (scan lines) of the display panel; It includes a data driving circuit supplying data voltages to a plurality of data lines, and a timing controller supplying image data and various control signals to the gate driving circuit and the data driving circuit.

The gate driving circuit may be composed of at least one gate drive IC, but in the process of forming sub-pixels with the plurality of signal lines (gate lines and data lines) of the display panel, the display panel is not displayed. can be formed simultaneously on the area.

That is, a gate-in-panel (hereinafter, referred to as “GIP driving circuit”) scheme is applied in which the gate driving circuit is directly integrated into the display panel.

1 is a block diagram showing the relationship between a driving circuit and a driving circuit of a conventional OLED display device.

Referring to FIG. 1 , the OLED display device 100 includes an OLED display panel PNL and a driving circuit for inputting data of an input image to a pixel array 110 of the OLED display panel PNL. do.

The OLED display panel PNL includes a plurality of gate lines 149 (scan lines) and a plurality of data lines 139 that are arranged to cross each other, and the plurality of gate lines 149 and the plurality of data lines 139 and a pixel array 110 in which sub-pixels in a matrix form defined by

Each of the sub-pixels includes an organic light emitting diode (OLED) composed of an anode and a cathode and an organic light emitting layer between the anode and the cathode, and a pixel circuit independently driving the OLED.

The pixel circuit may be configured in various ways, but includes at least one switching TFT, a capacitor, and a driving TFT.

The driving circuit for driving the OLED display panel PNL includes a data driving circuit 130 formed in the non-display area and supplying data voltages to a plurality of data lines 139 and a data voltage formed in the non-display area. and a Gate In Panel (GIP) driving circuit 140 for sequentially supplying a gate (scan) signal synchronized with , to a plurality of gate lines 149 , and a timing controller (TCON) 120 .

The timing controller 120 is disposed on a printed circuit board (PCB), aligns input image data received from an external host system, and supplies the data to the data driving circuit 130 . In addition, the timing controller 120 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock synchronized with an input image from the external system, and operates the data driving circuit 130 and the A control signal (Data Driver Control signal; DDC; Gate Driver Control signal; GDC) for controlling the operation timing of the GIP driving circuit 140 is generated.

The data driving circuit 130 receives input image data and a data driver control signal (DDC) from the timing controller 120, converts the input image data into a gamma compensation voltage to generate a data voltage, and generates a data voltage output to a plurality of data lines 150.

The data driving circuit 130 includes a plurality of source electrode driver ICs (Integrated Circuits), and each source electrode driver IC is composed of COF (Chip On Film) and the printed circuit board on which the timing controller 120 is mounted. It is connected between the pad part of and the pad part of the display panel PNL.

The GIP driving circuit 140 may be disposed on one edge or both edges of the display panel PNL according to the driving method. The gate driving circuit shown in FIG. 1 is an interlace type GIP driving circuit 140, and includes the first GIP driving circuit 140L disposed on the left side of the display panel PNL and the right side of the display panel PNL. and a second GIP driving circuit 140R disposed on.

The GIP driving circuit 140 may be composed of at least one gate drive IC, but the plurality of signal lines (gate lines and data lines) constituting the pixel array 110 of the OLED display panel PNL. In the process of forming the and sub-pixels, they may be simultaneously formed on the non-display area of the display panel.

The GIP driving circuit 140 sequentially supplies a gate (scan) signal to each gate line 149 according to the control signal GDC transmitted from the timing controller 120 .

The GIP driving circuit 140 as described above is configured to include a plurality of stages (hereinafter referred to as "GIP") equal to or greater than the number of gate lines in order to sequentially supply scan pulses to each gate line, and is driven. Oxide semiconductor thin film transistors are used to improve characteristics.

That is, the GIP driving circuit 140 includes a plurality of stages (GIP) connected cascadingly. Further, each stage (GIP) is connected to each gate line, receives a clock signal, a gate start signal, a gate high voltage, and a gate low voltage applied from the timing controller, and generates one carry pulse and one scan pulse. It includes an output unit that

2 is a block diagram of a general (n)th stage (GIP).

As shown in FIG. 2, each stage GIP is set by a start pulse or a carry pulse SET output from the previous stage GIP, and output from the next stage GIP. The node controller 100 is reset by the carry pulse RST to control the voltages of the first and second nodes Q and Qb, and for outputting one scan pulse among a plurality of clock signals SCCLKs for outputting scan pulses. A clock signal and one of the plurality of carry pulse output clock signals CRCLKs are received, and one scan pulse ((So (n)) and an output unit 200 outputting one carry pulse Co(n).

In the case of a stage GIP driven by a 6-phase clock signal, the node controller 100 is set by the carry pulse Co(n-3) output from the third preceding stage GIP, and It is reset by the carry pulse Co(n+3) output from the next stage GIP to control the voltages of the first and second nodes Q and Qb.

Although not shown in the drawing, the output unit 200 of the stage GIP includes a carry pulse output unit and a scan pulse output unit.

The carry pulse output unit includes a first pull-up transistor and a first pull-down connected in series between a clock signal terminal for outputting a carry pulse to which one of a plurality of clock signals for outputting a carry pulse is applied and a first gate low voltage terminal (VGL1) It is configured with a transistor.

The first pull-up transistor is turned on/off according to the voltage level of the first node (Q), and the first pull-down transistor is turned on/off according to the voltage level of the second node (Qb) to receive the input carry pulse. The output clock signal is output as a carry pulse (Co(n)).

The scan pulse output unit includes a second pull-up transistor connected in series between a clock signal terminal for outputting scan pulses to which one of a plurality of clock signals for outputting scan pulses is applied and a second gate low voltage terminal (VGL2); It is configured to include a pull-down transistor and a bootstrap capacitor connected between the gate electrode and the source electrode of the second pull-up transistor.

The second pull-up transistor is turned on/off according to the voltage level of the first node (Q), and the second pull-down transistor is turned on/off according to the voltage level of the second node (Qb) and receives the input scan pulse. The clock signal for output is output as a scan pulse (So(n)).

FIG. 3 is a waveform diagram showing the operation of the (n)th stage GIP shown in FIG. 2 .

In FIG. 3, as described above, the node controller 100 is set by the carry pulse Co(n-3) output from the third previous stage GIP, and the third subsequent stage GIP It is reset by the carry pulse Co(n+3) output from , and controls the voltages of the first and second nodes Q and Qb.

The (n)th stage GIP(n) is set by the carry pulse Co(n−3) output from the third previous stage GIP, and sets the first node Q to a gate high voltage ( VGH), and the second node Qb is discharged to the gate low voltage VGL. Accordingly, the first pull-up transistor of the carry pulse output unit and the second pull-up transistor of the scan pulse output unit are turned on, and the first pull-down transistor of the carry pulse output unit and the second pull-down transistor of the scan pulse output unit are turned off. do.

Clock signals CRCLK and SCCLK having the same phase are applied to the drain electrode of the first pull-up transistor of the carry pulse output unit and the drain electrode of the second pull-up transistor of the scan pulse output unit.

When high-level clock signals CRCLK and SCCLK are applied to the drain electrode of the first pull-up transistor and the drain electrode of the second pull-up transistor, the voltage of the first node Q floated by the bootstrap capacitor is It is bootstrapped and raised by 2VGH.

In this way, in a state where the first node Q is bootstrapped, the carry pulse output unit and the scan pulse output unit convert the input clock pulses CRCLK and SCCLK to carry pulses Co(n) and scan pulses, respectively. Output as (So(n)).

And, reset by the carry pulse Co(n+3) output from the third post stage GIP, the first node Q is in a low state, and the second node Qb is in a high state becomes Accordingly, the first pull-up transistor of the carry pulse output unit and the second pull-up transistor of the scan pulse output unit are turned off, and the first pull-down transistor of the carry pulse output unit and the second pull-down transistor of the scan pulse output unit are turned on. Then, the gate low voltage VGL is output with the carry pulse Co(n) and the scan pulse So(n).

However, in the conventional OLED display panel, since the GIP driving circuit is directly integrated in the non-display area of the display panel, it is difficult to design a narrow bezel of the display device.

An object of the present invention is to provide an OLED display panel for arranging a GIP driving circuit in a display area to minimize a bezel and minimizing a luminance deviation between adjacent pixels.

An OLED display panel according to the present invention for achieving the above object includes: a display area in which data lines and scan lines intersect and include sub-pixels disposed at each intersection; and a GIP driving circuit including a plurality of stages that are distributed in unit pixel areas within the display area and supply scan pulses to corresponding gate lines, wherein the unit pixel areas include at least three sub-pixel units, and a GIP drive circuit. A GIP unit in which one element constituting the driving circuit is disposed, and a GIP internal connection wiring unit in which connection wires connecting each element of the GIP driving circuit are disposed, and in the GIP unit, a signal for driving the GIP driving circuit is provided. The line is disposed, and one of the electrodes of the elements constituting the GIP driving circuit is disposed overlapping with the signal line.

The signal line is characterized in that it is disposed parallel to the data lines.

The signal lines include a line selection signal line, a signal line for real-time compensation, a clock signal line for outputting a carry pulse, a clock signal line for outputting a scan pulse, a reset signal line, a start pulse signal line, and constant voltage lines.

It is characterized in that one of a gate electrode, a source electrode, and a drain electrode of an element constituting the GIP driving circuit disposed in the GIP unit overlaps the signal line.

The OLED display panel according to the present invention having the above characteristics has the following effects.

That is, since elements constituting the GIP driving circuit are disposed in the GIP part so as to overlap a signal line for driving the GIP driving circuit, the area occupied by the GIP part can be reduced.

Therefore, since the area occupied by the GIP unit can be reduced, the distance between the at least three sub-pixel units and the GIP unit can be further increased, and thus the generation of capacitance between the at least three sub-pixel units and the GIP unit can be prevented. , In addition, capacitance variation between the at least three sub-pixel units and the GIP unit can be minimized and luminance variation between adjacent pixels can be prevented.

1 is a block diagram showing a driving circuit of a conventional OLED display device and the relationship between driving circuits;
2 is a block diagram of a conventional (n)th stage (GIP)
3 is a waveform diagram showing the operation of the (n)th stage (GIP) shown in FIG. 2;
4 is a circuit diagram of one sub-pixel in an OLED display panel according to an embodiment of the present invention.
5 is a circuit diagram of a (k)th stage of a GIP driving circuit according to an embodiment of the present invention.
6 is a configuration diagram of a display area of an OLED display panel according to a first embodiment of the present invention;
FIG. 7 is a configuration diagram showing two adjacent unit pixel areas disposed in the display area of the OLED display panel of FIG. 6 in more detail.
8 is a layout view of arbitrary elements constituting one stage of the GIP driving circuit formed in the GIP unit 31 according to the first embodiment of the present invention.
9 is a layout view of arbitrary elements constituting one stage of the GIP driving circuit formed in the GIP unit 31 according to the second embodiment of the present invention.
10 is a cross-sectional view taken along line II' of FIG. 9
11 is a cross-sectional view taken along line II-II' of FIG. 9

First, the present applicant has previously applied for an invention of distributing and arranging GIP driving circuits in the display area of a display panel in order to minimize the bezel of the display panel (Korean Patent Application No.: 10-2017-0125355 (filing date: 2017) September 27, 2009) reference).

The invention of the previously filed patent application (No. 10-2017-0125355) is briefly described as follows.

4 is a circuit diagram of one sub-pixel in an OLED display panel according to an embodiment of the present invention, and FIG. 5 is a circuit diagram of a (k)th stage of a GIP driving circuit according to an embodiment of the present invention.

That is, FIG. 4 corresponds to FIG. 4 of the previously filed patent application (No. 10-2017-000000), and FIG. 5 corresponds to FIG. 5 of the previously filed patent application (No. 10-2017-000000). do.

As shown in FIG. 4 , each sub-pixel of the OLED display panel according to the embodiment of the present invention includes an organic light emitting diode (OLED) and a pixel circuit that drives the organic light emitting diode.

The pixel circuit includes first and second switching TFTs (T1, T2), a storage capacitor (Cst), and a driving TFT (DT).

The first switching TFT (T1) charges the storage capacitor (Cst) with a data (DATA) voltage in response to a scan pulse (Scan). The driving TFT DT controls the amount of current supplied to the OLED according to the data voltage charged in the storage capacitor Cst to adjust the amount of light emitted from the OLED. The second switching TFT (T2) senses the threshold voltage and mobility of the driving TFT (DT) in response to a sensing signal.

The organic light emitting diode (OLED) may include a first electrode (eg, an anode electrode or a cathode electrode), an organic light emitting layer, and a second electrode (eg, a cathode electrode or an anode electrode).

The storage capacitor (Cst) is electrically connected between the gate electrode (gate) and the source electrode (source) of the driving TFT (DT), and a data voltage corresponding to the image signal voltage or a voltage corresponding thereto is supplied for one frame time. can keep you

Although FIG. 4 shows the configuration of a 3T1C sub-pixel composed of three TFTs (T1, T2, DT) and one storage capacitor (Cst), it is not limited thereto, and each sub-pixel of the OLED display panel according to the present invention is Sub-pixels such as 4T1C, 4T2C, 5T1C, and 5T2C may be provided.

On the other hand, the circuit of the (k)th stage of the GIP driving circuit according to the embodiment of the present invention, as shown in FIG. ), selectively stores the set signal CP(k) according to a line select pulse (LSP), and sets the corresponding stage to a blank time during a real-time compensation signal (VRT; The first and second nodes (Q, Qb) of the blank period in which the first node (Q) is charged to the first constant voltage (GVDD) and the second node (Qb) is discharged to the second constant voltage (GVSS2) according to vertical real time ) control units 21 and 26; It is composed of transistors T1, T1A, T3n, T3nA, T3q, T3, T3A, and T5, and the first node ( Q) is charged with the voltage of the carry pulse CP(k-3), and the first node Q and the third node Qh are charged according to the carry pulse CP(k+3) of the third stage. 2. The first to third node control units 23 and 25 in a driving period in which the third node Qh is discharged at the constant voltage GVSS2 and charged at the first constant voltage GVDD according to the voltage of the first node Q. ); an inverter unit 24 including transistors T4, T4l, T4q, and T5q and a capacitor C2 to invert the voltage of the first node Q and apply the inverted voltage to a second node Qb; It is composed of a pull-up transistor (T6cr, T6) and a pull-down transistor (T7cr, T7) and a bootstrapping capacitor (C3), and one clock signal (CRCLK(k)) among a plurality of clock signals for outputting a carry pulse and a plurality of scan signals A carry pulse CP(k) and a scan pulse SP are received according to voltages of the first node Q and the second node Qb by receiving one clock signal SCCLK(k) among clock signals for pulse output. an output buffer unit 27 outputting (k)); Further, it is configured to include transistors T3nB and T3nC, and the first node Q is connected to the second constant voltage GVSS2 according to the reset signal RST output from the timing controller during the blank time. It is configured with a resetting part 22 that discharges.

When the line select signal LSP is at a high level, the control units 21 and 26 of the first and second nodes Q and Qb in the blank period turn on the transistors TA, TB, and T3q to generate a set signal ( CP(k)) is stored in the capacitor C1.

In the blank period, when the real-time compensation signal VRT is at a high level, the transistors T1C and T5B are turned on to charge the first node Q with a first constant voltage GVDD. The second node Qb is discharged to the second constant voltage GVSS2.

In the first to third node controllers 23 and 25 during the driving period, the transistors T1, T1A and T5 are turned on when the carry pulse CP(k-3) of the third previous stage is at a high level during the driving period. -On, the first node Q is charged with the third previous stage carry pulse (CP(k-3)) voltage, and the second node Qb is discharged with the second constant voltage GVSS2. As such, when the first node Q is charged and the second node Qb is discharged, the transistor T3q is turned on to charge the third node Qh with the first constant voltage GVDD. .

Also, when the carry pulse CP(k+3) of the third stage is at a high level, the transistors T3n and T3nA are turned on to connect the first node Q and the third node Qh to the second node Qh. Discharge with constant voltage (GVSS2).

The inverter unit 24 inverts the voltage of the first node Q and applies it to the second node Qb.

In the output buffer unit 27, when the first node Q is at a high level and the second node Qb is at a low level, the pull-up transistor T6cr is turned on and the pull-down transistor T7cr is turned on. - It is turned off to output one clock signal CRCLK(k) among the plurality of carry pulse output clock signals as a carry pulse CP(k). In addition, when the first node Q is at a high level and the second node Qb is at a low level, the pull-up transistor T6 is turned on and the pull-down transistor T7 is turned off so that the plurality of scans One of the pulse output clock signals SCCLK(k) is output as the scan pulse SP(k).

At this time, when the clock signal SCCLK(k) for outputting the scan pulse is applied at a high level, the first node Q is bootstrapping by the bootstrapping capacitor C3 of the output buffer unit 27. (or coupled) to have a higher potential.

In this way, in the state where the first node Q is bootstrapped, the output buffer unit 27 outputs the clock signal CRCLK(k) for outputting the carry pulse and the clock signal SCCLK(k) for outputting the scan pulse, respectively. ) as the carry pulse CP(k) and the scan pulse SP(k), output loss can be prevented.

The reset unit 22 turns on the transistors T3nB and T3nC when the reset signal RST output from the timing controller 4 is at a high level during the blank time, 1 node (Q) is discharged to the second constant voltage (GVSS2).

Although the stage of the GIP driving circuit driven in 6 phases is shown in FIG. 5, it is not limited thereto, and the stage of the GIP driving circuit according to the present invention can be configured in various ways.

As shown in FIG. 5, each stage of the GIP driving circuit includes 25 transistors and 3 capacitors.

Therefore, if one unit element (transistor or capacitor) constituting the stage of the GIP driving circuit is distributed and arranged in one unit pixel area, one stage circuit for driving one gate line (scan line) can be arranged. can

FIG. 6 is a configuration diagram of the display area of the OLED display panel according to the first embodiment of the present invention, and FIG. 7 is a structure showing two adjacent unit pixel areas disposed in the display area of the OLED display panel of FIG. 6 in more detail. It is also

That is, FIG. 6 corresponds to FIG. 6 of the previously filed patent application (No. 10-2017-000000), and FIG. 7 corresponds to FIG. 7 of the previously filed patent application (No. 10-2017-000000). do.

6 and 7, in arranging the GIP driving circuit in the display area of the OLED display panel, the unit pixel area of the display area includes at least three sub-pixel parts (R, G, B, W) 33 ), GIP part 31, and GIP internal connection wiring part 32, etc.

The at least three sub-pixel parts R, G, B, and W 33 include a plurality of data lines DL1 to DL8, a plurality of reference voltage lines Vref, and first and second constant voltage lines EVDD and EVSS. ) are arranged in the vertical direction, and a plurality of gate lines (scan lines, SCAN) are arranged in the horizontal direction.

The GIP unit 31 corresponds to one unit element (transistor or capacitor) constituting one stage of the GIP driving circuit. That is, in the unit pixel area composed of red (R), green (G), blue (B), and white (W) sub-pixels, one unit element (transistor or capacitors) are distributed.

That is, at least one stage ST of the GIP driving circuit for driving one gate line (scan line) is disposed in a distributed manner in a plurality of unit pixel areas driven by one gate line (scan line).

And, since the GIP unit 31 corresponds to one unit element (transistor or capacitor) constituting one stage of the GIP driving circuit, the LSP and VRT as shown in FIG. 5 are included in the GIP unit 31. , GVDD, GVSS0, GVSS1, GVSS2, VST, CRCLK, and SCCLK signals are applied.

The GIP internal connection wiring unit 32 includes connection wires (Q node, Qb node, Qh node, carry pulse output terminal of the previous stage and carry pulse output terminal of the subsequent stage) connecting each element in one stage of the GIP driving circuit. This is the area where the connection line, etc.) is placed.

As such, as the GIP driving circuit is disposed in the display area, as shown in FIG. 7 , a plurality of data lines DL1 to DL1 to drive the sub-pixel parts R, G, B, and W 33. DL8), reference voltage line (Vref), constant voltage line (EVDD), as well as signal lines such as LSP, VRT, GVDD, GVSS0, GVSS1, GVSS2, VST, CRCLK, and SCCLK for driving the GIP driving circuit are arranged in a vertical direction do. That is, the signal lines are arranged parallel to the plurality of data lines DL1 to DL8 in an area adjacent to the GIP part 31 .

That is, when it is assumed that one of the transistors T3qA, T1B, T3q, and T4 T4l shown in FIG. 5 is disposed in the GIP part 31, a GVDD signal must be applied to the GIP part 31.

Assuming that one of the transistors T3nC, T3nA, T3A, T5q T5, T5B, and T7cr shown in FIG. 5 is disposed in the GIP unit 31, the GVSS2 signal should be applied to the GIP unit 31. .

Assuming that the transistor T6cr shown in FIG. 5 is disposed in the GIP part 31, the CRCLK(k) signal needs to be applied to the GIP part 31.

Assuming that the transistor T6 shown in FIG. 5 is disposed in the GIP part 31, the SCCLK(k) signal should be applied to the GIP part 31.

Assuming that the transistor T7 shown in FIG. 5 is disposed in the GIP part 31, the GVSS0 signal should be applied to the GIP part 31.

Assuming that the transistor T4q shown in FIG. 5 is disposed in the GIP part 31, the GVSS1 signal should be applied to the GIP part 31.

Assuming that one of the transistors TA and TB shown in FIG. 5 is disposed in the GIP part 31, the LSP signal must be applied to the GIP part 31.

Assuming that the transistor T5A shown in FIG. 5 is disposed in the GIP part 31, a VRT signal should be applied to the GIP part 31.

In FIG. 7, only the GVDD signal line is shown as an example of signal lines for driving the GIP driving circuit.

In this way, in arranging the GIP driving circuit in the display area, the connection wires (Q node, Qb node, Qh node, carry pulse output end and rear end of the previous stage) connecting each element constituting one stage of the GIP driving circuit The carry pulse output terminal of the stage) is disposed on the GIP internal connection wiring part 32, and the signal lines such as the LSP, VRT, GVDD, GVSS0, GVSS1, GVSS2, VST, CRCLK, and SCCLK are connected to the sub-pixel part (R, It should be arranged in the vertical direction like the plurality of data lines DL1 to DL8 for driving G, B, and W and the reference voltage line Vref.

In the OLED display panel according to the present invention configured as described above, an arbitrary element constituting one stage of the GIP driving circuit configured in the GIP unit 31 will be described in detail.

8 is a layout diagram of arbitrary elements constituting one stage of the GIP driving circuit formed in the GIP unit 31 according to the first embodiment of the present invention.

In FIG. 8, the transistor T3q among the circuits of the (k)th stage of the GIP driving circuit described in FIG. 5 is shown as an example.

5, the gate electrode of the transistor T3q is connected to the Q node, the drain electrode of the transistor T3q is connected to the Qh node, and the source electrode of the transistor T3q is connected to the first constant voltage line GVDD. connected to

Therefore, FIG. 8 shows the layout of the transistor T3q of the GIP driving circuit.

As shown in FIG. 8, an active layer (A) is formed on a substrate, a gate insulating film (not shown) is formed on the entire surface of the substrate including the active layer (A), and a gate on the upper side of the active layer (A). A gate electrode G is formed on the insulating film.

A source region and a drain region (not shown in the drawing) are formed in the active layer (A) on both sides of the gate electrode (G) by impurity ion implantation, and an interlayer insulating film (shown in the drawing) is formed on the entire surface of the substrate including the gate electrode (G). (not shown) is formed, and the interlayer insulating layer and the gate insulating layer above the source and drain regions are selectively removed to form contact holes, respectively.

A source electrode S and a drain electrode D are formed on the interlayer insulating layer to be connected to the source region and the drain region through the contact hole.

Here, as described above, the gate electrode G is connected to the Q node, the source electrode S is connected to the first constant voltage line GVDD, and the drain electrode D is connected to the Qh node. .

That is, the first constant voltage line GVDD is vertically disposed in parallel with the plurality of data lines DL1 to DL8 and the reference voltage line Vref for driving the sub-pixel units R, G, B, and W. ) has an extension electrode portion protruding into the GIP portion 31, and the extension electrode portion and the source electrode S of the transistor T3q are electrically connected.

In this way, an extension electrode part is formed on the signal line for driving the stage of the GIP driving circuit, and an arbitrary element constituting one stage of the GIP driving circuit formed in the GIP part 31 through the extension electrode part Since it is electrically connected, the area occupied by the GIP part 31 is large.

Therefore, there is a limit to securing a distance between the at least three sub-pixel units 33 and the GIP unit 31, and capacitance occurs between the at least three sub-pixel units 33 and the GIP unit 31. will do

However, since it is difficult to maintain a constant distance between the at least three sub-pixel parts 33 and the GIP part 31 in the entire area of the OLED display panel in the manufacturing process, the at least three sub-pixel parts 33 ) and the GIP unit 31, a capacitance deviation occurs, and such a capacitance deviation causes a luminance deviation between adjacent pixels.

In order to reduce the capacitance deviation between the at least three sub-pixel parts 33 and the GIP part 31, the at least three sub-pixel parts 33 and the GIP part 31 in the entire area of the OLED display panel. ). Accordingly, a distance between the at least three sub-pixel parts 33 and the GIP part 31 should be widened as much as possible.

Therefore, a method of securing a maximum distance between the at least three sub-pixel parts 33 and the GIP part 31 by reducing the area of the GIP part is proposed.

9 is a layout diagram of arbitrary elements constituting one stage of the GIP driving circuit formed in the GIP unit 31 according to the second embodiment of the present invention, and FIG. 10 is II' of FIG. It is a cross-sectional view along the line, and FIG. 11 is a cross-sectional view along line II-II' in FIG.

Similarly, among the circuits of the (k)th stage of the GIP driving circuit described in FIG. 5, the transistor T3q is shown as an example.

Arbitrary elements constituting one stage of the GIP driving circuit formed in the GIP unit according to the second embodiment of the present invention, as shown in FIGS. 9 to 11, a GIP driving circuit on a substrate Signal lines such as LSP, VRT, GVDD, GVSS0, GVSS1, GVSS2, VST, CRCLK, and SCCLK for driving are formed in a vertical direction. 9 to 11 illustrate the first constant voltage line GVDD as an example of the signal lines.

A buffer layer is formed on the entire surface of the substrate including the signal lines, an active layer (A) is formed on the buffer layer on the GIP part 31, and the entire surface of the substrate including the active layer (A) is formed. A gate insulating film GI is formed thereon, and a gate electrode G of the transistor T3q is formed on the gate insulating film GI above the active layer A. At this time, the active layer (A) is formed to overlap the signal line (GVDD).

A source region and a drain region (N+) are formed in the active layer (A) on both sides of the gate electrode (G) by impurity ion implantation, and an interlayer insulating film (ILD) is formed on the entire surface of the substrate including the gate electrode (G). , the interlayer insulating layer ILD and the gate insulating layer GI on the upper side of the source and drain regions N+ are selectively removed to form first contact holes C1, respectively.

Further, the source electrode S of the transistor T3q and the drain electrode D of the transistor T3q are connected to the source and drain regions N+ through the first contact hole C1 on the interlayer insulating layer ILD. ) is formed.

Here, as described above, the gate electrode G is connected to the Q node, the source electrode S is connected to the first constant voltage line GVDD, and the drain electrode D is connected to the Qh node. .

In this case, the source electrode S is formed to overlap the signal line GVDD, and the interlayer insulating layer ILD and the gate insulating layer on the signal line GVDD do not overlap with the active layer A. (GI) is selectively removed to form a second contact hole (C2), and the signal line (GVDD) and the source electrode (S) are electrically connected through the second contact hole (C2).

The first contact hole C1 and the second contact hole C2 are formed simultaneously.

As such, since the active layer (A) is formed to overlap the signal line for driving the stage of the GIP driving circuit, and the source electrode (S) is also formed to overlap the signal line (GVDD), the GIP unit ( 31) can be further reduced than in the first embodiment of the present invention.

Therefore, in the second embodiment of the present invention, since the area occupied by the GIP part 31 can be reduced, the distance between the at least three sub-pixel parts 33 and the GIP part 31 is reduced in the first embodiment of the present invention. It can be increased more than the embodiment.

In this way, since the distance between the at least three sub-pixel parts 33 and the GIP part 31 can be increased, generation of capacitance between the at least three sub-pixel parts 33 and the GIP part 31 is prevented. In addition, capacitance variation between the at least three sub-pixel units 33 and the GIP unit 31 can be minimized and luminance variation between adjacent pixels can be prevented.

9 to 11 show that the source electrode S of the transistor T3q overlaps the first constant voltage line GVDD, but is not limited thereto.

That is, in the GIP unit 31, one of signal lines such as LSP, VRT, GVDD, GVSS0, GVSS1, GVSS2, VST, CRCLK, and SCCLK for driving a GIP driving circuit and a unit pixel area in the display area Arbitrary electrodes of the elements of the GIP driving circuit distributed in the field are designed to overlap each other.

For example, assuming that one of the transistors T3qA, T1B, T3q, and T4 T4l shown in FIG. 5 is disposed in the GIP part 31, in the GIP part 31, the first constant voltage line ( GVDD) and the transistors overlap.

Specifically, the source electrodes of the transistors T3qA, T1B, and T4 overlap the first constant voltage line GVDD, and the gate electrodes or source electrodes of the transistors T3q and T4l overlap the first constant voltage line GVDD. nested in

Assuming that one of the transistors T3nC, T3nA, T3A, T5q T5, T5B, and T7cr shown in FIG. 5 is disposed in the GIP unit 31, the transistors T3nC, T3nA, T3A, T5q T5, T5B and T7cr) overlap the second constant voltage line GVSS2.

Specifically, drain electrodes of the transistors T3nC, T3nA, T3A, T5q T5, T5B, and T7cr overlap the second constant voltage line GVSS2.

Assuming that the transistor T6cr shown in FIG. 5 is disposed in the GIP part 31, the transistor T6cr overlaps the clock signal line CRCLK(k) for outputting the carry pulse.

Specifically, the source electrode of the transistor T6cr overlaps the clock signal line CRCLK(k) for outputting the carry pulse.

Assuming that the transistor T6 shown in FIG. 5 is disposed in the GIP part 31, the transistor T6 overlaps the clock signal line SCCLK(k) for outputting the scan pulse.

Specifically, the source electrode of the transistor T6 overlaps the clock signal line SCCLK(k) for outputting the scan pulse.

Assuming that the transistor T7 shown in FIG. 5 is disposed in the GIP part 31, the GVSS0 signal should be applied to the GIP part 31.

Assuming that the transistor T4q shown in FIG. 6 is disposed in the GIP part 31, the transistor T7 overlaps the third constant voltage line GVSS1.

Specifically, the drain electrode of the transistor T7 overlaps the third constant voltage line GVSS1.

Assuming that one of the transistors TA and TB shown in FIG. 5 is disposed in the GIP part 31, the transistors TA and TB overlap the line select signal line LSP.

Specifically, the gate electrodes of the transistors TA and TB overlap the line select signal line LSP.

Assuming that the transistor T5A shown in FIG. 5 is disposed in the GIP part 31, the transistor T5A overlaps the signal line VRT for real time compensation.

Specifically, the gate electrode of the transistor T5A overlaps the signal line VRT for real time compensation.

Through the above description, those skilled in the art will understand that various changes and modifications are possible without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

A: active layer G: gate electrode
D: drain electrode S: source electrode
C1, C2: contact hole GI: gate insulating film
Buffer: buffer layer GVDD: constant voltage line
ILD: Interlayer insulating film Substrate: Substrate
31: GIP part 32: GIP internal connection wiring part
33: at least three sub pixel units

Claims (6)

a display area in which data lines and scan lines intersect, including sub-pixels disposed at each intersection, and displaying a real image; and
A GIP driving circuit having a plurality of stages distributed in unit pixel areas within the display area and supplying scan pulses to corresponding gate lines;
The unit pixel area includes at least three sub-pixel parts, a GIP part in which one element constituting the GIP driving circuit is disposed, and a GIP internal connection wiring part in which connection wires connecting each element of the GIP driving circuit are disposed. equipped,
A signal line for driving the GIP driving circuit is disposed in the GIP unit, and one of electrodes of elements constituting the GIP driving circuit is disposed overlapping with the signal line. According to claim 1,
The signal line is disposed parallel to the data lines. According to claim 1,
The signal lines include a line selection signal line, a signal line for real-time compensation, a clock signal line for outputting a carry pulse, a clock signal line for outputting a scan pulse, a reset signal line, a start pulse signal line, and constant voltage lines. According to claim 1,
The elements constituting the GIP driving circuit disposed in the GIP unit,
A buffer layer formed on the entire surface of the substrate including the signal line;
an active layer formed on the buffer layer to overlap the signal line;
A gate insulating film formed on the entire surface of the substrate including the active layer;
A gate electrode formed on the gate insulating film on the upper side of the active layer;
Source and drain regions formed in the active layer (A) on both sides of the gate electrode (G);
An interlayer insulating film formed on the entire surface of the substrate including the gate electrode;
a source electrode and a drain electrode electrically connected to the source and drain regions and formed on the interlayer insulating film;
An OLED display panel in which the source electrode overlaps the signal line. According to claim 1,
The elements constituting the GIP driving circuit disposed in the GIP unit,
A buffer layer formed on the entire surface of the substrate including the signal line;
an active layer formed on the buffer layer to overlap the signal line;
A gate insulating film formed on the entire surface of the substrate including the active layer;
A gate electrode formed on the gate insulating film on the upper side of the active layer;
Source and drain regions formed in the active layer (A) on both sides of the gate electrode (G);
An interlayer insulating film formed on the entire surface of the substrate including the gate electrode;
a source electrode and a drain electrode electrically connected to the source and drain regions and formed on the interlayer insulating film;
An OLED display panel in which the drain electrode overlaps the signal line. According to claim 1,
The elements constituting the GIP driving circuit disposed in the GIP unit,
A buffer layer formed on the entire surface of the substrate including the signal line;
an active layer formed on the buffer layer to overlap the signal line;
A gate insulating film formed on the entire surface of the substrate including the active layer;
A gate electrode formed on the gate insulating film on the upper side of the active layer;
Source and drain regions formed in the active layer (A) on both sides of the gate electrode (G);
An interlayer insulating film formed on the entire surface of the substrate including the gate electrode;
a source electrode and a drain electrode electrically connected to the source and drain regions and formed on the interlayer insulating film;
An OLED display panel in which the gate electrode overlaps the signal line.

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