KR102278805B1 - Display device - Google Patents

Abstract

An object of the present invention is to provide a method for improving a defect caused by static electricity in a signal wiring that transmits a gate start signal Vst in a display device having a GIP structure.
To this end, the first and second signal wires for transmitting the gate start signal and the reset signal respectively to the GIP (gate in panel) circuit are extended to the lower part of the non-display area and connected to each other to form a closed loop structure.
Accordingly, the capacitance of the first and second signal wirings increases by increasing the overlapping area with the surrounding signal wirings, so that static electricity acceptance characteristics are improved so that defects caused by static electricity can be improved, and the signal for transmitting the gate start signal Even if a defect occurs in the wiring or the signal wiring that transmits the reset signal, the gate start signal or the reset signal can be normally applied to the GIP circuit so that the GIP circuit can operate normally.

Description

Display device

The present invention relates to a display device, and more particularly, to a display device capable of improving gate start (Vst) signal wiring defects due to static electricity in a display device having a gate in panel (GIP) structure.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and in recent years, a liquid crystal display device (LCD), a plasma display panel (PDP), an organic Various flat display devices such as an organic light emitting diode (OLED) are being used.

Among these flat panel display devices, the liquid crystal display device is widely used because it has the advantages of miniaturization, light weight, thinness, and low power driving.

As a liquid crystal display device, an active matrix type liquid crystal display device in which switching transistors are formed in each pixel arranged in a matrix form is currently commonly used.

In general, an active matrix type liquid crystal display device uses a display panel including gate wirings and data wirings, a gate driving circuit connected to the display panel for outputting a gate signal, and a data driving circuit for outputting a data signal.

Meanwhile, recently, a liquid crystal display device having a gate in panel (GIP) structure in which a gate driving circuit is directly formed on an array substrate of a display panel has been used.

1 is a diagram schematically illustrating a conventional liquid crystal display having a GIP structure.

Referring to FIG. 1 , a conventional liquid crystal display having a GIP structure includes a display panel 10 having a display area AA and a non-display area NA defined therein, and a driving IC (DIC) for driving the display panel 10 . ) is included.

In the non-display area NA of the display panel 10 , a gate driving circuit that outputs a gate signal to the gate wiring, that is, a GIP circuit GIP is directly formed on the array substrate of the display panel 10 . The GIP circuit GIP includes a plurality of stages connected to each corresponding gate line and outputting a corresponding gate signal.

Meanwhile, the driving IC (DIC) is connected to the display panel 10 and outputs a data signal to a data line. The driving IC DIC is a driving signal for driving the GIP circuit GIP, and outputs, for example, a plurality of clock signals CLK having different phases from the gate start signal Vst.

The driving signals CLK and Vst output from the driving IC DIC are transmitted to the GIP circuit GIP through corresponding signal lines LL formed in the non-display area NA.

Here, the first signal line LL1 transmitting the gate start signal Vst is configured to be connected to the first stage of the GIP circuit GIP. Meanwhile, the plurality of second signal wirings LL2 that transmit the clock signal CLK extend along the longitudinal direction of the GIP circuit GIP and are configured to be connected to a corresponding stage.

As such, the first signal line LL1 that transmits the gate start signal Vst is formed to have a fairly short length from the driving IC DIC to a position corresponding to the first stage. Accordingly, the first signal wiring LL1 has a very small capacitance formed by overlapping with the surrounding wiring pattern, and thus is vulnerable to static electricity generation. That is, when external static electricity is introduced, there is a very high possibility that a defect such as disconnection occurs in the first signal wiring LL1 due to static electricity.

Furthermore, since the first signal wiring LL1 is connected to the GIP circuit GIP in a serial form, when a defect such as a disconnection occurs in the first signal wiring LL1, the gate start signal Vst is transmitted to the GIP circuit GIP ), the GIP circuit (GIP) cannot be driven normally.

On the other hand, the above problem may occur not only in the liquid crystal display device but also in other types of display devices using the GIP structure.

An object of the present invention is to provide a method for improving a defect caused by static electricity in a signal wiring that transmits a gate start signal Vst in a display device having a GIP structure.

In order to achieve the above object, the present invention provides a gate in panel (GIP) circuit positioned in a non-display area of an array substrate and outputting gate signals to a plurality of gate wirings, and one end in the longitudinal direction of the non-display area. and a plurality of signal wirings extending from the portion to the other end portion and connected to the GIP circuit, wherein the plurality of signal wirings include a first signal line for transmitting a gate start signal, a reset signal and the other end of the non-display area and a second signal line connected to the first signal line in the display device.

Here, the plurality of signal wirings includes a third signal wiring, the third signal wiring is connected to the GIP circuit through a connection wiring extending in the width direction of the non-display area, and the first signal wiring is an insulating film It may be placed therebetween and overlap the connection wiring.

The first signal line may overlap the plurality of gate lines.

and a discharge circuit positioned at one of the one end portion and the other end portion of the non-display area and connected to one of the first and second signal lines.

The non-display area may include an electrostatic inductor positioned at the other of the one end portion and the other end portion and connected to one of the first and second signal lines.

In the present invention, in the display device of the GIP structure, the signal wiring for transmitting the gate start signal is extended from one end to the other end of the GIP circuit like other signal wiring, and the reset signal, which is the same signal as the gate start signal, is transmitted. A closed-loop structure is realized by connecting it to the signal wiring.

Accordingly, the signal wiring forming the closed loop structure increases the overlapping area of the signal wiring with the surrounding signal wiring, thereby increasing the capacitance, thereby improving the electrostatic accommodating characteristics, thereby improving defects caused by static electricity. Furthermore, even if a defect occurs in the signal wiring transmitting the gate start signal or the signal wiring transmitting the reset signal, the gate start signal or the reset signal can be normally applied to the GIP circuit, so that the GIP circuit can operate normally. .

In addition, a discharge circuit or an electrostatic inductor may be connected to the signal wiring of the closed loop structure. Accordingly, the static electricity flowing into the signal wiring can be induced to the discharge circuit or the static electricity inductor, so that defects caused by static electricity in the signal wiring can be further improved.

1 is a diagram schematically illustrating a conventional liquid crystal display device having a GIP structure.
2 is a diagram schematically illustrating a liquid crystal display device according to an embodiment of the present invention.
3 is a plan view illustrating a non-display area portion of an array substrate of a display panel on which GIP circuits and signal wirings are formed according to the first embodiment of the present invention;
FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 3 ;
5 is a diagram schematically illustrating a liquid crystal display device according to a second embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

As the display device according to the embodiment of the present invention, any type of display device having a GIP structure, for example, a liquid crystal display device, an organic light emitting device display device, a plasma display device, and the like may be used. However, hereinafter, for convenience of description, a liquid crystal display device will be described as an example.

2 is a diagram schematically illustrating a liquid crystal display device according to a first embodiment of the present invention.

Referring to FIG. 2 , the liquid crystal display 100 according to the first embodiment of the present invention is a liquid crystal display having a GIP structure, which includes a display panel 110 , a driving IC (DIC), and a driving board 300 . may include.

The display panel 110 includes a display area AA in which a plurality of pixels are arranged in a matrix to display an image, and a non-display area NA formed around the display area AA.

Here, the non-display area NA is connected to the first non-display area NA1 in which the GIP circuit GIP is formed as one end of the gate line GL and the driving IC DIC as one end of the data line DL. and a second non-display area NA2 that is

The display panel 110 includes two substrates facing each other, for example, an array substrate, an opposing substrate facing the same, and a liquid crystal layer positioned between the two substrates.

A plurality of gate lines GL extending along a row direction as a first direction and a plurality of data lines DL extending along a column direction in a second direction are formed on the array substrate of the display panel 110 . A plurality of pixels arranged in a matrix form are defined by the gate and data lines GL and DL crossing each other as described above.

Although not specifically illustrated, switching transistors connected to gate lines and data lines GL and DL are formed in each pixel. The switching transistor is connected to the pixel electrode. A common electrode is formed corresponding to the pixel electrode, and when a voltage is applied to the pixel electrode and the common electrode, an electric field is formed between them to drive the liquid crystal.

In addition, the pixel electrode, the common electrode, and the liquid crystal positioned between these electrodes constitute the liquid crystal capacitor. Meanwhile, in each pixel, a storage capacitor is further configured, which serves to store the data signal applied to the pixel electrode until the next frame.

Meanwhile, although not specifically illustrated, the liquid crystal display 100 may include a backlight unit as a light source for supplying light to the display panel 110 . The backlight unit may use a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), a light emitting diode (LED), or the like.

A GIP circuit GIP as a gate driving circuit may be formed in the first non-display area NA1 of the array substrate of the display panel 110 as described above. Meanwhile, in some cases, GIP circuits GIP may be formed on both sides of the array substrate facing each other. In the embodiment of the present invention, for convenience of description, a case in which the GIP circuit GIP is formed in the first non-display area NA1 on one side of the array substrate is taken as an example.

The GIP circuit GIP is a shift register circuit that sequentially outputs a gate signal, and includes a plurality of stages SR connected to each of the plurality of gate lines GL to output the gate signal.

The stage SR sequentially outputs the gate signal in units of row lines in every frame. That is, in each frame, each stage SR outputs the gate high voltage during the horizontal period of the corresponding row line, and outputs the gate low voltage during the remaining time.

When the gate high voltage is output from the stage SR, the switching transistor of the pixel connected to the corresponding gate line GL is turned on, and in synchronization with this, the data signal transmitted through the data line GL is applied to the corresponding pixel to be charged. .

As a driving signal for driving the GIP circuit GIP configured as described above, for example, a plurality of clock signals CLK and a reset signal RST of different phases from the gate start signal Vst are applied. Meanwhile, although not shown, a power supply voltage such as a low potential voltage may be applied to drive the GIP circuit GIP.

The clock signal CLK is applied to the drain terminal of the pull-up transistor of the corresponding stage SR, and the high voltage of the clock signal CLK is output as the gate high voltage during the signal output period of the corresponding stage SR.

Meanwhile, the gate signal output from the stage SR positioned at the front stage may be applied as a start signal for starting the operation of the stage SR positioned at the rear stage, for example. Here, for example, in the first stage SR, a separate gate start signal Vst may be transmitted from the driving IC DIC as a start signal.

Furthermore, the gate signal output from the stage SR located at the rear stage may be applied as a reset signal for resetting the stage SR located at the previous stage, for example. Here, for example, in the last stage SR, a separate reset signal RST may be transmitted from the driving IC DIC as a reset signal.

In this case, the gate start signal Vst and the reset signal RST as described above are substantially the same signal having the same waveform.

As described above, a plurality of signal lines LL for respectively transmitting driving signals for driving the GIP circuit GIP are formed in the non-display area NA, and these signal lines LL are corresponding to the driving ICs DIC. Each is connected to an output pin.

These signal lines LL include a first signal line LL1 transmitting the gate start signal Vst, a second signal line LL2 transmitting a reset signal RST, and a clock signal CLK. A third transmission line LL3 may be included. Meanwhile, the third signal line LL3 may include a power supply voltage transmission line.

These signal lines LL extend from the second non-display area NA2 of the display panel 110 to which the driving IC DIC is connected to the first non-display area NA1 , and then in the first non-display area NA1 . It extends along the longitudinal direction of the GIP circuit (GIP).

That is, the third signal line LL3 for transmitting the clock signal CLK is a lower portion of the first non-display area NA1 (ie, the GIP circuit GIP) along the length direction of the first non-display area NA1 . a lower portion of the first non-display area NA1 along the longitudinal direction of the second signal line LL2 that transmits the reset signal RST and is configured to extend to the lower end of the first non-display area NA1 designed to extend to

Similarly, the first signal line LL1 for transmitting the gate start signal Vst is also configured to extend to the lower end of the first non-display area NA1 in the longitudinal direction of the first non-display area NA1 .

In particular, the first signal line LL1 is configured to be connected to the second signal line LL2 at the lower end of the first non-display area NA1 . In other words, the first and second signal lines LL1 and LL2 to which the gate start signal and the reset signals Vst and RST, which are the same signals, are respectively applied, are in the first non-display area NA1 in the longitudinal direction thereof. extend substantially parallel to each other and have ends connected to each other.

Accordingly, the first and second signal lines LL1 and LL2 form a closed loop in a parallel connection structure.

As described above, by forming the first signal wiring LL1 for transmitting the gate start signal Vst to extend to the lower end of the GIP circuit GIP, the first signal wiring LL1 has an overlapping area with the surrounding signal wirings. is increased, the capacitance of the first signal line LL1 is increased.

In this regard, for example, the first signal line LL1 may overlap the third signal line LL3 for transmitting the clock signal CLK and the connection line CL of the GIP circuit GIP. Accordingly, the overlapping area of the first signal line LL1 with the surrounding signal lines is increased, so that the capacitance of the first signal line LL1 is increased.

As such, due to the increase in the capacitance of the first signal line LL1 , the static electricity accommodating characteristic of the first signal line LL1 is improved, so that defects due to static electricity can be improved compared to the related art.

Furthermore, since the first signal line LL1 is connected to the second signal line LL2 to form a closed loop structure, even if a defect such as disconnection occurs in the first signal line LL1 due to static electricity or the like, the gate start signal (Vst) can be normally transmitted to the GIP circuit (GIP).

In this regard, the first signal wiring and the second signal wiring LL1 and LL2 are connected in parallel to each other and are applied with the same signal, the gate start signal and the reset signal Vst, RST. The first signal wiring LL1 Even if a defect occurs in the , the gate start signal Vst may be normally transmitted to the GIP circuit GIP through the second signal line LL2 .

Likewise, even if a defect occurs in the second signal line LL2 , the reset signal RST can be normally transmitted to the GIP circuit GIP through the first signal line LL1 .

Accordingly, through the closed-loop structure of the first and second signal lines LL1 and LL2, even if a defect occurs in the corresponding signal lines LL1 and LL2 due to static electricity, the GIP circuit GIP can operate normally.

The driving IC DIC may be connected to the second non-display area NA2 as the other side adjacent to one side of the array substrate of the display panel 110 on which the GIP circuit GIP is formed.

The driving IC DIC corresponds to a data driving circuit that outputs a data signal to the data line DL. At least one driving IC (DIC) may be used to drive the display panel 110 . For convenience of description, a case in which three driving ICs (DIC) are used is exemplified.

The driving IC (DIC), for example, may be mounted on the flexible circuit film 210 on which the wiring pattern is formed, and may be connected to the display panel 110 while being mounted on the flexible circuit film 210 . As another example, the driving IC (DIC) may be configured to be directly mounted on the array substrate of the display panel 110 in a COG method. In the embodiment of the present invention, for convenience of description, a case in which the driving IC (DIC) is mounted on the flexible circuit film 210 is exemplified.

Meanwhile, the driving IC (DIC) located close to the GIP circuit (GIP) may be configured to output driving signals for driving the GIP circuit (GIP), and may include a signal output pin for outputting these driving signals. have.

The driving IC (DIC) is connected to the driving board 300 through the flexible circuit film 210 . A driving circuit for driving the display panel 110 is mounted on the driving board 300 . For example, the timing controller 310 may be mounted on the driving board 300 .

The timing controller 310 may receive image data and a timing signal from an external system, align the image data, and output the image data to the driving IC (DIC). Also, the timing controller 310 may output a driving signal for driving the GIP circuit GIP and the driving IC DIC.

Hereinafter, the signal lines LL connected to the GIP circuit GIP according to an embodiment of the present invention will be described in more detail with reference to FIGS. 3 and 4 .

3 is a plan view illustrating a portion of a non-display area of an array substrate of a display panel on which a GIP circuit and signal wiring are formed according to the first embodiment of the present invention, and FIG. 4 is a view taken along the cutting line IV-IV of FIG. It is a cross section.

Referring to FIG. 3 , the GIP circuit GIP is formed in the first non-display area NA1 of the array substrate 111 of the display panel 110 , and is a first non-display area NA2 in the longitudinal direction of the first non-display area NA2 . A plurality of signal lines LL extend along the direction.

Such a plurality of signal lines LL extend to the second non-display area NA2 connected to the driving IC (DIC of FIG. 2 ). A plurality of output pads PD to which signals output from the driving IC are applied are formed in the second non-display area NA2 . The plurality of signal lines LL are connected to a corresponding output pad PD among the plurality of output pads PD to receive a driving signal.

The signal line LL includes a first signal line LL1 transmitting the gate start signal Vst, a second signal line LL2 transmitting a reset signal RST, and a second signal line LLK transmitting the clock signal CLK. Three signal lines LL3 may be included.

These signal lines LL1 , LL2 , and LL3 all extend along the longitudinal direction of the first non-display area NA1 , that is, the longitudinal direction of the GIP circuit GIP.

That is, the third signal line LL3 for transmitting the clock signal CLK extends to the lower end of the first non-display area NA1 in the longitudinal direction of the first non-display area NA1, and the reset signal RST ), the second signal line LL2 also extends to the lower end of the first non-display area NA1 in the longitudinal direction of the first non-display area NA1 .

Similarly, the first signal line LL1 for transmitting the gate start signal Vst is also configured to extend to the lower end of the first non-display area NA1 in the longitudinal direction of the first non-display area NA1 .

In particular, the first signal line LL1 is configured to be connected to the second signal line LL2 at the lower end of the first non-display area NA1 .

Meanwhile, each signal line LL is connected to the GIP circuit GIP through a connection line CL extending along the second direction, which is the width direction of the first non-display area NA1 . That is, the signal line LL is configured to be connected to the corresponding stage SR of the GIP circuit GIP through the connection line CL.

The connection wiring CL is formed in different layers with the signal wiring LL and the insulating film interposed therebetween when viewed in cross-section, and is configured to contact the corresponding signal wiring LL through the contact hole CH.

In this regard, referring to FIG. 4 , for example, the signal line LL may be formed of the same material as the gate line GL and on the same layer, and at least one insulating layer 130 is formed on the signal line LL. A connection line CL formed of a transparent conductive material such as ITO may be positioned on the insulating layer 130 . Here, the connection wiring CL may be formed in the process of forming a pixel electrode positioned in each pixel of the display area AA, but is not limited thereto.

In this case, the first signal line LL1 for transmitting the gate start signal Vst overlaps with the connection line CL connected to the third signal line LL3 for transmitting the clock signal CLK, so that the capacitance ( Cp) occurs.

As such, the overlapping area of the first signal line LL1 with the surrounding signal lines increases, and as a result, the capacitance Cp of the first signal line LL1 increases.

In this regard, referring to FIG. 1 , in the conventional case, the first signal wiring LL1 for transmitting the gate start signal Vst is configured to extend only to the upper end of the GIP circuit GIP, so that the surrounding signal wiring and The overlapping area is very small, causing defects due to static electricity.

On the other hand, according to the present embodiment, as the first signal wiring LL1 extends to the lower end of the GIP circuit GIP, the first signal wiring LL1 overlaps with the surrounding signal wiring so that the overlapping area is conventionally By significantly increasing compared to that, it is possible to improve the electrostatic capacity.

As such, in the present embodiment, by increasing the length of the first signal line LL1, defects due to static electricity can be improved compared to the related art.

Meanwhile, as another example, the first signal line LL1 may be disposed in the first non-display area NA1 on the output side of the GIP circuit GIP. In this case, the first signal line LL1 overlaps the gate lines GL positioned on the output side of the GIP circuit GIP, and the capacitance of the first signal line LL1 increases according to the overlap. , it is possible to improve the defects caused by static electricity compared to the prior art.

In addition, the first signal line LL1 forms a closed loop in a parallel connection structure with the second signal line LL2 that transmits the same signal, so that the first signal line LL1 is connected to the first signal line LL1 by static electricity or the like. Even if a defect occurs, the gate start signal Vst can be normally transmitted to the GIP circuit GIP.

In this regard, in the related art, since the first signal line LL1 is connected to the GIP circuit GIP in a serial connection form, when a disconnection defect or the like occurs in the first signal line LL1, the gate start signal Vst is can not be applied to the GIP circuit (GIP), so that the GIP circuit (GIP) cannot be driven normally.

On the other hand, according to the present embodiment, the first signal wiring and the second signal wiring LL1 and LL2 transmitting the same signal are connected in parallel to each other, so that even if a defect occurs in the first signal wiring LL1, the second signal wiring LL1 The gate start signal Vst may be normally transmitted to the GIP circuit GIP through the signal line LL2.

Similarly, even if a defect occurs in the second signal line LL2 , the reset signal RST can be normally transmitted to the GIP circuit GIP through the first signal line LL1 .

As such, the first and second signal wirings LL1 and LL2 perform a function of a repair wiring to each other.

Accordingly, through the closed loop structure of the first and second signal lines LL1 and LL2, even if a defect occurs in the corresponding signal lines LL1 and LL2 due to static electricity, the GIP circuit GIP can operate normally.

On the other hand, since the first and second signal wirings LL1 and LL2 can be viewed as one signal wiring transmitting the same signal when viewed as a whole, their positions may be opposite to each other.

As described above, according to the first embodiment of the present invention, the signal wiring for transmitting the gate start signal is extended from one end of the GIP circuit to the other end of the GIP circuit like other signal wirings, and it is reset, which is the same signal as the gate start signal. A closed-loop structure is implemented by connecting with a signal wiring that transmits a signal.

Accordingly, the signal wiring forming the closed loop structure increases the overlapping area of the signal wiring with the surrounding signal wiring, thereby increasing the capacitance, thereby improving the electrostatic accommodating characteristics, thereby improving defects caused by static electricity.

Furthermore, even if a defect occurs in the signal wiring transmitting the gate start signal or the signal wiring transmitting the reset signal, the gate start signal or the reset signal can be normally applied to the GIP circuit, so that the GIP circuit can operate normally. .

Hereinafter, a second embodiment of the present invention will be described with reference to FIG. 5 . 5 is a diagram schematically illustrating a liquid crystal display device according to a second embodiment of the present invention.

In FIG. 5 , for convenience of explanation, the main components are briefly illustrated. Further, a detailed description of a configuration similar to that of the first embodiment may be omitted below.

Referring to FIG. 5 , the liquid crystal display 100 according to the second embodiment of the present invention may include at least one of a discharge circuit (ESD) and an electrostatic derivative (EI) to improve defects caused by static electricity. . Meanwhile, in this embodiment, a case in which both the discharge circuit ESD and the electrostatic inductor EI are provided is taken as an example.

The discharge circuit ESD and the electrostatic inductor EI are connected to the first and second signal lines LL1 and LL2 constituting the closed loop.

The discharge circuit ESD and the electrostatic inductor EI may be disposed at one or both ends of the first and second signal lines LL1 and LL2, respectively, in consideration of the limited area of the first non-display area NA. may be, but is not limited thereto.

Regarding the arrangement of the discharge circuit (ESD) and the electrostatic inductor (EI), the discharge circuit (ESD) and the electrostatic inductor (EI) are devices having a very large capacitance to prevent defects due to static electricity, and they occupy a large area. .

Meanwhile, a recent trend is to use a liquid crystal display having a narrow bezel. In this case, the width of the first non-display area NA1 is limited, and the first non-display area NA1 is Since various signal wirings are formed, the area thereof is extremely limited.

As such, it is not easy to form the discharge circuit ESD and the electrostatic inductor EI, which occupy a large area, in the portion where the signal lines LL are formed in the first non-display area NA1 .

Accordingly, it is preferable to form the discharge circuit ESD and the electrostatic inductor EI on the upper and lower ends of the first non-display area NA1 having relatively sufficient space.

In this embodiment, for convenience of explanation, a case in which the discharge circuit ESD is disposed on the upper end side of the first non-display area NA1 and is connected to one end side of the first signal line LL1 is taken as an example. . In addition, a case in which the electrostatic inductor EI is disposed on the lower end side of the first non-display area NA1 and connected to the other end side of the first signal line LL1 is taken as an example.

The discharge circuit ESD is configured to be connected between the first signal line LL1 and the discharge line ESL. Here, the discharge line ESL may be formed to extend along the periphery of the non-display area NA of the array substrate of the display panel 110 and may be connected to a ground terminal.

Accordingly, when static electricity flows into the first signal line LL1 , the static electricity can escape to the discharge line ESL through the discharge circuit ESD.

The electrostatic inductor EI may be configured by using a large-capacity capacitor having first and second electrodes facing each other with an insulating layer interposed therebetween. In this case, for example, the first electrode of the electrostatic inductor EI may be connected to the first signal line LL1 , and the other electrode may have a floating state.

Accordingly, the static electricity flowing into the first signal wiring LL1 is induced to the electrostatic inductor EI having a huge capacity, and thus static electricity burst is also generated in the static electricity inductor EI, not the first signal wiring LL1. .

As described above, by using the discharge circuit ESD or the electrostatic inductor EI, it is possible to further improve defects caused by static electricity in the first and second signal wirings LL1 and LL2.

In the above bar, a liquid crystal display device having a GIP structure has been described as an example, and as a display device in which a GIP circuit is directly formed on a display panel, a display device such as an organic light emitting diode display device or a plasma display device is described above according to the present invention. It is obvious that the embodiment may be applied.

As described above, according to the embodiments of the present invention, in the display device having the GIP structure, the signal wiring for transmitting the gate start signal is extended from one end to the other end of the GIP circuit like other signal wirings, and this A closed-loop structure is implemented by connecting with a signal wiring that transmits a reset signal, which is the same signal as the start signal.

Accordingly, the signal wiring forming the closed loop structure increases the overlapping area of the signal wiring with the surrounding signal wiring, thereby increasing the capacitance, thereby improving the electrostatic accommodating characteristics, thereby improving defects caused by static electricity. Furthermore, even if a defect occurs in the signal wiring transmitting the gate start signal or the signal wiring transmitting the reset signal, the gate start signal or the reset signal can be normally applied to the GIP circuit, so that the GIP circuit can operate normally. .

In addition, a discharge circuit or an electrostatic inductor may be connected to the signal wiring of the closed loop structure. Accordingly, the static electricity flowing into the signal wiring can be induced to the discharge circuit or the static electricity inductor, so that defects caused by static electricity in the signal wiring can be further improved.

The above-described embodiment of the present invention is an example of the present invention, and free modifications are possible within the scope included in the spirit of the present invention. Accordingly, the present invention includes modifications of the present invention provided they come within the scope of the appended claims and their equivalents.

100: liquid crystal display 110: display panel
111: array substrate 130: insulating layer
210: flexible circuit film 300: driving board
310: timing controller
GL, DL: Gate wiring, data wiring
LL: signal wiring
LL1, LL2, LL3: 1st signal wiring, 2nd signal wiring, 3rd signal wiring
GIP: GIP circuit
SR: Stage
DIC: Driving IC
AA, NA: display area, non-display area
NA1, NA2: first non-display area, second non-display area
Vst: gate start signal
RST: reset signal
CLK: clock signal
ESD: Discharge circuit
ESL: Discharge wiring
EI: electrostatic inductor

Claims (7)

a gate in panel (GIP) circuit positioned in a non-display area of the array substrate and outputting a gate signal to a plurality of gate wirings;
a driving IC for transmitting a gate start signal and a reset signal to the GIP circuit;
a plurality of signal wires extending from one end to the other end in the longitudinal direction of the non-display area and connected to the GIP circuit;
The plurality of signal wirings includes a first signal wiring for transmitting the gate start signal and a second signal wiring for transmitting the reset signal and connected to the first signal wiring at the other end of the non-display area,
The GIP circuit includes a plurality of stages,
The gate start signal is transmitted to the first stage closest to the driving IC among the plurality of stages,
The reset signal is transmitted to the last stage farthest from the driving IC among the plurality of stages,
The first signal wiring extends from the first stage among the plurality of stages to the last stage.
display device.
The method of claim 1,
The plurality of signal wirings include a third signal wiring,
the third signal wiring is connected to the GIP circuit through a connection wiring extending in the width direction of the non-display area;
The first signal wiring is overlapped with the connection wiring with an insulating film interposed therebetween.
display device.
The method of claim 1,
The first signal wiring overlaps the plurality of gate wirings.
display device.
The method of claim 1,
A discharge circuit positioned at one of the one end portion and the other end portion of the non-display area and connected to one of the first and second signal lines
A display device comprising a.
5. The method of claim 4,
An electrostatic inductor located at the other of the one end portion and the other end portion of the non-display area and connected to one of the first and second signal lines
A display device comprising a. The method of claim 1,
The plurality of signal wirings further include a plurality of third signal wirings for transmitting a plurality of clock signals and disposed between the first and second signal wirings,
The first signal wiring is connected to the first stage among the plurality of stages through a first connection wiring,
The second signal wiring is connected to the last stage among the plurality of stages through a second connection wiring,
Each of the plurality of third signal wires is connected to the plurality of stages through a plurality of third connection wires.
display device.
7. The method of claim 6,
The first signal wiring overlaps the plurality of third connection wirings.
display device.

Images