KR101595463B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of improving the space utilization of a simplified driving circuit and reducing the manufacturing cost by simplifying the driving control signals and the transmission line configuration of a liquid crystal display device capable of changing the direction of a display image A first gate driver provided on a first side of the liquid crystal panel for driving the gate lines of the liquid crystal panel in a positive direction; A second gate driver provided on a second side corresponding to the first side of the liquid crystal panel and driving gate lines of the liquid crystal panel in a reverse direction; A data driver driving data lines of the liquid crystal panel; And a gate selection circuit for generating a direction selection signal and a gate start signal in a high or low logic state for selecting a video display direction of the liquid crystal panel and outputting the direction selection signal and the gate start signal through the direction selection signal supply line and the gate start signal supply line, And a timing controller for supplying the timing control signal to the timing controller.

A direction selection signal, a gate start signal, a phase inversion element,

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

The present invention relates to an image display apparatus, and more particularly, to simplify driving control signals and a transmission line configuration of a liquid crystal display device capable of switching the direction of a display image, thereby improving the space utilization of a simplified driving circuit, To a liquid crystal display device.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, a driving circuit for driving the liquid crystal panel, and a backlight unit for irradiating light to the liquid crystal panel.

In general, a plurality of data integrated circuits constituting a driving circuit in a liquid crystal display device are respectively attached to at least one source printed circuit board or a printed circuit film. In the case of gate integrated circuits, the data integrated circuits are separately attached to either side of the liquid crystal panel, Lt; / RTI > In the case of a timing controller or a driving system, a separate control printed circuit board is separately provided on the back of the timing controller and the driving system to supply the driving control signals necessary for the gate and data integrated circuit.

In recent years, a liquid crystal display device has been developed which enables inversion of a display direction of an image according to need. Such liquid crystal display devices include a plurality of gate integrated circuits for displaying an image in a forward direction, A plurality of gate integrated circuits may be further provided for display.

However, since the conventional liquid crystal display device configured as described above needs to supply a plurality of direction switching signals for switching the display direction of an image and control signals for controlling the driving circuits to the respective driving circuits, And the transmission line structure of the control signals becomes complicated. In other words, conventionally, forward and backward switching signals for switching the display direction of the image and timing control signals for controlling the driving timing of the driving circuits are supplied to the respective data integrated circuits and gate integrated circuits in the same manner. Accordingly, in the conventional liquid crystal display devices, the structure of the driving circuits and the transmission line structures of the control signals are complicated, resulting in lower space utilization of the driving circuit, and increased manufacturing cost and size.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to improve the space utilization of the simplified signal transmission line and the driving circuit by simplifying the driving control signals of the liquid crystal display device, And it is an object of the present invention to provide a liquid crystal display device capable of reducing the manufacturing cost.

According to an aspect of the present invention, there is provided a liquid crystal display device including a first gate driver provided on a first side of a liquid crystal panel for driving gate lines of a liquid crystal panel in a positive direction; A second gate driver provided on a second side corresponding to the first side of the liquid crystal panel and driving gate lines of the liquid crystal panel in a reverse direction; A data driver driving data lines of the liquid crystal panel; And a gate selection circuit for generating a direction selection signal and a gate start signal in a high or low logic state for selecting a video display direction of the liquid crystal panel and outputting the direction selection signal and the gate start signal through the direction selection signal supply line and the gate start signal supply line, And a timing controller for supplying the timing control signal to the timing controller.

Wherein the direction selection signal supply line is configured such that a direction selection signal output from the timing controller is supplied to each of the data integrated circuits of the data driver and the first gate integrated circuits of the first gate driver, And the phase of the direction selection signal is inverted through the gate of the second gate driving unit to supply the direction selection signal inverted in phase to the second gate integrated circuits of the second gate driving unit.

Wherein the direction selection signal supply line is configured such that the direction selection signal is supplied to the respective data integrated circuit through a data circuit film on which at least one source printed circuit board and the data integrated circuits are mounted, A direction selection signal applied to the printed circuit board is transmitted through at least one first gate circuit film on which the at least one data circuit film, the non-display portion of the liquid crystal panel and each first gate integrated circuit are mounted, Wherein the directional select signal applied to the at least one source printed circuit board is inverted by the phase inversion element so that a phase inverted direction select signal is applied to the at least one A data circuit film, a non-display portion of the liquid crystal panel, Characterized by configured to bit integrated circuit are supplied to the at least one second gate integrated circuit via at least one second gate circuit film mounted.

Wherein the direction selection signal output from the timing controller is transmitted to the at least one source printed circuit board through the at least one first connector, at least one cable, and at least one second connector, And is supplied to a direction selection signal supply line provided.

The direction selection signal is generated and outputted in a high state when the liquid crystal panel displays the image in the forward direction so that the first gate integrated circuits sequentially drive the gate lines in a positive direction, A direction selection signal which is inverted in phase and inverted to a low state is input to the second gate integrated circuits to stop its operation.

The direction selection signal is generated and output in a low state when the image is displayed in the opposite direction to the liquid crystal panel so that the operations of the first gate integrated circuits are stopped. The direction selection signal inverted to the state is inputted to the second gate integrated circuits so that the gate lines are sequentially driven in the reverse direction.

The gate start signal supply line is configured to supply a gate start signal to at least one first gate integrated circuit of the first gate integrated circuits of the first gate driver through first and second resistance elements connected in parallel, And to supply the gate start signal to the second gate integrated circuit of at least one of the second gate integrated circuits of the second gate driver through the connected third and fourth resistance elements.

The gate start signal supply line is controlled so that the gate start signal output from the timing controller is supplied to both the first and second resistive elements and the third and fourth resistive elements configured in parallel via at least one stabilizing element Wherein the first and second resistive elements are connected in parallel to each other through at least one source printed circuit board, at least one data circuit film, a non-display area of the liquid crystal panel, and at least one first gate circuit film, Wherein the at least one source printed circuit board, the at least one data circuit film, and the at least one data circuit film are configured to supply a gate start signal to the at least one first gate integrated circuit, , The non-display region of the liquid crystal panel, and the at least one second gate circuit film And to supply the gate start signal to one second gate integrated circuit.

Wherein the gate-start signal output from the timing controller is applied to the at least one source printed circuit board via the at least one first connector, at least one cable, and at least one second connector, And supplying the gate start signal to the gate start signal supply line.

Wherein the gate start signal is generated in a logic high state at least every one horizontal period unit at a start timing of each frame and is supplied to the first and second gate integrated circuits through the gate start signal supply line, Only the first or second gate integrated circuits receiving the direction selection signal of the high state among the first and second gate integrated circuits sequentially drive the gate lines.

The liquid crystal display device according to an embodiment of the present invention having the above characteristics can simplify the driving control signals and the transmission line configuration of the liquid crystal display device capable of switching the direction of the display image. Accordingly, the present invention can increase the space utilization of the simplified signal transmission line and the driving circuit and reduce the manufacturing cost thereof.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic view illustrating a liquid crystal display device according to an embodiment of the present invention.

The liquid crystal display device shown in FIG. 1 includes a liquid crystal panel 2 having a plurality of pixel regions to display an image; A first gate driver for driving the gate lines GL1 to GLn of the liquid crystal panel 2 in the positive direction on the first side of the liquid crystal panel 2; A second gate driver provided on the second side corresponding to the first side of the liquid crystal panel 2 to drive the gate lines GL1 to GLn of the liquid crystal panel 2 in the opposite direction; A data driver for driving the data lines DL1 to DLm of the liquid crystal panel 2; And a timing controller (18) for generating a gate and a data control signal together with a direction selection signal for selecting a video display direction of the liquid crystal panel (2) and controlling the driving timings of the gate and the data driver, respectively. Here, the timing controller 18 supplies the direction selection signal in the high or low logic state to the first and second gate drivers through the direction selection signal supply line, respectively.

The liquid crystal panel 2 includes a thin film transistor (TFT) formed in each pixel region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, a liquid crystal capacitor (Clc). The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT, and a common electrode arranged between the pixel electrode and the liquid crystal. The TFT supplies a video signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the video signal supplied to the pixel electrode and the reference common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage to implement the gradation . The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied. The storage capacitor Cst may be formed by overlapping the pixel electrode with the previous gate line with the insulating film interposed therebetween, or the pixel electrode may be formed by overlapping the storage line with the insulating film interposed therebetween.

The data driver is provided between the third side of the liquid crystal panel 2 and at least one source printed circuit board 8a or 8b and includes a plurality of data integrated circuits 4a and 4b for driving the data lines DL1 to DLm ). Each of the plurality of data integrated circuits 4a and 4b is mounted on the data circuit films 6a and 6b and connected between the liquid crystal panel 2 and one of the source printed circuit boards 8a and 8b.

The data circuit films 6a and 6b may be formed of a tape carrier package (TCP) film or a chip on flexible printed circuit (COF) film. Particularly, in the case of the data circuit films 6a and 6b each having the data integrated circuits 4a and 4b mounted thereon, at least one source printed circuit board 8a and 8b and a liquid crystal panel (not shown) are formed by a TAB (Tape Automated Bonding) 2). In this case, each of the plurality of data integrated circuits 4a and 4b drives the data lines DL1 to Dlm of the liquid crystal panel 2 through the data circuit films 6a and 6b and a data pad portion .

Each of the data integrated circuits 4a and 4b generates a data drive control signal such as a source start signal SSP and a source shift clock SSC according to a direction selection signal from the timing controller 18. [ Clock, a source output enable (SOE) signal, or the like, to the data lines DL1 to DLm. In other words, each of the data integrated circuits 4a and 4b latches the digital image data inputted according to the SSC, and outputs it in units of horizontal lines in response to the SOE signal inputted through the timing controller 18. [ Then, each of the data integrated circuits 4a and 4b converts the digital video data of the horizontal line unit into an analog video voltage, that is, a video signal, and outputs it.

The first gate driver includes a plurality of first gate integrated circuits (3) provided on a first side of the liquid crystal panel (2) and sequentially driving the gate lines (GL1 to GLn) in a forward direction in accordance with the direction selection signal do. Here, the plurality of first gate integrated circuits 3 are mounted on the non-display region of the liquid crystal panel 2 and the first gate circuit film 5, respectively, and are electrically connected to the liquid crystal panel 2.

The first gate circuit film 5 may be a TCP film or a COF film. In particular, the first gate circuit films 5 each of which the first gate integrated circuits 3 are mounted are connected to the liquid crystal panel 2 by TAB method or the like. In this case, each of the plurality of first gate integrated circuits 3 includes at least one source printed circuit board 8a, 8b, data circuit films 6a, 6b, an image non-display area of the liquid crystal panel 2, And receives a direction selection signal and a gate control signal from the timing controller 18 through a gate circuit film 5 or the like.

Each of the first gate integrated circuits 3 provided in the first gate driver unit generates a gate control signal in accordance with a direction selection signal from the timing controller 18, for example, a gate start signal (GSP) A scan pulse or a gate low voltage is sequentially supplied to each gate line GL1 to GLn in a forward direction by using a gate shift clock (GSC), a gate output enable (GOE) signal or the like. For example, the first gate integrated circuits 3 shift the GSP according to the GSC when the logic signal of the high state is inputted from the timing controller 18, so that the gate gates GL1 to GLn are forward- A high-voltage scan pulse is sequentially supplied. A gate low voltage is supplied during a period in which no scan pulse is supplied to each of the gate lines GL1 to GLn. However, the first gate integrated circuits 3 stop the operation when the direction selection signal is inputted from the timing controller 18 as a logic signal in a low state.

The second gate driver includes a plurality of second gate integrated circuits 23 provided on a second side corresponding to the first side of the liquid crystal panel 2 and sequentially driving the gate lines GL1 to GLn in the reverse direction, . Here, the plurality of second gate integrated circuits 23 are also mounted on the non-display region of the liquid crystal panel 2 and the second gate circuit film 25, respectively, and electrically connected to the liquid crystal panel 2.

The second gate circuit film 25 on which the plurality of second gate integrated circuits 23 are mounted is also connected to the liquid crystal panel 2 by the TAB method or the like. In this case, each of the plurality of second gate integrated circuits 23 (Not shown) from the timing controller 18 through the at least one source printed circuit board 8a, 8b, the data circuit films 6a, 6b, the image non-display area of the liquid crystal panel 2, A direction selection signal, a gate control signal, and the like.

Each of the second gate integrated circuits 23 is connected to each of the gate lines GL1 to GLn in the reverse direction by using a gate control signal, for example, a GSP, GSC, or GOE signal in accordance with a direction selection signal from the timing controller 18. [ To sequentially supply a scan pulse or a gate low voltage. For example, each of the plurality of second gate integrated circuits 23 is driven in a direction opposite to that of the first gate integrated circuits 3, that is, when the direction selection signal from the timing controller 18 is supplied to the logic signal of the high state, And sequentially supplies scan pulses of a gate high voltage to the gate lines GL1 to GLn in the reverse direction. A gate low voltage is supplied during a period in which no scan pulse is supplied to each of the gate lines GL1 to GLn. However, when the direction selection signal is supplied to the logic signal in the low state, the second gate integrated circuits 23 stop operating. Here, the number of the data integrated circuits 4a, 4b and the first and second gate integrated circuits 3, 23 as described above is not limited to the number shown in FIG.

The timing controller 18 may be provided on a separate control printed circuit board 10 as shown in Fig. 1 or may be provided on at least one of the at least one source printed circuit boards 8a and 8b (not shown) And controls the data driver and the first and second gate drivers according to the plurality of synchronization signals. For example, when the timing controller 18 is provided on a separate control printed circuit board 10, the timing controller 18 includes at least one first connector 13a, 13b and at least one cable 12a, 12b 8b and each data circuit film 6a, 6b, etc. through at least one second connector 14a, 14b, and at least one second connector 14a, 14b.

Specifically, the timing controller 18 arranges image data inputted from an external system or the like so as to be suitable for driving the liquid crystal panel 2, and supplies the image data to the respective data integrated circuits 4a and 4b in at least one horizontal line unit or frame unit Supply. In addition, the timing controller 18 generates gate and data control signals using synchronizing signals input from the outside, for example, a dot clock, a data enable signal, and horizontal and vertical synchronizing signals, Controls the circuits 3 and 23 and the data integrated circuits 4a and 4b. Here, as shown in the following Table 1, the timing controller 18 generates a direction selection signal OPT by receiving a separate direction signal or the like and outputs it to the data integration circuits 4a and 4b 1 and the second gate integrated circuits (3, 23).

2 is a circuit diagram showing supply lines of a direction selection signal and a gate start signal of the present invention separately. FIG. 3 is a block diagram showing an example in which the direction selection signal and the gate start signal supply lines of FIG. 2 are configured in the liquid crystal display of FIG.

The direction selection signal supply line OPL shown in FIGS. 2 and 3 is configured such that the direction selection signal OPT output from the timing controller 18 is supplied to the respective data integration circuits 4a and 4b of the data driver, (OPT) inverted in phase by inverting the phase of the direction selection signal (OPT) through the phase inversion element (RD), and is supplied to the first gate integrated circuits (3) Is supplied to the second gate integrated circuits (3) of the second gate driver. Here, since the direction selection signal OPT can be a logic signal having a high or low state, the supply line OPL of the direction selection signal OPT can be a 1-bit line, that is, have.

More specifically, the direction selection signal supply line OPL includes a direction selection signal OPT output through the direction selection signal output terminal of the timing controller 18, Are supplied to the respective data integrated circuits 4a and 4b through at least one source printed circuit board 8a and 8b and respective data circuit films 6a and 6b.

In addition, the direction selection signal supply line OPL is connected to the at least one data circuit film 6a and 6b, the liquid crystal panel (not shown), the direction selection signal OPT applied to the at least one source PCB 8a and 8b 2) and the respective first gate circuit films (5) to the respective first gate integrated circuits (3).

In addition, the direction selection signal supply line OPL allows the phase of the direction selection signal OPT applied to the at least one source printed circuit board 8a, 8b to be inverted by the phase inversion element RD, The directional select signal OPT is applied to each of the second gate stacks 25a and 25b through the at least one data circuit film 6a and 6b, the non-display portion of the liquid crystal panel 2, Circuit 23 as shown in Fig.

On the other hand, when the timing controller 18 is provided on a separate control printed circuit board 10, the direction selection signal OPT output through the direction selection signal output terminal of the timing controller 18 is at least Is supplied to the at least one source printed circuit board (8a, 8b) through one first connector (13a, 13b), at least one cable (12a, 12b) and at least one second connector (14a, 14b) do. At least one of the cables 12a and 12b may be a flexible printed circuit or a flexible flat cable or an anisotropic conductive film.

Referring to the following Table 1, the direction selection signal OPT of the present invention can be generated as a 1-bit logic signal in a high or low state. By driving the liquid crystal panel 2 in the forward direction, When the direction signal from the external system is input to the timing controller 8 in a low state as shown in Table 1, the timing controller 18 generates and outputs the direction selection signal OPT in the high state. Output. At this time, the first gate integrated circuits 3 receiving the direction selection signal OPT in the high state sequentially drive the gate lines GL1 to GLn in the forward direction. On the other hand, the operation of the second gate integrated circuits 23, whose phase is inverted by the phase inversion element RD and receives the direction selection signal OPT in the low state, stops its operation.

On the other hand, when the liquid crystal panel 2 is driven in the reverse direction so that the image is displayed in the reverse direction, for example, when the direction signal from the external system is inputted to the timing controller 8 in a high state, Generates and outputs the direction selection signal OPT in the low state. At this time, the operation of the first gate integrated circuits 3 receiving the direction selection signal OPT in the low state is stopped. On the other hand, the second gate integrated circuits 23, which are inverted in phase by the phase inversion element RD and receive the direction selection signal OPT in the high state, sequentially drive the gate lines GL1 to GLn in the reverse direction do.

Referring to FIGS. 2 and 3, the GSP supply line SPL of the present invention is connected to the first gate integrated circuits 3 of the first gate driver through first and second resistance elements R2 and R3 connected in parallel (23) of the second gate driver through the third and fourth resistance elements (R4, R5) connected in parallel, and to supply the GSP to the at least one first gate integrated circuit (3) To the at least one second gate integrated circuit (23).

More specifically, the GSP supply line (SPL) is configured such that the GSP output from the timing controller 18 is coupled to the first and second resistors R2, < RTI ID = 0.0 > R3 and the third and fourth resistance elements R4 and R5 are connected to the first and second resistance elements R2 and R3 in parallel, (1) through at least one source printed circuit board (8b), at least one data circuit film (6b), a non-display area of the liquid crystal panel (2) and at least one first gate circuit film And to supply the GSP to the gate integrated circuit 3. [

In addition, the GSP supply line SPL is connected to the third and fourth resistor elements R4 and R5 in parallel to form at least one source printed circuit board 8a, at least one data circuit film 6a, The non-display area of the liquid crystal panel 2 and the at least one second gate circuit film 25 to the at least one second gate integrated circuit 23. [

When the timing controller 18 is provided on a separate control printed circuit board 10, the GSP output through the GSP output terminal of the timing controller 18 is connected to at least one of the first connectors 13a and 13b, Is also supplied to the at least one source printed circuit board (8a, 8b) through at least one cable (12a, 12b) and at least one second connector (14a, 14b).

As shown in Table 1, the GSP is generated in a logic high state at least every one horizontal period unit (H) at the start timing of every frame in units of frames, and is transmitted through the GSP supply line (SPL) Are supplied to the first and second gate integrated circuits (3, 23). Accordingly, only the first or second gate integrated circuits receiving the direction selection signal OPT of the high state among the first and second gate integrated circuits 3 and 23 sequentially receive the gate lines GL1 - 0.0 > GLn. ≪ / RTI >

As described above, the liquid crystal display according to the present invention supplies a direction selection signal OPT of high or low state to each gate and the data driver through a signal transmission line for transmitting a one-bit logic signal. Then, the GSP is supplied to the first and second gate drivers through a signal transmission line for transmitting the other one-bit logic signal. Therefore, in the liquid crystal display device capable of switching the direction of the display image, the drive control signals and the transmission line configuration thereof can be simplified. Thus, the present invention can increase the space utilization of the simplified signal transmission line and the driving circuit and reduce the manufacturing cost thereof.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

1 is a view schematically showing a liquid crystal display device according to an embodiment of the present invention.

2 is a circuit diagram separately showing supply lines of a direction select signal and a gate start signal according to the present invention;

FIG. 3 is a block diagram showing an example in which supply lines of the direction selection signal and the gate start signal of FIG. 2 are configured in the liquid crystal display device of FIG. 1;

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

2: liquid crystal panel 3: first gate integrated circuit

4a, 4b: data accumulation circuit 5: first gate circuit film

6a, 6b: data circuit film 8a, 8b: sub printed circuit board

10: control printed circuit board 18: timing controller

23: second gate integrated circuit 25: second gate circuit film

SPL: gate start signal supply line

OPL: direction selection signal supply line

RD: Phase Inversion Element

Claims (10)

A first gate driver provided on a first side of the liquid crystal panel for driving all the gate lines of the liquid crystal panel in a positive direction; A second gate driver provided on a second side corresponding to the first side of the liquid crystal panel and driving all the gate lines of the liquid crystal panel in a reverse direction; A data driver driving data lines of the liquid crystal panel; And A direction selection signal of a high or low logic state for selecting a video display direction of the liquid crystal panel and a gate start signal are generated and supplied to the first and second gate drivers through a direction selection signal supply line and a gate start signal supply line, Respectively, The direction selection signal supply line And a direction selection signal output from the timing controller is supplied to each of the data integrated circuits of the data driver and the first gate integrated circuits of the first gate driver, A direction selection signal inverted in phase by inverting the phase of the direction selection signal through at least one phase inversion element is supplied to the second gate integrated circuits of the second gate driving unit, And the gate driver is selectively driven according to a logic state of the direction selection signal. delete The method according to claim 1, The direction selection signal supply line Wherein the direction selection signal is configured to be supplied to each of the data integrated circuits through a data circuit film on which at least one source printed circuit board and the data integrated circuits are mounted, Wherein a directional select signal applied to the at least one source printed circuit board comprises at least one first circuit circuit film on which the at least one data circuit film, the non-display portion of the liquid crystal panel and each first gate integrated circuit are mounted To the at least one first gate integrated circuit, A direction selection signal applied to the at least one source printed circuit board is inverted by the phase inversion element so that a phase-inverted direction selection signal is applied to the at least one data circuit film, the non-display portion of the liquid crystal panel, Wherein each of the second gate integrated circuits is supplied to the at least one second gate integrated circuit through at least one second gate circuit film on which the second gate integrated circuits are mounted. The method of claim 3, The direction selection signal output from the timing controller is Wherein the timing controller is mounted on a control printed circuit board, at least one first connector, at least one cable, and at least one second connector, to a direction selection signal supply line provided in the at least one source printed circuit board, Display device. 5. The method of claim 4, The direction selection signal And the first gate integrated circuits drive the gate lines sequentially in a forward direction when the image is displayed on the liquid crystal panel in a forward direction and the phase thereof is inverted by the phase inversion element, The direction selection signal inverted to the second gate integrated circuits is input to the second gate integrated circuits to stop its operation. 6. The method of claim 5, The direction selection signal When the image is displayed on the liquid crystal panel in a reverse direction, the first gate integrated circuits are generated and output in a low state to stop the operation of the first gate integrated circuits, and the phases thereof are inverted by the phase inversion elements, And the selection signal is input to the second gate integrated circuits and sequentially drives the gate lines in a reverse direction. The method according to claim 1, The gate start signal supply line And to supply a gate start signal to at least one first gate integrated circuit of the first gate integrated circuits of the first gate driver through first and second resistive elements connected in parallel, And to supply the gate start signal to the second gate integrated circuit of at least one of the second gate integrated circuits of the second gate driver through the third and fourth resistance elements connected in parallel. 8. The method of claim 7, The gate start signal supply line Wherein the gate-start signal output from the timing controller is supplied to the first and second resistive elements and the third and fourth resistive elements configured in parallel via at least one stabilizing element, At least one data circuit film, a non-display region of the liquid crystal panel, and at least one first gate circuit film through at least one source printed circuit board, at least one data circuit film, And to supply the gate start signal to the first gate integrated circuit, And a second gate circuit film connected in parallel to the third and fourth resistance elements to form the second gate circuit film through the at least one source printed circuit board, the at least one data circuit film, the non-display area of the liquid crystal panel, And to supply the gate start signal to at least one second gate integrated circuit. 9. The method of claim 8, The gate start signal output from the timing controller Wherein the timing controller is supplied to the gate start signal supply line provided on the at least one source printed circuit board through a control printed circuit board mounted on the at least one source printed circuit board, at least one first connector, at least one cable, and at least one second connector Liquid crystal display device. 10. The method of claim 9, The gate start signal Logic state in at least one horizontal period unit at the start timing of each frame and supplied to the first and second gate integrated circuits through the gate start signal supply line, Only the first or second gate integrated circuits receiving the direction selection signal of the high state among the integrated circuits sequentially drives the gate lines.

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